001 package org.jikesrvm.compilers.opt.mir2mc.ia32;
002
003 import org.jikesrvm.*;
004
005 import org.jikesrvm.compilers.opt.*;
006
007 import org.jikesrvm.compilers.opt.ir.*;
008
009
010
011 /**
012 * This class is the automatically-generated assembler for
013 * the optimizing compiler. It consists of methods that
014 * understand the possible operand combinations of each
015 * instruction type, and how to translate those operands to
016 * calls to the Assember low-level emit method
017 *
018 * It is generated by GenerateAssembler.java
019 *
020 */
021 public abstract class AssemblerOpt extends AssemblerBase {
022
023 /**
024 * @see org.jikesrvm.ArchitectureSpecific.Assembler
025 */
026 public AssemblerOpt(int bcSize, boolean print, IR ir) {
027 super(bcSize, print, ir);
028 }
029
030 /**
031 * Emit the given instruction, assuming that
032 * it is a MIR_BinaryAcc instruction
033 * and has a FIMUL operator
034 *
035 * @param inst the instruction to assemble
036 */
037 private void doFIMUL(Instruction inst) {
038 if (isWord(inst)) {
039 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
040 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
041 emitFIMUL_Reg_Abs_Word(
042 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
043 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
044
045 } else {
046 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
047 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
048 emitFIMUL_Reg_RegDisp_Word(
049 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
050 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
051
052 } else {
053 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
054 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
055 emitFIMUL_Reg_RegOff_Word(
056 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
057 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
058
059 } else {
060 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
061 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
062 emitFIMUL_Reg_RegIdx_Word(
063 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
064 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
065
066 } else {
067 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
068 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
069 emitFIMUL_Reg_RegInd_Word(
070 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
071 getBase(MIR_BinaryAcc.getValue(inst)));
072 }
073 }
074 }
075 }
076
077 } else {
078 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
079 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
080 emitFIMUL_Reg_Abs(
081 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
082 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
083
084 } else {
085 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
086 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
087 emitFIMUL_Reg_RegDisp(
088 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
089 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
090
091 } else {
092 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
093 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
094 emitFIMUL_Reg_RegOff(
095 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
096 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
097
098 } else {
099 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
100 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
101 emitFIMUL_Reg_RegIdx(
102 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
103 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
104
105 } else {
106 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
107 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
108 emitFIMUL_Reg_RegInd(
109 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
110 getBase(MIR_BinaryAcc.getValue(inst)));
111 }
112 }
113 }
114 }
115 }
116 }
117
118 /**
119 * Emit the given instruction, assuming that
120 * it is a MIR_Nullary instruction
121 * and has a METHODSTART operator
122 *
123 * @param inst the instruction to assemble
124 */
125 private void doMETHODSTART(Instruction inst) {
126 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Nullary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
127 emitMETHODSTART_Reg(
128 getGPR_Reg(MIR_Nullary.getResult(inst)));
129 }
130
131 /**
132 * Emit the given instruction, assuming that
133 * it is a MIR_Unary instruction
134 * and has a CVTSS2SD operator
135 *
136 * @param inst the instruction to assemble
137 */
138 private void doCVTSS2SD(Instruction inst) {
139 if (isXMM_Reg(MIR_Unary.getVal(inst))) {
140 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
141 emitCVTSS2SD_Reg_Reg(
142 getXMM_Reg(MIR_Unary.getResult(inst)),
143 getXMM_Reg(MIR_Unary.getVal(inst)));
144
145 } else {
146 if (isAbs(MIR_Unary.getVal(inst))) {
147 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
148 emitCVTSS2SD_Reg_Abs(
149 getXMM_Reg(MIR_Unary.getResult(inst)),
150 getDisp(MIR_Unary.getVal(inst)).toWord().toAddress());
151
152 } else {
153 if (isRegDisp(MIR_Unary.getVal(inst))) {
154 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
155 emitCVTSS2SD_Reg_RegDisp(
156 getXMM_Reg(MIR_Unary.getResult(inst)),
157 getBase(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
158
159 } else {
160 if (isRegOff(MIR_Unary.getVal(inst))) {
161 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
162 emitCVTSS2SD_Reg_RegOff(
163 getXMM_Reg(MIR_Unary.getResult(inst)),
164 getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
165
166 } else {
167 if (isRegIdx(MIR_Unary.getVal(inst))) {
168 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
169 emitCVTSS2SD_Reg_RegIdx(
170 getXMM_Reg(MIR_Unary.getResult(inst)),
171 getBase(MIR_Unary.getVal(inst)), getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
172
173 } else {
174 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
175 if (VM.VerifyAssertions && !isRegInd(MIR_Unary.getVal(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
176 emitCVTSS2SD_Reg_RegInd(
177 getXMM_Reg(MIR_Unary.getResult(inst)),
178 getBase(MIR_Unary.getVal(inst)));
179 }
180 }
181 }
182 }
183 }
184 }
185
186 /**
187 * Emit the given instruction, assuming that
188 * it is a MIR_BinaryAcc instruction
189 * and has a CMPUNORDSS operator
190 *
191 * @param inst the instruction to assemble
192 */
193 private void doCMPUNORDSS(Instruction inst) {
194 if (isXMM_Reg(MIR_BinaryAcc.getValue(inst))) {
195 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
196 emitCMPUNORDSS_Reg_Reg(
197 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
198 getXMM_Reg(MIR_BinaryAcc.getValue(inst)));
199
200 } else {
201 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
202 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
203 emitCMPUNORDSS_Reg_Abs(
204 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
205 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
206
207 } else {
208 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
209 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
210 emitCMPUNORDSS_Reg_RegDisp(
211 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
212 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
213
214 } else {
215 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
216 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
217 emitCMPUNORDSS_Reg_RegOff(
218 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
219 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
220
221 } else {
222 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
223 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
224 emitCMPUNORDSS_Reg_RegIdx(
225 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
226 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
227
228 } else {
229 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
230 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
231 emitCMPUNORDSS_Reg_RegInd(
232 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
233 getBase(MIR_BinaryAcc.getValue(inst)));
234 }
235 }
236 }
237 }
238 }
239 }
240
241 /**
242 * Emit the given instruction, assuming that
243 * it is a MIR_BinaryAcc instruction
244 * and has a MULSS operator
245 *
246 * @param inst the instruction to assemble
247 */
248 private void doMULSS(Instruction inst) {
249 if (isXMM_Reg(MIR_BinaryAcc.getValue(inst))) {
250 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
251 emitMULSS_Reg_Reg(
252 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
253 getXMM_Reg(MIR_BinaryAcc.getValue(inst)));
254
255 } else {
256 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
257 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
258 emitMULSS_Reg_Abs(
259 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
260 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
261
262 } else {
263 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
264 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
265 emitMULSS_Reg_RegDisp(
266 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
267 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
268
269 } else {
270 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
271 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
272 emitMULSS_Reg_RegOff(
273 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
274 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
275
276 } else {
277 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
278 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
279 emitMULSS_Reg_RegIdx(
280 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
281 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
282
283 } else {
284 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
285 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
286 emitMULSS_Reg_RegInd(
287 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
288 getBase(MIR_BinaryAcc.getValue(inst)));
289 }
290 }
291 }
292 }
293 }
294 }
295
296 /**
297 * Emit the given instruction, assuming that
298 * it is a MIR_Unary instruction
299 * and has a CVTSS2SI operator
300 *
301 * @param inst the instruction to assemble
302 */
303 private void doCVTSS2SI(Instruction inst) {
304 if (isQuad(inst)) {
305 if (isXMM_Reg(MIR_Unary.getVal(inst))) {
306 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
307 emitCVTSS2SI_Reg_Reg_Quad(
308 getGPR_Reg(MIR_Unary.getResult(inst)),
309 getXMM_Reg(MIR_Unary.getVal(inst)));
310
311 } else {
312 if (isAbs(MIR_Unary.getVal(inst))) {
313 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
314 emitCVTSS2SI_Reg_Abs_Quad(
315 getGPR_Reg(MIR_Unary.getResult(inst)),
316 getDisp(MIR_Unary.getVal(inst)).toWord().toAddress());
317
318 } else {
319 if (isRegDisp(MIR_Unary.getVal(inst))) {
320 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
321 emitCVTSS2SI_Reg_RegDisp_Quad(
322 getGPR_Reg(MIR_Unary.getResult(inst)),
323 getBase(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
324
325 } else {
326 if (isRegOff(MIR_Unary.getVal(inst))) {
327 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
328 emitCVTSS2SI_Reg_RegOff_Quad(
329 getGPR_Reg(MIR_Unary.getResult(inst)),
330 getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
331
332 } else {
333 if (isRegIdx(MIR_Unary.getVal(inst))) {
334 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
335 emitCVTSS2SI_Reg_RegIdx_Quad(
336 getGPR_Reg(MIR_Unary.getResult(inst)),
337 getBase(MIR_Unary.getVal(inst)), getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
338
339 } else {
340 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
341 if (VM.VerifyAssertions && !isRegInd(MIR_Unary.getVal(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
342 emitCVTSS2SI_Reg_RegInd_Quad(
343 getGPR_Reg(MIR_Unary.getResult(inst)),
344 getBase(MIR_Unary.getVal(inst)));
345 }
346 }
347 }
348 }
349 }
350
351 } else {
352 if (isXMM_Reg(MIR_Unary.getVal(inst))) {
353 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
354 emitCVTSS2SI_Reg_Reg(
355 getGPR_Reg(MIR_Unary.getResult(inst)),
356 getXMM_Reg(MIR_Unary.getVal(inst)));
357
358 } else {
359 if (isAbs(MIR_Unary.getVal(inst))) {
360 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
361 emitCVTSS2SI_Reg_Abs(
362 getGPR_Reg(MIR_Unary.getResult(inst)),
363 getDisp(MIR_Unary.getVal(inst)).toWord().toAddress());
364
365 } else {
366 if (isRegDisp(MIR_Unary.getVal(inst))) {
367 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
368 emitCVTSS2SI_Reg_RegDisp(
369 getGPR_Reg(MIR_Unary.getResult(inst)),
370 getBase(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
371
372 } else {
373 if (isRegOff(MIR_Unary.getVal(inst))) {
374 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
375 emitCVTSS2SI_Reg_RegOff(
376 getGPR_Reg(MIR_Unary.getResult(inst)),
377 getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
378
379 } else {
380 if (isRegIdx(MIR_Unary.getVal(inst))) {
381 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
382 emitCVTSS2SI_Reg_RegIdx(
383 getGPR_Reg(MIR_Unary.getResult(inst)),
384 getBase(MIR_Unary.getVal(inst)), getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
385
386 } else {
387 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
388 if (VM.VerifyAssertions && !isRegInd(MIR_Unary.getVal(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
389 emitCVTSS2SI_Reg_RegInd(
390 getGPR_Reg(MIR_Unary.getResult(inst)),
391 getBase(MIR_Unary.getVal(inst)));
392 }
393 }
394 }
395 }
396 }
397 }
398 }
399
400 /**
401 * Emit the given instruction, assuming that
402 * it is a MIR_Move instruction
403 * and has a FSTP operator
404 *
405 * @param inst the instruction to assemble
406 */
407 private void doFSTP(Instruction inst) {
408 if (isQuad(inst)) {
409 if (isAbs(MIR_Move.getResult(inst))) {
410 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
411 emitFSTP_Abs_Reg_Quad(
412 getDisp(MIR_Move.getResult(inst)).toWord().toAddress(),
413 getFPR_Reg(MIR_Move.getValue(inst)));
414
415 } else {
416 if (isRegDisp(MIR_Move.getResult(inst))) {
417 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
418 emitFSTP_RegDisp_Reg_Quad(
419 getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
420 getFPR_Reg(MIR_Move.getValue(inst)));
421
422 } else {
423 if (isRegOff(MIR_Move.getResult(inst))) {
424 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
425 emitFSTP_RegOff_Reg_Quad(
426 getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
427 getFPR_Reg(MIR_Move.getValue(inst)));
428
429 } else {
430 if (isRegIdx(MIR_Move.getResult(inst))) {
431 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
432 emitFSTP_RegIdx_Reg_Quad(
433 getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
434 getFPR_Reg(MIR_Move.getValue(inst)));
435
436 } else {
437 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
438 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
439 emitFSTP_RegInd_Reg_Quad(
440 getBase(MIR_Move.getResult(inst)),
441 getFPR_Reg(MIR_Move.getValue(inst)));
442 }
443 }
444 }
445 }
446
447 } else {
448 if (isFPR_Reg(MIR_Move.getResult(inst))) {
449 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
450 emitFSTP_Reg_Reg(
451 getFPR_Reg(MIR_Move.getResult(inst)),
452 getFPR_Reg(MIR_Move.getValue(inst)));
453
454 } else {
455 if (isAbs(MIR_Move.getResult(inst))) {
456 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
457 emitFSTP_Abs_Reg(
458 getDisp(MIR_Move.getResult(inst)).toWord().toAddress(),
459 getFPR_Reg(MIR_Move.getValue(inst)));
460
461 } else {
462 if (isRegDisp(MIR_Move.getResult(inst))) {
463 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
464 emitFSTP_RegDisp_Reg(
465 getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
466 getFPR_Reg(MIR_Move.getValue(inst)));
467
468 } else {
469 if (isRegOff(MIR_Move.getResult(inst))) {
470 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
471 emitFSTP_RegOff_Reg(
472 getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
473 getFPR_Reg(MIR_Move.getValue(inst)));
474
475 } else {
476 if (isRegIdx(MIR_Move.getResult(inst))) {
477 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
478 emitFSTP_RegIdx_Reg(
479 getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
480 getFPR_Reg(MIR_Move.getValue(inst)));
481
482 } else {
483 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
484 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
485 emitFSTP_RegInd_Reg(
486 getBase(MIR_Move.getResult(inst)),
487 getFPR_Reg(MIR_Move.getValue(inst)));
488 }
489 }
490 }
491 }
492 }
493 }
494 }
495
496 /**
497 * Emit the given instruction, assuming that
498 * it is a MIR_Unary instruction
499 * and has a CVTTSD2SIQ operator
500 *
501 * @param inst the instruction to assemble
502 */
503 private void doCVTTSD2SIQ(Instruction inst) {
504 if (isXMM_Reg(MIR_Unary.getVal(inst))) {
505 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
506 if (VM.VerifyAssertions && !isQuad(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
507 emitCVTTSD2SIQ_Reg_Reg_Quad(
508 getGPR_Reg(MIR_Unary.getResult(inst)),
509 getXMM_Reg(MIR_Unary.getVal(inst)));
510
511 } else {
512 if (isAbs(MIR_Unary.getVal(inst))) {
513 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
514 if (VM.VerifyAssertions && !isQuad(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
515 emitCVTTSD2SIQ_Reg_Abs_Quad(
516 getGPR_Reg(MIR_Unary.getResult(inst)),
517 getDisp(MIR_Unary.getVal(inst)).toWord().toAddress());
518
519 } else {
520 if (isRegDisp(MIR_Unary.getVal(inst))) {
521 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
522 if (VM.VerifyAssertions && !isQuad(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
523 emitCVTTSD2SIQ_Reg_RegDisp_Quad(
524 getGPR_Reg(MIR_Unary.getResult(inst)),
525 getBase(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
526
527 } else {
528 if (isRegOff(MIR_Unary.getVal(inst))) {
529 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
530 if (VM.VerifyAssertions && !isQuad(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
531 emitCVTTSD2SIQ_Reg_RegOff_Quad(
532 getGPR_Reg(MIR_Unary.getResult(inst)),
533 getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
534
535 } else {
536 if (isRegIdx(MIR_Unary.getVal(inst))) {
537 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
538 if (VM.VerifyAssertions && !isQuad(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
539 emitCVTTSD2SIQ_Reg_RegIdx_Quad(
540 getGPR_Reg(MIR_Unary.getResult(inst)),
541 getBase(MIR_Unary.getVal(inst)), getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
542
543 } else {
544 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
545 if (VM.VerifyAssertions && !isRegInd(MIR_Unary.getVal(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
546 if (VM.VerifyAssertions && !isQuad(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
547 emitCVTTSD2SIQ_Reg_RegInd_Quad(
548 getGPR_Reg(MIR_Unary.getResult(inst)),
549 getBase(MIR_Unary.getVal(inst)));
550 }
551 }
552 }
553 }
554 }
555 }
556
557 /**
558 * Emit the given instruction, assuming that
559 * it is a MIR_ConvertDW2QW instruction
560 * and has a CDO operator
561 *
562 * @param inst the instruction to assemble
563 */
564 private void doCDO(Instruction inst) {
565 emitCDO();
566 }
567
568 /**
569 * Emit the given instruction, assuming that
570 * it is a MIR_BinaryAcc instruction
571 * and has a CMPLTSS operator
572 *
573 * @param inst the instruction to assemble
574 */
575 private void doCMPLTSS(Instruction inst) {
576 if (isXMM_Reg(MIR_BinaryAcc.getValue(inst))) {
577 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
578 emitCMPLTSS_Reg_Reg(
579 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
580 getXMM_Reg(MIR_BinaryAcc.getValue(inst)));
581
582 } else {
583 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
584 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
585 emitCMPLTSS_Reg_Abs(
586 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
587 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
588
589 } else {
590 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
591 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
592 emitCMPLTSS_Reg_RegDisp(
593 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
594 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
595
596 } else {
597 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
598 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
599 emitCMPLTSS_Reg_RegOff(
600 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
601 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
602
603 } else {
604 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
605 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
606 emitCMPLTSS_Reg_RegIdx(
607 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
608 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
609
610 } else {
611 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
612 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
613 emitCMPLTSS_Reg_RegInd(
614 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
615 getBase(MIR_BinaryAcc.getValue(inst)));
616 }
617 }
618 }
619 }
620 }
621 }
622
623 /**
624 * Emit the given instruction, assuming that
625 * it is a MIR_ConvertDW2QW instruction
626 * and has a CDQ operator
627 *
628 * @param inst the instruction to assemble
629 */
630 private void doCDQ(Instruction inst) {
631 emitCDQ();
632 }
633
634 /**
635 * Emit the given instruction, assuming that
636 * it is a MIR_BinaryAcc instruction
637 * and has a ORPD operator
638 *
639 * @param inst the instruction to assemble
640 */
641 private void doORPD(Instruction inst) {
642 if (isXMM_Reg(MIR_BinaryAcc.getValue(inst))) {
643 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
644 emitORPD_Reg_Reg(
645 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
646 getXMM_Reg(MIR_BinaryAcc.getValue(inst)));
647
648 } else {
649 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
650 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
651 emitORPD_Reg_Abs(
652 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
653 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
654
655 } else {
656 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
657 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
658 emitORPD_Reg_RegDisp(
659 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
660 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
661
662 } else {
663 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
664 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
665 emitORPD_Reg_RegOff(
666 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
667 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
668
669 } else {
670 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
671 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
672 emitORPD_Reg_RegIdx(
673 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
674 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
675
676 } else {
677 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
678 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
679 emitORPD_Reg_RegInd(
680 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
681 getBase(MIR_BinaryAcc.getValue(inst)));
682 }
683 }
684 }
685 }
686 }
687 }
688
689 /**
690 * Emit the given instruction, assuming that
691 * it is a MIR_CondMove instruction
692 * and has a FCMOV operator
693 *
694 * @param inst the instruction to assemble
695 */
696 private void doFCMOV(Instruction inst) {
697 if (VM.VerifyAssertions && !isCond(MIR_CondMove.getCond(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
698 if (VM.VerifyAssertions && !isFPR_Reg(MIR_CondMove.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
699 if (VM.VerifyAssertions && !isFPR_Reg(MIR_CondMove.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
700 emitFCMOV_Cond_Reg_Reg(
701 getCond(MIR_CondMove.getCond(inst)),
702 getFPR_Reg(MIR_CondMove.getResult(inst)),
703 getFPR_Reg(MIR_CondMove.getValue(inst)));
704 }
705
706 /**
707 * Emit the given instruction, assuming that
708 * it is a MIR_Unary instruction
709 * and has a MOVSXQ operator
710 *
711 * @param inst the instruction to assemble
712 */
713 private void doMOVSXQ(Instruction inst) {
714 if (isByte(inst)) {
715 if (isGPR_Reg(MIR_Unary.getVal(inst))) {
716 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
717 emitMOVSXQ_Reg_Reg_Byte(
718 getGPR_Reg(MIR_Unary.getResult(inst)),
719 getGPR_Reg(MIR_Unary.getVal(inst)));
720
721 } else {
722 if (isAbs(MIR_Unary.getVal(inst))) {
723 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
724 emitMOVSXQ_Reg_Abs_Byte(
725 getGPR_Reg(MIR_Unary.getResult(inst)),
726 getDisp(MIR_Unary.getVal(inst)).toWord().toAddress());
727
728 } else {
729 if (isRegDisp(MIR_Unary.getVal(inst))) {
730 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
731 emitMOVSXQ_Reg_RegDisp_Byte(
732 getGPR_Reg(MIR_Unary.getResult(inst)),
733 getBase(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
734
735 } else {
736 if (isRegOff(MIR_Unary.getVal(inst))) {
737 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
738 emitMOVSXQ_Reg_RegOff_Byte(
739 getGPR_Reg(MIR_Unary.getResult(inst)),
740 getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
741
742 } else {
743 if (isRegIdx(MIR_Unary.getVal(inst))) {
744 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
745 emitMOVSXQ_Reg_RegIdx_Byte(
746 getGPR_Reg(MIR_Unary.getResult(inst)),
747 getBase(MIR_Unary.getVal(inst)), getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
748
749 } else {
750 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
751 if (VM.VerifyAssertions && !isRegInd(MIR_Unary.getVal(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
752 emitMOVSXQ_Reg_RegInd_Byte(
753 getGPR_Reg(MIR_Unary.getResult(inst)),
754 getBase(MIR_Unary.getVal(inst)));
755 }
756 }
757 }
758 }
759 }
760
761 } else {
762 if (isGPR_Reg(MIR_Unary.getVal(inst))) {
763 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
764 if (VM.VerifyAssertions && !isWord(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
765 emitMOVSXQ_Reg_Reg_Word(
766 getGPR_Reg(MIR_Unary.getResult(inst)),
767 getGPR_Reg(MIR_Unary.getVal(inst)));
768
769 } else {
770 if (isAbs(MIR_Unary.getVal(inst))) {
771 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
772 if (VM.VerifyAssertions && !isWord(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
773 emitMOVSXQ_Reg_Abs_Word(
774 getGPR_Reg(MIR_Unary.getResult(inst)),
775 getDisp(MIR_Unary.getVal(inst)).toWord().toAddress());
776
777 } else {
778 if (isRegDisp(MIR_Unary.getVal(inst))) {
779 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
780 if (VM.VerifyAssertions && !isWord(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
781 emitMOVSXQ_Reg_RegDisp_Word(
782 getGPR_Reg(MIR_Unary.getResult(inst)),
783 getBase(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
784
785 } else {
786 if (isRegOff(MIR_Unary.getVal(inst))) {
787 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
788 if (VM.VerifyAssertions && !isWord(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
789 emitMOVSXQ_Reg_RegOff_Word(
790 getGPR_Reg(MIR_Unary.getResult(inst)),
791 getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
792
793 } else {
794 if (isRegIdx(MIR_Unary.getVal(inst))) {
795 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
796 if (VM.VerifyAssertions && !isWord(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
797 emitMOVSXQ_Reg_RegIdx_Word(
798 getGPR_Reg(MIR_Unary.getResult(inst)),
799 getBase(MIR_Unary.getVal(inst)), getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
800
801 } else {
802 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
803 if (VM.VerifyAssertions && !isRegInd(MIR_Unary.getVal(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
804 if (VM.VerifyAssertions && !isWord(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
805 emitMOVSXQ_Reg_RegInd_Word(
806 getGPR_Reg(MIR_Unary.getResult(inst)),
807 getBase(MIR_Unary.getVal(inst)));
808 }
809 }
810 }
811 }
812 }
813 }
814 }
815
816 /**
817 * Emit the given instruction, assuming that
818 * it is a MIR_Nullary instruction
819 * and has a FLDLG2 operator
820 *
821 * @param inst the instruction to assemble
822 */
823 private void doFLDLG2(Instruction inst) {
824 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Nullary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
825 emitFLDLG2_Reg(
826 getFPR_Reg(MIR_Nullary.getResult(inst)));
827 }
828
829 /**
830 * Emit the given instruction, assuming that
831 * it is a MIR_BinaryAcc instruction
832 * and has a FSUB operator
833 *
834 * @param inst the instruction to assemble
835 */
836 private void doFSUB(Instruction inst) {
837 if (isQuad(inst)) {
838 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
839 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
840 emitFSUB_Reg_Abs_Quad(
841 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
842 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
843
844 } else {
845 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
846 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
847 emitFSUB_Reg_RegDisp_Quad(
848 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
849 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
850
851 } else {
852 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
853 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
854 emitFSUB_Reg_RegOff_Quad(
855 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
856 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
857
858 } else {
859 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
860 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
861 emitFSUB_Reg_RegIdx_Quad(
862 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
863 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
864
865 } else {
866 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
867 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
868 emitFSUB_Reg_RegInd_Quad(
869 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
870 getBase(MIR_BinaryAcc.getValue(inst)));
871 }
872 }
873 }
874 }
875
876 } else {
877 if (isFPR_Reg(MIR_BinaryAcc.getValue(inst))) {
878 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
879 emitFSUB_Reg_Reg(
880 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
881 getFPR_Reg(MIR_BinaryAcc.getValue(inst)));
882
883 } else {
884 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
885 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
886 emitFSUB_Reg_Abs(
887 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
888 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
889
890 } else {
891 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
892 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
893 emitFSUB_Reg_RegDisp(
894 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
895 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
896
897 } else {
898 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
899 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
900 emitFSUB_Reg_RegOff(
901 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
902 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
903
904 } else {
905 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
906 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
907 emitFSUB_Reg_RegIdx(
908 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
909 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
910
911 } else {
912 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
913 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
914 emitFSUB_Reg_RegInd(
915 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
916 getBase(MIR_BinaryAcc.getValue(inst)));
917 }
918 }
919 }
920 }
921 }
922 }
923 }
924
925 /**
926 * Emit the given instruction, assuming that
927 * it is a MIR_UnaryNoRes instruction
928 * and has a PUSH operator
929 *
930 * @param inst the instruction to assemble
931 */
932 private void doPUSH(Instruction inst) {
933 if (isImm(MIR_UnaryNoRes.getVal(inst))) {
934 emitPUSH_Imm(
935 getImm(MIR_UnaryNoRes.getVal(inst)));
936
937 } else {
938 if (isGPR_Reg(MIR_UnaryNoRes.getVal(inst))) {
939 emitPUSH_Reg(
940 getGPR_Reg(MIR_UnaryNoRes.getVal(inst)));
941
942 } else {
943 if (isAbs(MIR_UnaryNoRes.getVal(inst))) {
944 emitPUSH_Abs(
945 getDisp(MIR_UnaryNoRes.getVal(inst)).toWord().toAddress());
946
947 } else {
948 if (isRegDisp(MIR_UnaryNoRes.getVal(inst))) {
949 emitPUSH_RegDisp(
950 getBase(MIR_UnaryNoRes.getVal(inst)), getDisp(MIR_UnaryNoRes.getVal(inst)));
951
952 } else {
953 if (isRegOff(MIR_UnaryNoRes.getVal(inst))) {
954 emitPUSH_RegOff(
955 getIndex(MIR_UnaryNoRes.getVal(inst)), getScale(MIR_UnaryNoRes.getVal(inst)), getDisp(MIR_UnaryNoRes.getVal(inst)));
956
957 } else {
958 if (isRegIdx(MIR_UnaryNoRes.getVal(inst))) {
959 emitPUSH_RegIdx(
960 getBase(MIR_UnaryNoRes.getVal(inst)), getIndex(MIR_UnaryNoRes.getVal(inst)), getScale(MIR_UnaryNoRes.getVal(inst)), getDisp(MIR_UnaryNoRes.getVal(inst)));
961
962 } else {
963 if (VM.VerifyAssertions && !isRegInd(MIR_UnaryNoRes.getVal(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
964 emitPUSH_RegInd(
965 getBase(MIR_UnaryNoRes.getVal(inst)));
966 }
967 }
968 }
969 }
970 }
971 }
972 }
973
974 /**
975 * Emit the given instruction, assuming that
976 * it is a MIR_BinaryAcc instruction
977 * and has a SUB operator
978 *
979 * @param inst the instruction to assemble
980 */
981 private void doSUB(Instruction inst) {
982 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
983 if (isByte(inst)) {
984 if (isImm(MIR_BinaryAcc.getValue(inst))) {
985 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
986 emitSUB_Reg_Imm_Byte(
987 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
988 getImm(MIR_BinaryAcc.getValue(inst)));
989
990 } else {
991 if (isGPR_Reg(MIR_BinaryAcc.getValue(inst))) {
992 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
993 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
994 emitSUB_Reg_Reg_Byte(
995 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
996 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
997
998 } else {
999 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
1000 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
1001 emitSUB_Reg_Abs_Byte(
1002 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
1003 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
1004
1005 } else {
1006 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
1007 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
1008 emitSUB_Reg_RegDisp_Byte(
1009 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
1010 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
1011
1012 } else {
1013 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
1014 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
1015 emitSUB_Reg_RegOff_Byte(
1016 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
1017 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
1018
1019 } else {
1020 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
1021 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
1022 emitSUB_Reg_RegIdx_Byte(
1023 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
1024 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
1025
1026 } else {
1027 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1028 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
1029 emitSUB_Reg_RegInd_Byte(
1030 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
1031 getBase(MIR_BinaryAcc.getValue(inst)));
1032 }
1033 }
1034 }
1035 }
1036 }
1037 }
1038
1039 } else {
1040 if (isWord(inst)) {
1041 if (isImm(MIR_BinaryAcc.getValue(inst))) {
1042 emitSUB_Reg_Imm_Word(
1043 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
1044 getImm(MIR_BinaryAcc.getValue(inst)));
1045
1046 } else {
1047 if (isGPR_Reg(MIR_BinaryAcc.getValue(inst))) {
1048 emitSUB_Reg_Reg_Word(
1049 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
1050 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
1051
1052 } else {
1053 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
1054 emitSUB_Reg_Abs_Word(
1055 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
1056 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
1057
1058 } else {
1059 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
1060 emitSUB_Reg_RegDisp_Word(
1061 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
1062 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
1063
1064 } else {
1065 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
1066 emitSUB_Reg_RegOff_Word(
1067 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
1068 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
1069
1070 } else {
1071 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
1072 emitSUB_Reg_RegIdx_Word(
1073 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
1074 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
1075
1076 } else {
1077 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1078 emitSUB_Reg_RegInd_Word(
1079 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
1080 getBase(MIR_BinaryAcc.getValue(inst)));
1081 }
1082 }
1083 }
1084 }
1085 }
1086 }
1087
1088 } else {
1089 if (isQuad(inst)) {
1090 if (isImm(MIR_BinaryAcc.getValue(inst))) {
1091 emitSUB_Reg_Imm_Quad(
1092 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
1093 getImm(MIR_BinaryAcc.getValue(inst)));
1094
1095 } else {
1096 if (isGPR_Reg(MIR_BinaryAcc.getValue(inst))) {
1097 emitSUB_Reg_Reg_Quad(
1098 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
1099 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
1100
1101 } else {
1102 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
1103 emitSUB_Reg_Abs_Quad(
1104 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
1105 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
1106
1107 } else {
1108 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
1109 emitSUB_Reg_RegDisp_Quad(
1110 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
1111 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
1112
1113 } else {
1114 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
1115 emitSUB_Reg_RegOff_Quad(
1116 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
1117 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
1118
1119 } else {
1120 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
1121 emitSUB_Reg_RegIdx_Quad(
1122 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
1123 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
1124
1125 } else {
1126 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1127 emitSUB_Reg_RegInd_Quad(
1128 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
1129 getBase(MIR_BinaryAcc.getValue(inst)));
1130 }
1131 }
1132 }
1133 }
1134 }
1135 }
1136
1137 } else {
1138 if (isImm(MIR_BinaryAcc.getValue(inst))) {
1139 emitSUB_Reg_Imm(
1140 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
1141 getImm(MIR_BinaryAcc.getValue(inst)));
1142
1143 } else {
1144 if (isGPR_Reg(MIR_BinaryAcc.getValue(inst))) {
1145 emitSUB_Reg_Reg(
1146 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
1147 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
1148
1149 } else {
1150 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
1151 emitSUB_Reg_Abs(
1152 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
1153 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
1154
1155 } else {
1156 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
1157 emitSUB_Reg_RegDisp(
1158 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
1159 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
1160
1161 } else {
1162 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
1163 emitSUB_Reg_RegOff(
1164 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
1165 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
1166
1167 } else {
1168 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
1169 emitSUB_Reg_RegIdx(
1170 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
1171 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
1172
1173 } else {
1174 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1175 emitSUB_Reg_RegInd(
1176 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
1177 getBase(MIR_BinaryAcc.getValue(inst)));
1178 }
1179 }
1180 }
1181 }
1182 }
1183 }
1184 }
1185 }
1186 }
1187
1188 } else {
1189 if (isImm(MIR_BinaryAcc.getValue(inst))) {
1190 if (isByte(inst)) {
1191 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
1192 emitSUB_Abs_Imm_Byte(
1193 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
1194 getImm(MIR_BinaryAcc.getValue(inst)));
1195
1196 } else {
1197 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
1198 emitSUB_RegDisp_Imm_Byte(
1199 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
1200 getImm(MIR_BinaryAcc.getValue(inst)));
1201
1202 } else {
1203 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
1204 emitSUB_RegOff_Imm_Byte(
1205 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
1206 getImm(MIR_BinaryAcc.getValue(inst)));
1207
1208 } else {
1209 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
1210 emitSUB_RegIdx_Imm_Byte(
1211 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
1212 getImm(MIR_BinaryAcc.getValue(inst)));
1213
1214 } else {
1215 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1216 emitSUB_RegInd_Imm_Byte(
1217 getBase(MIR_BinaryAcc.getResult(inst)),
1218 getImm(MIR_BinaryAcc.getValue(inst)));
1219 }
1220 }
1221 }
1222 }
1223
1224 } else {
1225 if (isWord(inst)) {
1226 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
1227 emitSUB_Abs_Imm_Word(
1228 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
1229 getImm(MIR_BinaryAcc.getValue(inst)));
1230
1231 } else {
1232 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
1233 emitSUB_RegDisp_Imm_Word(
1234 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
1235 getImm(MIR_BinaryAcc.getValue(inst)));
1236
1237 } else {
1238 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
1239 emitSUB_RegOff_Imm_Word(
1240 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
1241 getImm(MIR_BinaryAcc.getValue(inst)));
1242
1243 } else {
1244 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
1245 emitSUB_RegIdx_Imm_Word(
1246 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
1247 getImm(MIR_BinaryAcc.getValue(inst)));
1248
1249 } else {
1250 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1251 emitSUB_RegInd_Imm_Word(
1252 getBase(MIR_BinaryAcc.getResult(inst)),
1253 getImm(MIR_BinaryAcc.getValue(inst)));
1254 }
1255 }
1256 }
1257 }
1258
1259 } else {
1260 if (isQuad(inst)) {
1261 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
1262 emitSUB_Abs_Imm_Quad(
1263 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
1264 getImm(MIR_BinaryAcc.getValue(inst)));
1265
1266 } else {
1267 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
1268 emitSUB_RegDisp_Imm_Quad(
1269 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
1270 getImm(MIR_BinaryAcc.getValue(inst)));
1271
1272 } else {
1273 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
1274 emitSUB_RegOff_Imm_Quad(
1275 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
1276 getImm(MIR_BinaryAcc.getValue(inst)));
1277
1278 } else {
1279 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
1280 emitSUB_RegIdx_Imm_Quad(
1281 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
1282 getImm(MIR_BinaryAcc.getValue(inst)));
1283
1284 } else {
1285 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1286 emitSUB_RegInd_Imm_Quad(
1287 getBase(MIR_BinaryAcc.getResult(inst)),
1288 getImm(MIR_BinaryAcc.getValue(inst)));
1289 }
1290 }
1291 }
1292 }
1293
1294 } else {
1295 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
1296 emitSUB_Abs_Imm(
1297 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
1298 getImm(MIR_BinaryAcc.getValue(inst)));
1299
1300 } else {
1301 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
1302 emitSUB_RegDisp_Imm(
1303 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
1304 getImm(MIR_BinaryAcc.getValue(inst)));
1305
1306 } else {
1307 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
1308 emitSUB_RegOff_Imm(
1309 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
1310 getImm(MIR_BinaryAcc.getValue(inst)));
1311
1312 } else {
1313 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
1314 emitSUB_RegIdx_Imm(
1315 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
1316 getImm(MIR_BinaryAcc.getValue(inst)));
1317
1318 } else {
1319 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1320 emitSUB_RegInd_Imm(
1321 getBase(MIR_BinaryAcc.getResult(inst)),
1322 getImm(MIR_BinaryAcc.getValue(inst)));
1323 }
1324 }
1325 }
1326 }
1327 }
1328 }
1329 }
1330
1331 } else {
1332 if (isByte(inst)) {
1333 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
1334 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1335 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
1336 emitSUB_Abs_Reg_Byte(
1337 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
1338 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
1339
1340 } else {
1341 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
1342 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1343 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
1344 emitSUB_RegDisp_Reg_Byte(
1345 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
1346 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
1347
1348 } else {
1349 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
1350 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1351 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
1352 emitSUB_RegOff_Reg_Byte(
1353 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
1354 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
1355
1356 } else {
1357 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
1358 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1359 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
1360 emitSUB_RegIdx_Reg_Byte(
1361 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
1362 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
1363
1364 } else {
1365 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1366 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1367 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
1368 emitSUB_RegInd_Reg_Byte(
1369 getBase(MIR_BinaryAcc.getResult(inst)),
1370 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
1371 }
1372 }
1373 }
1374 }
1375
1376 } else {
1377 if (isWord(inst)) {
1378 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
1379 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1380 emitSUB_Abs_Reg_Word(
1381 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
1382 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
1383
1384 } else {
1385 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
1386 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1387 emitSUB_RegDisp_Reg_Word(
1388 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
1389 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
1390
1391 } else {
1392 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
1393 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1394 emitSUB_RegOff_Reg_Word(
1395 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
1396 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
1397
1398 } else {
1399 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
1400 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1401 emitSUB_RegIdx_Reg_Word(
1402 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
1403 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
1404
1405 } else {
1406 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1407 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1408 emitSUB_RegInd_Reg_Word(
1409 getBase(MIR_BinaryAcc.getResult(inst)),
1410 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
1411 }
1412 }
1413 }
1414 }
1415
1416 } else {
1417 if (isQuad(inst)) {
1418 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
1419 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1420 emitSUB_Abs_Reg_Quad(
1421 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
1422 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
1423
1424 } else {
1425 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
1426 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1427 emitSUB_RegDisp_Reg_Quad(
1428 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
1429 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
1430
1431 } else {
1432 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
1433 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1434 emitSUB_RegOff_Reg_Quad(
1435 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
1436 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
1437
1438 } else {
1439 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
1440 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1441 emitSUB_RegIdx_Reg_Quad(
1442 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
1443 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
1444
1445 } else {
1446 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1447 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1448 emitSUB_RegInd_Reg_Quad(
1449 getBase(MIR_BinaryAcc.getResult(inst)),
1450 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
1451 }
1452 }
1453 }
1454 }
1455
1456 } else {
1457 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
1458 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1459 emitSUB_Abs_Reg(
1460 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
1461 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
1462
1463 } else {
1464 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
1465 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1466 emitSUB_RegDisp_Reg(
1467 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
1468 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
1469
1470 } else {
1471 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
1472 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1473 emitSUB_RegOff_Reg(
1474 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
1475 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
1476
1477 } else {
1478 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
1479 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1480 emitSUB_RegIdx_Reg(
1481 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
1482 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
1483
1484 } else {
1485 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1486 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1487 emitSUB_RegInd_Reg(
1488 getBase(MIR_BinaryAcc.getResult(inst)),
1489 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
1490 }
1491 }
1492 }
1493 }
1494 }
1495 }
1496 }
1497 }
1498 }
1499 }
1500
1501 /**
1502 * Emit the given instruction, assuming that
1503 * it is a MIR_BinaryAcc instruction
1504 * and has a CMPEQSD operator
1505 *
1506 * @param inst the instruction to assemble
1507 */
1508 private void doCMPEQSD(Instruction inst) {
1509 if (isXMM_Reg(MIR_BinaryAcc.getValue(inst))) {
1510 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1511 emitCMPEQSD_Reg_Reg(
1512 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
1513 getXMM_Reg(MIR_BinaryAcc.getValue(inst)));
1514
1515 } else {
1516 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
1517 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1518 emitCMPEQSD_Reg_Abs(
1519 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
1520 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
1521
1522 } else {
1523 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
1524 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1525 emitCMPEQSD_Reg_RegDisp(
1526 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
1527 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
1528
1529 } else {
1530 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
1531 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1532 emitCMPEQSD_Reg_RegOff(
1533 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
1534 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
1535
1536 } else {
1537 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
1538 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1539 emitCMPEQSD_Reg_RegIdx(
1540 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
1541 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
1542
1543 } else {
1544 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1545 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1546 emitCMPEQSD_Reg_RegInd(
1547 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
1548 getBase(MIR_BinaryAcc.getValue(inst)));
1549 }
1550 }
1551 }
1552 }
1553 }
1554 }
1555
1556 /**
1557 * Emit the given instruction, assuming that
1558 * it is a MIR_BinaryAcc instruction
1559 * and has a ORPS operator
1560 *
1561 * @param inst the instruction to assemble
1562 */
1563 private void doORPS(Instruction inst) {
1564 if (isXMM_Reg(MIR_BinaryAcc.getValue(inst))) {
1565 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1566 emitORPS_Reg_Reg(
1567 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
1568 getXMM_Reg(MIR_BinaryAcc.getValue(inst)));
1569
1570 } else {
1571 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
1572 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1573 emitORPS_Reg_Abs(
1574 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
1575 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
1576
1577 } else {
1578 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
1579 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1580 emitORPS_Reg_RegDisp(
1581 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
1582 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
1583
1584 } else {
1585 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
1586 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1587 emitORPS_Reg_RegOff(
1588 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
1589 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
1590
1591 } else {
1592 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
1593 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1594 emitORPS_Reg_RegIdx(
1595 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
1596 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
1597
1598 } else {
1599 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1600 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1601 emitORPS_Reg_RegInd(
1602 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
1603 getBase(MIR_BinaryAcc.getValue(inst)));
1604 }
1605 }
1606 }
1607 }
1608 }
1609 }
1610
1611 /**
1612 * Emit the given instruction, assuming that
1613 * it is a MIR_Compare instruction
1614 * and has a CMP operator
1615 *
1616 * @param inst the instruction to assemble
1617 */
1618 private void doCMP(Instruction inst) {
1619 if (isGPR_Reg(MIR_Compare.getVal1(inst))) {
1620 if (isByte(inst)) {
1621 if (isImm(MIR_Compare.getVal2(inst))) {
1622 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_Compare.getVal1(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
1623 emitCMP_Reg_Imm_Byte(
1624 getGPR_Reg(MIR_Compare.getVal1(inst)),
1625 getImm(MIR_Compare.getVal2(inst)));
1626
1627 } else {
1628 if (isGPR_Reg(MIR_Compare.getVal2(inst))) {
1629 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_Compare.getVal1(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
1630 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_Compare.getVal2(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
1631 emitCMP_Reg_Reg_Byte(
1632 getGPR_Reg(MIR_Compare.getVal1(inst)),
1633 getGPR_Reg(MIR_Compare.getVal2(inst)));
1634
1635 } else {
1636 if (isAbs(MIR_Compare.getVal2(inst))) {
1637 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_Compare.getVal1(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
1638 emitCMP_Reg_Abs_Byte(
1639 getGPR_Reg(MIR_Compare.getVal1(inst)),
1640 getDisp(MIR_Compare.getVal2(inst)).toWord().toAddress());
1641
1642 } else {
1643 if (isRegDisp(MIR_Compare.getVal2(inst))) {
1644 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_Compare.getVal1(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
1645 emitCMP_Reg_RegDisp_Byte(
1646 getGPR_Reg(MIR_Compare.getVal1(inst)),
1647 getBase(MIR_Compare.getVal2(inst)), getDisp(MIR_Compare.getVal2(inst)));
1648
1649 } else {
1650 if (isRegOff(MIR_Compare.getVal2(inst))) {
1651 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_Compare.getVal1(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
1652 emitCMP_Reg_RegOff_Byte(
1653 getGPR_Reg(MIR_Compare.getVal1(inst)),
1654 getIndex(MIR_Compare.getVal2(inst)), getScale(MIR_Compare.getVal2(inst)), getDisp(MIR_Compare.getVal2(inst)));
1655
1656 } else {
1657 if (isRegIdx(MIR_Compare.getVal2(inst))) {
1658 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_Compare.getVal1(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
1659 emitCMP_Reg_RegIdx_Byte(
1660 getGPR_Reg(MIR_Compare.getVal1(inst)),
1661 getBase(MIR_Compare.getVal2(inst)), getIndex(MIR_Compare.getVal2(inst)), getScale(MIR_Compare.getVal2(inst)), getDisp(MIR_Compare.getVal2(inst)));
1662
1663 } else {
1664 if (VM.VerifyAssertions && !isRegInd(MIR_Compare.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1665 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_Compare.getVal1(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
1666 emitCMP_Reg_RegInd_Byte(
1667 getGPR_Reg(MIR_Compare.getVal1(inst)),
1668 getBase(MIR_Compare.getVal2(inst)));
1669 }
1670 }
1671 }
1672 }
1673 }
1674 }
1675
1676 } else {
1677 if (isWord(inst)) {
1678 if (isImm(MIR_Compare.getVal2(inst))) {
1679 emitCMP_Reg_Imm_Word(
1680 getGPR_Reg(MIR_Compare.getVal1(inst)),
1681 getImm(MIR_Compare.getVal2(inst)));
1682
1683 } else {
1684 if (isGPR_Reg(MIR_Compare.getVal2(inst))) {
1685 emitCMP_Reg_Reg_Word(
1686 getGPR_Reg(MIR_Compare.getVal1(inst)),
1687 getGPR_Reg(MIR_Compare.getVal2(inst)));
1688
1689 } else {
1690 if (isAbs(MIR_Compare.getVal2(inst))) {
1691 emitCMP_Reg_Abs_Word(
1692 getGPR_Reg(MIR_Compare.getVal1(inst)),
1693 getDisp(MIR_Compare.getVal2(inst)).toWord().toAddress());
1694
1695 } else {
1696 if (isRegDisp(MIR_Compare.getVal2(inst))) {
1697 emitCMP_Reg_RegDisp_Word(
1698 getGPR_Reg(MIR_Compare.getVal1(inst)),
1699 getBase(MIR_Compare.getVal2(inst)), getDisp(MIR_Compare.getVal2(inst)));
1700
1701 } else {
1702 if (isRegOff(MIR_Compare.getVal2(inst))) {
1703 emitCMP_Reg_RegOff_Word(
1704 getGPR_Reg(MIR_Compare.getVal1(inst)),
1705 getIndex(MIR_Compare.getVal2(inst)), getScale(MIR_Compare.getVal2(inst)), getDisp(MIR_Compare.getVal2(inst)));
1706
1707 } else {
1708 if (isRegIdx(MIR_Compare.getVal2(inst))) {
1709 emitCMP_Reg_RegIdx_Word(
1710 getGPR_Reg(MIR_Compare.getVal1(inst)),
1711 getBase(MIR_Compare.getVal2(inst)), getIndex(MIR_Compare.getVal2(inst)), getScale(MIR_Compare.getVal2(inst)), getDisp(MIR_Compare.getVal2(inst)));
1712
1713 } else {
1714 if (VM.VerifyAssertions && !isRegInd(MIR_Compare.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1715 emitCMP_Reg_RegInd_Word(
1716 getGPR_Reg(MIR_Compare.getVal1(inst)),
1717 getBase(MIR_Compare.getVal2(inst)));
1718 }
1719 }
1720 }
1721 }
1722 }
1723 }
1724
1725 } else {
1726 if (isQuad(inst)) {
1727 if (isImm(MIR_Compare.getVal2(inst))) {
1728 emitCMP_Reg_Imm_Quad(
1729 getGPR_Reg(MIR_Compare.getVal1(inst)),
1730 getImm(MIR_Compare.getVal2(inst)));
1731
1732 } else {
1733 if (isGPR_Reg(MIR_Compare.getVal2(inst))) {
1734 emitCMP_Reg_Reg_Quad(
1735 getGPR_Reg(MIR_Compare.getVal1(inst)),
1736 getGPR_Reg(MIR_Compare.getVal2(inst)));
1737
1738 } else {
1739 if (isAbs(MIR_Compare.getVal2(inst))) {
1740 emitCMP_Reg_Abs_Quad(
1741 getGPR_Reg(MIR_Compare.getVal1(inst)),
1742 getDisp(MIR_Compare.getVal2(inst)).toWord().toAddress());
1743
1744 } else {
1745 if (isRegDisp(MIR_Compare.getVal2(inst))) {
1746 emitCMP_Reg_RegDisp_Quad(
1747 getGPR_Reg(MIR_Compare.getVal1(inst)),
1748 getBase(MIR_Compare.getVal2(inst)), getDisp(MIR_Compare.getVal2(inst)));
1749
1750 } else {
1751 if (isRegOff(MIR_Compare.getVal2(inst))) {
1752 emitCMP_Reg_RegOff_Quad(
1753 getGPR_Reg(MIR_Compare.getVal1(inst)),
1754 getIndex(MIR_Compare.getVal2(inst)), getScale(MIR_Compare.getVal2(inst)), getDisp(MIR_Compare.getVal2(inst)));
1755
1756 } else {
1757 if (isRegIdx(MIR_Compare.getVal2(inst))) {
1758 emitCMP_Reg_RegIdx_Quad(
1759 getGPR_Reg(MIR_Compare.getVal1(inst)),
1760 getBase(MIR_Compare.getVal2(inst)), getIndex(MIR_Compare.getVal2(inst)), getScale(MIR_Compare.getVal2(inst)), getDisp(MIR_Compare.getVal2(inst)));
1761
1762 } else {
1763 if (VM.VerifyAssertions && !isRegInd(MIR_Compare.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1764 emitCMP_Reg_RegInd_Quad(
1765 getGPR_Reg(MIR_Compare.getVal1(inst)),
1766 getBase(MIR_Compare.getVal2(inst)));
1767 }
1768 }
1769 }
1770 }
1771 }
1772 }
1773
1774 } else {
1775 if (isImm(MIR_Compare.getVal2(inst))) {
1776 emitCMP_Reg_Imm(
1777 getGPR_Reg(MIR_Compare.getVal1(inst)),
1778 getImm(MIR_Compare.getVal2(inst)));
1779
1780 } else {
1781 if (isGPR_Reg(MIR_Compare.getVal2(inst))) {
1782 emitCMP_Reg_Reg(
1783 getGPR_Reg(MIR_Compare.getVal1(inst)),
1784 getGPR_Reg(MIR_Compare.getVal2(inst)));
1785
1786 } else {
1787 if (isAbs(MIR_Compare.getVal2(inst))) {
1788 emitCMP_Reg_Abs(
1789 getGPR_Reg(MIR_Compare.getVal1(inst)),
1790 getDisp(MIR_Compare.getVal2(inst)).toWord().toAddress());
1791
1792 } else {
1793 if (isRegDisp(MIR_Compare.getVal2(inst))) {
1794 emitCMP_Reg_RegDisp(
1795 getGPR_Reg(MIR_Compare.getVal1(inst)),
1796 getBase(MIR_Compare.getVal2(inst)), getDisp(MIR_Compare.getVal2(inst)));
1797
1798 } else {
1799 if (isRegOff(MIR_Compare.getVal2(inst))) {
1800 emitCMP_Reg_RegOff(
1801 getGPR_Reg(MIR_Compare.getVal1(inst)),
1802 getIndex(MIR_Compare.getVal2(inst)), getScale(MIR_Compare.getVal2(inst)), getDisp(MIR_Compare.getVal2(inst)));
1803
1804 } else {
1805 if (isRegIdx(MIR_Compare.getVal2(inst))) {
1806 emitCMP_Reg_RegIdx(
1807 getGPR_Reg(MIR_Compare.getVal1(inst)),
1808 getBase(MIR_Compare.getVal2(inst)), getIndex(MIR_Compare.getVal2(inst)), getScale(MIR_Compare.getVal2(inst)), getDisp(MIR_Compare.getVal2(inst)));
1809
1810 } else {
1811 if (VM.VerifyAssertions && !isRegInd(MIR_Compare.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1812 emitCMP_Reg_RegInd(
1813 getGPR_Reg(MIR_Compare.getVal1(inst)),
1814 getBase(MIR_Compare.getVal2(inst)));
1815 }
1816 }
1817 }
1818 }
1819 }
1820 }
1821 }
1822 }
1823 }
1824
1825 } else {
1826 if (isImm(MIR_Compare.getVal2(inst))) {
1827 if (isByte(inst)) {
1828 if (isAbs(MIR_Compare.getVal1(inst))) {
1829 emitCMP_Abs_Imm_Byte(
1830 getDisp(MIR_Compare.getVal1(inst)).toWord().toAddress(),
1831 getImm(MIR_Compare.getVal2(inst)));
1832
1833 } else {
1834 if (isRegDisp(MIR_Compare.getVal1(inst))) {
1835 emitCMP_RegDisp_Imm_Byte(
1836 getBase(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
1837 getImm(MIR_Compare.getVal2(inst)));
1838
1839 } else {
1840 if (isRegOff(MIR_Compare.getVal1(inst))) {
1841 emitCMP_RegOff_Imm_Byte(
1842 getIndex(MIR_Compare.getVal1(inst)), getScale(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
1843 getImm(MIR_Compare.getVal2(inst)));
1844
1845 } else {
1846 if (isRegIdx(MIR_Compare.getVal1(inst))) {
1847 emitCMP_RegIdx_Imm_Byte(
1848 getBase(MIR_Compare.getVal1(inst)), getIndex(MIR_Compare.getVal1(inst)), getScale(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
1849 getImm(MIR_Compare.getVal2(inst)));
1850
1851 } else {
1852 if (VM.VerifyAssertions && !isRegInd(MIR_Compare.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1853 emitCMP_RegInd_Imm_Byte(
1854 getBase(MIR_Compare.getVal1(inst)),
1855 getImm(MIR_Compare.getVal2(inst)));
1856 }
1857 }
1858 }
1859 }
1860
1861 } else {
1862 if (isWord(inst)) {
1863 if (isAbs(MIR_Compare.getVal1(inst))) {
1864 emitCMP_Abs_Imm_Word(
1865 getDisp(MIR_Compare.getVal1(inst)).toWord().toAddress(),
1866 getImm(MIR_Compare.getVal2(inst)));
1867
1868 } else {
1869 if (isRegDisp(MIR_Compare.getVal1(inst))) {
1870 emitCMP_RegDisp_Imm_Word(
1871 getBase(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
1872 getImm(MIR_Compare.getVal2(inst)));
1873
1874 } else {
1875 if (isRegOff(MIR_Compare.getVal1(inst))) {
1876 emitCMP_RegOff_Imm_Word(
1877 getIndex(MIR_Compare.getVal1(inst)), getScale(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
1878 getImm(MIR_Compare.getVal2(inst)));
1879
1880 } else {
1881 if (isRegIdx(MIR_Compare.getVal1(inst))) {
1882 emitCMP_RegIdx_Imm_Word(
1883 getBase(MIR_Compare.getVal1(inst)), getIndex(MIR_Compare.getVal1(inst)), getScale(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
1884 getImm(MIR_Compare.getVal2(inst)));
1885
1886 } else {
1887 if (VM.VerifyAssertions && !isRegInd(MIR_Compare.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1888 emitCMP_RegInd_Imm_Word(
1889 getBase(MIR_Compare.getVal1(inst)),
1890 getImm(MIR_Compare.getVal2(inst)));
1891 }
1892 }
1893 }
1894 }
1895
1896 } else {
1897 if (isQuad(inst)) {
1898 if (isAbs(MIR_Compare.getVal1(inst))) {
1899 emitCMP_Abs_Imm_Quad(
1900 getDisp(MIR_Compare.getVal1(inst)).toWord().toAddress(),
1901 getImm(MIR_Compare.getVal2(inst)));
1902
1903 } else {
1904 if (isRegDisp(MIR_Compare.getVal1(inst))) {
1905 emitCMP_RegDisp_Imm_Quad(
1906 getBase(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
1907 getImm(MIR_Compare.getVal2(inst)));
1908
1909 } else {
1910 if (isRegOff(MIR_Compare.getVal1(inst))) {
1911 emitCMP_RegOff_Imm_Quad(
1912 getIndex(MIR_Compare.getVal1(inst)), getScale(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
1913 getImm(MIR_Compare.getVal2(inst)));
1914
1915 } else {
1916 if (isRegIdx(MIR_Compare.getVal1(inst))) {
1917 emitCMP_RegIdx_Imm_Quad(
1918 getBase(MIR_Compare.getVal1(inst)), getIndex(MIR_Compare.getVal1(inst)), getScale(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
1919 getImm(MIR_Compare.getVal2(inst)));
1920
1921 } else {
1922 if (VM.VerifyAssertions && !isRegInd(MIR_Compare.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1923 emitCMP_RegInd_Imm_Quad(
1924 getBase(MIR_Compare.getVal1(inst)),
1925 getImm(MIR_Compare.getVal2(inst)));
1926 }
1927 }
1928 }
1929 }
1930
1931 } else {
1932 if (isAbs(MIR_Compare.getVal1(inst))) {
1933 emitCMP_Abs_Imm(
1934 getDisp(MIR_Compare.getVal1(inst)).toWord().toAddress(),
1935 getImm(MIR_Compare.getVal2(inst)));
1936
1937 } else {
1938 if (isRegDisp(MIR_Compare.getVal1(inst))) {
1939 emitCMP_RegDisp_Imm(
1940 getBase(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
1941 getImm(MIR_Compare.getVal2(inst)));
1942
1943 } else {
1944 if (isRegOff(MIR_Compare.getVal1(inst))) {
1945 emitCMP_RegOff_Imm(
1946 getIndex(MIR_Compare.getVal1(inst)), getScale(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
1947 getImm(MIR_Compare.getVal2(inst)));
1948
1949 } else {
1950 if (isRegIdx(MIR_Compare.getVal1(inst))) {
1951 emitCMP_RegIdx_Imm(
1952 getBase(MIR_Compare.getVal1(inst)), getIndex(MIR_Compare.getVal1(inst)), getScale(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
1953 getImm(MIR_Compare.getVal2(inst)));
1954
1955 } else {
1956 if (VM.VerifyAssertions && !isRegInd(MIR_Compare.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1957 emitCMP_RegInd_Imm(
1958 getBase(MIR_Compare.getVal1(inst)),
1959 getImm(MIR_Compare.getVal2(inst)));
1960 }
1961 }
1962 }
1963 }
1964 }
1965 }
1966 }
1967
1968 } else {
1969 if (isByte(inst)) {
1970 if (isAbs(MIR_Compare.getVal1(inst))) {
1971 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Compare.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1972 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_Compare.getVal2(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
1973 emitCMP_Abs_Reg_Byte(
1974 getDisp(MIR_Compare.getVal1(inst)).toWord().toAddress(),
1975 getGPR_Reg(MIR_Compare.getVal2(inst)));
1976
1977 } else {
1978 if (isRegDisp(MIR_Compare.getVal1(inst))) {
1979 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Compare.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1980 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_Compare.getVal2(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
1981 emitCMP_RegDisp_Reg_Byte(
1982 getBase(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
1983 getGPR_Reg(MIR_Compare.getVal2(inst)));
1984
1985 } else {
1986 if (isRegOff(MIR_Compare.getVal1(inst))) {
1987 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Compare.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1988 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_Compare.getVal2(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
1989 emitCMP_RegOff_Reg_Byte(
1990 getIndex(MIR_Compare.getVal1(inst)), getScale(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
1991 getGPR_Reg(MIR_Compare.getVal2(inst)));
1992
1993 } else {
1994 if (isRegIdx(MIR_Compare.getVal1(inst))) {
1995 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Compare.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
1996 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_Compare.getVal2(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
1997 emitCMP_RegIdx_Reg_Byte(
1998 getBase(MIR_Compare.getVal1(inst)), getIndex(MIR_Compare.getVal1(inst)), getScale(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
1999 getGPR_Reg(MIR_Compare.getVal2(inst)));
2000
2001 } else {
2002 if (VM.VerifyAssertions && !isRegInd(MIR_Compare.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2003 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Compare.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2004 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_Compare.getVal2(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
2005 emitCMP_RegInd_Reg_Byte(
2006 getBase(MIR_Compare.getVal1(inst)),
2007 getGPR_Reg(MIR_Compare.getVal2(inst)));
2008 }
2009 }
2010 }
2011 }
2012
2013 } else {
2014 if (isWord(inst)) {
2015 if (isAbs(MIR_Compare.getVal1(inst))) {
2016 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Compare.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2017 emitCMP_Abs_Reg_Word(
2018 getDisp(MIR_Compare.getVal1(inst)).toWord().toAddress(),
2019 getGPR_Reg(MIR_Compare.getVal2(inst)));
2020
2021 } else {
2022 if (isRegDisp(MIR_Compare.getVal1(inst))) {
2023 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Compare.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2024 emitCMP_RegDisp_Reg_Word(
2025 getBase(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
2026 getGPR_Reg(MIR_Compare.getVal2(inst)));
2027
2028 } else {
2029 if (isRegOff(MIR_Compare.getVal1(inst))) {
2030 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Compare.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2031 emitCMP_RegOff_Reg_Word(
2032 getIndex(MIR_Compare.getVal1(inst)), getScale(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
2033 getGPR_Reg(MIR_Compare.getVal2(inst)));
2034
2035 } else {
2036 if (isRegIdx(MIR_Compare.getVal1(inst))) {
2037 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Compare.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2038 emitCMP_RegIdx_Reg_Word(
2039 getBase(MIR_Compare.getVal1(inst)), getIndex(MIR_Compare.getVal1(inst)), getScale(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
2040 getGPR_Reg(MIR_Compare.getVal2(inst)));
2041
2042 } else {
2043 if (VM.VerifyAssertions && !isRegInd(MIR_Compare.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2044 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Compare.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2045 emitCMP_RegInd_Reg_Word(
2046 getBase(MIR_Compare.getVal1(inst)),
2047 getGPR_Reg(MIR_Compare.getVal2(inst)));
2048 }
2049 }
2050 }
2051 }
2052
2053 } else {
2054 if (isQuad(inst)) {
2055 if (isAbs(MIR_Compare.getVal1(inst))) {
2056 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Compare.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2057 emitCMP_Abs_Reg_Quad(
2058 getDisp(MIR_Compare.getVal1(inst)).toWord().toAddress(),
2059 getGPR_Reg(MIR_Compare.getVal2(inst)));
2060
2061 } else {
2062 if (isRegDisp(MIR_Compare.getVal1(inst))) {
2063 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Compare.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2064 emitCMP_RegDisp_Reg_Quad(
2065 getBase(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
2066 getGPR_Reg(MIR_Compare.getVal2(inst)));
2067
2068 } else {
2069 if (isRegOff(MIR_Compare.getVal1(inst))) {
2070 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Compare.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2071 emitCMP_RegOff_Reg_Quad(
2072 getIndex(MIR_Compare.getVal1(inst)), getScale(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
2073 getGPR_Reg(MIR_Compare.getVal2(inst)));
2074
2075 } else {
2076 if (isRegIdx(MIR_Compare.getVal1(inst))) {
2077 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Compare.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2078 emitCMP_RegIdx_Reg_Quad(
2079 getBase(MIR_Compare.getVal1(inst)), getIndex(MIR_Compare.getVal1(inst)), getScale(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
2080 getGPR_Reg(MIR_Compare.getVal2(inst)));
2081
2082 } else {
2083 if (VM.VerifyAssertions && !isRegInd(MIR_Compare.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2084 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Compare.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2085 emitCMP_RegInd_Reg_Quad(
2086 getBase(MIR_Compare.getVal1(inst)),
2087 getGPR_Reg(MIR_Compare.getVal2(inst)));
2088 }
2089 }
2090 }
2091 }
2092
2093 } else {
2094 if (isAbs(MIR_Compare.getVal1(inst))) {
2095 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Compare.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2096 emitCMP_Abs_Reg(
2097 getDisp(MIR_Compare.getVal1(inst)).toWord().toAddress(),
2098 getGPR_Reg(MIR_Compare.getVal2(inst)));
2099
2100 } else {
2101 if (isRegDisp(MIR_Compare.getVal1(inst))) {
2102 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Compare.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2103 emitCMP_RegDisp_Reg(
2104 getBase(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
2105 getGPR_Reg(MIR_Compare.getVal2(inst)));
2106
2107 } else {
2108 if (isRegOff(MIR_Compare.getVal1(inst))) {
2109 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Compare.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2110 emitCMP_RegOff_Reg(
2111 getIndex(MIR_Compare.getVal1(inst)), getScale(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
2112 getGPR_Reg(MIR_Compare.getVal2(inst)));
2113
2114 } else {
2115 if (isRegIdx(MIR_Compare.getVal1(inst))) {
2116 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Compare.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2117 emitCMP_RegIdx_Reg(
2118 getBase(MIR_Compare.getVal1(inst)), getIndex(MIR_Compare.getVal1(inst)), getScale(MIR_Compare.getVal1(inst)), getDisp(MIR_Compare.getVal1(inst)),
2119 getGPR_Reg(MIR_Compare.getVal2(inst)));
2120
2121 } else {
2122 if (VM.VerifyAssertions && !isRegInd(MIR_Compare.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2123 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Compare.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2124 emitCMP_RegInd_Reg(
2125 getBase(MIR_Compare.getVal1(inst)),
2126 getGPR_Reg(MIR_Compare.getVal2(inst)));
2127 }
2128 }
2129 }
2130 }
2131 }
2132 }
2133 }
2134 }
2135 }
2136 }
2137
2138 /**
2139 * Emit the given instruction, assuming that
2140 * it is a MIR_Move instruction
2141 * and has a FST operator
2142 *
2143 * @param inst the instruction to assemble
2144 */
2145 private void doFST(Instruction inst) {
2146 if (isQuad(inst)) {
2147 if (isAbs(MIR_Move.getResult(inst))) {
2148 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2149 emitFST_Abs_Reg_Quad(
2150 getDisp(MIR_Move.getResult(inst)).toWord().toAddress(),
2151 getFPR_Reg(MIR_Move.getValue(inst)));
2152
2153 } else {
2154 if (isRegDisp(MIR_Move.getResult(inst))) {
2155 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2156 emitFST_RegDisp_Reg_Quad(
2157 getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
2158 getFPR_Reg(MIR_Move.getValue(inst)));
2159
2160 } else {
2161 if (isRegOff(MIR_Move.getResult(inst))) {
2162 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2163 emitFST_RegOff_Reg_Quad(
2164 getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
2165 getFPR_Reg(MIR_Move.getValue(inst)));
2166
2167 } else {
2168 if (isRegIdx(MIR_Move.getResult(inst))) {
2169 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2170 emitFST_RegIdx_Reg_Quad(
2171 getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
2172 getFPR_Reg(MIR_Move.getValue(inst)));
2173
2174 } else {
2175 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2176 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2177 emitFST_RegInd_Reg_Quad(
2178 getBase(MIR_Move.getResult(inst)),
2179 getFPR_Reg(MIR_Move.getValue(inst)));
2180 }
2181 }
2182 }
2183 }
2184
2185 } else {
2186 if (isFPR_Reg(MIR_Move.getResult(inst))) {
2187 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2188 emitFST_Reg_Reg(
2189 getFPR_Reg(MIR_Move.getResult(inst)),
2190 getFPR_Reg(MIR_Move.getValue(inst)));
2191
2192 } else {
2193 if (isAbs(MIR_Move.getResult(inst))) {
2194 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2195 emitFST_Abs_Reg(
2196 getDisp(MIR_Move.getResult(inst)).toWord().toAddress(),
2197 getFPR_Reg(MIR_Move.getValue(inst)));
2198
2199 } else {
2200 if (isRegDisp(MIR_Move.getResult(inst))) {
2201 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2202 emitFST_RegDisp_Reg(
2203 getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
2204 getFPR_Reg(MIR_Move.getValue(inst)));
2205
2206 } else {
2207 if (isRegOff(MIR_Move.getResult(inst))) {
2208 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2209 emitFST_RegOff_Reg(
2210 getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
2211 getFPR_Reg(MIR_Move.getValue(inst)));
2212
2213 } else {
2214 if (isRegIdx(MIR_Move.getResult(inst))) {
2215 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2216 emitFST_RegIdx_Reg(
2217 getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
2218 getFPR_Reg(MIR_Move.getValue(inst)));
2219
2220 } else {
2221 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2222 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2223 emitFST_RegInd_Reg(
2224 getBase(MIR_Move.getResult(inst)),
2225 getFPR_Reg(MIR_Move.getValue(inst)));
2226 }
2227 }
2228 }
2229 }
2230 }
2231 }
2232 }
2233
2234 /**
2235 * Emit the given instruction, assuming that
2236 * it is a MIR_Test instruction
2237 * and has a BTC operator
2238 *
2239 * @param inst the instruction to assemble
2240 */
2241 private void doBTC(Instruction inst) {
2242 if (isImm(MIR_Test.getVal2(inst))) {
2243 if (isGPR_Reg(MIR_Test.getVal1(inst))) {
2244 emitBTC_Reg_Imm(
2245 getGPR_Reg(MIR_Test.getVal1(inst)),
2246 getImm(MIR_Test.getVal2(inst)));
2247
2248 } else {
2249 if (isAbs(MIR_Test.getVal1(inst))) {
2250 emitBTC_Abs_Imm(
2251 getDisp(MIR_Test.getVal1(inst)).toWord().toAddress(),
2252 getImm(MIR_Test.getVal2(inst)));
2253
2254 } else {
2255 if (isRegDisp(MIR_Test.getVal1(inst))) {
2256 emitBTC_RegDisp_Imm(
2257 getBase(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
2258 getImm(MIR_Test.getVal2(inst)));
2259
2260 } else {
2261 if (isRegOff(MIR_Test.getVal1(inst))) {
2262 emitBTC_RegOff_Imm(
2263 getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
2264 getImm(MIR_Test.getVal2(inst)));
2265
2266 } else {
2267 if (isRegIdx(MIR_Test.getVal1(inst))) {
2268 emitBTC_RegIdx_Imm(
2269 getBase(MIR_Test.getVal1(inst)), getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
2270 getImm(MIR_Test.getVal2(inst)));
2271
2272 } else {
2273 if (VM.VerifyAssertions && !isRegInd(MIR_Test.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2274 emitBTC_RegInd_Imm(
2275 getBase(MIR_Test.getVal1(inst)),
2276 getImm(MIR_Test.getVal2(inst)));
2277 }
2278 }
2279 }
2280 }
2281 }
2282
2283 } else {
2284 if (isGPR_Reg(MIR_Test.getVal1(inst))) {
2285 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2286 emitBTC_Reg_Reg(
2287 getGPR_Reg(MIR_Test.getVal1(inst)),
2288 getGPR_Reg(MIR_Test.getVal2(inst)));
2289
2290 } else {
2291 if (isAbs(MIR_Test.getVal1(inst))) {
2292 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2293 emitBTC_Abs_Reg(
2294 getDisp(MIR_Test.getVal1(inst)).toWord().toAddress(),
2295 getGPR_Reg(MIR_Test.getVal2(inst)));
2296
2297 } else {
2298 if (isRegDisp(MIR_Test.getVal1(inst))) {
2299 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2300 emitBTC_RegDisp_Reg(
2301 getBase(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
2302 getGPR_Reg(MIR_Test.getVal2(inst)));
2303
2304 } else {
2305 if (isRegOff(MIR_Test.getVal1(inst))) {
2306 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2307 emitBTC_RegOff_Reg(
2308 getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
2309 getGPR_Reg(MIR_Test.getVal2(inst)));
2310
2311 } else {
2312 if (isRegIdx(MIR_Test.getVal1(inst))) {
2313 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2314 emitBTC_RegIdx_Reg(
2315 getBase(MIR_Test.getVal1(inst)), getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
2316 getGPR_Reg(MIR_Test.getVal2(inst)));
2317
2318 } else {
2319 if (VM.VerifyAssertions && !isRegInd(MIR_Test.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2320 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2321 emitBTC_RegInd_Reg(
2322 getBase(MIR_Test.getVal1(inst)),
2323 getGPR_Reg(MIR_Test.getVal2(inst)));
2324 }
2325 }
2326 }
2327 }
2328 }
2329 }
2330 }
2331
2332 /**
2333 * Emit the given instruction, assuming that
2334 * it is a MIR_Nullary instruction
2335 * and has a POP operator
2336 *
2337 * @param inst the instruction to assemble
2338 */
2339 private void doPOP(Instruction inst) {
2340 if (isGPR_Reg(MIR_Nullary.getResult(inst))) {
2341 emitPOP_Reg(
2342 getGPR_Reg(MIR_Nullary.getResult(inst)));
2343
2344 } else {
2345 if (isAbs(MIR_Nullary.getResult(inst))) {
2346 emitPOP_Abs(
2347 getDisp(MIR_Nullary.getResult(inst)).toWord().toAddress());
2348
2349 } else {
2350 if (isRegDisp(MIR_Nullary.getResult(inst))) {
2351 emitPOP_RegDisp(
2352 getBase(MIR_Nullary.getResult(inst)), getDisp(MIR_Nullary.getResult(inst)));
2353
2354 } else {
2355 if (isRegOff(MIR_Nullary.getResult(inst))) {
2356 emitPOP_RegOff(
2357 getIndex(MIR_Nullary.getResult(inst)), getScale(MIR_Nullary.getResult(inst)), getDisp(MIR_Nullary.getResult(inst)));
2358
2359 } else {
2360 if (isRegIdx(MIR_Nullary.getResult(inst))) {
2361 emitPOP_RegIdx(
2362 getBase(MIR_Nullary.getResult(inst)), getIndex(MIR_Nullary.getResult(inst)), getScale(MIR_Nullary.getResult(inst)), getDisp(MIR_Nullary.getResult(inst)));
2363
2364 } else {
2365 if (VM.VerifyAssertions && !isRegInd(MIR_Nullary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2366 emitPOP_RegInd(
2367 getBase(MIR_Nullary.getResult(inst)));
2368 }
2369 }
2370 }
2371 }
2372 }
2373 }
2374
2375 /**
2376 * Emit the given instruction, assuming that
2377 * it is a MIR_UnaryNoRes instruction
2378 * and has a FLDCW operator
2379 *
2380 * @param inst the instruction to assemble
2381 */
2382 private void doFLDCW(Instruction inst) {
2383 if (isAbs(MIR_UnaryNoRes.getVal(inst))) {
2384 emitFLDCW_Abs(
2385 getDisp(MIR_UnaryNoRes.getVal(inst)).toWord().toAddress());
2386
2387 } else {
2388 if (isRegDisp(MIR_UnaryNoRes.getVal(inst))) {
2389 emitFLDCW_RegDisp(
2390 getBase(MIR_UnaryNoRes.getVal(inst)), getDisp(MIR_UnaryNoRes.getVal(inst)));
2391
2392 } else {
2393 if (isRegOff(MIR_UnaryNoRes.getVal(inst))) {
2394 emitFLDCW_RegOff(
2395 getIndex(MIR_UnaryNoRes.getVal(inst)), getScale(MIR_UnaryNoRes.getVal(inst)), getDisp(MIR_UnaryNoRes.getVal(inst)));
2396
2397 } else {
2398 if (isRegIdx(MIR_UnaryNoRes.getVal(inst))) {
2399 emitFLDCW_RegIdx(
2400 getBase(MIR_UnaryNoRes.getVal(inst)), getIndex(MIR_UnaryNoRes.getVal(inst)), getScale(MIR_UnaryNoRes.getVal(inst)), getDisp(MIR_UnaryNoRes.getVal(inst)));
2401
2402 } else {
2403 if (VM.VerifyAssertions && !isRegInd(MIR_UnaryNoRes.getVal(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2404 emitFLDCW_RegInd(
2405 getBase(MIR_UnaryNoRes.getVal(inst)));
2406 }
2407 }
2408 }
2409 }
2410 }
2411
2412 /**
2413 * Emit the given instruction, assuming that
2414 * it is a MIR_RDTSC instruction
2415 * and has a RDTSC operator
2416 *
2417 * @param inst the instruction to assemble
2418 */
2419 private void doRDTSC(Instruction inst) {
2420 emitRDTSC();
2421 }
2422
2423 /**
2424 * Emit the given instruction, assuming that
2425 * it is a MIR_Unary instruction
2426 * and has a MOVZX operator
2427 *
2428 * @param inst the instruction to assemble
2429 */
2430 private void doMOVZX(Instruction inst) {
2431 if (isByte(inst)) {
2432 if (isGPR_Reg(MIR_Unary.getVal(inst))) {
2433 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2434 emitMOVZX_Reg_Reg_Byte(
2435 getGPR_Reg(MIR_Unary.getResult(inst)),
2436 getGPR_Reg(MIR_Unary.getVal(inst)));
2437
2438 } else {
2439 if (isAbs(MIR_Unary.getVal(inst))) {
2440 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2441 emitMOVZX_Reg_Abs_Byte(
2442 getGPR_Reg(MIR_Unary.getResult(inst)),
2443 getDisp(MIR_Unary.getVal(inst)).toWord().toAddress());
2444
2445 } else {
2446 if (isRegDisp(MIR_Unary.getVal(inst))) {
2447 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2448 emitMOVZX_Reg_RegDisp_Byte(
2449 getGPR_Reg(MIR_Unary.getResult(inst)),
2450 getBase(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
2451
2452 } else {
2453 if (isRegOff(MIR_Unary.getVal(inst))) {
2454 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2455 emitMOVZX_Reg_RegOff_Byte(
2456 getGPR_Reg(MIR_Unary.getResult(inst)),
2457 getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
2458
2459 } else {
2460 if (isRegIdx(MIR_Unary.getVal(inst))) {
2461 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2462 emitMOVZX_Reg_RegIdx_Byte(
2463 getGPR_Reg(MIR_Unary.getResult(inst)),
2464 getBase(MIR_Unary.getVal(inst)), getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
2465
2466 } else {
2467 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2468 if (VM.VerifyAssertions && !isRegInd(MIR_Unary.getVal(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2469 emitMOVZX_Reg_RegInd_Byte(
2470 getGPR_Reg(MIR_Unary.getResult(inst)),
2471 getBase(MIR_Unary.getVal(inst)));
2472 }
2473 }
2474 }
2475 }
2476 }
2477
2478 } else {
2479 if (isGPR_Reg(MIR_Unary.getVal(inst))) {
2480 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2481 if (VM.VerifyAssertions && !isWord(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
2482 emitMOVZX_Reg_Reg_Word(
2483 getGPR_Reg(MIR_Unary.getResult(inst)),
2484 getGPR_Reg(MIR_Unary.getVal(inst)));
2485
2486 } else {
2487 if (isAbs(MIR_Unary.getVal(inst))) {
2488 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2489 if (VM.VerifyAssertions && !isWord(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
2490 emitMOVZX_Reg_Abs_Word(
2491 getGPR_Reg(MIR_Unary.getResult(inst)),
2492 getDisp(MIR_Unary.getVal(inst)).toWord().toAddress());
2493
2494 } else {
2495 if (isRegDisp(MIR_Unary.getVal(inst))) {
2496 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2497 if (VM.VerifyAssertions && !isWord(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
2498 emitMOVZX_Reg_RegDisp_Word(
2499 getGPR_Reg(MIR_Unary.getResult(inst)),
2500 getBase(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
2501
2502 } else {
2503 if (isRegOff(MIR_Unary.getVal(inst))) {
2504 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2505 if (VM.VerifyAssertions && !isWord(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
2506 emitMOVZX_Reg_RegOff_Word(
2507 getGPR_Reg(MIR_Unary.getResult(inst)),
2508 getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
2509
2510 } else {
2511 if (isRegIdx(MIR_Unary.getVal(inst))) {
2512 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2513 if (VM.VerifyAssertions && !isWord(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
2514 emitMOVZX_Reg_RegIdx_Word(
2515 getGPR_Reg(MIR_Unary.getResult(inst)),
2516 getBase(MIR_Unary.getVal(inst)), getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
2517
2518 } else {
2519 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2520 if (VM.VerifyAssertions && !isRegInd(MIR_Unary.getVal(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2521 if (VM.VerifyAssertions && !isWord(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
2522 emitMOVZX_Reg_RegInd_Word(
2523 getGPR_Reg(MIR_Unary.getResult(inst)),
2524 getBase(MIR_Unary.getVal(inst)));
2525 }
2526 }
2527 }
2528 }
2529 }
2530 }
2531 }
2532
2533 /**
2534 * Emit the given instruction, assuming that
2535 * it is a MIR_BinaryAcc instruction
2536 * and has a CMPEQSS operator
2537 *
2538 * @param inst the instruction to assemble
2539 */
2540 private void doCMPEQSS(Instruction inst) {
2541 if (isXMM_Reg(MIR_BinaryAcc.getValue(inst))) {
2542 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2543 emitCMPEQSS_Reg_Reg(
2544 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
2545 getXMM_Reg(MIR_BinaryAcc.getValue(inst)));
2546
2547 } else {
2548 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
2549 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2550 emitCMPEQSS_Reg_Abs(
2551 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
2552 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
2553
2554 } else {
2555 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
2556 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2557 emitCMPEQSS_Reg_RegDisp(
2558 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
2559 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
2560
2561 } else {
2562 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
2563 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2564 emitCMPEQSS_Reg_RegOff(
2565 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
2566 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
2567
2568 } else {
2569 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
2570 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2571 emitCMPEQSS_Reg_RegIdx(
2572 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
2573 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
2574
2575 } else {
2576 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2577 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2578 emitCMPEQSS_Reg_RegInd(
2579 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
2580 getBase(MIR_BinaryAcc.getValue(inst)));
2581 }
2582 }
2583 }
2584 }
2585 }
2586 }
2587
2588 /**
2589 * Emit the given instruction, assuming that
2590 * it is a MIR_BinaryAcc instruction
2591 * and has a FADDP operator
2592 *
2593 * @param inst the instruction to assemble
2594 */
2595 private void doFADDP(Instruction inst) {
2596 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2597 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2598 emitFADDP_Reg_Reg(
2599 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
2600 getFPR_Reg(MIR_BinaryAcc.getValue(inst)));
2601 }
2602
2603 /**
2604 * Emit the given instruction, assuming that
2605 * it is a MIR_ConvertDW2QW instruction
2606 * and has a CDQE operator
2607 *
2608 * @param inst the instruction to assemble
2609 */
2610 private void doCDQE(Instruction inst) {
2611 emitCDQE();
2612 }
2613
2614 /**
2615 * Emit the given instruction, assuming that
2616 * it is a MIR_BinaryAcc instruction
2617 * and has a XOR operator
2618 *
2619 * @param inst the instruction to assemble
2620 */
2621 private void doXOR(Instruction inst) {
2622 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
2623 if (isByte(inst)) {
2624 if (isImm(MIR_BinaryAcc.getValue(inst))) {
2625 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
2626 emitXOR_Reg_Imm_Byte(
2627 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
2628 getImm(MIR_BinaryAcc.getValue(inst)));
2629
2630 } else {
2631 if (isGPR_Reg(MIR_BinaryAcc.getValue(inst))) {
2632 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
2633 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
2634 emitXOR_Reg_Reg_Byte(
2635 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
2636 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
2637
2638 } else {
2639 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
2640 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
2641 emitXOR_Reg_Abs_Byte(
2642 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
2643 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
2644
2645 } else {
2646 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
2647 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
2648 emitXOR_Reg_RegDisp_Byte(
2649 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
2650 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
2651
2652 } else {
2653 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
2654 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
2655 emitXOR_Reg_RegOff_Byte(
2656 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
2657 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
2658
2659 } else {
2660 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
2661 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
2662 emitXOR_Reg_RegIdx_Byte(
2663 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
2664 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
2665
2666 } else {
2667 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2668 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
2669 emitXOR_Reg_RegInd_Byte(
2670 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
2671 getBase(MIR_BinaryAcc.getValue(inst)));
2672 }
2673 }
2674 }
2675 }
2676 }
2677 }
2678
2679 } else {
2680 if (isWord(inst)) {
2681 if (isImm(MIR_BinaryAcc.getValue(inst))) {
2682 emitXOR_Reg_Imm_Word(
2683 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
2684 getImm(MIR_BinaryAcc.getValue(inst)));
2685
2686 } else {
2687 if (isGPR_Reg(MIR_BinaryAcc.getValue(inst))) {
2688 emitXOR_Reg_Reg_Word(
2689 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
2690 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
2691
2692 } else {
2693 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
2694 emitXOR_Reg_Abs_Word(
2695 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
2696 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
2697
2698 } else {
2699 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
2700 emitXOR_Reg_RegDisp_Word(
2701 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
2702 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
2703
2704 } else {
2705 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
2706 emitXOR_Reg_RegOff_Word(
2707 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
2708 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
2709
2710 } else {
2711 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
2712 emitXOR_Reg_RegIdx_Word(
2713 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
2714 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
2715
2716 } else {
2717 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2718 emitXOR_Reg_RegInd_Word(
2719 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
2720 getBase(MIR_BinaryAcc.getValue(inst)));
2721 }
2722 }
2723 }
2724 }
2725 }
2726 }
2727
2728 } else {
2729 if (isQuad(inst)) {
2730 if (isImm(MIR_BinaryAcc.getValue(inst))) {
2731 emitXOR_Reg_Imm_Quad(
2732 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
2733 getImm(MIR_BinaryAcc.getValue(inst)));
2734
2735 } else {
2736 if (isGPR_Reg(MIR_BinaryAcc.getValue(inst))) {
2737 emitXOR_Reg_Reg_Quad(
2738 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
2739 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
2740
2741 } else {
2742 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
2743 emitXOR_Reg_Abs_Quad(
2744 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
2745 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
2746
2747 } else {
2748 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
2749 emitXOR_Reg_RegDisp_Quad(
2750 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
2751 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
2752
2753 } else {
2754 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
2755 emitXOR_Reg_RegOff_Quad(
2756 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
2757 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
2758
2759 } else {
2760 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
2761 emitXOR_Reg_RegIdx_Quad(
2762 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
2763 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
2764
2765 } else {
2766 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2767 emitXOR_Reg_RegInd_Quad(
2768 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
2769 getBase(MIR_BinaryAcc.getValue(inst)));
2770 }
2771 }
2772 }
2773 }
2774 }
2775 }
2776
2777 } else {
2778 if (isImm(MIR_BinaryAcc.getValue(inst))) {
2779 emitXOR_Reg_Imm(
2780 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
2781 getImm(MIR_BinaryAcc.getValue(inst)));
2782
2783 } else {
2784 if (isGPR_Reg(MIR_BinaryAcc.getValue(inst))) {
2785 emitXOR_Reg_Reg(
2786 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
2787 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
2788
2789 } else {
2790 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
2791 emitXOR_Reg_Abs(
2792 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
2793 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
2794
2795 } else {
2796 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
2797 emitXOR_Reg_RegDisp(
2798 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
2799 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
2800
2801 } else {
2802 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
2803 emitXOR_Reg_RegOff(
2804 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
2805 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
2806
2807 } else {
2808 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
2809 emitXOR_Reg_RegIdx(
2810 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
2811 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
2812
2813 } else {
2814 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2815 emitXOR_Reg_RegInd(
2816 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
2817 getBase(MIR_BinaryAcc.getValue(inst)));
2818 }
2819 }
2820 }
2821 }
2822 }
2823 }
2824 }
2825 }
2826 }
2827
2828 } else {
2829 if (isImm(MIR_BinaryAcc.getValue(inst))) {
2830 if (isByte(inst)) {
2831 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
2832 emitXOR_Abs_Imm_Byte(
2833 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
2834 getImm(MIR_BinaryAcc.getValue(inst)));
2835
2836 } else {
2837 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
2838 emitXOR_RegDisp_Imm_Byte(
2839 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
2840 getImm(MIR_BinaryAcc.getValue(inst)));
2841
2842 } else {
2843 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
2844 emitXOR_RegOff_Imm_Byte(
2845 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
2846 getImm(MIR_BinaryAcc.getValue(inst)));
2847
2848 } else {
2849 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
2850 emitXOR_RegIdx_Imm_Byte(
2851 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
2852 getImm(MIR_BinaryAcc.getValue(inst)));
2853
2854 } else {
2855 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2856 emitXOR_RegInd_Imm_Byte(
2857 getBase(MIR_BinaryAcc.getResult(inst)),
2858 getImm(MIR_BinaryAcc.getValue(inst)));
2859 }
2860 }
2861 }
2862 }
2863
2864 } else {
2865 if (isWord(inst)) {
2866 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
2867 emitXOR_Abs_Imm_Word(
2868 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
2869 getImm(MIR_BinaryAcc.getValue(inst)));
2870
2871 } else {
2872 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
2873 emitXOR_RegDisp_Imm_Word(
2874 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
2875 getImm(MIR_BinaryAcc.getValue(inst)));
2876
2877 } else {
2878 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
2879 emitXOR_RegOff_Imm_Word(
2880 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
2881 getImm(MIR_BinaryAcc.getValue(inst)));
2882
2883 } else {
2884 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
2885 emitXOR_RegIdx_Imm_Word(
2886 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
2887 getImm(MIR_BinaryAcc.getValue(inst)));
2888
2889 } else {
2890 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2891 emitXOR_RegInd_Imm_Word(
2892 getBase(MIR_BinaryAcc.getResult(inst)),
2893 getImm(MIR_BinaryAcc.getValue(inst)));
2894 }
2895 }
2896 }
2897 }
2898
2899 } else {
2900 if (isQuad(inst)) {
2901 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
2902 emitXOR_Abs_Imm_Quad(
2903 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
2904 getImm(MIR_BinaryAcc.getValue(inst)));
2905
2906 } else {
2907 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
2908 emitXOR_RegDisp_Imm_Quad(
2909 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
2910 getImm(MIR_BinaryAcc.getValue(inst)));
2911
2912 } else {
2913 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
2914 emitXOR_RegOff_Imm_Quad(
2915 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
2916 getImm(MIR_BinaryAcc.getValue(inst)));
2917
2918 } else {
2919 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
2920 emitXOR_RegIdx_Imm_Quad(
2921 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
2922 getImm(MIR_BinaryAcc.getValue(inst)));
2923
2924 } else {
2925 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2926 emitXOR_RegInd_Imm_Quad(
2927 getBase(MIR_BinaryAcc.getResult(inst)),
2928 getImm(MIR_BinaryAcc.getValue(inst)));
2929 }
2930 }
2931 }
2932 }
2933
2934 } else {
2935 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
2936 emitXOR_Abs_Imm(
2937 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
2938 getImm(MIR_BinaryAcc.getValue(inst)));
2939
2940 } else {
2941 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
2942 emitXOR_RegDisp_Imm(
2943 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
2944 getImm(MIR_BinaryAcc.getValue(inst)));
2945
2946 } else {
2947 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
2948 emitXOR_RegOff_Imm(
2949 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
2950 getImm(MIR_BinaryAcc.getValue(inst)));
2951
2952 } else {
2953 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
2954 emitXOR_RegIdx_Imm(
2955 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
2956 getImm(MIR_BinaryAcc.getValue(inst)));
2957
2958 } else {
2959 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2960 emitXOR_RegInd_Imm(
2961 getBase(MIR_BinaryAcc.getResult(inst)),
2962 getImm(MIR_BinaryAcc.getValue(inst)));
2963 }
2964 }
2965 }
2966 }
2967 }
2968 }
2969 }
2970
2971 } else {
2972 if (isByte(inst)) {
2973 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
2974 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2975 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
2976 emitXOR_Abs_Reg_Byte(
2977 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
2978 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
2979
2980 } else {
2981 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
2982 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2983 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
2984 emitXOR_RegDisp_Reg_Byte(
2985 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
2986 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
2987
2988 } else {
2989 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
2990 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2991 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
2992 emitXOR_RegOff_Reg_Byte(
2993 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
2994 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
2995
2996 } else {
2997 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
2998 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
2999 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
3000 emitXOR_RegIdx_Reg_Byte(
3001 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3002 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3003
3004 } else {
3005 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3006 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3007 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
3008 emitXOR_RegInd_Reg_Byte(
3009 getBase(MIR_BinaryAcc.getResult(inst)),
3010 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3011 }
3012 }
3013 }
3014 }
3015
3016 } else {
3017 if (isWord(inst)) {
3018 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
3019 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3020 emitXOR_Abs_Reg_Word(
3021 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
3022 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3023
3024 } else {
3025 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
3026 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3027 emitXOR_RegDisp_Reg_Word(
3028 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3029 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3030
3031 } else {
3032 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
3033 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3034 emitXOR_RegOff_Reg_Word(
3035 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3036 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3037
3038 } else {
3039 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
3040 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3041 emitXOR_RegIdx_Reg_Word(
3042 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3043 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3044
3045 } else {
3046 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3047 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3048 emitXOR_RegInd_Reg_Word(
3049 getBase(MIR_BinaryAcc.getResult(inst)),
3050 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3051 }
3052 }
3053 }
3054 }
3055
3056 } else {
3057 if (isQuad(inst)) {
3058 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
3059 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3060 emitXOR_Abs_Reg_Quad(
3061 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
3062 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3063
3064 } else {
3065 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
3066 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3067 emitXOR_RegDisp_Reg_Quad(
3068 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3069 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3070
3071 } else {
3072 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
3073 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3074 emitXOR_RegOff_Reg_Quad(
3075 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3076 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3077
3078 } else {
3079 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
3080 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3081 emitXOR_RegIdx_Reg_Quad(
3082 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3083 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3084
3085 } else {
3086 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3087 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3088 emitXOR_RegInd_Reg_Quad(
3089 getBase(MIR_BinaryAcc.getResult(inst)),
3090 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3091 }
3092 }
3093 }
3094 }
3095
3096 } else {
3097 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
3098 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3099 emitXOR_Abs_Reg(
3100 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
3101 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3102
3103 } else {
3104 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
3105 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3106 emitXOR_RegDisp_Reg(
3107 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3108 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3109
3110 } else {
3111 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
3112 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3113 emitXOR_RegOff_Reg(
3114 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3115 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3116
3117 } else {
3118 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
3119 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3120 emitXOR_RegIdx_Reg(
3121 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3122 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3123
3124 } else {
3125 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3126 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3127 emitXOR_RegInd_Reg(
3128 getBase(MIR_BinaryAcc.getResult(inst)),
3129 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3130 }
3131 }
3132 }
3133 }
3134 }
3135 }
3136 }
3137 }
3138 }
3139 }
3140
3141 /**
3142 * Emit the given instruction, assuming that
3143 * it is a MIR_BinaryAcc instruction
3144 * and has a RCL operator
3145 *
3146 * @param inst the instruction to assemble
3147 */
3148 private void doRCL(Instruction inst) {
3149 if (isImm(MIR_BinaryAcc.getValue(inst))) {
3150 if (isByte(inst)) {
3151 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
3152 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
3153 emitRCL_Reg_Imm_Byte(
3154 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
3155 getImm(MIR_BinaryAcc.getValue(inst)));
3156
3157 } else {
3158 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
3159 emitRCL_Abs_Imm_Byte(
3160 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
3161 getImm(MIR_BinaryAcc.getValue(inst)));
3162
3163 } else {
3164 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
3165 emitRCL_RegDisp_Imm_Byte(
3166 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3167 getImm(MIR_BinaryAcc.getValue(inst)));
3168
3169 } else {
3170 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
3171 emitRCL_RegOff_Imm_Byte(
3172 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3173 getImm(MIR_BinaryAcc.getValue(inst)));
3174
3175 } else {
3176 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
3177 emitRCL_RegIdx_Imm_Byte(
3178 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3179 getImm(MIR_BinaryAcc.getValue(inst)));
3180
3181 } else {
3182 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3183 emitRCL_RegInd_Imm_Byte(
3184 getBase(MIR_BinaryAcc.getResult(inst)),
3185 getImm(MIR_BinaryAcc.getValue(inst)));
3186 }
3187 }
3188 }
3189 }
3190 }
3191
3192 } else {
3193 if (isWord(inst)) {
3194 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
3195 emitRCL_Reg_Imm_Word(
3196 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
3197 getImm(MIR_BinaryAcc.getValue(inst)));
3198
3199 } else {
3200 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
3201 emitRCL_Abs_Imm_Word(
3202 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
3203 getImm(MIR_BinaryAcc.getValue(inst)));
3204
3205 } else {
3206 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
3207 emitRCL_RegDisp_Imm_Word(
3208 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3209 getImm(MIR_BinaryAcc.getValue(inst)));
3210
3211 } else {
3212 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
3213 emitRCL_RegOff_Imm_Word(
3214 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3215 getImm(MIR_BinaryAcc.getValue(inst)));
3216
3217 } else {
3218 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
3219 emitRCL_RegIdx_Imm_Word(
3220 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3221 getImm(MIR_BinaryAcc.getValue(inst)));
3222
3223 } else {
3224 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3225 emitRCL_RegInd_Imm_Word(
3226 getBase(MIR_BinaryAcc.getResult(inst)),
3227 getImm(MIR_BinaryAcc.getValue(inst)));
3228 }
3229 }
3230 }
3231 }
3232 }
3233
3234 } else {
3235 if (isQuad(inst)) {
3236 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
3237 emitRCL_Reg_Imm_Quad(
3238 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
3239 getImm(MIR_BinaryAcc.getValue(inst)));
3240
3241 } else {
3242 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
3243 emitRCL_Abs_Imm_Quad(
3244 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
3245 getImm(MIR_BinaryAcc.getValue(inst)));
3246
3247 } else {
3248 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
3249 emitRCL_RegDisp_Imm_Quad(
3250 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3251 getImm(MIR_BinaryAcc.getValue(inst)));
3252
3253 } else {
3254 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
3255 emitRCL_RegOff_Imm_Quad(
3256 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3257 getImm(MIR_BinaryAcc.getValue(inst)));
3258
3259 } else {
3260 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
3261 emitRCL_RegIdx_Imm_Quad(
3262 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3263 getImm(MIR_BinaryAcc.getValue(inst)));
3264
3265 } else {
3266 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3267 emitRCL_RegInd_Imm_Quad(
3268 getBase(MIR_BinaryAcc.getResult(inst)),
3269 getImm(MIR_BinaryAcc.getValue(inst)));
3270 }
3271 }
3272 }
3273 }
3274 }
3275
3276 } else {
3277 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
3278 emitRCL_Reg_Imm(
3279 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
3280 getImm(MIR_BinaryAcc.getValue(inst)));
3281
3282 } else {
3283 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
3284 emitRCL_Abs_Imm(
3285 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
3286 getImm(MIR_BinaryAcc.getValue(inst)));
3287
3288 } else {
3289 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
3290 emitRCL_RegDisp_Imm(
3291 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3292 getImm(MIR_BinaryAcc.getValue(inst)));
3293
3294 } else {
3295 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
3296 emitRCL_RegOff_Imm(
3297 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3298 getImm(MIR_BinaryAcc.getValue(inst)));
3299
3300 } else {
3301 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
3302 emitRCL_RegIdx_Imm(
3303 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3304 getImm(MIR_BinaryAcc.getValue(inst)));
3305
3306 } else {
3307 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3308 emitRCL_RegInd_Imm(
3309 getBase(MIR_BinaryAcc.getResult(inst)),
3310 getImm(MIR_BinaryAcc.getValue(inst)));
3311 }
3312 }
3313 }
3314 }
3315 }
3316 }
3317 }
3318 }
3319
3320 } else {
3321 if (isByte(inst)) {
3322 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
3323 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3324 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
3325 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
3326 emitRCL_Reg_Reg_Byte(
3327 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
3328 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3329
3330 } else {
3331 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
3332 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3333 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
3334 emitRCL_Abs_Reg_Byte(
3335 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
3336 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3337
3338 } else {
3339 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
3340 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3341 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
3342 emitRCL_RegDisp_Reg_Byte(
3343 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3344 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3345
3346 } else {
3347 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
3348 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3349 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
3350 emitRCL_RegOff_Reg_Byte(
3351 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3352 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3353
3354 } else {
3355 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
3356 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3357 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
3358 emitRCL_RegIdx_Reg_Byte(
3359 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3360 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3361
3362 } else {
3363 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3364 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3365 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
3366 emitRCL_RegInd_Reg_Byte(
3367 getBase(MIR_BinaryAcc.getResult(inst)),
3368 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3369 }
3370 }
3371 }
3372 }
3373 }
3374
3375 } else {
3376 if (isWord(inst)) {
3377 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
3378 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3379 emitRCL_Reg_Reg_Word(
3380 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
3381 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3382
3383 } else {
3384 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
3385 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3386 emitRCL_Abs_Reg_Word(
3387 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
3388 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3389
3390 } else {
3391 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
3392 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3393 emitRCL_RegDisp_Reg_Word(
3394 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3395 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3396
3397 } else {
3398 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
3399 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3400 emitRCL_RegOff_Reg_Word(
3401 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3402 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3403
3404 } else {
3405 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
3406 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3407 emitRCL_RegIdx_Reg_Word(
3408 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3409 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3410
3411 } else {
3412 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3413 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3414 emitRCL_RegInd_Reg_Word(
3415 getBase(MIR_BinaryAcc.getResult(inst)),
3416 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3417 }
3418 }
3419 }
3420 }
3421 }
3422
3423 } else {
3424 if (isQuad(inst)) {
3425 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
3426 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3427 emitRCL_Reg_Reg_Quad(
3428 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
3429 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3430
3431 } else {
3432 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
3433 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3434 emitRCL_Abs_Reg_Quad(
3435 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
3436 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3437
3438 } else {
3439 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
3440 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3441 emitRCL_RegDisp_Reg_Quad(
3442 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3443 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3444
3445 } else {
3446 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
3447 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3448 emitRCL_RegOff_Reg_Quad(
3449 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3450 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3451
3452 } else {
3453 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
3454 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3455 emitRCL_RegIdx_Reg_Quad(
3456 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3457 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3458
3459 } else {
3460 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3461 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3462 emitRCL_RegInd_Reg_Quad(
3463 getBase(MIR_BinaryAcc.getResult(inst)),
3464 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3465 }
3466 }
3467 }
3468 }
3469 }
3470
3471 } else {
3472 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
3473 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3474 emitRCL_Reg_Reg(
3475 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
3476 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3477
3478 } else {
3479 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
3480 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3481 emitRCL_Abs_Reg(
3482 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
3483 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3484
3485 } else {
3486 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
3487 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3488 emitRCL_RegDisp_Reg(
3489 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3490 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3491
3492 } else {
3493 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
3494 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3495 emitRCL_RegOff_Reg(
3496 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3497 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3498
3499 } else {
3500 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
3501 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3502 emitRCL_RegIdx_Reg(
3503 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3504 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3505
3506 } else {
3507 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3508 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3509 emitRCL_RegInd_Reg(
3510 getBase(MIR_BinaryAcc.getResult(inst)),
3511 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
3512 }
3513 }
3514 }
3515 }
3516 }
3517 }
3518 }
3519 }
3520 }
3521 }
3522
3523 /**
3524 * Emit the given instruction, assuming that
3525 * it is a MIR_Move instruction
3526 * and has a FLD operator
3527 *
3528 * @param inst the instruction to assemble
3529 */
3530 private void doFLD(Instruction inst) {
3531 if (isQuad(inst)) {
3532 if (isAbs(MIR_Move.getValue(inst))) {
3533 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3534 emitFLD_Reg_Abs_Quad(
3535 getFPR_Reg(MIR_Move.getResult(inst)),
3536 getDisp(MIR_Move.getValue(inst)).toWord().toAddress());
3537
3538 } else {
3539 if (isRegDisp(MIR_Move.getValue(inst))) {
3540 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3541 emitFLD_Reg_RegDisp_Quad(
3542 getFPR_Reg(MIR_Move.getResult(inst)),
3543 getBase(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
3544
3545 } else {
3546 if (isRegOff(MIR_Move.getValue(inst))) {
3547 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3548 emitFLD_Reg_RegOff_Quad(
3549 getFPR_Reg(MIR_Move.getResult(inst)),
3550 getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
3551
3552 } else {
3553 if (isRegIdx(MIR_Move.getValue(inst))) {
3554 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3555 emitFLD_Reg_RegIdx_Quad(
3556 getFPR_Reg(MIR_Move.getResult(inst)),
3557 getBase(MIR_Move.getValue(inst)), getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
3558
3559 } else {
3560 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3561 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3562 emitFLD_Reg_RegInd_Quad(
3563 getFPR_Reg(MIR_Move.getResult(inst)),
3564 getBase(MIR_Move.getValue(inst)));
3565 }
3566 }
3567 }
3568 }
3569
3570 } else {
3571 if (isFPR_Reg(MIR_Move.getValue(inst))) {
3572 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3573 emitFLD_Reg_Reg(
3574 getFPR_Reg(MIR_Move.getResult(inst)),
3575 getFPR_Reg(MIR_Move.getValue(inst)));
3576
3577 } else {
3578 if (isAbs(MIR_Move.getValue(inst))) {
3579 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3580 emitFLD_Reg_Abs(
3581 getFPR_Reg(MIR_Move.getResult(inst)),
3582 getDisp(MIR_Move.getValue(inst)).toWord().toAddress());
3583
3584 } else {
3585 if (isRegDisp(MIR_Move.getValue(inst))) {
3586 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3587 emitFLD_Reg_RegDisp(
3588 getFPR_Reg(MIR_Move.getResult(inst)),
3589 getBase(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
3590
3591 } else {
3592 if (isRegOff(MIR_Move.getValue(inst))) {
3593 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3594 emitFLD_Reg_RegOff(
3595 getFPR_Reg(MIR_Move.getResult(inst)),
3596 getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
3597
3598 } else {
3599 if (isRegIdx(MIR_Move.getValue(inst))) {
3600 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3601 emitFLD_Reg_RegIdx(
3602 getFPR_Reg(MIR_Move.getResult(inst)),
3603 getBase(MIR_Move.getValue(inst)), getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
3604
3605 } else {
3606 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3607 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3608 emitFLD_Reg_RegInd(
3609 getFPR_Reg(MIR_Move.getResult(inst)),
3610 getBase(MIR_Move.getValue(inst)));
3611 }
3612 }
3613 }
3614 }
3615 }
3616 }
3617 }
3618
3619 /**
3620 * Emit the given instruction, assuming that
3621 * it is a MIR_Test instruction
3622 * and has a BTR operator
3623 *
3624 * @param inst the instruction to assemble
3625 */
3626 private void doBTR(Instruction inst) {
3627 if (isImm(MIR_Test.getVal2(inst))) {
3628 if (isGPR_Reg(MIR_Test.getVal1(inst))) {
3629 emitBTR_Reg_Imm(
3630 getGPR_Reg(MIR_Test.getVal1(inst)),
3631 getImm(MIR_Test.getVal2(inst)));
3632
3633 } else {
3634 if (isAbs(MIR_Test.getVal1(inst))) {
3635 emitBTR_Abs_Imm(
3636 getDisp(MIR_Test.getVal1(inst)).toWord().toAddress(),
3637 getImm(MIR_Test.getVal2(inst)));
3638
3639 } else {
3640 if (isRegDisp(MIR_Test.getVal1(inst))) {
3641 emitBTR_RegDisp_Imm(
3642 getBase(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
3643 getImm(MIR_Test.getVal2(inst)));
3644
3645 } else {
3646 if (isRegOff(MIR_Test.getVal1(inst))) {
3647 emitBTR_RegOff_Imm(
3648 getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
3649 getImm(MIR_Test.getVal2(inst)));
3650
3651 } else {
3652 if (isRegIdx(MIR_Test.getVal1(inst))) {
3653 emitBTR_RegIdx_Imm(
3654 getBase(MIR_Test.getVal1(inst)), getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
3655 getImm(MIR_Test.getVal2(inst)));
3656
3657 } else {
3658 if (VM.VerifyAssertions && !isRegInd(MIR_Test.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3659 emitBTR_RegInd_Imm(
3660 getBase(MIR_Test.getVal1(inst)),
3661 getImm(MIR_Test.getVal2(inst)));
3662 }
3663 }
3664 }
3665 }
3666 }
3667
3668 } else {
3669 if (isGPR_Reg(MIR_Test.getVal1(inst))) {
3670 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3671 emitBTR_Reg_Reg(
3672 getGPR_Reg(MIR_Test.getVal1(inst)),
3673 getGPR_Reg(MIR_Test.getVal2(inst)));
3674
3675 } else {
3676 if (isAbs(MIR_Test.getVal1(inst))) {
3677 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3678 emitBTR_Abs_Reg(
3679 getDisp(MIR_Test.getVal1(inst)).toWord().toAddress(),
3680 getGPR_Reg(MIR_Test.getVal2(inst)));
3681
3682 } else {
3683 if (isRegDisp(MIR_Test.getVal1(inst))) {
3684 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3685 emitBTR_RegDisp_Reg(
3686 getBase(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
3687 getGPR_Reg(MIR_Test.getVal2(inst)));
3688
3689 } else {
3690 if (isRegOff(MIR_Test.getVal1(inst))) {
3691 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3692 emitBTR_RegOff_Reg(
3693 getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
3694 getGPR_Reg(MIR_Test.getVal2(inst)));
3695
3696 } else {
3697 if (isRegIdx(MIR_Test.getVal1(inst))) {
3698 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3699 emitBTR_RegIdx_Reg(
3700 getBase(MIR_Test.getVal1(inst)), getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
3701 getGPR_Reg(MIR_Test.getVal2(inst)));
3702
3703 } else {
3704 if (VM.VerifyAssertions && !isRegInd(MIR_Test.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3705 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3706 emitBTR_RegInd_Reg(
3707 getBase(MIR_Test.getVal1(inst)),
3708 getGPR_Reg(MIR_Test.getVal2(inst)));
3709 }
3710 }
3711 }
3712 }
3713 }
3714 }
3715 }
3716
3717 /**
3718 * Emit the given instruction, assuming that
3719 * it is a MIR_Test instruction
3720 * and has a BTS operator
3721 *
3722 * @param inst the instruction to assemble
3723 */
3724 private void doBTS(Instruction inst) {
3725 if (isImm(MIR_Test.getVal2(inst))) {
3726 if (isGPR_Reg(MIR_Test.getVal1(inst))) {
3727 emitBTS_Reg_Imm(
3728 getGPR_Reg(MIR_Test.getVal1(inst)),
3729 getImm(MIR_Test.getVal2(inst)));
3730
3731 } else {
3732 if (isAbs(MIR_Test.getVal1(inst))) {
3733 emitBTS_Abs_Imm(
3734 getDisp(MIR_Test.getVal1(inst)).toWord().toAddress(),
3735 getImm(MIR_Test.getVal2(inst)));
3736
3737 } else {
3738 if (isRegDisp(MIR_Test.getVal1(inst))) {
3739 emitBTS_RegDisp_Imm(
3740 getBase(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
3741 getImm(MIR_Test.getVal2(inst)));
3742
3743 } else {
3744 if (isRegOff(MIR_Test.getVal1(inst))) {
3745 emitBTS_RegOff_Imm(
3746 getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
3747 getImm(MIR_Test.getVal2(inst)));
3748
3749 } else {
3750 if (isRegIdx(MIR_Test.getVal1(inst))) {
3751 emitBTS_RegIdx_Imm(
3752 getBase(MIR_Test.getVal1(inst)), getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
3753 getImm(MIR_Test.getVal2(inst)));
3754
3755 } else {
3756 if (VM.VerifyAssertions && !isRegInd(MIR_Test.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3757 emitBTS_RegInd_Imm(
3758 getBase(MIR_Test.getVal1(inst)),
3759 getImm(MIR_Test.getVal2(inst)));
3760 }
3761 }
3762 }
3763 }
3764 }
3765
3766 } else {
3767 if (isGPR_Reg(MIR_Test.getVal1(inst))) {
3768 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3769 emitBTS_Reg_Reg(
3770 getGPR_Reg(MIR_Test.getVal1(inst)),
3771 getGPR_Reg(MIR_Test.getVal2(inst)));
3772
3773 } else {
3774 if (isAbs(MIR_Test.getVal1(inst))) {
3775 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3776 emitBTS_Abs_Reg(
3777 getDisp(MIR_Test.getVal1(inst)).toWord().toAddress(),
3778 getGPR_Reg(MIR_Test.getVal2(inst)));
3779
3780 } else {
3781 if (isRegDisp(MIR_Test.getVal1(inst))) {
3782 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3783 emitBTS_RegDisp_Reg(
3784 getBase(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
3785 getGPR_Reg(MIR_Test.getVal2(inst)));
3786
3787 } else {
3788 if (isRegOff(MIR_Test.getVal1(inst))) {
3789 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3790 emitBTS_RegOff_Reg(
3791 getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
3792 getGPR_Reg(MIR_Test.getVal2(inst)));
3793
3794 } else {
3795 if (isRegIdx(MIR_Test.getVal1(inst))) {
3796 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3797 emitBTS_RegIdx_Reg(
3798 getBase(MIR_Test.getVal1(inst)), getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
3799 getGPR_Reg(MIR_Test.getVal2(inst)));
3800
3801 } else {
3802 if (VM.VerifyAssertions && !isRegInd(MIR_Test.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3803 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3804 emitBTS_RegInd_Reg(
3805 getBase(MIR_Test.getVal1(inst)),
3806 getGPR_Reg(MIR_Test.getVal2(inst)));
3807 }
3808 }
3809 }
3810 }
3811 }
3812 }
3813 }
3814
3815 /**
3816 * Emit the given instruction, assuming that
3817 * it is a MIR_BinaryAcc instruction
3818 * and has a RCR operator
3819 *
3820 * @param inst the instruction to assemble
3821 */
3822 private void doRCR(Instruction inst) {
3823 if (isImm(MIR_BinaryAcc.getValue(inst))) {
3824 if (isByte(inst)) {
3825 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
3826 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
3827 emitRCR_Reg_Imm_Byte(
3828 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
3829 getImm(MIR_BinaryAcc.getValue(inst)));
3830
3831 } else {
3832 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
3833 emitRCR_Abs_Imm_Byte(
3834 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
3835 getImm(MIR_BinaryAcc.getValue(inst)));
3836
3837 } else {
3838 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
3839 emitRCR_RegDisp_Imm_Byte(
3840 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3841 getImm(MIR_BinaryAcc.getValue(inst)));
3842
3843 } else {
3844 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
3845 emitRCR_RegOff_Imm_Byte(
3846 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3847 getImm(MIR_BinaryAcc.getValue(inst)));
3848
3849 } else {
3850 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
3851 emitRCR_RegIdx_Imm_Byte(
3852 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3853 getImm(MIR_BinaryAcc.getValue(inst)));
3854
3855 } else {
3856 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3857 emitRCR_RegInd_Imm_Byte(
3858 getBase(MIR_BinaryAcc.getResult(inst)),
3859 getImm(MIR_BinaryAcc.getValue(inst)));
3860 }
3861 }
3862 }
3863 }
3864 }
3865
3866 } else {
3867 if (isWord(inst)) {
3868 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
3869 emitRCR_Reg_Imm_Word(
3870 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
3871 getImm(MIR_BinaryAcc.getValue(inst)));
3872
3873 } else {
3874 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
3875 emitRCR_Abs_Imm_Word(
3876 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
3877 getImm(MIR_BinaryAcc.getValue(inst)));
3878
3879 } else {
3880 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
3881 emitRCR_RegDisp_Imm_Word(
3882 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3883 getImm(MIR_BinaryAcc.getValue(inst)));
3884
3885 } else {
3886 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
3887 emitRCR_RegOff_Imm_Word(
3888 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3889 getImm(MIR_BinaryAcc.getValue(inst)));
3890
3891 } else {
3892 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
3893 emitRCR_RegIdx_Imm_Word(
3894 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3895 getImm(MIR_BinaryAcc.getValue(inst)));
3896
3897 } else {
3898 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3899 emitRCR_RegInd_Imm_Word(
3900 getBase(MIR_BinaryAcc.getResult(inst)),
3901 getImm(MIR_BinaryAcc.getValue(inst)));
3902 }
3903 }
3904 }
3905 }
3906 }
3907
3908 } else {
3909 if (isQuad(inst)) {
3910 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
3911 emitRCR_Reg_Imm_Quad(
3912 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
3913 getImm(MIR_BinaryAcc.getValue(inst)));
3914
3915 } else {
3916 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
3917 emitRCR_Abs_Imm_Quad(
3918 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
3919 getImm(MIR_BinaryAcc.getValue(inst)));
3920
3921 } else {
3922 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
3923 emitRCR_RegDisp_Imm_Quad(
3924 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3925 getImm(MIR_BinaryAcc.getValue(inst)));
3926
3927 } else {
3928 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
3929 emitRCR_RegOff_Imm_Quad(
3930 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3931 getImm(MIR_BinaryAcc.getValue(inst)));
3932
3933 } else {
3934 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
3935 emitRCR_RegIdx_Imm_Quad(
3936 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3937 getImm(MIR_BinaryAcc.getValue(inst)));
3938
3939 } else {
3940 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3941 emitRCR_RegInd_Imm_Quad(
3942 getBase(MIR_BinaryAcc.getResult(inst)),
3943 getImm(MIR_BinaryAcc.getValue(inst)));
3944 }
3945 }
3946 }
3947 }
3948 }
3949
3950 } else {
3951 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
3952 emitRCR_Reg_Imm(
3953 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
3954 getImm(MIR_BinaryAcc.getValue(inst)));
3955
3956 } else {
3957 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
3958 emitRCR_Abs_Imm(
3959 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
3960 getImm(MIR_BinaryAcc.getValue(inst)));
3961
3962 } else {
3963 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
3964 emitRCR_RegDisp_Imm(
3965 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3966 getImm(MIR_BinaryAcc.getValue(inst)));
3967
3968 } else {
3969 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
3970 emitRCR_RegOff_Imm(
3971 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3972 getImm(MIR_BinaryAcc.getValue(inst)));
3973
3974 } else {
3975 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
3976 emitRCR_RegIdx_Imm(
3977 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
3978 getImm(MIR_BinaryAcc.getValue(inst)));
3979
3980 } else {
3981 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3982 emitRCR_RegInd_Imm(
3983 getBase(MIR_BinaryAcc.getResult(inst)),
3984 getImm(MIR_BinaryAcc.getValue(inst)));
3985 }
3986 }
3987 }
3988 }
3989 }
3990 }
3991 }
3992 }
3993
3994 } else {
3995 if (isByte(inst)) {
3996 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
3997 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
3998 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
3999 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
4000 emitRCR_Reg_Reg_Byte(
4001 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
4002 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
4003
4004 } else {
4005 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
4006 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4007 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
4008 emitRCR_Abs_Reg_Byte(
4009 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
4010 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
4011
4012 } else {
4013 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
4014 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4015 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
4016 emitRCR_RegDisp_Reg_Byte(
4017 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
4018 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
4019
4020 } else {
4021 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
4022 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4023 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
4024 emitRCR_RegOff_Reg_Byte(
4025 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
4026 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
4027
4028 } else {
4029 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
4030 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4031 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
4032 emitRCR_RegIdx_Reg_Byte(
4033 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
4034 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
4035
4036 } else {
4037 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4038 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4039 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
4040 emitRCR_RegInd_Reg_Byte(
4041 getBase(MIR_BinaryAcc.getResult(inst)),
4042 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
4043 }
4044 }
4045 }
4046 }
4047 }
4048
4049 } else {
4050 if (isWord(inst)) {
4051 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
4052 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4053 emitRCR_Reg_Reg_Word(
4054 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
4055 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
4056
4057 } else {
4058 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
4059 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4060 emitRCR_Abs_Reg_Word(
4061 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
4062 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
4063
4064 } else {
4065 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
4066 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4067 emitRCR_RegDisp_Reg_Word(
4068 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
4069 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
4070
4071 } else {
4072 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
4073 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4074 emitRCR_RegOff_Reg_Word(
4075 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
4076 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
4077
4078 } else {
4079 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
4080 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4081 emitRCR_RegIdx_Reg_Word(
4082 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
4083 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
4084
4085 } else {
4086 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4087 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4088 emitRCR_RegInd_Reg_Word(
4089 getBase(MIR_BinaryAcc.getResult(inst)),
4090 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
4091 }
4092 }
4093 }
4094 }
4095 }
4096
4097 } else {
4098 if (isQuad(inst)) {
4099 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
4100 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4101 emitRCR_Reg_Reg_Quad(
4102 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
4103 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
4104
4105 } else {
4106 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
4107 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4108 emitRCR_Abs_Reg_Quad(
4109 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
4110 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
4111
4112 } else {
4113 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
4114 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4115 emitRCR_RegDisp_Reg_Quad(
4116 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
4117 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
4118
4119 } else {
4120 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
4121 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4122 emitRCR_RegOff_Reg_Quad(
4123 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
4124 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
4125
4126 } else {
4127 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
4128 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4129 emitRCR_RegIdx_Reg_Quad(
4130 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
4131 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
4132
4133 } else {
4134 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4135 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4136 emitRCR_RegInd_Reg_Quad(
4137 getBase(MIR_BinaryAcc.getResult(inst)),
4138 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
4139 }
4140 }
4141 }
4142 }
4143 }
4144
4145 } else {
4146 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
4147 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4148 emitRCR_Reg_Reg(
4149 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
4150 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
4151
4152 } else {
4153 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
4154 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4155 emitRCR_Abs_Reg(
4156 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
4157 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
4158
4159 } else {
4160 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
4161 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4162 emitRCR_RegDisp_Reg(
4163 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
4164 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
4165
4166 } else {
4167 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
4168 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4169 emitRCR_RegOff_Reg(
4170 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
4171 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
4172
4173 } else {
4174 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
4175 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4176 emitRCR_RegIdx_Reg(
4177 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
4178 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
4179
4180 } else {
4181 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4182 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4183 emitRCR_RegInd_Reg(
4184 getBase(MIR_BinaryAcc.getResult(inst)),
4185 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
4186 }
4187 }
4188 }
4189 }
4190 }
4191 }
4192 }
4193 }
4194 }
4195 }
4196
4197 /**
4198 * Emit the given instruction, assuming that
4199 * it is a MIR_Set instruction
4200 * and has a SET operator
4201 *
4202 * @param inst the instruction to assemble
4203 */
4204 private void doSET(Instruction inst) {
4205 if (isGPR_Reg(MIR_Set.getResult(inst))) {
4206 if (VM.VerifyAssertions && !isCond(MIR_Set.getCond(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4207 if (VM.VerifyAssertions && !isByte(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
4208 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_Set.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
4209 emitSET_Cond_Reg_Byte(
4210 getCond(MIR_Set.getCond(inst)),
4211 getGPR_Reg(MIR_Set.getResult(inst)));
4212
4213 } else {
4214 if (isAbs(MIR_Set.getResult(inst))) {
4215 if (VM.VerifyAssertions && !isCond(MIR_Set.getCond(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4216 if (VM.VerifyAssertions && !isByte(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
4217 emitSET_Cond_Abs_Byte(
4218 getCond(MIR_Set.getCond(inst)),
4219 getDisp(MIR_Set.getResult(inst)).toWord().toAddress());
4220
4221 } else {
4222 if (isRegDisp(MIR_Set.getResult(inst))) {
4223 if (VM.VerifyAssertions && !isCond(MIR_Set.getCond(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4224 if (VM.VerifyAssertions && !isByte(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
4225 emitSET_Cond_RegDisp_Byte(
4226 getCond(MIR_Set.getCond(inst)),
4227 getBase(MIR_Set.getResult(inst)), getDisp(MIR_Set.getResult(inst)));
4228
4229 } else {
4230 if (isRegOff(MIR_Set.getResult(inst))) {
4231 if (VM.VerifyAssertions && !isCond(MIR_Set.getCond(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4232 if (VM.VerifyAssertions && !isByte(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
4233 emitSET_Cond_RegOff_Byte(
4234 getCond(MIR_Set.getCond(inst)),
4235 getIndex(MIR_Set.getResult(inst)), getScale(MIR_Set.getResult(inst)), getDisp(MIR_Set.getResult(inst)));
4236
4237 } else {
4238 if (isRegIdx(MIR_Set.getResult(inst))) {
4239 if (VM.VerifyAssertions && !isCond(MIR_Set.getCond(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4240 if (VM.VerifyAssertions && !isByte(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
4241 emitSET_Cond_RegIdx_Byte(
4242 getCond(MIR_Set.getCond(inst)),
4243 getBase(MIR_Set.getResult(inst)), getIndex(MIR_Set.getResult(inst)), getScale(MIR_Set.getResult(inst)), getDisp(MIR_Set.getResult(inst)));
4244
4245 } else {
4246 if (VM.VerifyAssertions && !isCond(MIR_Set.getCond(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4247 if (VM.VerifyAssertions && !isRegInd(MIR_Set.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4248 if (VM.VerifyAssertions && !isByte(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
4249 emitSET_Cond_RegInd_Byte(
4250 getCond(MIR_Set.getCond(inst)),
4251 getBase(MIR_Set.getResult(inst)));
4252 }
4253 }
4254 }
4255 }
4256 }
4257 }
4258
4259 /**
4260 * Emit the given instruction, assuming that
4261 * it is a MIR_BinaryAcc instruction
4262 * and has a FIDIVR operator
4263 *
4264 * @param inst the instruction to assemble
4265 */
4266 private void doFIDIVR(Instruction inst) {
4267 if (isWord(inst)) {
4268 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
4269 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4270 emitFIDIVR_Reg_Abs_Word(
4271 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
4272 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
4273
4274 } else {
4275 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
4276 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4277 emitFIDIVR_Reg_RegDisp_Word(
4278 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
4279 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
4280
4281 } else {
4282 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
4283 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4284 emitFIDIVR_Reg_RegOff_Word(
4285 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
4286 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
4287
4288 } else {
4289 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
4290 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4291 emitFIDIVR_Reg_RegIdx_Word(
4292 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
4293 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
4294
4295 } else {
4296 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4297 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4298 emitFIDIVR_Reg_RegInd_Word(
4299 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
4300 getBase(MIR_BinaryAcc.getValue(inst)));
4301 }
4302 }
4303 }
4304 }
4305
4306 } else {
4307 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
4308 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4309 emitFIDIVR_Reg_Abs(
4310 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
4311 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
4312
4313 } else {
4314 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
4315 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4316 emitFIDIVR_Reg_RegDisp(
4317 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
4318 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
4319
4320 } else {
4321 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
4322 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4323 emitFIDIVR_Reg_RegOff(
4324 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
4325 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
4326
4327 } else {
4328 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
4329 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4330 emitFIDIVR_Reg_RegIdx(
4331 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
4332 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
4333
4334 } else {
4335 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4336 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4337 emitFIDIVR_Reg_RegInd(
4338 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
4339 getBase(MIR_BinaryAcc.getValue(inst)));
4340 }
4341 }
4342 }
4343 }
4344 }
4345 }
4346
4347 /**
4348 * Emit the given instruction, assuming that
4349 * it is a MIR_FSave instruction
4350 * and has a FNSAVE operator
4351 *
4352 * @param inst the instruction to assemble
4353 */
4354 private void doFNSAVE(Instruction inst) {
4355 if (isAbs(MIR_FSave.getDestination(inst))) {
4356 emitFNSAVE_Abs(
4357 getDisp(MIR_FSave.getDestination(inst)).toWord().toAddress());
4358
4359 } else {
4360 if (isRegDisp(MIR_FSave.getDestination(inst))) {
4361 emitFNSAVE_RegDisp(
4362 getBase(MIR_FSave.getDestination(inst)), getDisp(MIR_FSave.getDestination(inst)));
4363
4364 } else {
4365 if (isRegOff(MIR_FSave.getDestination(inst))) {
4366 emitFNSAVE_RegOff(
4367 getIndex(MIR_FSave.getDestination(inst)), getScale(MIR_FSave.getDestination(inst)), getDisp(MIR_FSave.getDestination(inst)));
4368
4369 } else {
4370 if (isRegIdx(MIR_FSave.getDestination(inst))) {
4371 emitFNSAVE_RegIdx(
4372 getBase(MIR_FSave.getDestination(inst)), getIndex(MIR_FSave.getDestination(inst)), getScale(MIR_FSave.getDestination(inst)), getDisp(MIR_FSave.getDestination(inst)));
4373
4374 } else {
4375 if (VM.VerifyAssertions && !isRegInd(MIR_FSave.getDestination(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4376 emitFNSAVE_RegInd(
4377 getBase(MIR_FSave.getDestination(inst)));
4378 }
4379 }
4380 }
4381 }
4382 }
4383
4384 /**
4385 * Emit the given instruction, assuming that
4386 * it is a MIR_BinaryAcc instruction
4387 * and has a FDIVP operator
4388 *
4389 * @param inst the instruction to assemble
4390 */
4391 private void doFDIVP(Instruction inst) {
4392 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4393 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4394 emitFDIVP_Reg_Reg(
4395 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
4396 getFPR_Reg(MIR_BinaryAcc.getValue(inst)));
4397 }
4398
4399 /**
4400 * Emit the given instruction, assuming that
4401 * it is a MIR_Move instruction
4402 * and has a MOVSD operator
4403 *
4404 * @param inst the instruction to assemble
4405 */
4406 private void doMOVSD(Instruction inst) {
4407 if (isXMM_Reg(MIR_Move.getResult(inst))) {
4408 if (isXMM_Reg(MIR_Move.getValue(inst))) {
4409 emitMOVSD_Reg_Reg(
4410 getXMM_Reg(MIR_Move.getResult(inst)),
4411 getXMM_Reg(MIR_Move.getValue(inst)));
4412
4413 } else {
4414 if (isAbs(MIR_Move.getValue(inst))) {
4415 emitMOVSD_Reg_Abs(
4416 getXMM_Reg(MIR_Move.getResult(inst)),
4417 getDisp(MIR_Move.getValue(inst)).toWord().toAddress());
4418
4419 } else {
4420 if (isRegDisp(MIR_Move.getValue(inst))) {
4421 emitMOVSD_Reg_RegDisp(
4422 getXMM_Reg(MIR_Move.getResult(inst)),
4423 getBase(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
4424
4425 } else {
4426 if (isRegOff(MIR_Move.getValue(inst))) {
4427 emitMOVSD_Reg_RegOff(
4428 getXMM_Reg(MIR_Move.getResult(inst)),
4429 getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
4430
4431 } else {
4432 if (isRegIdx(MIR_Move.getValue(inst))) {
4433 emitMOVSD_Reg_RegIdx(
4434 getXMM_Reg(MIR_Move.getResult(inst)),
4435 getBase(MIR_Move.getValue(inst)), getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
4436
4437 } else {
4438 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4439 emitMOVSD_Reg_RegInd(
4440 getXMM_Reg(MIR_Move.getResult(inst)),
4441 getBase(MIR_Move.getValue(inst)));
4442 }
4443 }
4444 }
4445 }
4446 }
4447
4448 } else {
4449 if (isAbs(MIR_Move.getResult(inst))) {
4450 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4451 emitMOVSD_Abs_Reg(
4452 getDisp(MIR_Move.getResult(inst)).toWord().toAddress(),
4453 getXMM_Reg(MIR_Move.getValue(inst)));
4454
4455 } else {
4456 if (isRegDisp(MIR_Move.getResult(inst))) {
4457 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4458 emitMOVSD_RegDisp_Reg(
4459 getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
4460 getXMM_Reg(MIR_Move.getValue(inst)));
4461
4462 } else {
4463 if (isRegOff(MIR_Move.getResult(inst))) {
4464 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4465 emitMOVSD_RegOff_Reg(
4466 getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
4467 getXMM_Reg(MIR_Move.getValue(inst)));
4468
4469 } else {
4470 if (isRegIdx(MIR_Move.getResult(inst))) {
4471 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4472 emitMOVSD_RegIdx_Reg(
4473 getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
4474 getXMM_Reg(MIR_Move.getValue(inst)));
4475
4476 } else {
4477 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4478 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4479 emitMOVSD_RegInd_Reg(
4480 getBase(MIR_Move.getResult(inst)),
4481 getXMM_Reg(MIR_Move.getValue(inst)));
4482 }
4483 }
4484 }
4485 }
4486 }
4487 }
4488
4489 /**
4490 * Emit the given instruction, assuming that
4491 * it is a MIR_BinaryAcc instruction
4492 * and has a FDIVR operator
4493 *
4494 * @param inst the instruction to assemble
4495 */
4496 private void doFDIVR(Instruction inst) {
4497 if (isQuad(inst)) {
4498 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
4499 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4500 emitFDIVR_Reg_Abs_Quad(
4501 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
4502 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
4503
4504 } else {
4505 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
4506 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4507 emitFDIVR_Reg_RegDisp_Quad(
4508 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
4509 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
4510
4511 } else {
4512 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
4513 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4514 emitFDIVR_Reg_RegOff_Quad(
4515 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
4516 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
4517
4518 } else {
4519 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
4520 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4521 emitFDIVR_Reg_RegIdx_Quad(
4522 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
4523 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
4524
4525 } else {
4526 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4527 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4528 emitFDIVR_Reg_RegInd_Quad(
4529 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
4530 getBase(MIR_BinaryAcc.getValue(inst)));
4531 }
4532 }
4533 }
4534 }
4535
4536 } else {
4537 if (isFPR_Reg(MIR_BinaryAcc.getValue(inst))) {
4538 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4539 emitFDIVR_Reg_Reg(
4540 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
4541 getFPR_Reg(MIR_BinaryAcc.getValue(inst)));
4542
4543 } else {
4544 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
4545 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4546 emitFDIVR_Reg_Abs(
4547 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
4548 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
4549
4550 } else {
4551 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
4552 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4553 emitFDIVR_Reg_RegDisp(
4554 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
4555 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
4556
4557 } else {
4558 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
4559 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4560 emitFDIVR_Reg_RegOff(
4561 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
4562 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
4563
4564 } else {
4565 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
4566 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4567 emitFDIVR_Reg_RegIdx(
4568 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
4569 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
4570
4571 } else {
4572 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4573 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4574 emitFDIVR_Reg_RegInd(
4575 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
4576 getBase(MIR_BinaryAcc.getValue(inst)));
4577 }
4578 }
4579 }
4580 }
4581 }
4582 }
4583 }
4584
4585 /**
4586 * Emit the given instruction, assuming that
4587 * it is a MIR_DoubleShift instruction
4588 * and has a SHRD operator
4589 *
4590 * @param inst the instruction to assemble
4591 */
4592 private void doSHRD(Instruction inst) {
4593 if (isQuad(inst)) {
4594 if (isImm(MIR_DoubleShift.getBitsToShift(inst))) {
4595 if (isGPR_Reg(MIR_DoubleShift.getResult(inst))) {
4596 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4597 emitSHRD_Reg_Reg_Imm_Quad(
4598 getGPR_Reg(MIR_DoubleShift.getResult(inst)),
4599 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
4600 getImm(MIR_DoubleShift.getBitsToShift(inst)));
4601
4602 } else {
4603 if (isAbs(MIR_DoubleShift.getResult(inst))) {
4604 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4605 emitSHRD_Abs_Reg_Imm_Quad(
4606 getDisp(MIR_DoubleShift.getResult(inst)).toWord().toAddress(),
4607 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
4608 getImm(MIR_DoubleShift.getBitsToShift(inst)));
4609
4610 } else {
4611 if (isRegDisp(MIR_DoubleShift.getResult(inst))) {
4612 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4613 emitSHRD_RegDisp_Reg_Imm_Quad(
4614 getBase(MIR_DoubleShift.getResult(inst)), getDisp(MIR_DoubleShift.getResult(inst)),
4615 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
4616 getImm(MIR_DoubleShift.getBitsToShift(inst)));
4617
4618 } else {
4619 if (isRegOff(MIR_DoubleShift.getResult(inst))) {
4620 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4621 emitSHRD_RegOff_Reg_Imm_Quad(
4622 getIndex(MIR_DoubleShift.getResult(inst)), getScale(MIR_DoubleShift.getResult(inst)), getDisp(MIR_DoubleShift.getResult(inst)),
4623 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
4624 getImm(MIR_DoubleShift.getBitsToShift(inst)));
4625
4626 } else {
4627 if (isRegIdx(MIR_DoubleShift.getResult(inst))) {
4628 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4629 emitSHRD_RegIdx_Reg_Imm_Quad(
4630 getBase(MIR_DoubleShift.getResult(inst)), getIndex(MIR_DoubleShift.getResult(inst)), getScale(MIR_DoubleShift.getResult(inst)), getDisp(MIR_DoubleShift.getResult(inst)),
4631 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
4632 getImm(MIR_DoubleShift.getBitsToShift(inst)));
4633
4634 } else {
4635 if (VM.VerifyAssertions && !isRegInd(MIR_DoubleShift.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4636 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4637 emitSHRD_RegInd_Reg_Imm_Quad(
4638 getBase(MIR_DoubleShift.getResult(inst)),
4639 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
4640 getImm(MIR_DoubleShift.getBitsToShift(inst)));
4641 }
4642 }
4643 }
4644 }
4645 }
4646
4647 } else {
4648 if (isGPR_Reg(MIR_DoubleShift.getResult(inst))) {
4649 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4650 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getBitsToShift(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4651 emitSHRD_Reg_Reg_Reg_Quad(
4652 getGPR_Reg(MIR_DoubleShift.getResult(inst)),
4653 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
4654 getGPR_Reg(MIR_DoubleShift.getBitsToShift(inst)));
4655
4656 } else {
4657 if (isAbs(MIR_DoubleShift.getResult(inst))) {
4658 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4659 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getBitsToShift(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4660 emitSHRD_Abs_Reg_Reg_Quad(
4661 getDisp(MIR_DoubleShift.getResult(inst)).toWord().toAddress(),
4662 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
4663 getGPR_Reg(MIR_DoubleShift.getBitsToShift(inst)));
4664
4665 } else {
4666 if (isRegDisp(MIR_DoubleShift.getResult(inst))) {
4667 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4668 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getBitsToShift(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4669 emitSHRD_RegDisp_Reg_Reg_Quad(
4670 getBase(MIR_DoubleShift.getResult(inst)), getDisp(MIR_DoubleShift.getResult(inst)),
4671 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
4672 getGPR_Reg(MIR_DoubleShift.getBitsToShift(inst)));
4673
4674 } else {
4675 if (isRegOff(MIR_DoubleShift.getResult(inst))) {
4676 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4677 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getBitsToShift(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4678 emitSHRD_RegOff_Reg_Reg_Quad(
4679 getIndex(MIR_DoubleShift.getResult(inst)), getScale(MIR_DoubleShift.getResult(inst)), getDisp(MIR_DoubleShift.getResult(inst)),
4680 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
4681 getGPR_Reg(MIR_DoubleShift.getBitsToShift(inst)));
4682
4683 } else {
4684 if (isRegIdx(MIR_DoubleShift.getResult(inst))) {
4685 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4686 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getBitsToShift(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4687 emitSHRD_RegIdx_Reg_Reg_Quad(
4688 getBase(MIR_DoubleShift.getResult(inst)), getIndex(MIR_DoubleShift.getResult(inst)), getScale(MIR_DoubleShift.getResult(inst)), getDisp(MIR_DoubleShift.getResult(inst)),
4689 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
4690 getGPR_Reg(MIR_DoubleShift.getBitsToShift(inst)));
4691
4692 } else {
4693 if (VM.VerifyAssertions && !isRegInd(MIR_DoubleShift.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4694 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4695 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getBitsToShift(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4696 emitSHRD_RegInd_Reg_Reg_Quad(
4697 getBase(MIR_DoubleShift.getResult(inst)),
4698 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
4699 getGPR_Reg(MIR_DoubleShift.getBitsToShift(inst)));
4700 }
4701 }
4702 }
4703 }
4704 }
4705 }
4706
4707 } else {
4708 if (isImm(MIR_DoubleShift.getBitsToShift(inst))) {
4709 if (isGPR_Reg(MIR_DoubleShift.getResult(inst))) {
4710 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4711 emitSHRD_Reg_Reg_Imm(
4712 getGPR_Reg(MIR_DoubleShift.getResult(inst)),
4713 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
4714 getImm(MIR_DoubleShift.getBitsToShift(inst)));
4715
4716 } else {
4717 if (isAbs(MIR_DoubleShift.getResult(inst))) {
4718 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4719 emitSHRD_Abs_Reg_Imm(
4720 getDisp(MIR_DoubleShift.getResult(inst)).toWord().toAddress(),
4721 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
4722 getImm(MIR_DoubleShift.getBitsToShift(inst)));
4723
4724 } else {
4725 if (isRegDisp(MIR_DoubleShift.getResult(inst))) {
4726 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4727 emitSHRD_RegDisp_Reg_Imm(
4728 getBase(MIR_DoubleShift.getResult(inst)), getDisp(MIR_DoubleShift.getResult(inst)),
4729 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
4730 getImm(MIR_DoubleShift.getBitsToShift(inst)));
4731
4732 } else {
4733 if (isRegOff(MIR_DoubleShift.getResult(inst))) {
4734 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4735 emitSHRD_RegOff_Reg_Imm(
4736 getIndex(MIR_DoubleShift.getResult(inst)), getScale(MIR_DoubleShift.getResult(inst)), getDisp(MIR_DoubleShift.getResult(inst)),
4737 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
4738 getImm(MIR_DoubleShift.getBitsToShift(inst)));
4739
4740 } else {
4741 if (isRegIdx(MIR_DoubleShift.getResult(inst))) {
4742 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4743 emitSHRD_RegIdx_Reg_Imm(
4744 getBase(MIR_DoubleShift.getResult(inst)), getIndex(MIR_DoubleShift.getResult(inst)), getScale(MIR_DoubleShift.getResult(inst)), getDisp(MIR_DoubleShift.getResult(inst)),
4745 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
4746 getImm(MIR_DoubleShift.getBitsToShift(inst)));
4747
4748 } else {
4749 if (VM.VerifyAssertions && !isRegInd(MIR_DoubleShift.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4750 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4751 emitSHRD_RegInd_Reg_Imm(
4752 getBase(MIR_DoubleShift.getResult(inst)),
4753 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
4754 getImm(MIR_DoubleShift.getBitsToShift(inst)));
4755 }
4756 }
4757 }
4758 }
4759 }
4760
4761 } else {
4762 if (isGPR_Reg(MIR_DoubleShift.getResult(inst))) {
4763 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4764 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getBitsToShift(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4765 emitSHRD_Reg_Reg_Reg(
4766 getGPR_Reg(MIR_DoubleShift.getResult(inst)),
4767 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
4768 getGPR_Reg(MIR_DoubleShift.getBitsToShift(inst)));
4769
4770 } else {
4771 if (isAbs(MIR_DoubleShift.getResult(inst))) {
4772 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4773 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getBitsToShift(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4774 emitSHRD_Abs_Reg_Reg(
4775 getDisp(MIR_DoubleShift.getResult(inst)).toWord().toAddress(),
4776 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
4777 getGPR_Reg(MIR_DoubleShift.getBitsToShift(inst)));
4778
4779 } else {
4780 if (isRegDisp(MIR_DoubleShift.getResult(inst))) {
4781 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4782 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getBitsToShift(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4783 emitSHRD_RegDisp_Reg_Reg(
4784 getBase(MIR_DoubleShift.getResult(inst)), getDisp(MIR_DoubleShift.getResult(inst)),
4785 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
4786 getGPR_Reg(MIR_DoubleShift.getBitsToShift(inst)));
4787
4788 } else {
4789 if (isRegOff(MIR_DoubleShift.getResult(inst))) {
4790 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4791 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getBitsToShift(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4792 emitSHRD_RegOff_Reg_Reg(
4793 getIndex(MIR_DoubleShift.getResult(inst)), getScale(MIR_DoubleShift.getResult(inst)), getDisp(MIR_DoubleShift.getResult(inst)),
4794 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
4795 getGPR_Reg(MIR_DoubleShift.getBitsToShift(inst)));
4796
4797 } else {
4798 if (isRegIdx(MIR_DoubleShift.getResult(inst))) {
4799 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4800 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getBitsToShift(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4801 emitSHRD_RegIdx_Reg_Reg(
4802 getBase(MIR_DoubleShift.getResult(inst)), getIndex(MIR_DoubleShift.getResult(inst)), getScale(MIR_DoubleShift.getResult(inst)), getDisp(MIR_DoubleShift.getResult(inst)),
4803 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
4804 getGPR_Reg(MIR_DoubleShift.getBitsToShift(inst)));
4805
4806 } else {
4807 if (VM.VerifyAssertions && !isRegInd(MIR_DoubleShift.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4808 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4809 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getBitsToShift(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4810 emitSHRD_RegInd_Reg_Reg(
4811 getBase(MIR_DoubleShift.getResult(inst)),
4812 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
4813 getGPR_Reg(MIR_DoubleShift.getBitsToShift(inst)));
4814 }
4815 }
4816 }
4817 }
4818 }
4819 }
4820 }
4821 }
4822
4823 /**
4824 * Emit the given instruction, assuming that
4825 * it is a MIR_Unary instruction
4826 * and has a CVTSI2SD operator
4827 *
4828 * @param inst the instruction to assemble
4829 */
4830 private void doCVTSI2SD(Instruction inst) {
4831 if (isGPR_Reg(MIR_Unary.getVal(inst))) {
4832 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4833 emitCVTSI2SD_Reg_Reg(
4834 getXMM_Reg(MIR_Unary.getResult(inst)),
4835 getGPR_Reg(MIR_Unary.getVal(inst)));
4836
4837 } else {
4838 if (isAbs(MIR_Unary.getVal(inst))) {
4839 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4840 emitCVTSI2SD_Reg_Abs(
4841 getXMM_Reg(MIR_Unary.getResult(inst)),
4842 getDisp(MIR_Unary.getVal(inst)).toWord().toAddress());
4843
4844 } else {
4845 if (isRegDisp(MIR_Unary.getVal(inst))) {
4846 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4847 emitCVTSI2SD_Reg_RegDisp(
4848 getXMM_Reg(MIR_Unary.getResult(inst)),
4849 getBase(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
4850
4851 } else {
4852 if (isRegOff(MIR_Unary.getVal(inst))) {
4853 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4854 emitCVTSI2SD_Reg_RegOff(
4855 getXMM_Reg(MIR_Unary.getResult(inst)),
4856 getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
4857
4858 } else {
4859 if (isRegIdx(MIR_Unary.getVal(inst))) {
4860 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4861 emitCVTSI2SD_Reg_RegIdx(
4862 getXMM_Reg(MIR_Unary.getResult(inst)),
4863 getBase(MIR_Unary.getVal(inst)), getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
4864
4865 } else {
4866 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4867 if (VM.VerifyAssertions && !isRegInd(MIR_Unary.getVal(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4868 emitCVTSI2SD_Reg_RegInd(
4869 getXMM_Reg(MIR_Unary.getResult(inst)),
4870 getBase(MIR_Unary.getVal(inst)));
4871 }
4872 }
4873 }
4874 }
4875 }
4876 }
4877
4878 /**
4879 * Emit the given instruction, assuming that
4880 * it is a MIR_Compare instruction
4881 * and has a FCOMI operator
4882 *
4883 * @param inst the instruction to assemble
4884 */
4885 private void doFCOMI(Instruction inst) {
4886 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Compare.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4887 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Compare.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4888 emitFCOMI_Reg_Reg(
4889 getFPR_Reg(MIR_Compare.getVal1(inst)),
4890 getFPR_Reg(MIR_Compare.getVal2(inst)));
4891 }
4892
4893 /**
4894 * Emit the given instruction, assuming that
4895 * it is a MIR_CompareExchange instruction
4896 * and has a CMPXCHG operator
4897 *
4898 * @param inst the instruction to assemble
4899 */
4900 private void doCMPXCHG(Instruction inst) {
4901 if (isQuad(inst)) {
4902 if (isGPR_Reg(MIR_CompareExchange.getMemAddr(inst))) {
4903 if (VM.VerifyAssertions && !isGPR_Reg(MIR_CompareExchange.getNewValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4904 emitCMPXCHG_Reg_Reg_Quad(
4905 getGPR_Reg(MIR_CompareExchange.getMemAddr(inst)),
4906 getGPR_Reg(MIR_CompareExchange.getNewValue(inst)));
4907
4908 } else {
4909 if (isAbs(MIR_CompareExchange.getMemAddr(inst))) {
4910 if (VM.VerifyAssertions && !isGPR_Reg(MIR_CompareExchange.getNewValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4911 emitCMPXCHG_Abs_Reg_Quad(
4912 getDisp(MIR_CompareExchange.getMemAddr(inst)).toWord().toAddress(),
4913 getGPR_Reg(MIR_CompareExchange.getNewValue(inst)));
4914
4915 } else {
4916 if (isRegDisp(MIR_CompareExchange.getMemAddr(inst))) {
4917 if (VM.VerifyAssertions && !isGPR_Reg(MIR_CompareExchange.getNewValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4918 emitCMPXCHG_RegDisp_Reg_Quad(
4919 getBase(MIR_CompareExchange.getMemAddr(inst)), getDisp(MIR_CompareExchange.getMemAddr(inst)),
4920 getGPR_Reg(MIR_CompareExchange.getNewValue(inst)));
4921
4922 } else {
4923 if (isRegOff(MIR_CompareExchange.getMemAddr(inst))) {
4924 if (VM.VerifyAssertions && !isGPR_Reg(MIR_CompareExchange.getNewValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4925 emitCMPXCHG_RegOff_Reg_Quad(
4926 getIndex(MIR_CompareExchange.getMemAddr(inst)), getScale(MIR_CompareExchange.getMemAddr(inst)), getDisp(MIR_CompareExchange.getMemAddr(inst)),
4927 getGPR_Reg(MIR_CompareExchange.getNewValue(inst)));
4928
4929 } else {
4930 if (isRegIdx(MIR_CompareExchange.getMemAddr(inst))) {
4931 if (VM.VerifyAssertions && !isGPR_Reg(MIR_CompareExchange.getNewValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4932 emitCMPXCHG_RegIdx_Reg_Quad(
4933 getBase(MIR_CompareExchange.getMemAddr(inst)), getIndex(MIR_CompareExchange.getMemAddr(inst)), getScale(MIR_CompareExchange.getMemAddr(inst)), getDisp(MIR_CompareExchange.getMemAddr(inst)),
4934 getGPR_Reg(MIR_CompareExchange.getNewValue(inst)));
4935
4936 } else {
4937 if (VM.VerifyAssertions && !isRegInd(MIR_CompareExchange.getMemAddr(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4938 if (VM.VerifyAssertions && !isGPR_Reg(MIR_CompareExchange.getNewValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4939 emitCMPXCHG_RegInd_Reg_Quad(
4940 getBase(MIR_CompareExchange.getMemAddr(inst)),
4941 getGPR_Reg(MIR_CompareExchange.getNewValue(inst)));
4942 }
4943 }
4944 }
4945 }
4946 }
4947
4948 } else {
4949 if (isGPR_Reg(MIR_CompareExchange.getMemAddr(inst))) {
4950 if (VM.VerifyAssertions && !isGPR_Reg(MIR_CompareExchange.getNewValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4951 emitCMPXCHG_Reg_Reg(
4952 getGPR_Reg(MIR_CompareExchange.getMemAddr(inst)),
4953 getGPR_Reg(MIR_CompareExchange.getNewValue(inst)));
4954
4955 } else {
4956 if (isAbs(MIR_CompareExchange.getMemAddr(inst))) {
4957 if (VM.VerifyAssertions && !isGPR_Reg(MIR_CompareExchange.getNewValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4958 emitCMPXCHG_Abs_Reg(
4959 getDisp(MIR_CompareExchange.getMemAddr(inst)).toWord().toAddress(),
4960 getGPR_Reg(MIR_CompareExchange.getNewValue(inst)));
4961
4962 } else {
4963 if (isRegDisp(MIR_CompareExchange.getMemAddr(inst))) {
4964 if (VM.VerifyAssertions && !isGPR_Reg(MIR_CompareExchange.getNewValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4965 emitCMPXCHG_RegDisp_Reg(
4966 getBase(MIR_CompareExchange.getMemAddr(inst)), getDisp(MIR_CompareExchange.getMemAddr(inst)),
4967 getGPR_Reg(MIR_CompareExchange.getNewValue(inst)));
4968
4969 } else {
4970 if (isRegOff(MIR_CompareExchange.getMemAddr(inst))) {
4971 if (VM.VerifyAssertions && !isGPR_Reg(MIR_CompareExchange.getNewValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4972 emitCMPXCHG_RegOff_Reg(
4973 getIndex(MIR_CompareExchange.getMemAddr(inst)), getScale(MIR_CompareExchange.getMemAddr(inst)), getDisp(MIR_CompareExchange.getMemAddr(inst)),
4974 getGPR_Reg(MIR_CompareExchange.getNewValue(inst)));
4975
4976 } else {
4977 if (isRegIdx(MIR_CompareExchange.getMemAddr(inst))) {
4978 if (VM.VerifyAssertions && !isGPR_Reg(MIR_CompareExchange.getNewValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4979 emitCMPXCHG_RegIdx_Reg(
4980 getBase(MIR_CompareExchange.getMemAddr(inst)), getIndex(MIR_CompareExchange.getMemAddr(inst)), getScale(MIR_CompareExchange.getMemAddr(inst)), getDisp(MIR_CompareExchange.getMemAddr(inst)),
4981 getGPR_Reg(MIR_CompareExchange.getNewValue(inst)));
4982
4983 } else {
4984 if (VM.VerifyAssertions && !isRegInd(MIR_CompareExchange.getMemAddr(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4985 if (VM.VerifyAssertions && !isGPR_Reg(MIR_CompareExchange.getNewValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
4986 emitCMPXCHG_RegInd_Reg(
4987 getBase(MIR_CompareExchange.getMemAddr(inst)),
4988 getGPR_Reg(MIR_CompareExchange.getNewValue(inst)));
4989 }
4990 }
4991 }
4992 }
4993 }
4994 }
4995 }
4996
4997 /**
4998 * Emit the given instruction, assuming that
4999 * it is a MIR_Test instruction
5000 * and has a BT operator
5001 *
5002 * @param inst the instruction to assemble
5003 */
5004 private void doBT(Instruction inst) {
5005 if (isImm(MIR_Test.getVal2(inst))) {
5006 if (isGPR_Reg(MIR_Test.getVal1(inst))) {
5007 emitBT_Reg_Imm(
5008 getGPR_Reg(MIR_Test.getVal1(inst)),
5009 getImm(MIR_Test.getVal2(inst)));
5010
5011 } else {
5012 if (isAbs(MIR_Test.getVal1(inst))) {
5013 emitBT_Abs_Imm(
5014 getDisp(MIR_Test.getVal1(inst)).toWord().toAddress(),
5015 getImm(MIR_Test.getVal2(inst)));
5016
5017 } else {
5018 if (isRegDisp(MIR_Test.getVal1(inst))) {
5019 emitBT_RegDisp_Imm(
5020 getBase(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
5021 getImm(MIR_Test.getVal2(inst)));
5022
5023 } else {
5024 if (isRegOff(MIR_Test.getVal1(inst))) {
5025 emitBT_RegOff_Imm(
5026 getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
5027 getImm(MIR_Test.getVal2(inst)));
5028
5029 } else {
5030 if (isRegIdx(MIR_Test.getVal1(inst))) {
5031 emitBT_RegIdx_Imm(
5032 getBase(MIR_Test.getVal1(inst)), getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
5033 getImm(MIR_Test.getVal2(inst)));
5034
5035 } else {
5036 if (VM.VerifyAssertions && !isRegInd(MIR_Test.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5037 emitBT_RegInd_Imm(
5038 getBase(MIR_Test.getVal1(inst)),
5039 getImm(MIR_Test.getVal2(inst)));
5040 }
5041 }
5042 }
5043 }
5044 }
5045
5046 } else {
5047 if (isGPR_Reg(MIR_Test.getVal1(inst))) {
5048 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5049 emitBT_Reg_Reg(
5050 getGPR_Reg(MIR_Test.getVal1(inst)),
5051 getGPR_Reg(MIR_Test.getVal2(inst)));
5052
5053 } else {
5054 if (isAbs(MIR_Test.getVal1(inst))) {
5055 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5056 emitBT_Abs_Reg(
5057 getDisp(MIR_Test.getVal1(inst)).toWord().toAddress(),
5058 getGPR_Reg(MIR_Test.getVal2(inst)));
5059
5060 } else {
5061 if (isRegDisp(MIR_Test.getVal1(inst))) {
5062 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5063 emitBT_RegDisp_Reg(
5064 getBase(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
5065 getGPR_Reg(MIR_Test.getVal2(inst)));
5066
5067 } else {
5068 if (isRegOff(MIR_Test.getVal1(inst))) {
5069 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5070 emitBT_RegOff_Reg(
5071 getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
5072 getGPR_Reg(MIR_Test.getVal2(inst)));
5073
5074 } else {
5075 if (isRegIdx(MIR_Test.getVal1(inst))) {
5076 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5077 emitBT_RegIdx_Reg(
5078 getBase(MIR_Test.getVal1(inst)), getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
5079 getGPR_Reg(MIR_Test.getVal2(inst)));
5080
5081 } else {
5082 if (VM.VerifyAssertions && !isRegInd(MIR_Test.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5083 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5084 emitBT_RegInd_Reg(
5085 getBase(MIR_Test.getVal1(inst)),
5086 getGPR_Reg(MIR_Test.getVal2(inst)));
5087 }
5088 }
5089 }
5090 }
5091 }
5092 }
5093 }
5094
5095 /**
5096 * Emit the given instruction, assuming that
5097 * it is a MIR_Move instruction
5098 * and has a MOVSS operator
5099 *
5100 * @param inst the instruction to assemble
5101 */
5102 private void doMOVSS(Instruction inst) {
5103 if (isXMM_Reg(MIR_Move.getResult(inst))) {
5104 if (isXMM_Reg(MIR_Move.getValue(inst))) {
5105 emitMOVSS_Reg_Reg(
5106 getXMM_Reg(MIR_Move.getResult(inst)),
5107 getXMM_Reg(MIR_Move.getValue(inst)));
5108
5109 } else {
5110 if (isAbs(MIR_Move.getValue(inst))) {
5111 emitMOVSS_Reg_Abs(
5112 getXMM_Reg(MIR_Move.getResult(inst)),
5113 getDisp(MIR_Move.getValue(inst)).toWord().toAddress());
5114
5115 } else {
5116 if (isRegDisp(MIR_Move.getValue(inst))) {
5117 emitMOVSS_Reg_RegDisp(
5118 getXMM_Reg(MIR_Move.getResult(inst)),
5119 getBase(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
5120
5121 } else {
5122 if (isRegOff(MIR_Move.getValue(inst))) {
5123 emitMOVSS_Reg_RegOff(
5124 getXMM_Reg(MIR_Move.getResult(inst)),
5125 getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
5126
5127 } else {
5128 if (isRegIdx(MIR_Move.getValue(inst))) {
5129 emitMOVSS_Reg_RegIdx(
5130 getXMM_Reg(MIR_Move.getResult(inst)),
5131 getBase(MIR_Move.getValue(inst)), getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
5132
5133 } else {
5134 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5135 emitMOVSS_Reg_RegInd(
5136 getXMM_Reg(MIR_Move.getResult(inst)),
5137 getBase(MIR_Move.getValue(inst)));
5138 }
5139 }
5140 }
5141 }
5142 }
5143
5144 } else {
5145 if (isAbs(MIR_Move.getResult(inst))) {
5146 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5147 emitMOVSS_Abs_Reg(
5148 getDisp(MIR_Move.getResult(inst)).toWord().toAddress(),
5149 getXMM_Reg(MIR_Move.getValue(inst)));
5150
5151 } else {
5152 if (isRegDisp(MIR_Move.getResult(inst))) {
5153 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5154 emitMOVSS_RegDisp_Reg(
5155 getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
5156 getXMM_Reg(MIR_Move.getValue(inst)));
5157
5158 } else {
5159 if (isRegOff(MIR_Move.getResult(inst))) {
5160 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5161 emitMOVSS_RegOff_Reg(
5162 getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
5163 getXMM_Reg(MIR_Move.getValue(inst)));
5164
5165 } else {
5166 if (isRegIdx(MIR_Move.getResult(inst))) {
5167 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5168 emitMOVSS_RegIdx_Reg(
5169 getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
5170 getXMM_Reg(MIR_Move.getValue(inst)));
5171
5172 } else {
5173 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5174 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5175 emitMOVSS_RegInd_Reg(
5176 getBase(MIR_Move.getResult(inst)),
5177 getXMM_Reg(MIR_Move.getValue(inst)));
5178 }
5179 }
5180 }
5181 }
5182 }
5183 }
5184
5185 /**
5186 * Emit the given instruction, assuming that
5187 * it is a MIR_Unary instruction
5188 * and has a CVTTSS2SI operator
5189 *
5190 * @param inst the instruction to assemble
5191 */
5192 private void doCVTTSS2SI(Instruction inst) {
5193 if (isQuad(inst)) {
5194 if (isXMM_Reg(MIR_Unary.getVal(inst))) {
5195 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5196 emitCVTTSS2SI_Reg_Reg_Quad(
5197 getGPR_Reg(MIR_Unary.getResult(inst)),
5198 getXMM_Reg(MIR_Unary.getVal(inst)));
5199
5200 } else {
5201 if (isAbs(MIR_Unary.getVal(inst))) {
5202 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5203 emitCVTTSS2SI_Reg_Abs_Quad(
5204 getGPR_Reg(MIR_Unary.getResult(inst)),
5205 getDisp(MIR_Unary.getVal(inst)).toWord().toAddress());
5206
5207 } else {
5208 if (isRegDisp(MIR_Unary.getVal(inst))) {
5209 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5210 emitCVTTSS2SI_Reg_RegDisp_Quad(
5211 getGPR_Reg(MIR_Unary.getResult(inst)),
5212 getBase(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
5213
5214 } else {
5215 if (isRegOff(MIR_Unary.getVal(inst))) {
5216 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5217 emitCVTTSS2SI_Reg_RegOff_Quad(
5218 getGPR_Reg(MIR_Unary.getResult(inst)),
5219 getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
5220
5221 } else {
5222 if (isRegIdx(MIR_Unary.getVal(inst))) {
5223 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5224 emitCVTTSS2SI_Reg_RegIdx_Quad(
5225 getGPR_Reg(MIR_Unary.getResult(inst)),
5226 getBase(MIR_Unary.getVal(inst)), getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
5227
5228 } else {
5229 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5230 if (VM.VerifyAssertions && !isRegInd(MIR_Unary.getVal(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5231 emitCVTTSS2SI_Reg_RegInd_Quad(
5232 getGPR_Reg(MIR_Unary.getResult(inst)),
5233 getBase(MIR_Unary.getVal(inst)));
5234 }
5235 }
5236 }
5237 }
5238 }
5239
5240 } else {
5241 if (isXMM_Reg(MIR_Unary.getVal(inst))) {
5242 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5243 emitCVTTSS2SI_Reg_Reg(
5244 getGPR_Reg(MIR_Unary.getResult(inst)),
5245 getXMM_Reg(MIR_Unary.getVal(inst)));
5246
5247 } else {
5248 if (isAbs(MIR_Unary.getVal(inst))) {
5249 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5250 emitCVTTSS2SI_Reg_Abs(
5251 getGPR_Reg(MIR_Unary.getResult(inst)),
5252 getDisp(MIR_Unary.getVal(inst)).toWord().toAddress());
5253
5254 } else {
5255 if (isRegDisp(MIR_Unary.getVal(inst))) {
5256 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5257 emitCVTTSS2SI_Reg_RegDisp(
5258 getGPR_Reg(MIR_Unary.getResult(inst)),
5259 getBase(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
5260
5261 } else {
5262 if (isRegOff(MIR_Unary.getVal(inst))) {
5263 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5264 emitCVTTSS2SI_Reg_RegOff(
5265 getGPR_Reg(MIR_Unary.getResult(inst)),
5266 getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
5267
5268 } else {
5269 if (isRegIdx(MIR_Unary.getVal(inst))) {
5270 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5271 emitCVTTSS2SI_Reg_RegIdx(
5272 getGPR_Reg(MIR_Unary.getResult(inst)),
5273 getBase(MIR_Unary.getVal(inst)), getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
5274
5275 } else {
5276 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5277 if (VM.VerifyAssertions && !isRegInd(MIR_Unary.getVal(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5278 emitCVTTSS2SI_Reg_RegInd(
5279 getGPR_Reg(MIR_Unary.getResult(inst)),
5280 getBase(MIR_Unary.getVal(inst)));
5281 }
5282 }
5283 }
5284 }
5285 }
5286 }
5287 }
5288
5289 /**
5290 * Emit the given instruction, assuming that
5291 * it is a MIR_Empty instruction
5292 * and has a FINIT operator
5293 *
5294 * @param inst the instruction to assemble
5295 */
5296 private void doFINIT(Instruction inst) {
5297 emitFINIT();
5298 }
5299
5300 /**
5301 * Emit the given instruction, assuming that
5302 * it is a MIR_Compare instruction
5303 * and has a FUCOMI operator
5304 *
5305 * @param inst the instruction to assemble
5306 */
5307 private void doFUCOMI(Instruction inst) {
5308 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Compare.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5309 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Compare.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5310 emitFUCOMI_Reg_Reg(
5311 getFPR_Reg(MIR_Compare.getVal1(inst)),
5312 getFPR_Reg(MIR_Compare.getVal2(inst)));
5313 }
5314
5315 /**
5316 * Emit the given instruction, assuming that
5317 * it is a MIR_Unary instruction
5318 * and has a MOVSX operator
5319 *
5320 * @param inst the instruction to assemble
5321 */
5322 private void doMOVSX(Instruction inst) {
5323 if (isByte(inst)) {
5324 if (isGPR_Reg(MIR_Unary.getVal(inst))) {
5325 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5326 emitMOVSX_Reg_Reg_Byte(
5327 getGPR_Reg(MIR_Unary.getResult(inst)),
5328 getGPR_Reg(MIR_Unary.getVal(inst)));
5329
5330 } else {
5331 if (isAbs(MIR_Unary.getVal(inst))) {
5332 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5333 emitMOVSX_Reg_Abs_Byte(
5334 getGPR_Reg(MIR_Unary.getResult(inst)),
5335 getDisp(MIR_Unary.getVal(inst)).toWord().toAddress());
5336
5337 } else {
5338 if (isRegDisp(MIR_Unary.getVal(inst))) {
5339 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5340 emitMOVSX_Reg_RegDisp_Byte(
5341 getGPR_Reg(MIR_Unary.getResult(inst)),
5342 getBase(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
5343
5344 } else {
5345 if (isRegOff(MIR_Unary.getVal(inst))) {
5346 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5347 emitMOVSX_Reg_RegOff_Byte(
5348 getGPR_Reg(MIR_Unary.getResult(inst)),
5349 getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
5350
5351 } else {
5352 if (isRegIdx(MIR_Unary.getVal(inst))) {
5353 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5354 emitMOVSX_Reg_RegIdx_Byte(
5355 getGPR_Reg(MIR_Unary.getResult(inst)),
5356 getBase(MIR_Unary.getVal(inst)), getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
5357
5358 } else {
5359 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5360 if (VM.VerifyAssertions && !isRegInd(MIR_Unary.getVal(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5361 emitMOVSX_Reg_RegInd_Byte(
5362 getGPR_Reg(MIR_Unary.getResult(inst)),
5363 getBase(MIR_Unary.getVal(inst)));
5364 }
5365 }
5366 }
5367 }
5368 }
5369
5370 } else {
5371 if (isGPR_Reg(MIR_Unary.getVal(inst))) {
5372 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5373 if (VM.VerifyAssertions && !isWord(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
5374 emitMOVSX_Reg_Reg_Word(
5375 getGPR_Reg(MIR_Unary.getResult(inst)),
5376 getGPR_Reg(MIR_Unary.getVal(inst)));
5377
5378 } else {
5379 if (isAbs(MIR_Unary.getVal(inst))) {
5380 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5381 if (VM.VerifyAssertions && !isWord(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
5382 emitMOVSX_Reg_Abs_Word(
5383 getGPR_Reg(MIR_Unary.getResult(inst)),
5384 getDisp(MIR_Unary.getVal(inst)).toWord().toAddress());
5385
5386 } else {
5387 if (isRegDisp(MIR_Unary.getVal(inst))) {
5388 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5389 if (VM.VerifyAssertions && !isWord(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
5390 emitMOVSX_Reg_RegDisp_Word(
5391 getGPR_Reg(MIR_Unary.getResult(inst)),
5392 getBase(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
5393
5394 } else {
5395 if (isRegOff(MIR_Unary.getVal(inst))) {
5396 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5397 if (VM.VerifyAssertions && !isWord(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
5398 emitMOVSX_Reg_RegOff_Word(
5399 getGPR_Reg(MIR_Unary.getResult(inst)),
5400 getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
5401
5402 } else {
5403 if (isRegIdx(MIR_Unary.getVal(inst))) {
5404 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5405 if (VM.VerifyAssertions && !isWord(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
5406 emitMOVSX_Reg_RegIdx_Word(
5407 getGPR_Reg(MIR_Unary.getResult(inst)),
5408 getBase(MIR_Unary.getVal(inst)), getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
5409
5410 } else {
5411 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5412 if (VM.VerifyAssertions && !isRegInd(MIR_Unary.getVal(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5413 if (VM.VerifyAssertions && !isWord(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
5414 emitMOVSX_Reg_RegInd_Word(
5415 getGPR_Reg(MIR_Unary.getResult(inst)),
5416 getBase(MIR_Unary.getVal(inst)));
5417 }
5418 }
5419 }
5420 }
5421 }
5422 }
5423 }
5424
5425 /**
5426 * Emit the given instruction, assuming that
5427 * it is a MIR_CompareExchange8B instruction
5428 * and has a CMPXCHG8B operator
5429 *
5430 * @param inst the instruction to assemble
5431 */
5432 private void doCMPXCHG8B(Instruction inst) {
5433 if (isRegDisp(MIR_CompareExchange8B.getMemAddr(inst))) {
5434 emitCMPXCHG8B_RegDisp(
5435 getBase(MIR_CompareExchange8B.getMemAddr(inst)), getDisp(MIR_CompareExchange8B.getMemAddr(inst)));
5436
5437 } else {
5438 if (isRegOff(MIR_CompareExchange8B.getMemAddr(inst))) {
5439 emitCMPXCHG8B_RegOff(
5440 getIndex(MIR_CompareExchange8B.getMemAddr(inst)), getScale(MIR_CompareExchange8B.getMemAddr(inst)), getDisp(MIR_CompareExchange8B.getMemAddr(inst)));
5441
5442 } else {
5443 if (isRegIdx(MIR_CompareExchange8B.getMemAddr(inst))) {
5444 emitCMPXCHG8B_RegIdx(
5445 getBase(MIR_CompareExchange8B.getMemAddr(inst)), getIndex(MIR_CompareExchange8B.getMemAddr(inst)), getScale(MIR_CompareExchange8B.getMemAddr(inst)), getDisp(MIR_CompareExchange8B.getMemAddr(inst)));
5446
5447 } else {
5448 if (VM.VerifyAssertions && !isRegInd(MIR_CompareExchange8B.getMemAddr(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5449 emitCMPXCHG8B_RegInd(
5450 getBase(MIR_CompareExchange8B.getMemAddr(inst)));
5451 }
5452 }
5453 }
5454 }
5455
5456 /**
5457 * Emit the given instruction, assuming that
5458 * it is a MIR_Unary instruction
5459 * and has a CVTSI2SS operator
5460 *
5461 * @param inst the instruction to assemble
5462 */
5463 private void doCVTSI2SS(Instruction inst) {
5464 if (isQuad(inst)) {
5465 if (isGPR_Reg(MIR_Unary.getVal(inst))) {
5466 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5467 emitCVTSI2SS_Reg_Reg_Quad(
5468 getXMM_Reg(MIR_Unary.getResult(inst)),
5469 getGPR_Reg(MIR_Unary.getVal(inst)));
5470
5471 } else {
5472 if (isAbs(MIR_Unary.getVal(inst))) {
5473 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5474 emitCVTSI2SS_Reg_Abs_Quad(
5475 getXMM_Reg(MIR_Unary.getResult(inst)),
5476 getDisp(MIR_Unary.getVal(inst)).toWord().toAddress());
5477
5478 } else {
5479 if (isRegDisp(MIR_Unary.getVal(inst))) {
5480 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5481 emitCVTSI2SS_Reg_RegDisp_Quad(
5482 getXMM_Reg(MIR_Unary.getResult(inst)),
5483 getBase(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
5484
5485 } else {
5486 if (isRegOff(MIR_Unary.getVal(inst))) {
5487 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5488 emitCVTSI2SS_Reg_RegOff_Quad(
5489 getXMM_Reg(MIR_Unary.getResult(inst)),
5490 getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
5491
5492 } else {
5493 if (isRegIdx(MIR_Unary.getVal(inst))) {
5494 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5495 emitCVTSI2SS_Reg_RegIdx_Quad(
5496 getXMM_Reg(MIR_Unary.getResult(inst)),
5497 getBase(MIR_Unary.getVal(inst)), getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
5498
5499 } else {
5500 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5501 if (VM.VerifyAssertions && !isRegInd(MIR_Unary.getVal(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5502 emitCVTSI2SS_Reg_RegInd_Quad(
5503 getXMM_Reg(MIR_Unary.getResult(inst)),
5504 getBase(MIR_Unary.getVal(inst)));
5505 }
5506 }
5507 }
5508 }
5509 }
5510
5511 } else {
5512 if (isGPR_Reg(MIR_Unary.getVal(inst))) {
5513 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5514 emitCVTSI2SS_Reg_Reg(
5515 getXMM_Reg(MIR_Unary.getResult(inst)),
5516 getGPR_Reg(MIR_Unary.getVal(inst)));
5517
5518 } else {
5519 if (isAbs(MIR_Unary.getVal(inst))) {
5520 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5521 emitCVTSI2SS_Reg_Abs(
5522 getXMM_Reg(MIR_Unary.getResult(inst)),
5523 getDisp(MIR_Unary.getVal(inst)).toWord().toAddress());
5524
5525 } else {
5526 if (isRegDisp(MIR_Unary.getVal(inst))) {
5527 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5528 emitCVTSI2SS_Reg_RegDisp(
5529 getXMM_Reg(MIR_Unary.getResult(inst)),
5530 getBase(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
5531
5532 } else {
5533 if (isRegOff(MIR_Unary.getVal(inst))) {
5534 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5535 emitCVTSI2SS_Reg_RegOff(
5536 getXMM_Reg(MIR_Unary.getResult(inst)),
5537 getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
5538
5539 } else {
5540 if (isRegIdx(MIR_Unary.getVal(inst))) {
5541 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5542 emitCVTSI2SS_Reg_RegIdx(
5543 getXMM_Reg(MIR_Unary.getResult(inst)),
5544 getBase(MIR_Unary.getVal(inst)), getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
5545
5546 } else {
5547 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5548 if (VM.VerifyAssertions && !isRegInd(MIR_Unary.getVal(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5549 emitCVTSI2SS_Reg_RegInd(
5550 getXMM_Reg(MIR_Unary.getResult(inst)),
5551 getBase(MIR_Unary.getVal(inst)));
5552 }
5553 }
5554 }
5555 }
5556 }
5557 }
5558 }
5559
5560 /**
5561 * Emit the given instruction, assuming that
5562 * it is a MIR_UnaryNoRes instruction
5563 * and has a FNSTCW operator
5564 *
5565 * @param inst the instruction to assemble
5566 */
5567 private void doFNSTCW(Instruction inst) {
5568 if (isAbs(MIR_UnaryNoRes.getVal(inst))) {
5569 emitFNSTCW_Abs(
5570 getDisp(MIR_UnaryNoRes.getVal(inst)).toWord().toAddress());
5571
5572 } else {
5573 if (isRegDisp(MIR_UnaryNoRes.getVal(inst))) {
5574 emitFNSTCW_RegDisp(
5575 getBase(MIR_UnaryNoRes.getVal(inst)), getDisp(MIR_UnaryNoRes.getVal(inst)));
5576
5577 } else {
5578 if (isRegOff(MIR_UnaryNoRes.getVal(inst))) {
5579 emitFNSTCW_RegOff(
5580 getIndex(MIR_UnaryNoRes.getVal(inst)), getScale(MIR_UnaryNoRes.getVal(inst)), getDisp(MIR_UnaryNoRes.getVal(inst)));
5581
5582 } else {
5583 if (isRegIdx(MIR_UnaryNoRes.getVal(inst))) {
5584 emitFNSTCW_RegIdx(
5585 getBase(MIR_UnaryNoRes.getVal(inst)), getIndex(MIR_UnaryNoRes.getVal(inst)), getScale(MIR_UnaryNoRes.getVal(inst)), getDisp(MIR_UnaryNoRes.getVal(inst)));
5586
5587 } else {
5588 if (VM.VerifyAssertions && !isRegInd(MIR_UnaryNoRes.getVal(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5589 emitFNSTCW_RegInd(
5590 getBase(MIR_UnaryNoRes.getVal(inst)));
5591 }
5592 }
5593 }
5594 }
5595 }
5596
5597 /**
5598 * Emit the given instruction, assuming that
5599 * it is a MIR_Call instruction
5600 * and has a CALL operator
5601 *
5602 * @param inst the instruction to assemble
5603 */
5604 private void doCALL(Instruction inst) {
5605 if (isImm(MIR_Call.getTarget(inst))) {
5606 emitCALL_Imm(
5607 getImm(MIR_Call.getTarget(inst)));
5608
5609 } else {
5610 if (isGPR_Reg(MIR_Call.getTarget(inst))) {
5611 emitCALL_Reg(
5612 getGPR_Reg(MIR_Call.getTarget(inst)));
5613
5614 } else {
5615 if (isAbs(MIR_Call.getTarget(inst))) {
5616 emitCALL_Abs(
5617 getDisp(MIR_Call.getTarget(inst)).toWord().toAddress());
5618
5619 } else {
5620 if (isRegDisp(MIR_Call.getTarget(inst))) {
5621 emitCALL_RegDisp(
5622 getBase(MIR_Call.getTarget(inst)), getDisp(MIR_Call.getTarget(inst)));
5623
5624 } else {
5625 if (isRegOff(MIR_Call.getTarget(inst))) {
5626 emitCALL_RegOff(
5627 getIndex(MIR_Call.getTarget(inst)), getScale(MIR_Call.getTarget(inst)), getDisp(MIR_Call.getTarget(inst)));
5628
5629 } else {
5630 if (isRegIdx(MIR_Call.getTarget(inst))) {
5631 emitCALL_RegIdx(
5632 getBase(MIR_Call.getTarget(inst)), getIndex(MIR_Call.getTarget(inst)), getScale(MIR_Call.getTarget(inst)), getDisp(MIR_Call.getTarget(inst)));
5633
5634 } else {
5635 if (isRegInd(MIR_Call.getTarget(inst))) {
5636 emitCALL_RegInd(
5637 getBase(MIR_Call.getTarget(inst)));
5638
5639 } else {
5640 if (isLabel(MIR_Call.getTarget(inst))) {
5641 emitCALL_Label(
5642 getLabel(MIR_Call.getTarget(inst)));
5643
5644 } else {
5645 if (VM.VerifyAssertions && !isImmOrLabel(MIR_Call.getTarget(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5646 emitCALL_ImmOrLabel(
5647 getImm(MIR_Call.getTarget(inst)), getLabel(MIR_Call.getTarget(inst)));
5648 }
5649 }
5650 }
5651 }
5652 }
5653 }
5654 }
5655 }
5656 }
5657
5658 /**
5659 * Emit the given instruction, assuming that
5660 * it is a MIR_Unary instruction
5661 * and has a MOVZXQ operator
5662 *
5663 * @param inst the instruction to assemble
5664 */
5665 private void doMOVZXQ(Instruction inst) {
5666 if (isByte(inst)) {
5667 if (isGPR_Reg(MIR_Unary.getVal(inst))) {
5668 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5669 emitMOVZXQ_Reg_Reg_Byte(
5670 getGPR_Reg(MIR_Unary.getResult(inst)),
5671 getGPR_Reg(MIR_Unary.getVal(inst)));
5672
5673 } else {
5674 if (isAbs(MIR_Unary.getVal(inst))) {
5675 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5676 emitMOVZXQ_Reg_Abs_Byte(
5677 getGPR_Reg(MIR_Unary.getResult(inst)),
5678 getDisp(MIR_Unary.getVal(inst)).toWord().toAddress());
5679
5680 } else {
5681 if (isRegDisp(MIR_Unary.getVal(inst))) {
5682 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5683 emitMOVZXQ_Reg_RegDisp_Byte(
5684 getGPR_Reg(MIR_Unary.getResult(inst)),
5685 getBase(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
5686
5687 } else {
5688 if (isRegOff(MIR_Unary.getVal(inst))) {
5689 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5690 emitMOVZXQ_Reg_RegOff_Byte(
5691 getGPR_Reg(MIR_Unary.getResult(inst)),
5692 getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
5693
5694 } else {
5695 if (isRegIdx(MIR_Unary.getVal(inst))) {
5696 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5697 emitMOVZXQ_Reg_RegIdx_Byte(
5698 getGPR_Reg(MIR_Unary.getResult(inst)),
5699 getBase(MIR_Unary.getVal(inst)), getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
5700
5701 } else {
5702 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5703 if (VM.VerifyAssertions && !isRegInd(MIR_Unary.getVal(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5704 emitMOVZXQ_Reg_RegInd_Byte(
5705 getGPR_Reg(MIR_Unary.getResult(inst)),
5706 getBase(MIR_Unary.getVal(inst)));
5707 }
5708 }
5709 }
5710 }
5711 }
5712
5713 } else {
5714 if (isGPR_Reg(MIR_Unary.getVal(inst))) {
5715 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5716 if (VM.VerifyAssertions && !isWord(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
5717 emitMOVZXQ_Reg_Reg_Word(
5718 getGPR_Reg(MIR_Unary.getResult(inst)),
5719 getGPR_Reg(MIR_Unary.getVal(inst)));
5720
5721 } else {
5722 if (isAbs(MIR_Unary.getVal(inst))) {
5723 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5724 if (VM.VerifyAssertions && !isWord(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
5725 emitMOVZXQ_Reg_Abs_Word(
5726 getGPR_Reg(MIR_Unary.getResult(inst)),
5727 getDisp(MIR_Unary.getVal(inst)).toWord().toAddress());
5728
5729 } else {
5730 if (isRegDisp(MIR_Unary.getVal(inst))) {
5731 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5732 if (VM.VerifyAssertions && !isWord(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
5733 emitMOVZXQ_Reg_RegDisp_Word(
5734 getGPR_Reg(MIR_Unary.getResult(inst)),
5735 getBase(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
5736
5737 } else {
5738 if (isRegOff(MIR_Unary.getVal(inst))) {
5739 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5740 if (VM.VerifyAssertions && !isWord(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
5741 emitMOVZXQ_Reg_RegOff_Word(
5742 getGPR_Reg(MIR_Unary.getResult(inst)),
5743 getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
5744
5745 } else {
5746 if (isRegIdx(MIR_Unary.getVal(inst))) {
5747 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5748 if (VM.VerifyAssertions && !isWord(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
5749 emitMOVZXQ_Reg_RegIdx_Word(
5750 getGPR_Reg(MIR_Unary.getResult(inst)),
5751 getBase(MIR_Unary.getVal(inst)), getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
5752
5753 } else {
5754 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5755 if (VM.VerifyAssertions && !isRegInd(MIR_Unary.getVal(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5756 if (VM.VerifyAssertions && !isWord(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
5757 emitMOVZXQ_Reg_RegInd_Word(
5758 getGPR_Reg(MIR_Unary.getResult(inst)),
5759 getBase(MIR_Unary.getVal(inst)));
5760 }
5761 }
5762 }
5763 }
5764 }
5765 }
5766 }
5767
5768 /**
5769 * Emit the given instruction, assuming that
5770 * it is a MIR_Move instruction
5771 * and has a FIST operator
5772 *
5773 * @param inst the instruction to assemble
5774 */
5775 private void doFIST(Instruction inst) {
5776 if (isWord(inst)) {
5777 if (isAbs(MIR_Move.getResult(inst))) {
5778 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5779 emitFIST_Abs_Reg_Word(
5780 getDisp(MIR_Move.getResult(inst)).toWord().toAddress(),
5781 getFPR_Reg(MIR_Move.getValue(inst)));
5782
5783 } else {
5784 if (isRegDisp(MIR_Move.getResult(inst))) {
5785 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5786 emitFIST_RegDisp_Reg_Word(
5787 getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
5788 getFPR_Reg(MIR_Move.getValue(inst)));
5789
5790 } else {
5791 if (isRegOff(MIR_Move.getResult(inst))) {
5792 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5793 emitFIST_RegOff_Reg_Word(
5794 getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
5795 getFPR_Reg(MIR_Move.getValue(inst)));
5796
5797 } else {
5798 if (isRegIdx(MIR_Move.getResult(inst))) {
5799 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5800 emitFIST_RegIdx_Reg_Word(
5801 getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
5802 getFPR_Reg(MIR_Move.getValue(inst)));
5803
5804 } else {
5805 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5806 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5807 emitFIST_RegInd_Reg_Word(
5808 getBase(MIR_Move.getResult(inst)),
5809 getFPR_Reg(MIR_Move.getValue(inst)));
5810 }
5811 }
5812 }
5813 }
5814
5815 } else {
5816 if (isAbs(MIR_Move.getResult(inst))) {
5817 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5818 emitFIST_Abs_Reg(
5819 getDisp(MIR_Move.getResult(inst)).toWord().toAddress(),
5820 getFPR_Reg(MIR_Move.getValue(inst)));
5821
5822 } else {
5823 if (isRegDisp(MIR_Move.getResult(inst))) {
5824 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5825 emitFIST_RegDisp_Reg(
5826 getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
5827 getFPR_Reg(MIR_Move.getValue(inst)));
5828
5829 } else {
5830 if (isRegOff(MIR_Move.getResult(inst))) {
5831 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5832 emitFIST_RegOff_Reg(
5833 getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
5834 getFPR_Reg(MIR_Move.getValue(inst)));
5835
5836 } else {
5837 if (isRegIdx(MIR_Move.getResult(inst))) {
5838 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5839 emitFIST_RegIdx_Reg(
5840 getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
5841 getFPR_Reg(MIR_Move.getValue(inst)));
5842
5843 } else {
5844 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5845 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5846 emitFIST_RegInd_Reg(
5847 getBase(MIR_Move.getResult(inst)),
5848 getFPR_Reg(MIR_Move.getValue(inst)));
5849 }
5850 }
5851 }
5852 }
5853 }
5854 }
5855
5856 /**
5857 * Emit the given instruction, assuming that
5858 * it is a MIR_BinaryAcc instruction
5859 * and has a FDIV operator
5860 *
5861 * @param inst the instruction to assemble
5862 */
5863 private void doFDIV(Instruction inst) {
5864 if (isQuad(inst)) {
5865 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
5866 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5867 emitFDIV_Reg_Abs_Quad(
5868 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
5869 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
5870
5871 } else {
5872 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
5873 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5874 emitFDIV_Reg_RegDisp_Quad(
5875 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
5876 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
5877
5878 } else {
5879 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
5880 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5881 emitFDIV_Reg_RegOff_Quad(
5882 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
5883 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
5884
5885 } else {
5886 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
5887 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5888 emitFDIV_Reg_RegIdx_Quad(
5889 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
5890 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
5891
5892 } else {
5893 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5894 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5895 emitFDIV_Reg_RegInd_Quad(
5896 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
5897 getBase(MIR_BinaryAcc.getValue(inst)));
5898 }
5899 }
5900 }
5901 }
5902
5903 } else {
5904 if (isFPR_Reg(MIR_BinaryAcc.getValue(inst))) {
5905 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5906 emitFDIV_Reg_Reg(
5907 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
5908 getFPR_Reg(MIR_BinaryAcc.getValue(inst)));
5909
5910 } else {
5911 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
5912 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5913 emitFDIV_Reg_Abs(
5914 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
5915 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
5916
5917 } else {
5918 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
5919 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5920 emitFDIV_Reg_RegDisp(
5921 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
5922 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
5923
5924 } else {
5925 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
5926 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5927 emitFDIV_Reg_RegOff(
5928 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
5929 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
5930
5931 } else {
5932 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
5933 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5934 emitFDIV_Reg_RegIdx(
5935 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
5936 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
5937
5938 } else {
5939 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5940 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5941 emitFDIV_Reg_RegInd(
5942 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
5943 getBase(MIR_BinaryAcc.getValue(inst)));
5944 }
5945 }
5946 }
5947 }
5948 }
5949 }
5950 }
5951
5952 /**
5953 * Emit the given instruction, assuming that
5954 * it is a MIR_Move instruction
5955 * and has a FISTP operator
5956 *
5957 * @param inst the instruction to assemble
5958 */
5959 private void doFISTP(Instruction inst) {
5960 if (isWord(inst)) {
5961 if (isAbs(MIR_Move.getResult(inst))) {
5962 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5963 emitFISTP_Abs_Reg_Word(
5964 getDisp(MIR_Move.getResult(inst)).toWord().toAddress(),
5965 getFPR_Reg(MIR_Move.getValue(inst)));
5966
5967 } else {
5968 if (isRegDisp(MIR_Move.getResult(inst))) {
5969 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5970 emitFISTP_RegDisp_Reg_Word(
5971 getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
5972 getFPR_Reg(MIR_Move.getValue(inst)));
5973
5974 } else {
5975 if (isRegOff(MIR_Move.getResult(inst))) {
5976 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5977 emitFISTP_RegOff_Reg_Word(
5978 getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
5979 getFPR_Reg(MIR_Move.getValue(inst)));
5980
5981 } else {
5982 if (isRegIdx(MIR_Move.getResult(inst))) {
5983 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5984 emitFISTP_RegIdx_Reg_Word(
5985 getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
5986 getFPR_Reg(MIR_Move.getValue(inst)));
5987
5988 } else {
5989 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5990 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
5991 emitFISTP_RegInd_Reg_Word(
5992 getBase(MIR_Move.getResult(inst)),
5993 getFPR_Reg(MIR_Move.getValue(inst)));
5994 }
5995 }
5996 }
5997 }
5998
5999 } else {
6000 if (isQuad(inst)) {
6001 if (isAbs(MIR_Move.getResult(inst))) {
6002 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6003 emitFISTP_Abs_Reg_Quad(
6004 getDisp(MIR_Move.getResult(inst)).toWord().toAddress(),
6005 getFPR_Reg(MIR_Move.getValue(inst)));
6006
6007 } else {
6008 if (isRegDisp(MIR_Move.getResult(inst))) {
6009 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6010 emitFISTP_RegDisp_Reg_Quad(
6011 getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
6012 getFPR_Reg(MIR_Move.getValue(inst)));
6013
6014 } else {
6015 if (isRegOff(MIR_Move.getResult(inst))) {
6016 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6017 emitFISTP_RegOff_Reg_Quad(
6018 getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
6019 getFPR_Reg(MIR_Move.getValue(inst)));
6020
6021 } else {
6022 if (isRegIdx(MIR_Move.getResult(inst))) {
6023 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6024 emitFISTP_RegIdx_Reg_Quad(
6025 getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
6026 getFPR_Reg(MIR_Move.getValue(inst)));
6027
6028 } else {
6029 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6030 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6031 emitFISTP_RegInd_Reg_Quad(
6032 getBase(MIR_Move.getResult(inst)),
6033 getFPR_Reg(MIR_Move.getValue(inst)));
6034 }
6035 }
6036 }
6037 }
6038
6039 } else {
6040 if (isAbs(MIR_Move.getResult(inst))) {
6041 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6042 emitFISTP_Abs_Reg(
6043 getDisp(MIR_Move.getResult(inst)).toWord().toAddress(),
6044 getFPR_Reg(MIR_Move.getValue(inst)));
6045
6046 } else {
6047 if (isRegDisp(MIR_Move.getResult(inst))) {
6048 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6049 emitFISTP_RegDisp_Reg(
6050 getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
6051 getFPR_Reg(MIR_Move.getValue(inst)));
6052
6053 } else {
6054 if (isRegOff(MIR_Move.getResult(inst))) {
6055 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6056 emitFISTP_RegOff_Reg(
6057 getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
6058 getFPR_Reg(MIR_Move.getValue(inst)));
6059
6060 } else {
6061 if (isRegIdx(MIR_Move.getResult(inst))) {
6062 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6063 emitFISTP_RegIdx_Reg(
6064 getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
6065 getFPR_Reg(MIR_Move.getValue(inst)));
6066
6067 } else {
6068 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6069 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6070 emitFISTP_RegInd_Reg(
6071 getBase(MIR_Move.getResult(inst)),
6072 getFPR_Reg(MIR_Move.getValue(inst)));
6073 }
6074 }
6075 }
6076 }
6077 }
6078 }
6079 }
6080
6081 /**
6082 * Emit the given instruction, assuming that
6083 * it is a MIR_BinaryAcc instruction
6084 * and has a CMPORDSD operator
6085 *
6086 * @param inst the instruction to assemble
6087 */
6088 private void doCMPORDSD(Instruction inst) {
6089 if (isXMM_Reg(MIR_BinaryAcc.getValue(inst))) {
6090 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6091 emitCMPORDSD_Reg_Reg(
6092 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
6093 getXMM_Reg(MIR_BinaryAcc.getValue(inst)));
6094
6095 } else {
6096 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
6097 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6098 emitCMPORDSD_Reg_Abs(
6099 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
6100 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
6101
6102 } else {
6103 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
6104 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6105 emitCMPORDSD_Reg_RegDisp(
6106 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
6107 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
6108
6109 } else {
6110 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
6111 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6112 emitCMPORDSD_Reg_RegOff(
6113 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
6114 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
6115
6116 } else {
6117 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
6118 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6119 emitCMPORDSD_Reg_RegIdx(
6120 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
6121 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
6122
6123 } else {
6124 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6125 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6126 emitCMPORDSD_Reg_RegInd(
6127 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
6128 getBase(MIR_BinaryAcc.getValue(inst)));
6129 }
6130 }
6131 }
6132 }
6133 }
6134 }
6135
6136 /**
6137 * Emit the given instruction, assuming that
6138 * it is a MIR_BinaryAcc instruction
6139 * and has a CMPNESD operator
6140 *
6141 * @param inst the instruction to assemble
6142 */
6143 private void doCMPNESD(Instruction inst) {
6144 if (isXMM_Reg(MIR_BinaryAcc.getValue(inst))) {
6145 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6146 emitCMPNESD_Reg_Reg(
6147 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
6148 getXMM_Reg(MIR_BinaryAcc.getValue(inst)));
6149
6150 } else {
6151 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
6152 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6153 emitCMPNESD_Reg_Abs(
6154 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
6155 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
6156
6157 } else {
6158 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
6159 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6160 emitCMPNESD_Reg_RegDisp(
6161 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
6162 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
6163
6164 } else {
6165 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
6166 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6167 emitCMPNESD_Reg_RegOff(
6168 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
6169 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
6170
6171 } else {
6172 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
6173 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6174 emitCMPNESD_Reg_RegIdx(
6175 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
6176 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
6177
6178 } else {
6179 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6180 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6181 emitCMPNESD_Reg_RegInd(
6182 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
6183 getBase(MIR_BinaryAcc.getValue(inst)));
6184 }
6185 }
6186 }
6187 }
6188 }
6189 }
6190
6191 /**
6192 * Emit the given instruction, assuming that
6193 * it is a MIR_BinaryAcc instruction
6194 * and has a XORPD operator
6195 *
6196 * @param inst the instruction to assemble
6197 */
6198 private void doXORPD(Instruction inst) {
6199 if (isXMM_Reg(MIR_BinaryAcc.getValue(inst))) {
6200 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6201 emitXORPD_Reg_Reg(
6202 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
6203 getXMM_Reg(MIR_BinaryAcc.getValue(inst)));
6204
6205 } else {
6206 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
6207 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6208 emitXORPD_Reg_Abs(
6209 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
6210 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
6211
6212 } else {
6213 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
6214 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6215 emitXORPD_Reg_RegDisp(
6216 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
6217 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
6218
6219 } else {
6220 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
6221 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6222 emitXORPD_Reg_RegOff(
6223 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
6224 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
6225
6226 } else {
6227 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
6228 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6229 emitXORPD_Reg_RegIdx(
6230 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
6231 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
6232
6233 } else {
6234 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6235 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6236 emitXORPD_Reg_RegInd(
6237 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
6238 getBase(MIR_BinaryAcc.getValue(inst)));
6239 }
6240 }
6241 }
6242 }
6243 }
6244 }
6245
6246 /**
6247 * Emit the given instruction, assuming that
6248 * it is a MIR_UnaryAcc instruction
6249 * and has a NEG operator
6250 *
6251 * @param inst the instruction to assemble
6252 */
6253 private void doNEG(Instruction inst) {
6254 if (isByte(inst)) {
6255 if (isGPR_Reg(MIR_UnaryAcc.getResult(inst))) {
6256 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_UnaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
6257 emitNEG_Reg_Byte(
6258 getGPR_Reg(MIR_UnaryAcc.getResult(inst)));
6259
6260 } else {
6261 if (isAbs(MIR_UnaryAcc.getResult(inst))) {
6262 emitNEG_Abs_Byte(
6263 getDisp(MIR_UnaryAcc.getResult(inst)).toWord().toAddress());
6264
6265 } else {
6266 if (isRegDisp(MIR_UnaryAcc.getResult(inst))) {
6267 emitNEG_RegDisp_Byte(
6268 getBase(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
6269
6270 } else {
6271 if (isRegOff(MIR_UnaryAcc.getResult(inst))) {
6272 emitNEG_RegOff_Byte(
6273 getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
6274
6275 } else {
6276 if (isRegIdx(MIR_UnaryAcc.getResult(inst))) {
6277 emitNEG_RegIdx_Byte(
6278 getBase(MIR_UnaryAcc.getResult(inst)), getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
6279
6280 } else {
6281 if (VM.VerifyAssertions && !isRegInd(MIR_UnaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6282 emitNEG_RegInd_Byte(
6283 getBase(MIR_UnaryAcc.getResult(inst)));
6284 }
6285 }
6286 }
6287 }
6288 }
6289
6290 } else {
6291 if (isWord(inst)) {
6292 if (isGPR_Reg(MIR_UnaryAcc.getResult(inst))) {
6293 emitNEG_Reg_Word(
6294 getGPR_Reg(MIR_UnaryAcc.getResult(inst)));
6295
6296 } else {
6297 if (isAbs(MIR_UnaryAcc.getResult(inst))) {
6298 emitNEG_Abs_Word(
6299 getDisp(MIR_UnaryAcc.getResult(inst)).toWord().toAddress());
6300
6301 } else {
6302 if (isRegDisp(MIR_UnaryAcc.getResult(inst))) {
6303 emitNEG_RegDisp_Word(
6304 getBase(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
6305
6306 } else {
6307 if (isRegOff(MIR_UnaryAcc.getResult(inst))) {
6308 emitNEG_RegOff_Word(
6309 getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
6310
6311 } else {
6312 if (isRegIdx(MIR_UnaryAcc.getResult(inst))) {
6313 emitNEG_RegIdx_Word(
6314 getBase(MIR_UnaryAcc.getResult(inst)), getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
6315
6316 } else {
6317 if (VM.VerifyAssertions && !isRegInd(MIR_UnaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6318 emitNEG_RegInd_Word(
6319 getBase(MIR_UnaryAcc.getResult(inst)));
6320 }
6321 }
6322 }
6323 }
6324 }
6325
6326 } else {
6327 if (isQuad(inst)) {
6328 if (isGPR_Reg(MIR_UnaryAcc.getResult(inst))) {
6329 emitNEG_Reg_Quad(
6330 getGPR_Reg(MIR_UnaryAcc.getResult(inst)));
6331
6332 } else {
6333 if (isAbs(MIR_UnaryAcc.getResult(inst))) {
6334 emitNEG_Abs_Quad(
6335 getDisp(MIR_UnaryAcc.getResult(inst)).toWord().toAddress());
6336
6337 } else {
6338 if (isRegDisp(MIR_UnaryAcc.getResult(inst))) {
6339 emitNEG_RegDisp_Quad(
6340 getBase(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
6341
6342 } else {
6343 if (isRegOff(MIR_UnaryAcc.getResult(inst))) {
6344 emitNEG_RegOff_Quad(
6345 getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
6346
6347 } else {
6348 if (isRegIdx(MIR_UnaryAcc.getResult(inst))) {
6349 emitNEG_RegIdx_Quad(
6350 getBase(MIR_UnaryAcc.getResult(inst)), getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
6351
6352 } else {
6353 if (VM.VerifyAssertions && !isRegInd(MIR_UnaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6354 emitNEG_RegInd_Quad(
6355 getBase(MIR_UnaryAcc.getResult(inst)));
6356 }
6357 }
6358 }
6359 }
6360 }
6361
6362 } else {
6363 if (isGPR_Reg(MIR_UnaryAcc.getResult(inst))) {
6364 emitNEG_Reg(
6365 getGPR_Reg(MIR_UnaryAcc.getResult(inst)));
6366
6367 } else {
6368 if (isAbs(MIR_UnaryAcc.getResult(inst))) {
6369 emitNEG_Abs(
6370 getDisp(MIR_UnaryAcc.getResult(inst)).toWord().toAddress());
6371
6372 } else {
6373 if (isRegDisp(MIR_UnaryAcc.getResult(inst))) {
6374 emitNEG_RegDisp(
6375 getBase(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
6376
6377 } else {
6378 if (isRegOff(MIR_UnaryAcc.getResult(inst))) {
6379 emitNEG_RegOff(
6380 getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
6381
6382 } else {
6383 if (isRegIdx(MIR_UnaryAcc.getResult(inst))) {
6384 emitNEG_RegIdx(
6385 getBase(MIR_UnaryAcc.getResult(inst)), getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
6386
6387 } else {
6388 if (VM.VerifyAssertions && !isRegInd(MIR_UnaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6389 emitNEG_RegInd(
6390 getBase(MIR_UnaryAcc.getResult(inst)));
6391 }
6392 }
6393 }
6394 }
6395 }
6396 }
6397 }
6398 }
6399 }
6400
6401 /**
6402 * Emit the given instruction, assuming that
6403 * it is a MIR_BinaryAcc instruction
6404 * and has a FPREM operator
6405 *
6406 * @param inst the instruction to assemble
6407 */
6408 private void doFPREM(Instruction inst) {
6409 emitFPREM();
6410 }
6411
6412 /**
6413 * Emit the given instruction, assuming that
6414 * it is a MIR_Divide instruction
6415 * and has a DIV operator
6416 *
6417 * @param inst the instruction to assemble
6418 */
6419 private void doDIV(Instruction inst) {
6420 if (isQuad(inst)) {
6421 if (isGPR_Reg(MIR_Divide.getValue(inst))) {
6422 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Divide.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6423 emitDIV_Reg_Reg_Quad(
6424 getGPR_Reg(MIR_Divide.getResult2(inst)),
6425 getGPR_Reg(MIR_Divide.getValue(inst)));
6426
6427 } else {
6428 if (isAbs(MIR_Divide.getValue(inst))) {
6429 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Divide.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6430 emitDIV_Reg_Abs_Quad(
6431 getGPR_Reg(MIR_Divide.getResult2(inst)),
6432 getDisp(MIR_Divide.getValue(inst)).toWord().toAddress());
6433
6434 } else {
6435 if (isRegDisp(MIR_Divide.getValue(inst))) {
6436 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Divide.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6437 emitDIV_Reg_RegDisp_Quad(
6438 getGPR_Reg(MIR_Divide.getResult2(inst)),
6439 getBase(MIR_Divide.getValue(inst)), getDisp(MIR_Divide.getValue(inst)));
6440
6441 } else {
6442 if (isRegOff(MIR_Divide.getValue(inst))) {
6443 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Divide.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6444 emitDIV_Reg_RegOff_Quad(
6445 getGPR_Reg(MIR_Divide.getResult2(inst)),
6446 getIndex(MIR_Divide.getValue(inst)), getScale(MIR_Divide.getValue(inst)), getDisp(MIR_Divide.getValue(inst)));
6447
6448 } else {
6449 if (isRegIdx(MIR_Divide.getValue(inst))) {
6450 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Divide.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6451 emitDIV_Reg_RegIdx_Quad(
6452 getGPR_Reg(MIR_Divide.getResult2(inst)),
6453 getBase(MIR_Divide.getValue(inst)), getIndex(MIR_Divide.getValue(inst)), getScale(MIR_Divide.getValue(inst)), getDisp(MIR_Divide.getValue(inst)));
6454
6455 } else {
6456 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Divide.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6457 if (VM.VerifyAssertions && !isRegInd(MIR_Divide.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6458 emitDIV_Reg_RegInd_Quad(
6459 getGPR_Reg(MIR_Divide.getResult2(inst)),
6460 getBase(MIR_Divide.getValue(inst)));
6461 }
6462 }
6463 }
6464 }
6465 }
6466
6467 } else {
6468 if (isGPR_Reg(MIR_Divide.getValue(inst))) {
6469 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Divide.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6470 emitDIV_Reg_Reg(
6471 getGPR_Reg(MIR_Divide.getResult2(inst)),
6472 getGPR_Reg(MIR_Divide.getValue(inst)));
6473
6474 } else {
6475 if (isAbs(MIR_Divide.getValue(inst))) {
6476 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Divide.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6477 emitDIV_Reg_Abs(
6478 getGPR_Reg(MIR_Divide.getResult2(inst)),
6479 getDisp(MIR_Divide.getValue(inst)).toWord().toAddress());
6480
6481 } else {
6482 if (isRegDisp(MIR_Divide.getValue(inst))) {
6483 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Divide.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6484 emitDIV_Reg_RegDisp(
6485 getGPR_Reg(MIR_Divide.getResult2(inst)),
6486 getBase(MIR_Divide.getValue(inst)), getDisp(MIR_Divide.getValue(inst)));
6487
6488 } else {
6489 if (isRegOff(MIR_Divide.getValue(inst))) {
6490 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Divide.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6491 emitDIV_Reg_RegOff(
6492 getGPR_Reg(MIR_Divide.getResult2(inst)),
6493 getIndex(MIR_Divide.getValue(inst)), getScale(MIR_Divide.getValue(inst)), getDisp(MIR_Divide.getValue(inst)));
6494
6495 } else {
6496 if (isRegIdx(MIR_Divide.getValue(inst))) {
6497 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Divide.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6498 emitDIV_Reg_RegIdx(
6499 getGPR_Reg(MIR_Divide.getResult2(inst)),
6500 getBase(MIR_Divide.getValue(inst)), getIndex(MIR_Divide.getValue(inst)), getScale(MIR_Divide.getValue(inst)), getDisp(MIR_Divide.getValue(inst)));
6501
6502 } else {
6503 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Divide.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6504 if (VM.VerifyAssertions && !isRegInd(MIR_Divide.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6505 emitDIV_Reg_RegInd(
6506 getGPR_Reg(MIR_Divide.getResult2(inst)),
6507 getBase(MIR_Divide.getValue(inst)));
6508 }
6509 }
6510 }
6511 }
6512 }
6513 }
6514 }
6515
6516 /**
6517 * Emit the given instruction, assuming that
6518 * it is a MIR_BinaryAcc instruction
6519 * and has a SUBSD operator
6520 *
6521 * @param inst the instruction to assemble
6522 */
6523 private void doSUBSD(Instruction inst) {
6524 if (isXMM_Reg(MIR_BinaryAcc.getValue(inst))) {
6525 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6526 emitSUBSD_Reg_Reg(
6527 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
6528 getXMM_Reg(MIR_BinaryAcc.getValue(inst)));
6529
6530 } else {
6531 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
6532 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6533 emitSUBSD_Reg_Abs(
6534 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
6535 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
6536
6537 } else {
6538 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
6539 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6540 emitSUBSD_Reg_RegDisp(
6541 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
6542 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
6543
6544 } else {
6545 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
6546 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6547 emitSUBSD_Reg_RegOff(
6548 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
6549 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
6550
6551 } else {
6552 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
6553 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6554 emitSUBSD_Reg_RegIdx(
6555 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
6556 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
6557
6558 } else {
6559 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6560 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6561 emitSUBSD_Reg_RegInd(
6562 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
6563 getBase(MIR_BinaryAcc.getValue(inst)));
6564 }
6565 }
6566 }
6567 }
6568 }
6569 }
6570
6571 /**
6572 * Emit the given instruction, assuming that
6573 * it is a MIR_Unary instruction
6574 * and has a SQRTSD operator
6575 *
6576 * @param inst the instruction to assemble
6577 */
6578 private void doSQRTSD(Instruction inst) {
6579 if (isXMM_Reg(MIR_Unary.getVal(inst))) {
6580 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6581 emitSQRTSD_Reg_Reg(
6582 getXMM_Reg(MIR_Unary.getResult(inst)),
6583 getXMM_Reg(MIR_Unary.getVal(inst)));
6584
6585 } else {
6586 if (isAbs(MIR_Unary.getVal(inst))) {
6587 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6588 emitSQRTSD_Reg_Abs(
6589 getXMM_Reg(MIR_Unary.getResult(inst)),
6590 getDisp(MIR_Unary.getVal(inst)).toWord().toAddress());
6591
6592 } else {
6593 if (isRegDisp(MIR_Unary.getVal(inst))) {
6594 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6595 emitSQRTSD_Reg_RegDisp(
6596 getXMM_Reg(MIR_Unary.getResult(inst)),
6597 getBase(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
6598
6599 } else {
6600 if (isRegOff(MIR_Unary.getVal(inst))) {
6601 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6602 emitSQRTSD_Reg_RegOff(
6603 getXMM_Reg(MIR_Unary.getResult(inst)),
6604 getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
6605
6606 } else {
6607 if (isRegIdx(MIR_Unary.getVal(inst))) {
6608 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6609 emitSQRTSD_Reg_RegIdx(
6610 getXMM_Reg(MIR_Unary.getResult(inst)),
6611 getBase(MIR_Unary.getVal(inst)), getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
6612
6613 } else {
6614 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6615 if (VM.VerifyAssertions && !isRegInd(MIR_Unary.getVal(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6616 emitSQRTSD_Reg_RegInd(
6617 getXMM_Reg(MIR_Unary.getResult(inst)),
6618 getBase(MIR_Unary.getVal(inst)));
6619 }
6620 }
6621 }
6622 }
6623 }
6624 }
6625
6626 /**
6627 * Emit the given instruction, assuming that
6628 * it is a MIR_BinaryAcc instruction
6629 * and has a FMULP operator
6630 *
6631 * @param inst the instruction to assemble
6632 */
6633 private void doFMULP(Instruction inst) {
6634 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6635 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6636 emitFMULP_Reg_Reg(
6637 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
6638 getFPR_Reg(MIR_BinaryAcc.getValue(inst)));
6639 }
6640
6641 /**
6642 * Emit the given instruction, assuming that
6643 * it is a MIR_BinaryAcc instruction
6644 * and has a CMPNLESD operator
6645 *
6646 * @param inst the instruction to assemble
6647 */
6648 private void doCMPNLESD(Instruction inst) {
6649 if (isXMM_Reg(MIR_BinaryAcc.getValue(inst))) {
6650 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6651 emitCMPNLESD_Reg_Reg(
6652 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
6653 getXMM_Reg(MIR_BinaryAcc.getValue(inst)));
6654
6655 } else {
6656 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
6657 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6658 emitCMPNLESD_Reg_Abs(
6659 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
6660 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
6661
6662 } else {
6663 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
6664 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6665 emitCMPNLESD_Reg_RegDisp(
6666 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
6667 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
6668
6669 } else {
6670 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
6671 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6672 emitCMPNLESD_Reg_RegOff(
6673 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
6674 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
6675
6676 } else {
6677 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
6678 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6679 emitCMPNLESD_Reg_RegIdx(
6680 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
6681 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
6682
6683 } else {
6684 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6685 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6686 emitCMPNLESD_Reg_RegInd(
6687 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
6688 getBase(MIR_BinaryAcc.getValue(inst)));
6689 }
6690 }
6691 }
6692 }
6693 }
6694 }
6695
6696 /**
6697 * Emit the given instruction, assuming that
6698 * it is a MIR_BinaryAcc instruction
6699 * and has a PSRLQ operator
6700 *
6701 * @param inst the instruction to assemble
6702 */
6703 private void doPSRLQ(Instruction inst) {
6704 if (isMM_Reg(MIR_BinaryAcc.getResult(inst))) {
6705 if (isMM_Reg(MIR_BinaryAcc.getValue(inst))) {
6706 emitPSRLQ_Reg_Reg(
6707 getMM_Reg(MIR_BinaryAcc.getResult(inst)),
6708 getMM_Reg(MIR_BinaryAcc.getValue(inst)));
6709
6710 } else {
6711 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
6712 emitPSRLQ_Reg_Abs(
6713 getMM_Reg(MIR_BinaryAcc.getResult(inst)),
6714 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
6715
6716 } else {
6717 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
6718 emitPSRLQ_Reg_RegDisp(
6719 getMM_Reg(MIR_BinaryAcc.getResult(inst)),
6720 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
6721
6722 } else {
6723 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
6724 emitPSRLQ_Reg_RegOff(
6725 getMM_Reg(MIR_BinaryAcc.getResult(inst)),
6726 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
6727
6728 } else {
6729 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
6730 emitPSRLQ_Reg_RegIdx(
6731 getMM_Reg(MIR_BinaryAcc.getResult(inst)),
6732 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
6733
6734 } else {
6735 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6736 emitPSRLQ_Reg_RegInd(
6737 getMM_Reg(MIR_BinaryAcc.getResult(inst)),
6738 getBase(MIR_BinaryAcc.getValue(inst)));
6739 }
6740 }
6741 }
6742 }
6743 }
6744
6745 } else {
6746 if (isXMM_Reg(MIR_BinaryAcc.getValue(inst))) {
6747 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6748 emitPSRLQ_Reg_Reg(
6749 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
6750 getXMM_Reg(MIR_BinaryAcc.getValue(inst)));
6751
6752 } else {
6753 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
6754 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6755 emitPSRLQ_Reg_Abs(
6756 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
6757 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
6758
6759 } else {
6760 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
6761 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6762 emitPSRLQ_Reg_RegDisp(
6763 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
6764 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
6765
6766 } else {
6767 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
6768 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6769 emitPSRLQ_Reg_RegOff(
6770 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
6771 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
6772
6773 } else {
6774 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
6775 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6776 emitPSRLQ_Reg_RegIdx(
6777 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
6778 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
6779
6780 } else {
6781 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6782 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6783 emitPSRLQ_Reg_RegInd(
6784 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
6785 getBase(MIR_BinaryAcc.getValue(inst)));
6786 }
6787 }
6788 }
6789 }
6790 }
6791 }
6792 }
6793
6794 /**
6795 * Emit the given instruction, assuming that
6796 * it is a MIR_BinaryAcc instruction
6797 * and has a FISUBR operator
6798 *
6799 * @param inst the instruction to assemble
6800 */
6801 private void doFISUBR(Instruction inst) {
6802 if (isWord(inst)) {
6803 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
6804 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6805 emitFISUBR_Reg_Abs_Word(
6806 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
6807 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
6808
6809 } else {
6810 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
6811 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6812 emitFISUBR_Reg_RegDisp_Word(
6813 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
6814 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
6815
6816 } else {
6817 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
6818 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6819 emitFISUBR_Reg_RegOff_Word(
6820 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
6821 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
6822
6823 } else {
6824 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
6825 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6826 emitFISUBR_Reg_RegIdx_Word(
6827 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
6828 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
6829
6830 } else {
6831 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6832 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6833 emitFISUBR_Reg_RegInd_Word(
6834 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
6835 getBase(MIR_BinaryAcc.getValue(inst)));
6836 }
6837 }
6838 }
6839 }
6840
6841 } else {
6842 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
6843 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6844 emitFISUBR_Reg_Abs(
6845 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
6846 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
6847
6848 } else {
6849 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
6850 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6851 emitFISUBR_Reg_RegDisp(
6852 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
6853 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
6854
6855 } else {
6856 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
6857 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6858 emitFISUBR_Reg_RegOff(
6859 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
6860 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
6861
6862 } else {
6863 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
6864 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6865 emitFISUBR_Reg_RegIdx(
6866 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
6867 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
6868
6869 } else {
6870 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6871 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6872 emitFISUBR_Reg_RegInd(
6873 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
6874 getBase(MIR_BinaryAcc.getValue(inst)));
6875 }
6876 }
6877 }
6878 }
6879 }
6880 }
6881
6882 /**
6883 * Emit the given instruction, assuming that
6884 * it is a MIR_BinaryAcc instruction
6885 * and has a FSUBP operator
6886 *
6887 * @param inst the instruction to assemble
6888 */
6889 private void doFSUBP(Instruction inst) {
6890 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6891 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6892 emitFSUBP_Reg_Reg(
6893 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
6894 getFPR_Reg(MIR_BinaryAcc.getValue(inst)));
6895 }
6896
6897 /**
6898 * Emit the given instruction, assuming that
6899 * it is a MIR_Unary instruction
6900 * and has a CVTSD2SI operator
6901 *
6902 * @param inst the instruction to assemble
6903 */
6904 private void doCVTSD2SI(Instruction inst) {
6905 if (isXMM_Reg(MIR_Unary.getVal(inst))) {
6906 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6907 emitCVTSD2SI_Reg_Reg(
6908 getGPR_Reg(MIR_Unary.getResult(inst)),
6909 getXMM_Reg(MIR_Unary.getVal(inst)));
6910
6911 } else {
6912 if (isAbs(MIR_Unary.getVal(inst))) {
6913 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6914 emitCVTSD2SI_Reg_Abs(
6915 getGPR_Reg(MIR_Unary.getResult(inst)),
6916 getDisp(MIR_Unary.getVal(inst)).toWord().toAddress());
6917
6918 } else {
6919 if (isRegDisp(MIR_Unary.getVal(inst))) {
6920 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6921 emitCVTSD2SI_Reg_RegDisp(
6922 getGPR_Reg(MIR_Unary.getResult(inst)),
6923 getBase(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
6924
6925 } else {
6926 if (isRegOff(MIR_Unary.getVal(inst))) {
6927 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6928 emitCVTSD2SI_Reg_RegOff(
6929 getGPR_Reg(MIR_Unary.getResult(inst)),
6930 getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
6931
6932 } else {
6933 if (isRegIdx(MIR_Unary.getVal(inst))) {
6934 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6935 emitCVTSD2SI_Reg_RegIdx(
6936 getGPR_Reg(MIR_Unary.getResult(inst)),
6937 getBase(MIR_Unary.getVal(inst)), getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
6938
6939 } else {
6940 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6941 if (VM.VerifyAssertions && !isRegInd(MIR_Unary.getVal(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6942 emitCVTSD2SI_Reg_RegInd(
6943 getGPR_Reg(MIR_Unary.getResult(inst)),
6944 getBase(MIR_Unary.getVal(inst)));
6945 }
6946 }
6947 }
6948 }
6949 }
6950 }
6951
6952 /**
6953 * Emit the given instruction, assuming that
6954 * it is a MIR_BinaryAcc instruction
6955 * and has a FSUBR operator
6956 *
6957 * @param inst the instruction to assemble
6958 */
6959 private void doFSUBR(Instruction inst) {
6960 if (isQuad(inst)) {
6961 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
6962 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6963 emitFSUBR_Reg_Abs_Quad(
6964 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
6965 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
6966
6967 } else {
6968 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
6969 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6970 emitFSUBR_Reg_RegDisp_Quad(
6971 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
6972 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
6973
6974 } else {
6975 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
6976 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6977 emitFSUBR_Reg_RegOff_Quad(
6978 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
6979 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
6980
6981 } else {
6982 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
6983 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6984 emitFSUBR_Reg_RegIdx_Quad(
6985 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
6986 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
6987
6988 } else {
6989 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6990 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
6991 emitFSUBR_Reg_RegInd_Quad(
6992 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
6993 getBase(MIR_BinaryAcc.getValue(inst)));
6994 }
6995 }
6996 }
6997 }
6998
6999 } else {
7000 if (isFPR_Reg(MIR_BinaryAcc.getValue(inst))) {
7001 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7002 emitFSUBR_Reg_Reg(
7003 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
7004 getFPR_Reg(MIR_BinaryAcc.getValue(inst)));
7005
7006 } else {
7007 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
7008 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7009 emitFSUBR_Reg_Abs(
7010 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
7011 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
7012
7013 } else {
7014 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
7015 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7016 emitFSUBR_Reg_RegDisp(
7017 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
7018 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
7019
7020 } else {
7021 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
7022 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7023 emitFSUBR_Reg_RegOff(
7024 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
7025 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
7026
7027 } else {
7028 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
7029 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7030 emitFSUBR_Reg_RegIdx(
7031 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
7032 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
7033
7034 } else {
7035 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7036 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7037 emitFSUBR_Reg_RegInd(
7038 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
7039 getBase(MIR_BinaryAcc.getValue(inst)));
7040 }
7041 }
7042 }
7043 }
7044 }
7045 }
7046 }
7047
7048 /**
7049 * Emit the given instruction, assuming that
7050 * it is a MIR_Move instruction
7051 * and has a FILD operator
7052 *
7053 * @param inst the instruction to assemble
7054 */
7055 private void doFILD(Instruction inst) {
7056 if (isWord(inst)) {
7057 if (isAbs(MIR_Move.getValue(inst))) {
7058 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7059 emitFILD_Reg_Abs_Word(
7060 getFPR_Reg(MIR_Move.getResult(inst)),
7061 getDisp(MIR_Move.getValue(inst)).toWord().toAddress());
7062
7063 } else {
7064 if (isRegDisp(MIR_Move.getValue(inst))) {
7065 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7066 emitFILD_Reg_RegDisp_Word(
7067 getFPR_Reg(MIR_Move.getResult(inst)),
7068 getBase(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
7069
7070 } else {
7071 if (isRegOff(MIR_Move.getValue(inst))) {
7072 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7073 emitFILD_Reg_RegOff_Word(
7074 getFPR_Reg(MIR_Move.getResult(inst)),
7075 getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
7076
7077 } else {
7078 if (isRegIdx(MIR_Move.getValue(inst))) {
7079 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7080 emitFILD_Reg_RegIdx_Word(
7081 getFPR_Reg(MIR_Move.getResult(inst)),
7082 getBase(MIR_Move.getValue(inst)), getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
7083
7084 } else {
7085 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7086 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7087 emitFILD_Reg_RegInd_Word(
7088 getFPR_Reg(MIR_Move.getResult(inst)),
7089 getBase(MIR_Move.getValue(inst)));
7090 }
7091 }
7092 }
7093 }
7094
7095 } else {
7096 if (isQuad(inst)) {
7097 if (isAbs(MIR_Move.getValue(inst))) {
7098 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7099 emitFILD_Reg_Abs_Quad(
7100 getFPR_Reg(MIR_Move.getResult(inst)),
7101 getDisp(MIR_Move.getValue(inst)).toWord().toAddress());
7102
7103 } else {
7104 if (isRegDisp(MIR_Move.getValue(inst))) {
7105 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7106 emitFILD_Reg_RegDisp_Quad(
7107 getFPR_Reg(MIR_Move.getResult(inst)),
7108 getBase(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
7109
7110 } else {
7111 if (isRegOff(MIR_Move.getValue(inst))) {
7112 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7113 emitFILD_Reg_RegOff_Quad(
7114 getFPR_Reg(MIR_Move.getResult(inst)),
7115 getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
7116
7117 } else {
7118 if (isRegIdx(MIR_Move.getValue(inst))) {
7119 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7120 emitFILD_Reg_RegIdx_Quad(
7121 getFPR_Reg(MIR_Move.getResult(inst)),
7122 getBase(MIR_Move.getValue(inst)), getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
7123
7124 } else {
7125 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7126 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7127 emitFILD_Reg_RegInd_Quad(
7128 getFPR_Reg(MIR_Move.getResult(inst)),
7129 getBase(MIR_Move.getValue(inst)));
7130 }
7131 }
7132 }
7133 }
7134
7135 } else {
7136 if (isAbs(MIR_Move.getValue(inst))) {
7137 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7138 emitFILD_Reg_Abs(
7139 getFPR_Reg(MIR_Move.getResult(inst)),
7140 getDisp(MIR_Move.getValue(inst)).toWord().toAddress());
7141
7142 } else {
7143 if (isRegDisp(MIR_Move.getValue(inst))) {
7144 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7145 emitFILD_Reg_RegDisp(
7146 getFPR_Reg(MIR_Move.getResult(inst)),
7147 getBase(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
7148
7149 } else {
7150 if (isRegOff(MIR_Move.getValue(inst))) {
7151 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7152 emitFILD_Reg_RegOff(
7153 getFPR_Reg(MIR_Move.getResult(inst)),
7154 getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
7155
7156 } else {
7157 if (isRegIdx(MIR_Move.getValue(inst))) {
7158 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7159 emitFILD_Reg_RegIdx(
7160 getFPR_Reg(MIR_Move.getResult(inst)),
7161 getBase(MIR_Move.getValue(inst)), getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
7162
7163 } else {
7164 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7165 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7166 emitFILD_Reg_RegInd(
7167 getFPR_Reg(MIR_Move.getResult(inst)),
7168 getBase(MIR_Move.getValue(inst)));
7169 }
7170 }
7171 }
7172 }
7173 }
7174 }
7175 }
7176
7177 /**
7178 * Emit the given instruction, assuming that
7179 * it is a MIR_BinaryAcc instruction
7180 * and has a FADD operator
7181 *
7182 * @param inst the instruction to assemble
7183 */
7184 private void doFADD(Instruction inst) {
7185 if (isQuad(inst)) {
7186 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
7187 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7188 emitFADD_Reg_Abs_Quad(
7189 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
7190 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
7191
7192 } else {
7193 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
7194 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7195 emitFADD_Reg_RegDisp_Quad(
7196 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
7197 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
7198
7199 } else {
7200 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
7201 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7202 emitFADD_Reg_RegOff_Quad(
7203 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
7204 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
7205
7206 } else {
7207 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
7208 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7209 emitFADD_Reg_RegIdx_Quad(
7210 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
7211 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
7212
7213 } else {
7214 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7215 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7216 emitFADD_Reg_RegInd_Quad(
7217 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
7218 getBase(MIR_BinaryAcc.getValue(inst)));
7219 }
7220 }
7221 }
7222 }
7223
7224 } else {
7225 if (isFPR_Reg(MIR_BinaryAcc.getValue(inst))) {
7226 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7227 emitFADD_Reg_Reg(
7228 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
7229 getFPR_Reg(MIR_BinaryAcc.getValue(inst)));
7230
7231 } else {
7232 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
7233 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7234 emitFADD_Reg_Abs(
7235 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
7236 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
7237
7238 } else {
7239 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
7240 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7241 emitFADD_Reg_RegDisp(
7242 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
7243 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
7244
7245 } else {
7246 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
7247 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7248 emitFADD_Reg_RegOff(
7249 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
7250 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
7251
7252 } else {
7253 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
7254 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7255 emitFADD_Reg_RegIdx(
7256 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
7257 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
7258
7259 } else {
7260 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7261 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7262 emitFADD_Reg_RegInd(
7263 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
7264 getBase(MIR_BinaryAcc.getValue(inst)));
7265 }
7266 }
7267 }
7268 }
7269 }
7270 }
7271 }
7272
7273 /**
7274 * Emit the given instruction, assuming that
7275 * it is a MIR_BinaryAcc instruction
7276 * and has a CMPORDSS operator
7277 *
7278 * @param inst the instruction to assemble
7279 */
7280 private void doCMPORDSS(Instruction inst) {
7281 if (isXMM_Reg(MIR_BinaryAcc.getValue(inst))) {
7282 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7283 emitCMPORDSS_Reg_Reg(
7284 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
7285 getXMM_Reg(MIR_BinaryAcc.getValue(inst)));
7286
7287 } else {
7288 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
7289 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7290 emitCMPORDSS_Reg_Abs(
7291 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
7292 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
7293
7294 } else {
7295 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
7296 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7297 emitCMPORDSS_Reg_RegDisp(
7298 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
7299 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
7300
7301 } else {
7302 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
7303 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7304 emitCMPORDSS_Reg_RegOff(
7305 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
7306 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
7307
7308 } else {
7309 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
7310 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7311 emitCMPORDSS_Reg_RegIdx(
7312 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
7313 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
7314
7315 } else {
7316 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7317 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7318 emitCMPORDSS_Reg_RegInd(
7319 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
7320 getBase(MIR_BinaryAcc.getValue(inst)));
7321 }
7322 }
7323 }
7324 }
7325 }
7326 }
7327
7328 /**
7329 * Emit the given instruction, assuming that
7330 * it is a MIR_BinaryAcc instruction
7331 * and has a FISUB operator
7332 *
7333 * @param inst the instruction to assemble
7334 */
7335 private void doFISUB(Instruction inst) {
7336 if (isWord(inst)) {
7337 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
7338 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7339 emitFISUB_Reg_Abs_Word(
7340 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
7341 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
7342
7343 } else {
7344 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
7345 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7346 emitFISUB_Reg_RegDisp_Word(
7347 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
7348 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
7349
7350 } else {
7351 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
7352 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7353 emitFISUB_Reg_RegOff_Word(
7354 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
7355 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
7356
7357 } else {
7358 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
7359 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7360 emitFISUB_Reg_RegIdx_Word(
7361 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
7362 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
7363
7364 } else {
7365 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7366 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7367 emitFISUB_Reg_RegInd_Word(
7368 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
7369 getBase(MIR_BinaryAcc.getValue(inst)));
7370 }
7371 }
7372 }
7373 }
7374
7375 } else {
7376 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
7377 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7378 emitFISUB_Reg_Abs(
7379 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
7380 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
7381
7382 } else {
7383 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
7384 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7385 emitFISUB_Reg_RegDisp(
7386 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
7387 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
7388
7389 } else {
7390 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
7391 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7392 emitFISUB_Reg_RegOff(
7393 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
7394 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
7395
7396 } else {
7397 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
7398 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7399 emitFISUB_Reg_RegIdx(
7400 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
7401 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
7402
7403 } else {
7404 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7405 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7406 emitFISUB_Reg_RegInd(
7407 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
7408 getBase(MIR_BinaryAcc.getValue(inst)));
7409 }
7410 }
7411 }
7412 }
7413 }
7414 }
7415
7416 /**
7417 * Emit the given instruction, assuming that
7418 * it is a MIR_BinaryAcc instruction
7419 * and has a CMPNESS operator
7420 *
7421 * @param inst the instruction to assemble
7422 */
7423 private void doCMPNESS(Instruction inst) {
7424 if (isXMM_Reg(MIR_BinaryAcc.getValue(inst))) {
7425 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7426 emitCMPNESS_Reg_Reg(
7427 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
7428 getXMM_Reg(MIR_BinaryAcc.getValue(inst)));
7429
7430 } else {
7431 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
7432 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7433 emitCMPNESS_Reg_Abs(
7434 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
7435 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
7436
7437 } else {
7438 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
7439 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7440 emitCMPNESS_Reg_RegDisp(
7441 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
7442 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
7443
7444 } else {
7445 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
7446 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7447 emitCMPNESS_Reg_RegOff(
7448 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
7449 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
7450
7451 } else {
7452 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
7453 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7454 emitCMPNESS_Reg_RegIdx(
7455 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
7456 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
7457
7458 } else {
7459 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7460 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7461 emitCMPNESS_Reg_RegInd(
7462 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
7463 getBase(MIR_BinaryAcc.getValue(inst)));
7464 }
7465 }
7466 }
7467 }
7468 }
7469 }
7470
7471 /**
7472 * Emit the given instruction, assuming that
7473 * it is a MIR_BinaryAcc instruction
7474 * and has a XORPS operator
7475 *
7476 * @param inst the instruction to assemble
7477 */
7478 private void doXORPS(Instruction inst) {
7479 if (isXMM_Reg(MIR_BinaryAcc.getValue(inst))) {
7480 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7481 emitXORPS_Reg_Reg(
7482 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
7483 getXMM_Reg(MIR_BinaryAcc.getValue(inst)));
7484
7485 } else {
7486 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
7487 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7488 emitXORPS_Reg_Abs(
7489 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
7490 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
7491
7492 } else {
7493 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
7494 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7495 emitXORPS_Reg_RegDisp(
7496 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
7497 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
7498
7499 } else {
7500 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
7501 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7502 emitXORPS_Reg_RegOff(
7503 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
7504 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
7505
7506 } else {
7507 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
7508 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7509 emitXORPS_Reg_RegIdx(
7510 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
7511 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
7512
7513 } else {
7514 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7515 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7516 emitXORPS_Reg_RegInd(
7517 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
7518 getBase(MIR_BinaryAcc.getValue(inst)));
7519 }
7520 }
7521 }
7522 }
7523 }
7524 }
7525
7526 /**
7527 * Emit the given instruction, assuming that
7528 * it is a MIR_Unary instruction
7529 * and has a CVTSD2SS operator
7530 *
7531 * @param inst the instruction to assemble
7532 */
7533 private void doCVTSD2SS(Instruction inst) {
7534 if (isXMM_Reg(MIR_Unary.getVal(inst))) {
7535 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7536 emitCVTSD2SS_Reg_Reg(
7537 getXMM_Reg(MIR_Unary.getResult(inst)),
7538 getXMM_Reg(MIR_Unary.getVal(inst)));
7539
7540 } else {
7541 if (isAbs(MIR_Unary.getVal(inst))) {
7542 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7543 emitCVTSD2SS_Reg_Abs(
7544 getXMM_Reg(MIR_Unary.getResult(inst)),
7545 getDisp(MIR_Unary.getVal(inst)).toWord().toAddress());
7546
7547 } else {
7548 if (isRegDisp(MIR_Unary.getVal(inst))) {
7549 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7550 emitCVTSD2SS_Reg_RegDisp(
7551 getXMM_Reg(MIR_Unary.getResult(inst)),
7552 getBase(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
7553
7554 } else {
7555 if (isRegOff(MIR_Unary.getVal(inst))) {
7556 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7557 emitCVTSD2SS_Reg_RegOff(
7558 getXMM_Reg(MIR_Unary.getResult(inst)),
7559 getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
7560
7561 } else {
7562 if (isRegIdx(MIR_Unary.getVal(inst))) {
7563 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7564 emitCVTSD2SS_Reg_RegIdx(
7565 getXMM_Reg(MIR_Unary.getResult(inst)),
7566 getBase(MIR_Unary.getVal(inst)), getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
7567
7568 } else {
7569 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7570 if (VM.VerifyAssertions && !isRegInd(MIR_Unary.getVal(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7571 emitCVTSD2SS_Reg_RegInd(
7572 getXMM_Reg(MIR_Unary.getResult(inst)),
7573 getBase(MIR_Unary.getVal(inst)));
7574 }
7575 }
7576 }
7577 }
7578 }
7579 }
7580
7581 /**
7582 * Emit the given instruction, assuming that
7583 * it is a MIR_BinaryAcc instruction
7584 * and has a ADC operator
7585 *
7586 * @param inst the instruction to assemble
7587 */
7588 private void doADC(Instruction inst) {
7589 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
7590 if (isByte(inst)) {
7591 if (isImm(MIR_BinaryAcc.getValue(inst))) {
7592 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
7593 emitADC_Reg_Imm_Byte(
7594 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
7595 getImm(MIR_BinaryAcc.getValue(inst)));
7596
7597 } else {
7598 if (isGPR_Reg(MIR_BinaryAcc.getValue(inst))) {
7599 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
7600 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
7601 emitADC_Reg_Reg_Byte(
7602 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
7603 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
7604
7605 } else {
7606 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
7607 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
7608 emitADC_Reg_Abs_Byte(
7609 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
7610 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
7611
7612 } else {
7613 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
7614 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
7615 emitADC_Reg_RegDisp_Byte(
7616 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
7617 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
7618
7619 } else {
7620 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
7621 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
7622 emitADC_Reg_RegOff_Byte(
7623 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
7624 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
7625
7626 } else {
7627 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
7628 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
7629 emitADC_Reg_RegIdx_Byte(
7630 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
7631 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
7632
7633 } else {
7634 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7635 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
7636 emitADC_Reg_RegInd_Byte(
7637 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
7638 getBase(MIR_BinaryAcc.getValue(inst)));
7639 }
7640 }
7641 }
7642 }
7643 }
7644 }
7645
7646 } else {
7647 if (isWord(inst)) {
7648 if (isImm(MIR_BinaryAcc.getValue(inst))) {
7649 emitADC_Reg_Imm_Word(
7650 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
7651 getImm(MIR_BinaryAcc.getValue(inst)));
7652
7653 } else {
7654 if (isGPR_Reg(MIR_BinaryAcc.getValue(inst))) {
7655 emitADC_Reg_Reg_Word(
7656 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
7657 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
7658
7659 } else {
7660 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
7661 emitADC_Reg_Abs_Word(
7662 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
7663 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
7664
7665 } else {
7666 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
7667 emitADC_Reg_RegDisp_Word(
7668 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
7669 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
7670
7671 } else {
7672 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
7673 emitADC_Reg_RegOff_Word(
7674 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
7675 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
7676
7677 } else {
7678 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
7679 emitADC_Reg_RegIdx_Word(
7680 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
7681 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
7682
7683 } else {
7684 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7685 emitADC_Reg_RegInd_Word(
7686 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
7687 getBase(MIR_BinaryAcc.getValue(inst)));
7688 }
7689 }
7690 }
7691 }
7692 }
7693 }
7694
7695 } else {
7696 if (isQuad(inst)) {
7697 if (isImm(MIR_BinaryAcc.getValue(inst))) {
7698 emitADC_Reg_Imm_Quad(
7699 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
7700 getImm(MIR_BinaryAcc.getValue(inst)));
7701
7702 } else {
7703 if (isGPR_Reg(MIR_BinaryAcc.getValue(inst))) {
7704 emitADC_Reg_Reg_Quad(
7705 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
7706 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
7707
7708 } else {
7709 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
7710 emitADC_Reg_Abs_Quad(
7711 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
7712 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
7713
7714 } else {
7715 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
7716 emitADC_Reg_RegDisp_Quad(
7717 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
7718 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
7719
7720 } else {
7721 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
7722 emitADC_Reg_RegOff_Quad(
7723 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
7724 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
7725
7726 } else {
7727 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
7728 emitADC_Reg_RegIdx_Quad(
7729 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
7730 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
7731
7732 } else {
7733 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7734 emitADC_Reg_RegInd_Quad(
7735 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
7736 getBase(MIR_BinaryAcc.getValue(inst)));
7737 }
7738 }
7739 }
7740 }
7741 }
7742 }
7743
7744 } else {
7745 if (isImm(MIR_BinaryAcc.getValue(inst))) {
7746 emitADC_Reg_Imm(
7747 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
7748 getImm(MIR_BinaryAcc.getValue(inst)));
7749
7750 } else {
7751 if (isGPR_Reg(MIR_BinaryAcc.getValue(inst))) {
7752 emitADC_Reg_Reg(
7753 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
7754 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
7755
7756 } else {
7757 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
7758 emitADC_Reg_Abs(
7759 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
7760 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
7761
7762 } else {
7763 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
7764 emitADC_Reg_RegDisp(
7765 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
7766 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
7767
7768 } else {
7769 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
7770 emitADC_Reg_RegOff(
7771 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
7772 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
7773
7774 } else {
7775 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
7776 emitADC_Reg_RegIdx(
7777 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
7778 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
7779
7780 } else {
7781 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7782 emitADC_Reg_RegInd(
7783 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
7784 getBase(MIR_BinaryAcc.getValue(inst)));
7785 }
7786 }
7787 }
7788 }
7789 }
7790 }
7791 }
7792 }
7793 }
7794
7795 } else {
7796 if (isImm(MIR_BinaryAcc.getValue(inst))) {
7797 if (isByte(inst)) {
7798 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
7799 emitADC_Abs_Imm_Byte(
7800 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
7801 getImm(MIR_BinaryAcc.getValue(inst)));
7802
7803 } else {
7804 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
7805 emitADC_RegDisp_Imm_Byte(
7806 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
7807 getImm(MIR_BinaryAcc.getValue(inst)));
7808
7809 } else {
7810 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
7811 emitADC_RegOff_Imm_Byte(
7812 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
7813 getImm(MIR_BinaryAcc.getValue(inst)));
7814
7815 } else {
7816 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
7817 emitADC_RegIdx_Imm_Byte(
7818 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
7819 getImm(MIR_BinaryAcc.getValue(inst)));
7820
7821 } else {
7822 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7823 emitADC_RegInd_Imm_Byte(
7824 getBase(MIR_BinaryAcc.getResult(inst)),
7825 getImm(MIR_BinaryAcc.getValue(inst)));
7826 }
7827 }
7828 }
7829 }
7830
7831 } else {
7832 if (isWord(inst)) {
7833 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
7834 emitADC_Abs_Imm_Word(
7835 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
7836 getImm(MIR_BinaryAcc.getValue(inst)));
7837
7838 } else {
7839 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
7840 emitADC_RegDisp_Imm_Word(
7841 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
7842 getImm(MIR_BinaryAcc.getValue(inst)));
7843
7844 } else {
7845 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
7846 emitADC_RegOff_Imm_Word(
7847 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
7848 getImm(MIR_BinaryAcc.getValue(inst)));
7849
7850 } else {
7851 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
7852 emitADC_RegIdx_Imm_Word(
7853 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
7854 getImm(MIR_BinaryAcc.getValue(inst)));
7855
7856 } else {
7857 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7858 emitADC_RegInd_Imm_Word(
7859 getBase(MIR_BinaryAcc.getResult(inst)),
7860 getImm(MIR_BinaryAcc.getValue(inst)));
7861 }
7862 }
7863 }
7864 }
7865
7866 } else {
7867 if (isQuad(inst)) {
7868 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
7869 emitADC_Abs_Imm_Quad(
7870 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
7871 getImm(MIR_BinaryAcc.getValue(inst)));
7872
7873 } else {
7874 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
7875 emitADC_RegDisp_Imm_Quad(
7876 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
7877 getImm(MIR_BinaryAcc.getValue(inst)));
7878
7879 } else {
7880 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
7881 emitADC_RegOff_Imm_Quad(
7882 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
7883 getImm(MIR_BinaryAcc.getValue(inst)));
7884
7885 } else {
7886 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
7887 emitADC_RegIdx_Imm_Quad(
7888 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
7889 getImm(MIR_BinaryAcc.getValue(inst)));
7890
7891 } else {
7892 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7893 emitADC_RegInd_Imm_Quad(
7894 getBase(MIR_BinaryAcc.getResult(inst)),
7895 getImm(MIR_BinaryAcc.getValue(inst)));
7896 }
7897 }
7898 }
7899 }
7900
7901 } else {
7902 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
7903 emitADC_Abs_Imm(
7904 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
7905 getImm(MIR_BinaryAcc.getValue(inst)));
7906
7907 } else {
7908 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
7909 emitADC_RegDisp_Imm(
7910 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
7911 getImm(MIR_BinaryAcc.getValue(inst)));
7912
7913 } else {
7914 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
7915 emitADC_RegOff_Imm(
7916 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
7917 getImm(MIR_BinaryAcc.getValue(inst)));
7918
7919 } else {
7920 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
7921 emitADC_RegIdx_Imm(
7922 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
7923 getImm(MIR_BinaryAcc.getValue(inst)));
7924
7925 } else {
7926 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7927 emitADC_RegInd_Imm(
7928 getBase(MIR_BinaryAcc.getResult(inst)),
7929 getImm(MIR_BinaryAcc.getValue(inst)));
7930 }
7931 }
7932 }
7933 }
7934 }
7935 }
7936 }
7937
7938 } else {
7939 if (isByte(inst)) {
7940 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
7941 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7942 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
7943 emitADC_Abs_Reg_Byte(
7944 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
7945 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
7946
7947 } else {
7948 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
7949 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7950 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
7951 emitADC_RegDisp_Reg_Byte(
7952 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
7953 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
7954
7955 } else {
7956 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
7957 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7958 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
7959 emitADC_RegOff_Reg_Byte(
7960 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
7961 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
7962
7963 } else {
7964 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
7965 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7966 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
7967 emitADC_RegIdx_Reg_Byte(
7968 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
7969 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
7970
7971 } else {
7972 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7973 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7974 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
7975 emitADC_RegInd_Reg_Byte(
7976 getBase(MIR_BinaryAcc.getResult(inst)),
7977 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
7978 }
7979 }
7980 }
7981 }
7982
7983 } else {
7984 if (isWord(inst)) {
7985 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
7986 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7987 emitADC_Abs_Reg_Word(
7988 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
7989 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
7990
7991 } else {
7992 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
7993 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
7994 emitADC_RegDisp_Reg_Word(
7995 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
7996 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
7997
7998 } else {
7999 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
8000 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8001 emitADC_RegOff_Reg_Word(
8002 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
8003 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
8004
8005 } else {
8006 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
8007 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8008 emitADC_RegIdx_Reg_Word(
8009 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
8010 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
8011
8012 } else {
8013 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8014 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8015 emitADC_RegInd_Reg_Word(
8016 getBase(MIR_BinaryAcc.getResult(inst)),
8017 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
8018 }
8019 }
8020 }
8021 }
8022
8023 } else {
8024 if (isQuad(inst)) {
8025 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
8026 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8027 emitADC_Abs_Reg_Quad(
8028 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
8029 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
8030
8031 } else {
8032 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
8033 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8034 emitADC_RegDisp_Reg_Quad(
8035 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
8036 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
8037
8038 } else {
8039 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
8040 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8041 emitADC_RegOff_Reg_Quad(
8042 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
8043 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
8044
8045 } else {
8046 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
8047 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8048 emitADC_RegIdx_Reg_Quad(
8049 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
8050 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
8051
8052 } else {
8053 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8054 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8055 emitADC_RegInd_Reg_Quad(
8056 getBase(MIR_BinaryAcc.getResult(inst)),
8057 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
8058 }
8059 }
8060 }
8061 }
8062
8063 } else {
8064 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
8065 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8066 emitADC_Abs_Reg(
8067 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
8068 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
8069
8070 } else {
8071 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
8072 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8073 emitADC_RegDisp_Reg(
8074 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
8075 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
8076
8077 } else {
8078 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
8079 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8080 emitADC_RegOff_Reg(
8081 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
8082 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
8083
8084 } else {
8085 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
8086 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8087 emitADC_RegIdx_Reg(
8088 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
8089 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
8090
8091 } else {
8092 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8093 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8094 emitADC_RegInd_Reg(
8095 getBase(MIR_BinaryAcc.getResult(inst)),
8096 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
8097 }
8098 }
8099 }
8100 }
8101 }
8102 }
8103 }
8104 }
8105 }
8106 }
8107
8108 /**
8109 * Emit the given instruction, assuming that
8110 * it is a MIR_BinaryAcc instruction
8111 * and has a SUBSS operator
8112 *
8113 * @param inst the instruction to assemble
8114 */
8115 private void doSUBSS(Instruction inst) {
8116 if (isXMM_Reg(MIR_BinaryAcc.getValue(inst))) {
8117 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8118 emitSUBSS_Reg_Reg(
8119 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
8120 getXMM_Reg(MIR_BinaryAcc.getValue(inst)));
8121
8122 } else {
8123 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
8124 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8125 emitSUBSS_Reg_Abs(
8126 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
8127 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
8128
8129 } else {
8130 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
8131 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8132 emitSUBSS_Reg_RegDisp(
8133 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
8134 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
8135
8136 } else {
8137 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
8138 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8139 emitSUBSS_Reg_RegOff(
8140 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
8141 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
8142
8143 } else {
8144 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
8145 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8146 emitSUBSS_Reg_RegIdx(
8147 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
8148 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
8149
8150 } else {
8151 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8152 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8153 emitSUBSS_Reg_RegInd(
8154 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
8155 getBase(MIR_BinaryAcc.getValue(inst)));
8156 }
8157 }
8158 }
8159 }
8160 }
8161 }
8162
8163 /**
8164 * Emit the given instruction, assuming that
8165 * it is a MIR_Unary instruction
8166 * and has a SQRTSS operator
8167 *
8168 * @param inst the instruction to assemble
8169 */
8170 private void doSQRTSS(Instruction inst) {
8171 if (isXMM_Reg(MIR_Unary.getVal(inst))) {
8172 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8173 emitSQRTSS_Reg_Reg(
8174 getXMM_Reg(MIR_Unary.getResult(inst)),
8175 getXMM_Reg(MIR_Unary.getVal(inst)));
8176
8177 } else {
8178 if (isAbs(MIR_Unary.getVal(inst))) {
8179 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8180 emitSQRTSS_Reg_Abs(
8181 getXMM_Reg(MIR_Unary.getResult(inst)),
8182 getDisp(MIR_Unary.getVal(inst)).toWord().toAddress());
8183
8184 } else {
8185 if (isRegDisp(MIR_Unary.getVal(inst))) {
8186 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8187 emitSQRTSS_Reg_RegDisp(
8188 getXMM_Reg(MIR_Unary.getResult(inst)),
8189 getBase(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
8190
8191 } else {
8192 if (isRegOff(MIR_Unary.getVal(inst))) {
8193 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8194 emitSQRTSS_Reg_RegOff(
8195 getXMM_Reg(MIR_Unary.getResult(inst)),
8196 getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
8197
8198 } else {
8199 if (isRegIdx(MIR_Unary.getVal(inst))) {
8200 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8201 emitSQRTSS_Reg_RegIdx(
8202 getXMM_Reg(MIR_Unary.getResult(inst)),
8203 getBase(MIR_Unary.getVal(inst)), getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
8204
8205 } else {
8206 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8207 if (VM.VerifyAssertions && !isRegInd(MIR_Unary.getVal(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8208 emitSQRTSS_Reg_RegInd(
8209 getXMM_Reg(MIR_Unary.getResult(inst)),
8210 getBase(MIR_Unary.getVal(inst)));
8211 }
8212 }
8213 }
8214 }
8215 }
8216 }
8217
8218 /**
8219 * Emit the given instruction, assuming that
8220 * it is a MIR_BinaryAcc instruction
8221 * and has a ADD operator
8222 *
8223 * @param inst the instruction to assemble
8224 */
8225 private void doADD(Instruction inst) {
8226 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
8227 if (isByte(inst)) {
8228 if (isImm(MIR_BinaryAcc.getValue(inst))) {
8229 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
8230 emitADD_Reg_Imm_Byte(
8231 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
8232 getImm(MIR_BinaryAcc.getValue(inst)));
8233
8234 } else {
8235 if (isGPR_Reg(MIR_BinaryAcc.getValue(inst))) {
8236 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
8237 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
8238 emitADD_Reg_Reg_Byte(
8239 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
8240 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
8241
8242 } else {
8243 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
8244 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
8245 emitADD_Reg_Abs_Byte(
8246 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
8247 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
8248
8249 } else {
8250 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
8251 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
8252 emitADD_Reg_RegDisp_Byte(
8253 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
8254 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
8255
8256 } else {
8257 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
8258 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
8259 emitADD_Reg_RegOff_Byte(
8260 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
8261 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
8262
8263 } else {
8264 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
8265 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
8266 emitADD_Reg_RegIdx_Byte(
8267 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
8268 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
8269
8270 } else {
8271 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8272 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
8273 emitADD_Reg_RegInd_Byte(
8274 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
8275 getBase(MIR_BinaryAcc.getValue(inst)));
8276 }
8277 }
8278 }
8279 }
8280 }
8281 }
8282
8283 } else {
8284 if (isWord(inst)) {
8285 if (isImm(MIR_BinaryAcc.getValue(inst))) {
8286 emitADD_Reg_Imm_Word(
8287 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
8288 getImm(MIR_BinaryAcc.getValue(inst)));
8289
8290 } else {
8291 if (isGPR_Reg(MIR_BinaryAcc.getValue(inst))) {
8292 emitADD_Reg_Reg_Word(
8293 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
8294 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
8295
8296 } else {
8297 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
8298 emitADD_Reg_Abs_Word(
8299 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
8300 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
8301
8302 } else {
8303 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
8304 emitADD_Reg_RegDisp_Word(
8305 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
8306 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
8307
8308 } else {
8309 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
8310 emitADD_Reg_RegOff_Word(
8311 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
8312 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
8313
8314 } else {
8315 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
8316 emitADD_Reg_RegIdx_Word(
8317 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
8318 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
8319
8320 } else {
8321 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8322 emitADD_Reg_RegInd_Word(
8323 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
8324 getBase(MIR_BinaryAcc.getValue(inst)));
8325 }
8326 }
8327 }
8328 }
8329 }
8330 }
8331
8332 } else {
8333 if (isQuad(inst)) {
8334 if (isImm(MIR_BinaryAcc.getValue(inst))) {
8335 emitADD_Reg_Imm_Quad(
8336 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
8337 getImm(MIR_BinaryAcc.getValue(inst)));
8338
8339 } else {
8340 if (isGPR_Reg(MIR_BinaryAcc.getValue(inst))) {
8341 emitADD_Reg_Reg_Quad(
8342 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
8343 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
8344
8345 } else {
8346 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
8347 emitADD_Reg_Abs_Quad(
8348 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
8349 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
8350
8351 } else {
8352 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
8353 emitADD_Reg_RegDisp_Quad(
8354 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
8355 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
8356
8357 } else {
8358 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
8359 emitADD_Reg_RegOff_Quad(
8360 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
8361 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
8362
8363 } else {
8364 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
8365 emitADD_Reg_RegIdx_Quad(
8366 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
8367 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
8368
8369 } else {
8370 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8371 emitADD_Reg_RegInd_Quad(
8372 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
8373 getBase(MIR_BinaryAcc.getValue(inst)));
8374 }
8375 }
8376 }
8377 }
8378 }
8379 }
8380
8381 } else {
8382 if (isImm(MIR_BinaryAcc.getValue(inst))) {
8383 emitADD_Reg_Imm(
8384 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
8385 getImm(MIR_BinaryAcc.getValue(inst)));
8386
8387 } else {
8388 if (isGPR_Reg(MIR_BinaryAcc.getValue(inst))) {
8389 emitADD_Reg_Reg(
8390 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
8391 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
8392
8393 } else {
8394 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
8395 emitADD_Reg_Abs(
8396 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
8397 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
8398
8399 } else {
8400 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
8401 emitADD_Reg_RegDisp(
8402 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
8403 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
8404
8405 } else {
8406 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
8407 emitADD_Reg_RegOff(
8408 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
8409 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
8410
8411 } else {
8412 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
8413 emitADD_Reg_RegIdx(
8414 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
8415 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
8416
8417 } else {
8418 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8419 emitADD_Reg_RegInd(
8420 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
8421 getBase(MIR_BinaryAcc.getValue(inst)));
8422 }
8423 }
8424 }
8425 }
8426 }
8427 }
8428 }
8429 }
8430 }
8431
8432 } else {
8433 if (isImm(MIR_BinaryAcc.getValue(inst))) {
8434 if (isByte(inst)) {
8435 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
8436 emitADD_Abs_Imm_Byte(
8437 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
8438 getImm(MIR_BinaryAcc.getValue(inst)));
8439
8440 } else {
8441 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
8442 emitADD_RegDisp_Imm_Byte(
8443 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
8444 getImm(MIR_BinaryAcc.getValue(inst)));
8445
8446 } else {
8447 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
8448 emitADD_RegOff_Imm_Byte(
8449 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
8450 getImm(MIR_BinaryAcc.getValue(inst)));
8451
8452 } else {
8453 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
8454 emitADD_RegIdx_Imm_Byte(
8455 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
8456 getImm(MIR_BinaryAcc.getValue(inst)));
8457
8458 } else {
8459 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8460 emitADD_RegInd_Imm_Byte(
8461 getBase(MIR_BinaryAcc.getResult(inst)),
8462 getImm(MIR_BinaryAcc.getValue(inst)));
8463 }
8464 }
8465 }
8466 }
8467
8468 } else {
8469 if (isWord(inst)) {
8470 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
8471 emitADD_Abs_Imm_Word(
8472 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
8473 getImm(MIR_BinaryAcc.getValue(inst)));
8474
8475 } else {
8476 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
8477 emitADD_RegDisp_Imm_Word(
8478 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
8479 getImm(MIR_BinaryAcc.getValue(inst)));
8480
8481 } else {
8482 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
8483 emitADD_RegOff_Imm_Word(
8484 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
8485 getImm(MIR_BinaryAcc.getValue(inst)));
8486
8487 } else {
8488 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
8489 emitADD_RegIdx_Imm_Word(
8490 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
8491 getImm(MIR_BinaryAcc.getValue(inst)));
8492
8493 } else {
8494 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8495 emitADD_RegInd_Imm_Word(
8496 getBase(MIR_BinaryAcc.getResult(inst)),
8497 getImm(MIR_BinaryAcc.getValue(inst)));
8498 }
8499 }
8500 }
8501 }
8502
8503 } else {
8504 if (isQuad(inst)) {
8505 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
8506 emitADD_Abs_Imm_Quad(
8507 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
8508 getImm(MIR_BinaryAcc.getValue(inst)));
8509
8510 } else {
8511 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
8512 emitADD_RegDisp_Imm_Quad(
8513 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
8514 getImm(MIR_BinaryAcc.getValue(inst)));
8515
8516 } else {
8517 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
8518 emitADD_RegOff_Imm_Quad(
8519 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
8520 getImm(MIR_BinaryAcc.getValue(inst)));
8521
8522 } else {
8523 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
8524 emitADD_RegIdx_Imm_Quad(
8525 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
8526 getImm(MIR_BinaryAcc.getValue(inst)));
8527
8528 } else {
8529 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8530 emitADD_RegInd_Imm_Quad(
8531 getBase(MIR_BinaryAcc.getResult(inst)),
8532 getImm(MIR_BinaryAcc.getValue(inst)));
8533 }
8534 }
8535 }
8536 }
8537
8538 } else {
8539 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
8540 emitADD_Abs_Imm(
8541 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
8542 getImm(MIR_BinaryAcc.getValue(inst)));
8543
8544 } else {
8545 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
8546 emitADD_RegDisp_Imm(
8547 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
8548 getImm(MIR_BinaryAcc.getValue(inst)));
8549
8550 } else {
8551 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
8552 emitADD_RegOff_Imm(
8553 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
8554 getImm(MIR_BinaryAcc.getValue(inst)));
8555
8556 } else {
8557 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
8558 emitADD_RegIdx_Imm(
8559 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
8560 getImm(MIR_BinaryAcc.getValue(inst)));
8561
8562 } else {
8563 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8564 emitADD_RegInd_Imm(
8565 getBase(MIR_BinaryAcc.getResult(inst)),
8566 getImm(MIR_BinaryAcc.getValue(inst)));
8567 }
8568 }
8569 }
8570 }
8571 }
8572 }
8573 }
8574
8575 } else {
8576 if (isByte(inst)) {
8577 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
8578 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8579 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
8580 emitADD_Abs_Reg_Byte(
8581 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
8582 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
8583
8584 } else {
8585 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
8586 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8587 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
8588 emitADD_RegDisp_Reg_Byte(
8589 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
8590 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
8591
8592 } else {
8593 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
8594 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8595 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
8596 emitADD_RegOff_Reg_Byte(
8597 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
8598 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
8599
8600 } else {
8601 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
8602 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8603 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
8604 emitADD_RegIdx_Reg_Byte(
8605 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
8606 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
8607
8608 } else {
8609 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8610 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8611 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
8612 emitADD_RegInd_Reg_Byte(
8613 getBase(MIR_BinaryAcc.getResult(inst)),
8614 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
8615 }
8616 }
8617 }
8618 }
8619
8620 } else {
8621 if (isWord(inst)) {
8622 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
8623 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8624 emitADD_Abs_Reg_Word(
8625 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
8626 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
8627
8628 } else {
8629 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
8630 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8631 emitADD_RegDisp_Reg_Word(
8632 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
8633 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
8634
8635 } else {
8636 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
8637 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8638 emitADD_RegOff_Reg_Word(
8639 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
8640 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
8641
8642 } else {
8643 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
8644 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8645 emitADD_RegIdx_Reg_Word(
8646 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
8647 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
8648
8649 } else {
8650 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8651 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8652 emitADD_RegInd_Reg_Word(
8653 getBase(MIR_BinaryAcc.getResult(inst)),
8654 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
8655 }
8656 }
8657 }
8658 }
8659
8660 } else {
8661 if (isQuad(inst)) {
8662 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
8663 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8664 emitADD_Abs_Reg_Quad(
8665 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
8666 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
8667
8668 } else {
8669 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
8670 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8671 emitADD_RegDisp_Reg_Quad(
8672 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
8673 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
8674
8675 } else {
8676 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
8677 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8678 emitADD_RegOff_Reg_Quad(
8679 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
8680 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
8681
8682 } else {
8683 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
8684 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8685 emitADD_RegIdx_Reg_Quad(
8686 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
8687 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
8688
8689 } else {
8690 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8691 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8692 emitADD_RegInd_Reg_Quad(
8693 getBase(MIR_BinaryAcc.getResult(inst)),
8694 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
8695 }
8696 }
8697 }
8698 }
8699
8700 } else {
8701 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
8702 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8703 emitADD_Abs_Reg(
8704 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
8705 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
8706
8707 } else {
8708 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
8709 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8710 emitADD_RegDisp_Reg(
8711 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
8712 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
8713
8714 } else {
8715 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
8716 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8717 emitADD_RegOff_Reg(
8718 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
8719 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
8720
8721 } else {
8722 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
8723 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8724 emitADD_RegIdx_Reg(
8725 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
8726 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
8727
8728 } else {
8729 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8730 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8731 emitADD_RegInd_Reg(
8732 getBase(MIR_BinaryAcc.getResult(inst)),
8733 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
8734 }
8735 }
8736 }
8737 }
8738 }
8739 }
8740 }
8741 }
8742 }
8743 }
8744
8745 /**
8746 * Emit the given instruction, assuming that
8747 * it is a MIR_Return instruction
8748 * and has a RET operator
8749 *
8750 * @param inst the instruction to assemble
8751 */
8752 private void doRET(Instruction inst) {
8753 if (isImm(MIR_Return.getPopBytes(inst))) {
8754 emitRET_Imm(
8755 getImm(MIR_Return.getPopBytes(inst)));
8756
8757 } else {
8758 emitRET();
8759 }
8760 }
8761
8762 /**
8763 * Emit the given instruction, assuming that
8764 * it is a MIR_BinaryAcc instruction
8765 * and has a CMPNLESS operator
8766 *
8767 * @param inst the instruction to assemble
8768 */
8769 private void doCMPNLESS(Instruction inst) {
8770 if (isXMM_Reg(MIR_BinaryAcc.getValue(inst))) {
8771 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8772 emitCMPNLESS_Reg_Reg(
8773 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
8774 getXMM_Reg(MIR_BinaryAcc.getValue(inst)));
8775
8776 } else {
8777 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
8778 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8779 emitCMPNLESS_Reg_Abs(
8780 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
8781 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
8782
8783 } else {
8784 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
8785 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8786 emitCMPNLESS_Reg_RegDisp(
8787 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
8788 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
8789
8790 } else {
8791 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
8792 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8793 emitCMPNLESS_Reg_RegOff(
8794 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
8795 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
8796
8797 } else {
8798 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
8799 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8800 emitCMPNLESS_Reg_RegIdx(
8801 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
8802 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
8803
8804 } else {
8805 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8806 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8807 emitCMPNLESS_Reg_RegInd(
8808 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
8809 getBase(MIR_BinaryAcc.getValue(inst)));
8810 }
8811 }
8812 }
8813 }
8814 }
8815 }
8816
8817 /**
8818 * Emit the given instruction, assuming that
8819 * it is a MIR_BinaryAcc instruction
8820 * and has a DIVSD operator
8821 *
8822 * @param inst the instruction to assemble
8823 */
8824 private void doDIVSD(Instruction inst) {
8825 if (isXMM_Reg(MIR_BinaryAcc.getValue(inst))) {
8826 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8827 emitDIVSD_Reg_Reg(
8828 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
8829 getXMM_Reg(MIR_BinaryAcc.getValue(inst)));
8830
8831 } else {
8832 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
8833 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8834 emitDIVSD_Reg_Abs(
8835 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
8836 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
8837
8838 } else {
8839 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
8840 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8841 emitDIVSD_Reg_RegDisp(
8842 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
8843 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
8844
8845 } else {
8846 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
8847 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8848 emitDIVSD_Reg_RegOff(
8849 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
8850 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
8851
8852 } else {
8853 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
8854 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8855 emitDIVSD_Reg_RegIdx(
8856 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
8857 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
8858
8859 } else {
8860 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8861 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8862 emitDIVSD_Reg_RegInd(
8863 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
8864 getBase(MIR_BinaryAcc.getValue(inst)));
8865 }
8866 }
8867 }
8868 }
8869 }
8870 }
8871
8872 /**
8873 * Emit the given instruction, assuming that
8874 * it is a MIR_Unary instruction
8875 * and has a CVTSI2SDQ operator
8876 *
8877 * @param inst the instruction to assemble
8878 */
8879 private void doCVTSI2SDQ(Instruction inst) {
8880 if (isGPR_Reg(MIR_Unary.getVal(inst))) {
8881 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8882 if (VM.VerifyAssertions && !isQuad(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
8883 emitCVTSI2SDQ_Reg_Reg_Quad(
8884 getXMM_Reg(MIR_Unary.getResult(inst)),
8885 getGPR_Reg(MIR_Unary.getVal(inst)));
8886
8887 } else {
8888 if (isAbs(MIR_Unary.getVal(inst))) {
8889 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8890 if (VM.VerifyAssertions && !isQuad(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
8891 emitCVTSI2SDQ_Reg_Abs_Quad(
8892 getXMM_Reg(MIR_Unary.getResult(inst)),
8893 getDisp(MIR_Unary.getVal(inst)).toWord().toAddress());
8894
8895 } else {
8896 if (isRegDisp(MIR_Unary.getVal(inst))) {
8897 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8898 if (VM.VerifyAssertions && !isQuad(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
8899 emitCVTSI2SDQ_Reg_RegDisp_Quad(
8900 getXMM_Reg(MIR_Unary.getResult(inst)),
8901 getBase(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
8902
8903 } else {
8904 if (isRegOff(MIR_Unary.getVal(inst))) {
8905 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8906 if (VM.VerifyAssertions && !isQuad(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
8907 emitCVTSI2SDQ_Reg_RegOff_Quad(
8908 getXMM_Reg(MIR_Unary.getResult(inst)),
8909 getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
8910
8911 } else {
8912 if (isRegIdx(MIR_Unary.getVal(inst))) {
8913 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8914 if (VM.VerifyAssertions && !isQuad(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
8915 emitCVTSI2SDQ_Reg_RegIdx_Quad(
8916 getXMM_Reg(MIR_Unary.getResult(inst)),
8917 getBase(MIR_Unary.getVal(inst)), getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
8918
8919 } else {
8920 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8921 if (VM.VerifyAssertions && !isRegInd(MIR_Unary.getVal(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8922 if (VM.VerifyAssertions && !isQuad(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
8923 emitCVTSI2SDQ_Reg_RegInd_Quad(
8924 getXMM_Reg(MIR_Unary.getResult(inst)),
8925 getBase(MIR_Unary.getVal(inst)));
8926 }
8927 }
8928 }
8929 }
8930 }
8931 }
8932
8933 /**
8934 * Emit the given instruction, assuming that
8935 * it is a MIR_UnaryAcc instruction
8936 * and has a FCHS operator
8937 *
8938 * @param inst the instruction to assemble
8939 */
8940 private void doFCHS(Instruction inst) {
8941 emitFCHS();
8942 }
8943
8944 /**
8945 * Emit the given instruction, assuming that
8946 * it is a MIR_Divide instruction
8947 * and has a IDIV operator
8948 *
8949 * @param inst the instruction to assemble
8950 */
8951 private void doIDIV(Instruction inst) {
8952 if (isQuad(inst)) {
8953 if (isGPR_Reg(MIR_Divide.getValue(inst))) {
8954 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Divide.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8955 emitIDIV_Reg_Reg_Quad(
8956 getGPR_Reg(MIR_Divide.getResult2(inst)),
8957 getGPR_Reg(MIR_Divide.getValue(inst)));
8958
8959 } else {
8960 if (isAbs(MIR_Divide.getValue(inst))) {
8961 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Divide.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8962 emitIDIV_Reg_Abs_Quad(
8963 getGPR_Reg(MIR_Divide.getResult2(inst)),
8964 getDisp(MIR_Divide.getValue(inst)).toWord().toAddress());
8965
8966 } else {
8967 if (isRegDisp(MIR_Divide.getValue(inst))) {
8968 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Divide.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8969 emitIDIV_Reg_RegDisp_Quad(
8970 getGPR_Reg(MIR_Divide.getResult2(inst)),
8971 getBase(MIR_Divide.getValue(inst)), getDisp(MIR_Divide.getValue(inst)));
8972
8973 } else {
8974 if (isRegOff(MIR_Divide.getValue(inst))) {
8975 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Divide.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8976 emitIDIV_Reg_RegOff_Quad(
8977 getGPR_Reg(MIR_Divide.getResult2(inst)),
8978 getIndex(MIR_Divide.getValue(inst)), getScale(MIR_Divide.getValue(inst)), getDisp(MIR_Divide.getValue(inst)));
8979
8980 } else {
8981 if (isRegIdx(MIR_Divide.getValue(inst))) {
8982 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Divide.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8983 emitIDIV_Reg_RegIdx_Quad(
8984 getGPR_Reg(MIR_Divide.getResult2(inst)),
8985 getBase(MIR_Divide.getValue(inst)), getIndex(MIR_Divide.getValue(inst)), getScale(MIR_Divide.getValue(inst)), getDisp(MIR_Divide.getValue(inst)));
8986
8987 } else {
8988 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Divide.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8989 if (VM.VerifyAssertions && !isRegInd(MIR_Divide.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
8990 emitIDIV_Reg_RegInd_Quad(
8991 getGPR_Reg(MIR_Divide.getResult2(inst)),
8992 getBase(MIR_Divide.getValue(inst)));
8993 }
8994 }
8995 }
8996 }
8997 }
8998
8999 } else {
9000 if (isGPR_Reg(MIR_Divide.getValue(inst))) {
9001 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Divide.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9002 emitIDIV_Reg_Reg(
9003 getGPR_Reg(MIR_Divide.getResult2(inst)),
9004 getGPR_Reg(MIR_Divide.getValue(inst)));
9005
9006 } else {
9007 if (isAbs(MIR_Divide.getValue(inst))) {
9008 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Divide.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9009 emitIDIV_Reg_Abs(
9010 getGPR_Reg(MIR_Divide.getResult2(inst)),
9011 getDisp(MIR_Divide.getValue(inst)).toWord().toAddress());
9012
9013 } else {
9014 if (isRegDisp(MIR_Divide.getValue(inst))) {
9015 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Divide.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9016 emitIDIV_Reg_RegDisp(
9017 getGPR_Reg(MIR_Divide.getResult2(inst)),
9018 getBase(MIR_Divide.getValue(inst)), getDisp(MIR_Divide.getValue(inst)));
9019
9020 } else {
9021 if (isRegOff(MIR_Divide.getValue(inst))) {
9022 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Divide.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9023 emitIDIV_Reg_RegOff(
9024 getGPR_Reg(MIR_Divide.getResult2(inst)),
9025 getIndex(MIR_Divide.getValue(inst)), getScale(MIR_Divide.getValue(inst)), getDisp(MIR_Divide.getValue(inst)));
9026
9027 } else {
9028 if (isRegIdx(MIR_Divide.getValue(inst))) {
9029 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Divide.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9030 emitIDIV_Reg_RegIdx(
9031 getGPR_Reg(MIR_Divide.getResult2(inst)),
9032 getBase(MIR_Divide.getValue(inst)), getIndex(MIR_Divide.getValue(inst)), getScale(MIR_Divide.getValue(inst)), getDisp(MIR_Divide.getValue(inst)));
9033
9034 } else {
9035 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Divide.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9036 if (VM.VerifyAssertions && !isRegInd(MIR_Divide.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9037 emitIDIV_Reg_RegInd(
9038 getGPR_Reg(MIR_Divide.getResult2(inst)),
9039 getBase(MIR_Divide.getValue(inst)));
9040 }
9041 }
9042 }
9043 }
9044 }
9045 }
9046 }
9047
9048 /**
9049 * Emit the given instruction, assuming that
9050 * it is a MIR_DoubleShift instruction
9051 * and has a SHLD operator
9052 *
9053 * @param inst the instruction to assemble
9054 */
9055 private void doSHLD(Instruction inst) {
9056 if (isQuad(inst)) {
9057 if (isImm(MIR_DoubleShift.getBitsToShift(inst))) {
9058 if (isGPR_Reg(MIR_DoubleShift.getResult(inst))) {
9059 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9060 emitSHLD_Reg_Reg_Imm_Quad(
9061 getGPR_Reg(MIR_DoubleShift.getResult(inst)),
9062 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
9063 getImm(MIR_DoubleShift.getBitsToShift(inst)));
9064
9065 } else {
9066 if (isAbs(MIR_DoubleShift.getResult(inst))) {
9067 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9068 emitSHLD_Abs_Reg_Imm_Quad(
9069 getDisp(MIR_DoubleShift.getResult(inst)).toWord().toAddress(),
9070 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
9071 getImm(MIR_DoubleShift.getBitsToShift(inst)));
9072
9073 } else {
9074 if (isRegDisp(MIR_DoubleShift.getResult(inst))) {
9075 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9076 emitSHLD_RegDisp_Reg_Imm_Quad(
9077 getBase(MIR_DoubleShift.getResult(inst)), getDisp(MIR_DoubleShift.getResult(inst)),
9078 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
9079 getImm(MIR_DoubleShift.getBitsToShift(inst)));
9080
9081 } else {
9082 if (isRegOff(MIR_DoubleShift.getResult(inst))) {
9083 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9084 emitSHLD_RegOff_Reg_Imm_Quad(
9085 getIndex(MIR_DoubleShift.getResult(inst)), getScale(MIR_DoubleShift.getResult(inst)), getDisp(MIR_DoubleShift.getResult(inst)),
9086 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
9087 getImm(MIR_DoubleShift.getBitsToShift(inst)));
9088
9089 } else {
9090 if (isRegIdx(MIR_DoubleShift.getResult(inst))) {
9091 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9092 emitSHLD_RegIdx_Reg_Imm_Quad(
9093 getBase(MIR_DoubleShift.getResult(inst)), getIndex(MIR_DoubleShift.getResult(inst)), getScale(MIR_DoubleShift.getResult(inst)), getDisp(MIR_DoubleShift.getResult(inst)),
9094 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
9095 getImm(MIR_DoubleShift.getBitsToShift(inst)));
9096
9097 } else {
9098 if (VM.VerifyAssertions && !isRegInd(MIR_DoubleShift.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9099 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9100 emitSHLD_RegInd_Reg_Imm_Quad(
9101 getBase(MIR_DoubleShift.getResult(inst)),
9102 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
9103 getImm(MIR_DoubleShift.getBitsToShift(inst)));
9104 }
9105 }
9106 }
9107 }
9108 }
9109
9110 } else {
9111 if (isGPR_Reg(MIR_DoubleShift.getResult(inst))) {
9112 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9113 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getBitsToShift(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9114 emitSHLD_Reg_Reg_Reg_Quad(
9115 getGPR_Reg(MIR_DoubleShift.getResult(inst)),
9116 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
9117 getGPR_Reg(MIR_DoubleShift.getBitsToShift(inst)));
9118
9119 } else {
9120 if (isAbs(MIR_DoubleShift.getResult(inst))) {
9121 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9122 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getBitsToShift(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9123 emitSHLD_Abs_Reg_Reg_Quad(
9124 getDisp(MIR_DoubleShift.getResult(inst)).toWord().toAddress(),
9125 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
9126 getGPR_Reg(MIR_DoubleShift.getBitsToShift(inst)));
9127
9128 } else {
9129 if (isRegDisp(MIR_DoubleShift.getResult(inst))) {
9130 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9131 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getBitsToShift(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9132 emitSHLD_RegDisp_Reg_Reg_Quad(
9133 getBase(MIR_DoubleShift.getResult(inst)), getDisp(MIR_DoubleShift.getResult(inst)),
9134 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
9135 getGPR_Reg(MIR_DoubleShift.getBitsToShift(inst)));
9136
9137 } else {
9138 if (isRegOff(MIR_DoubleShift.getResult(inst))) {
9139 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9140 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getBitsToShift(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9141 emitSHLD_RegOff_Reg_Reg_Quad(
9142 getIndex(MIR_DoubleShift.getResult(inst)), getScale(MIR_DoubleShift.getResult(inst)), getDisp(MIR_DoubleShift.getResult(inst)),
9143 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
9144 getGPR_Reg(MIR_DoubleShift.getBitsToShift(inst)));
9145
9146 } else {
9147 if (isRegIdx(MIR_DoubleShift.getResult(inst))) {
9148 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9149 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getBitsToShift(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9150 emitSHLD_RegIdx_Reg_Reg_Quad(
9151 getBase(MIR_DoubleShift.getResult(inst)), getIndex(MIR_DoubleShift.getResult(inst)), getScale(MIR_DoubleShift.getResult(inst)), getDisp(MIR_DoubleShift.getResult(inst)),
9152 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
9153 getGPR_Reg(MIR_DoubleShift.getBitsToShift(inst)));
9154
9155 } else {
9156 if (VM.VerifyAssertions && !isRegInd(MIR_DoubleShift.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9157 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9158 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getBitsToShift(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9159 emitSHLD_RegInd_Reg_Reg_Quad(
9160 getBase(MIR_DoubleShift.getResult(inst)),
9161 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
9162 getGPR_Reg(MIR_DoubleShift.getBitsToShift(inst)));
9163 }
9164 }
9165 }
9166 }
9167 }
9168 }
9169
9170 } else {
9171 if (isImm(MIR_DoubleShift.getBitsToShift(inst))) {
9172 if (isGPR_Reg(MIR_DoubleShift.getResult(inst))) {
9173 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9174 emitSHLD_Reg_Reg_Imm(
9175 getGPR_Reg(MIR_DoubleShift.getResult(inst)),
9176 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
9177 getImm(MIR_DoubleShift.getBitsToShift(inst)));
9178
9179 } else {
9180 if (isAbs(MIR_DoubleShift.getResult(inst))) {
9181 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9182 emitSHLD_Abs_Reg_Imm(
9183 getDisp(MIR_DoubleShift.getResult(inst)).toWord().toAddress(),
9184 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
9185 getImm(MIR_DoubleShift.getBitsToShift(inst)));
9186
9187 } else {
9188 if (isRegDisp(MIR_DoubleShift.getResult(inst))) {
9189 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9190 emitSHLD_RegDisp_Reg_Imm(
9191 getBase(MIR_DoubleShift.getResult(inst)), getDisp(MIR_DoubleShift.getResult(inst)),
9192 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
9193 getImm(MIR_DoubleShift.getBitsToShift(inst)));
9194
9195 } else {
9196 if (isRegOff(MIR_DoubleShift.getResult(inst))) {
9197 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9198 emitSHLD_RegOff_Reg_Imm(
9199 getIndex(MIR_DoubleShift.getResult(inst)), getScale(MIR_DoubleShift.getResult(inst)), getDisp(MIR_DoubleShift.getResult(inst)),
9200 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
9201 getImm(MIR_DoubleShift.getBitsToShift(inst)));
9202
9203 } else {
9204 if (isRegIdx(MIR_DoubleShift.getResult(inst))) {
9205 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9206 emitSHLD_RegIdx_Reg_Imm(
9207 getBase(MIR_DoubleShift.getResult(inst)), getIndex(MIR_DoubleShift.getResult(inst)), getScale(MIR_DoubleShift.getResult(inst)), getDisp(MIR_DoubleShift.getResult(inst)),
9208 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
9209 getImm(MIR_DoubleShift.getBitsToShift(inst)));
9210
9211 } else {
9212 if (VM.VerifyAssertions && !isRegInd(MIR_DoubleShift.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9213 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9214 emitSHLD_RegInd_Reg_Imm(
9215 getBase(MIR_DoubleShift.getResult(inst)),
9216 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
9217 getImm(MIR_DoubleShift.getBitsToShift(inst)));
9218 }
9219 }
9220 }
9221 }
9222 }
9223
9224 } else {
9225 if (isGPR_Reg(MIR_DoubleShift.getResult(inst))) {
9226 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9227 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getBitsToShift(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9228 emitSHLD_Reg_Reg_Reg(
9229 getGPR_Reg(MIR_DoubleShift.getResult(inst)),
9230 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
9231 getGPR_Reg(MIR_DoubleShift.getBitsToShift(inst)));
9232
9233 } else {
9234 if (isAbs(MIR_DoubleShift.getResult(inst))) {
9235 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9236 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getBitsToShift(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9237 emitSHLD_Abs_Reg_Reg(
9238 getDisp(MIR_DoubleShift.getResult(inst)).toWord().toAddress(),
9239 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
9240 getGPR_Reg(MIR_DoubleShift.getBitsToShift(inst)));
9241
9242 } else {
9243 if (isRegDisp(MIR_DoubleShift.getResult(inst))) {
9244 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9245 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getBitsToShift(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9246 emitSHLD_RegDisp_Reg_Reg(
9247 getBase(MIR_DoubleShift.getResult(inst)), getDisp(MIR_DoubleShift.getResult(inst)),
9248 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
9249 getGPR_Reg(MIR_DoubleShift.getBitsToShift(inst)));
9250
9251 } else {
9252 if (isRegOff(MIR_DoubleShift.getResult(inst))) {
9253 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9254 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getBitsToShift(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9255 emitSHLD_RegOff_Reg_Reg(
9256 getIndex(MIR_DoubleShift.getResult(inst)), getScale(MIR_DoubleShift.getResult(inst)), getDisp(MIR_DoubleShift.getResult(inst)),
9257 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
9258 getGPR_Reg(MIR_DoubleShift.getBitsToShift(inst)));
9259
9260 } else {
9261 if (isRegIdx(MIR_DoubleShift.getResult(inst))) {
9262 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9263 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getBitsToShift(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9264 emitSHLD_RegIdx_Reg_Reg(
9265 getBase(MIR_DoubleShift.getResult(inst)), getIndex(MIR_DoubleShift.getResult(inst)), getScale(MIR_DoubleShift.getResult(inst)), getDisp(MIR_DoubleShift.getResult(inst)),
9266 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
9267 getGPR_Reg(MIR_DoubleShift.getBitsToShift(inst)));
9268
9269 } else {
9270 if (VM.VerifyAssertions && !isRegInd(MIR_DoubleShift.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9271 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getSource(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9272 if (VM.VerifyAssertions && !isGPR_Reg(MIR_DoubleShift.getBitsToShift(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9273 emitSHLD_RegInd_Reg_Reg(
9274 getBase(MIR_DoubleShift.getResult(inst)),
9275 getGPR_Reg(MIR_DoubleShift.getSource(inst)),
9276 getGPR_Reg(MIR_DoubleShift.getBitsToShift(inst)));
9277 }
9278 }
9279 }
9280 }
9281 }
9282 }
9283 }
9284 }
9285
9286 /**
9287 * Emit the given instruction, assuming that
9288 * it is a MIR_BinaryAcc instruction
9289 * and has a DIVSS operator
9290 *
9291 * @param inst the instruction to assemble
9292 */
9293 private void doDIVSS(Instruction inst) {
9294 if (isXMM_Reg(MIR_BinaryAcc.getValue(inst))) {
9295 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9296 emitDIVSS_Reg_Reg(
9297 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
9298 getXMM_Reg(MIR_BinaryAcc.getValue(inst)));
9299
9300 } else {
9301 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
9302 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9303 emitDIVSS_Reg_Abs(
9304 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
9305 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
9306
9307 } else {
9308 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
9309 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9310 emitDIVSS_Reg_RegDisp(
9311 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
9312 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
9313
9314 } else {
9315 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
9316 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9317 emitDIVSS_Reg_RegOff(
9318 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
9319 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
9320
9321 } else {
9322 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
9323 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9324 emitDIVSS_Reg_RegIdx(
9325 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
9326 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
9327
9328 } else {
9329 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9330 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9331 emitDIVSS_Reg_RegInd(
9332 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
9333 getBase(MIR_BinaryAcc.getValue(inst)));
9334 }
9335 }
9336 }
9337 }
9338 }
9339 }
9340
9341 /**
9342 * Emit the given instruction, assuming that
9343 * it is a MIR_Test instruction
9344 * and has a TEST operator
9345 *
9346 * @param inst the instruction to assemble
9347 */
9348 private void doTEST(Instruction inst) {
9349 if (isImm(MIR_Test.getVal2(inst))) {
9350 if (isByte(inst)) {
9351 if (isGPR_Reg(MIR_Test.getVal1(inst))) {
9352 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_Test.getVal1(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
9353 emitTEST_Reg_Imm_Byte(
9354 getGPR_Reg(MIR_Test.getVal1(inst)),
9355 getImm(MIR_Test.getVal2(inst)));
9356
9357 } else {
9358 if (isAbs(MIR_Test.getVal1(inst))) {
9359 emitTEST_Abs_Imm_Byte(
9360 getDisp(MIR_Test.getVal1(inst)).toWord().toAddress(),
9361 getImm(MIR_Test.getVal2(inst)));
9362
9363 } else {
9364 if (isRegDisp(MIR_Test.getVal1(inst))) {
9365 emitTEST_RegDisp_Imm_Byte(
9366 getBase(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
9367 getImm(MIR_Test.getVal2(inst)));
9368
9369 } else {
9370 if (isRegOff(MIR_Test.getVal1(inst))) {
9371 emitTEST_RegOff_Imm_Byte(
9372 getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
9373 getImm(MIR_Test.getVal2(inst)));
9374
9375 } else {
9376 if (isRegIdx(MIR_Test.getVal1(inst))) {
9377 emitTEST_RegIdx_Imm_Byte(
9378 getBase(MIR_Test.getVal1(inst)), getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
9379 getImm(MIR_Test.getVal2(inst)));
9380
9381 } else {
9382 if (VM.VerifyAssertions && !isRegInd(MIR_Test.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9383 emitTEST_RegInd_Imm_Byte(
9384 getBase(MIR_Test.getVal1(inst)),
9385 getImm(MIR_Test.getVal2(inst)));
9386 }
9387 }
9388 }
9389 }
9390 }
9391
9392 } else {
9393 if (isWord(inst)) {
9394 if (isGPR_Reg(MIR_Test.getVal1(inst))) {
9395 emitTEST_Reg_Imm_Word(
9396 getGPR_Reg(MIR_Test.getVal1(inst)),
9397 getImm(MIR_Test.getVal2(inst)));
9398
9399 } else {
9400 if (isAbs(MIR_Test.getVal1(inst))) {
9401 emitTEST_Abs_Imm_Word(
9402 getDisp(MIR_Test.getVal1(inst)).toWord().toAddress(),
9403 getImm(MIR_Test.getVal2(inst)));
9404
9405 } else {
9406 if (isRegDisp(MIR_Test.getVal1(inst))) {
9407 emitTEST_RegDisp_Imm_Word(
9408 getBase(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
9409 getImm(MIR_Test.getVal2(inst)));
9410
9411 } else {
9412 if (isRegOff(MIR_Test.getVal1(inst))) {
9413 emitTEST_RegOff_Imm_Word(
9414 getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
9415 getImm(MIR_Test.getVal2(inst)));
9416
9417 } else {
9418 if (isRegIdx(MIR_Test.getVal1(inst))) {
9419 emitTEST_RegIdx_Imm_Word(
9420 getBase(MIR_Test.getVal1(inst)), getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
9421 getImm(MIR_Test.getVal2(inst)));
9422
9423 } else {
9424 if (VM.VerifyAssertions && !isRegInd(MIR_Test.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9425 emitTEST_RegInd_Imm_Word(
9426 getBase(MIR_Test.getVal1(inst)),
9427 getImm(MIR_Test.getVal2(inst)));
9428 }
9429 }
9430 }
9431 }
9432 }
9433
9434 } else {
9435 if (isQuad(inst)) {
9436 if (isGPR_Reg(MIR_Test.getVal1(inst))) {
9437 emitTEST_Reg_Imm_Quad(
9438 getGPR_Reg(MIR_Test.getVal1(inst)),
9439 getImm(MIR_Test.getVal2(inst)));
9440
9441 } else {
9442 if (isAbs(MIR_Test.getVal1(inst))) {
9443 emitTEST_Abs_Imm_Quad(
9444 getDisp(MIR_Test.getVal1(inst)).toWord().toAddress(),
9445 getImm(MIR_Test.getVal2(inst)));
9446
9447 } else {
9448 if (isRegDisp(MIR_Test.getVal1(inst))) {
9449 emitTEST_RegDisp_Imm_Quad(
9450 getBase(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
9451 getImm(MIR_Test.getVal2(inst)));
9452
9453 } else {
9454 if (isRegOff(MIR_Test.getVal1(inst))) {
9455 emitTEST_RegOff_Imm_Quad(
9456 getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
9457 getImm(MIR_Test.getVal2(inst)));
9458
9459 } else {
9460 if (isRegIdx(MIR_Test.getVal1(inst))) {
9461 emitTEST_RegIdx_Imm_Quad(
9462 getBase(MIR_Test.getVal1(inst)), getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
9463 getImm(MIR_Test.getVal2(inst)));
9464
9465 } else {
9466 if (VM.VerifyAssertions && !isRegInd(MIR_Test.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9467 emitTEST_RegInd_Imm_Quad(
9468 getBase(MIR_Test.getVal1(inst)),
9469 getImm(MIR_Test.getVal2(inst)));
9470 }
9471 }
9472 }
9473 }
9474 }
9475
9476 } else {
9477 if (isGPR_Reg(MIR_Test.getVal1(inst))) {
9478 emitTEST_Reg_Imm(
9479 getGPR_Reg(MIR_Test.getVal1(inst)),
9480 getImm(MIR_Test.getVal2(inst)));
9481
9482 } else {
9483 if (isAbs(MIR_Test.getVal1(inst))) {
9484 emitTEST_Abs_Imm(
9485 getDisp(MIR_Test.getVal1(inst)).toWord().toAddress(),
9486 getImm(MIR_Test.getVal2(inst)));
9487
9488 } else {
9489 if (isRegDisp(MIR_Test.getVal1(inst))) {
9490 emitTEST_RegDisp_Imm(
9491 getBase(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
9492 getImm(MIR_Test.getVal2(inst)));
9493
9494 } else {
9495 if (isRegOff(MIR_Test.getVal1(inst))) {
9496 emitTEST_RegOff_Imm(
9497 getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
9498 getImm(MIR_Test.getVal2(inst)));
9499
9500 } else {
9501 if (isRegIdx(MIR_Test.getVal1(inst))) {
9502 emitTEST_RegIdx_Imm(
9503 getBase(MIR_Test.getVal1(inst)), getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
9504 getImm(MIR_Test.getVal2(inst)));
9505
9506 } else {
9507 if (VM.VerifyAssertions && !isRegInd(MIR_Test.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9508 emitTEST_RegInd_Imm(
9509 getBase(MIR_Test.getVal1(inst)),
9510 getImm(MIR_Test.getVal2(inst)));
9511 }
9512 }
9513 }
9514 }
9515 }
9516 }
9517 }
9518 }
9519
9520 } else {
9521 if (isByte(inst)) {
9522 if (isGPR_Reg(MIR_Test.getVal1(inst))) {
9523 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9524 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_Test.getVal1(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
9525 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_Test.getVal2(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
9526 emitTEST_Reg_Reg_Byte(
9527 getGPR_Reg(MIR_Test.getVal1(inst)),
9528 getGPR_Reg(MIR_Test.getVal2(inst)));
9529
9530 } else {
9531 if (isAbs(MIR_Test.getVal1(inst))) {
9532 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9533 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_Test.getVal2(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
9534 emitTEST_Abs_Reg_Byte(
9535 getDisp(MIR_Test.getVal1(inst)).toWord().toAddress(),
9536 getGPR_Reg(MIR_Test.getVal2(inst)));
9537
9538 } else {
9539 if (isRegDisp(MIR_Test.getVal1(inst))) {
9540 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9541 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_Test.getVal2(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
9542 emitTEST_RegDisp_Reg_Byte(
9543 getBase(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
9544 getGPR_Reg(MIR_Test.getVal2(inst)));
9545
9546 } else {
9547 if (isRegOff(MIR_Test.getVal1(inst))) {
9548 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9549 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_Test.getVal2(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
9550 emitTEST_RegOff_Reg_Byte(
9551 getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
9552 getGPR_Reg(MIR_Test.getVal2(inst)));
9553
9554 } else {
9555 if (isRegIdx(MIR_Test.getVal1(inst))) {
9556 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9557 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_Test.getVal2(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
9558 emitTEST_RegIdx_Reg_Byte(
9559 getBase(MIR_Test.getVal1(inst)), getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
9560 getGPR_Reg(MIR_Test.getVal2(inst)));
9561
9562 } else {
9563 if (VM.VerifyAssertions && !isRegInd(MIR_Test.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9564 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9565 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_Test.getVal2(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
9566 emitTEST_RegInd_Reg_Byte(
9567 getBase(MIR_Test.getVal1(inst)),
9568 getGPR_Reg(MIR_Test.getVal2(inst)));
9569 }
9570 }
9571 }
9572 }
9573 }
9574
9575 } else {
9576 if (isWord(inst)) {
9577 if (isGPR_Reg(MIR_Test.getVal1(inst))) {
9578 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9579 emitTEST_Reg_Reg_Word(
9580 getGPR_Reg(MIR_Test.getVal1(inst)),
9581 getGPR_Reg(MIR_Test.getVal2(inst)));
9582
9583 } else {
9584 if (isAbs(MIR_Test.getVal1(inst))) {
9585 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9586 emitTEST_Abs_Reg_Word(
9587 getDisp(MIR_Test.getVal1(inst)).toWord().toAddress(),
9588 getGPR_Reg(MIR_Test.getVal2(inst)));
9589
9590 } else {
9591 if (isRegDisp(MIR_Test.getVal1(inst))) {
9592 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9593 emitTEST_RegDisp_Reg_Word(
9594 getBase(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
9595 getGPR_Reg(MIR_Test.getVal2(inst)));
9596
9597 } else {
9598 if (isRegOff(MIR_Test.getVal1(inst))) {
9599 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9600 emitTEST_RegOff_Reg_Word(
9601 getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
9602 getGPR_Reg(MIR_Test.getVal2(inst)));
9603
9604 } else {
9605 if (isRegIdx(MIR_Test.getVal1(inst))) {
9606 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9607 emitTEST_RegIdx_Reg_Word(
9608 getBase(MIR_Test.getVal1(inst)), getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
9609 getGPR_Reg(MIR_Test.getVal2(inst)));
9610
9611 } else {
9612 if (VM.VerifyAssertions && !isRegInd(MIR_Test.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9613 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9614 emitTEST_RegInd_Reg_Word(
9615 getBase(MIR_Test.getVal1(inst)),
9616 getGPR_Reg(MIR_Test.getVal2(inst)));
9617 }
9618 }
9619 }
9620 }
9621 }
9622
9623 } else {
9624 if (isQuad(inst)) {
9625 if (isGPR_Reg(MIR_Test.getVal1(inst))) {
9626 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9627 emitTEST_Reg_Reg_Quad(
9628 getGPR_Reg(MIR_Test.getVal1(inst)),
9629 getGPR_Reg(MIR_Test.getVal2(inst)));
9630
9631 } else {
9632 if (isAbs(MIR_Test.getVal1(inst))) {
9633 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9634 emitTEST_Abs_Reg_Quad(
9635 getDisp(MIR_Test.getVal1(inst)).toWord().toAddress(),
9636 getGPR_Reg(MIR_Test.getVal2(inst)));
9637
9638 } else {
9639 if (isRegDisp(MIR_Test.getVal1(inst))) {
9640 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9641 emitTEST_RegDisp_Reg_Quad(
9642 getBase(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
9643 getGPR_Reg(MIR_Test.getVal2(inst)));
9644
9645 } else {
9646 if (isRegOff(MIR_Test.getVal1(inst))) {
9647 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9648 emitTEST_RegOff_Reg_Quad(
9649 getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
9650 getGPR_Reg(MIR_Test.getVal2(inst)));
9651
9652 } else {
9653 if (isRegIdx(MIR_Test.getVal1(inst))) {
9654 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9655 emitTEST_RegIdx_Reg_Quad(
9656 getBase(MIR_Test.getVal1(inst)), getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
9657 getGPR_Reg(MIR_Test.getVal2(inst)));
9658
9659 } else {
9660 if (VM.VerifyAssertions && !isRegInd(MIR_Test.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9661 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9662 emitTEST_RegInd_Reg_Quad(
9663 getBase(MIR_Test.getVal1(inst)),
9664 getGPR_Reg(MIR_Test.getVal2(inst)));
9665 }
9666 }
9667 }
9668 }
9669 }
9670
9671 } else {
9672 if (isGPR_Reg(MIR_Test.getVal1(inst))) {
9673 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9674 emitTEST_Reg_Reg(
9675 getGPR_Reg(MIR_Test.getVal1(inst)),
9676 getGPR_Reg(MIR_Test.getVal2(inst)));
9677
9678 } else {
9679 if (isAbs(MIR_Test.getVal1(inst))) {
9680 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9681 emitTEST_Abs_Reg(
9682 getDisp(MIR_Test.getVal1(inst)).toWord().toAddress(),
9683 getGPR_Reg(MIR_Test.getVal2(inst)));
9684
9685 } else {
9686 if (isRegDisp(MIR_Test.getVal1(inst))) {
9687 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9688 emitTEST_RegDisp_Reg(
9689 getBase(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
9690 getGPR_Reg(MIR_Test.getVal2(inst)));
9691
9692 } else {
9693 if (isRegOff(MIR_Test.getVal1(inst))) {
9694 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9695 emitTEST_RegOff_Reg(
9696 getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
9697 getGPR_Reg(MIR_Test.getVal2(inst)));
9698
9699 } else {
9700 if (isRegIdx(MIR_Test.getVal1(inst))) {
9701 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9702 emitTEST_RegIdx_Reg(
9703 getBase(MIR_Test.getVal1(inst)), getIndex(MIR_Test.getVal1(inst)), getScale(MIR_Test.getVal1(inst)), getDisp(MIR_Test.getVal1(inst)),
9704 getGPR_Reg(MIR_Test.getVal2(inst)));
9705
9706 } else {
9707 if (VM.VerifyAssertions && !isRegInd(MIR_Test.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9708 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Test.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9709 emitTEST_RegInd_Reg(
9710 getBase(MIR_Test.getVal1(inst)),
9711 getGPR_Reg(MIR_Test.getVal2(inst)));
9712 }
9713 }
9714 }
9715 }
9716 }
9717 }
9718 }
9719 }
9720 }
9721 }
9722
9723 /**
9724 * Emit the given instruction, assuming that
9725 * it is a MIR_BinaryAcc instruction
9726 * and has a ADDSD operator
9727 *
9728 * @param inst the instruction to assemble
9729 */
9730 private void doADDSD(Instruction inst) {
9731 if (isXMM_Reg(MIR_BinaryAcc.getValue(inst))) {
9732 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9733 emitADDSD_Reg_Reg(
9734 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
9735 getXMM_Reg(MIR_BinaryAcc.getValue(inst)));
9736
9737 } else {
9738 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
9739 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9740 emitADDSD_Reg_Abs(
9741 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
9742 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
9743
9744 } else {
9745 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
9746 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9747 emitADDSD_Reg_RegDisp(
9748 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
9749 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
9750
9751 } else {
9752 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
9753 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9754 emitADDSD_Reg_RegOff(
9755 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
9756 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
9757
9758 } else {
9759 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
9760 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9761 emitADDSD_Reg_RegIdx(
9762 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
9763 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
9764
9765 } else {
9766 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9767 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9768 emitADDSD_Reg_RegInd(
9769 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
9770 getBase(MIR_BinaryAcc.getValue(inst)));
9771 }
9772 }
9773 }
9774 }
9775 }
9776 }
9777
9778 /**
9779 * Emit the given instruction, assuming that
9780 * it is a MIR_CaseLabel instruction
9781 * and has a OFFSET operator
9782 *
9783 * @param inst the instruction to assemble
9784 */
9785 private void doOFFSET(Instruction inst) {
9786 if (VM.VerifyAssertions && !isImm(MIR_CaseLabel.getIndex(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9787 if (VM.VerifyAssertions && !isImmOrLabel(MIR_CaseLabel.getTarget(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9788 emitOFFSET_Imm_ImmOrLabel(
9789 getImm(MIR_CaseLabel.getIndex(inst)),
9790 getImm(MIR_CaseLabel.getTarget(inst)), getLabel(MIR_CaseLabel.getTarget(inst)));
9791 }
9792
9793 /**
9794 * Emit the given instruction, assuming that
9795 * it is a MIR_BinaryAcc instruction
9796 * and has a SHL operator
9797 *
9798 * @param inst the instruction to assemble
9799 */
9800 private void doSHL(Instruction inst) {
9801 if (isImm(MIR_BinaryAcc.getValue(inst))) {
9802 if (isByte(inst)) {
9803 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
9804 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
9805 emitSHL_Reg_Imm_Byte(
9806 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
9807 getImm(MIR_BinaryAcc.getValue(inst)));
9808
9809 } else {
9810 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
9811 emitSHL_Abs_Imm_Byte(
9812 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
9813 getImm(MIR_BinaryAcc.getValue(inst)));
9814
9815 } else {
9816 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
9817 emitSHL_RegDisp_Imm_Byte(
9818 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
9819 getImm(MIR_BinaryAcc.getValue(inst)));
9820
9821 } else {
9822 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
9823 emitSHL_RegOff_Imm_Byte(
9824 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
9825 getImm(MIR_BinaryAcc.getValue(inst)));
9826
9827 } else {
9828 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
9829 emitSHL_RegIdx_Imm_Byte(
9830 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
9831 getImm(MIR_BinaryAcc.getValue(inst)));
9832
9833 } else {
9834 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9835 emitSHL_RegInd_Imm_Byte(
9836 getBase(MIR_BinaryAcc.getResult(inst)),
9837 getImm(MIR_BinaryAcc.getValue(inst)));
9838 }
9839 }
9840 }
9841 }
9842 }
9843
9844 } else {
9845 if (isWord(inst)) {
9846 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
9847 emitSHL_Reg_Imm_Word(
9848 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
9849 getImm(MIR_BinaryAcc.getValue(inst)));
9850
9851 } else {
9852 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
9853 emitSHL_Abs_Imm_Word(
9854 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
9855 getImm(MIR_BinaryAcc.getValue(inst)));
9856
9857 } else {
9858 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
9859 emitSHL_RegDisp_Imm_Word(
9860 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
9861 getImm(MIR_BinaryAcc.getValue(inst)));
9862
9863 } else {
9864 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
9865 emitSHL_RegOff_Imm_Word(
9866 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
9867 getImm(MIR_BinaryAcc.getValue(inst)));
9868
9869 } else {
9870 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
9871 emitSHL_RegIdx_Imm_Word(
9872 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
9873 getImm(MIR_BinaryAcc.getValue(inst)));
9874
9875 } else {
9876 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9877 emitSHL_RegInd_Imm_Word(
9878 getBase(MIR_BinaryAcc.getResult(inst)),
9879 getImm(MIR_BinaryAcc.getValue(inst)));
9880 }
9881 }
9882 }
9883 }
9884 }
9885
9886 } else {
9887 if (isQuad(inst)) {
9888 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
9889 emitSHL_Reg_Imm_Quad(
9890 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
9891 getImm(MIR_BinaryAcc.getValue(inst)));
9892
9893 } else {
9894 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
9895 emitSHL_Abs_Imm_Quad(
9896 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
9897 getImm(MIR_BinaryAcc.getValue(inst)));
9898
9899 } else {
9900 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
9901 emitSHL_RegDisp_Imm_Quad(
9902 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
9903 getImm(MIR_BinaryAcc.getValue(inst)));
9904
9905 } else {
9906 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
9907 emitSHL_RegOff_Imm_Quad(
9908 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
9909 getImm(MIR_BinaryAcc.getValue(inst)));
9910
9911 } else {
9912 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
9913 emitSHL_RegIdx_Imm_Quad(
9914 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
9915 getImm(MIR_BinaryAcc.getValue(inst)));
9916
9917 } else {
9918 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9919 emitSHL_RegInd_Imm_Quad(
9920 getBase(MIR_BinaryAcc.getResult(inst)),
9921 getImm(MIR_BinaryAcc.getValue(inst)));
9922 }
9923 }
9924 }
9925 }
9926 }
9927
9928 } else {
9929 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
9930 emitSHL_Reg_Imm(
9931 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
9932 getImm(MIR_BinaryAcc.getValue(inst)));
9933
9934 } else {
9935 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
9936 emitSHL_Abs_Imm(
9937 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
9938 getImm(MIR_BinaryAcc.getValue(inst)));
9939
9940 } else {
9941 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
9942 emitSHL_RegDisp_Imm(
9943 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
9944 getImm(MIR_BinaryAcc.getValue(inst)));
9945
9946 } else {
9947 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
9948 emitSHL_RegOff_Imm(
9949 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
9950 getImm(MIR_BinaryAcc.getValue(inst)));
9951
9952 } else {
9953 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
9954 emitSHL_RegIdx_Imm(
9955 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
9956 getImm(MIR_BinaryAcc.getValue(inst)));
9957
9958 } else {
9959 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9960 emitSHL_RegInd_Imm(
9961 getBase(MIR_BinaryAcc.getResult(inst)),
9962 getImm(MIR_BinaryAcc.getValue(inst)));
9963 }
9964 }
9965 }
9966 }
9967 }
9968 }
9969 }
9970 }
9971
9972 } else {
9973 if (isByte(inst)) {
9974 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
9975 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9976 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
9977 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
9978 emitSHL_Reg_Reg_Byte(
9979 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
9980 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
9981
9982 } else {
9983 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
9984 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9985 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
9986 emitSHL_Abs_Reg_Byte(
9987 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
9988 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
9989
9990 } else {
9991 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
9992 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
9993 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
9994 emitSHL_RegDisp_Reg_Byte(
9995 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
9996 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
9997
9998 } else {
9999 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
10000 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10001 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
10002 emitSHL_RegOff_Reg_Byte(
10003 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10004 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10005
10006 } else {
10007 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
10008 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10009 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
10010 emitSHL_RegIdx_Reg_Byte(
10011 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10012 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10013
10014 } else {
10015 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10016 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10017 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
10018 emitSHL_RegInd_Reg_Byte(
10019 getBase(MIR_BinaryAcc.getResult(inst)),
10020 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10021 }
10022 }
10023 }
10024 }
10025 }
10026
10027 } else {
10028 if (isWord(inst)) {
10029 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
10030 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10031 emitSHL_Reg_Reg_Word(
10032 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
10033 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10034
10035 } else {
10036 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
10037 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10038 emitSHL_Abs_Reg_Word(
10039 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
10040 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10041
10042 } else {
10043 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
10044 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10045 emitSHL_RegDisp_Reg_Word(
10046 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10047 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10048
10049 } else {
10050 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
10051 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10052 emitSHL_RegOff_Reg_Word(
10053 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10054 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10055
10056 } else {
10057 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
10058 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10059 emitSHL_RegIdx_Reg_Word(
10060 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10061 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10062
10063 } else {
10064 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10065 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10066 emitSHL_RegInd_Reg_Word(
10067 getBase(MIR_BinaryAcc.getResult(inst)),
10068 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10069 }
10070 }
10071 }
10072 }
10073 }
10074
10075 } else {
10076 if (isQuad(inst)) {
10077 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
10078 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10079 emitSHL_Reg_Reg_Quad(
10080 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
10081 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10082
10083 } else {
10084 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
10085 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10086 emitSHL_Abs_Reg_Quad(
10087 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
10088 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10089
10090 } else {
10091 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
10092 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10093 emitSHL_RegDisp_Reg_Quad(
10094 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10095 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10096
10097 } else {
10098 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
10099 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10100 emitSHL_RegOff_Reg_Quad(
10101 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10102 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10103
10104 } else {
10105 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
10106 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10107 emitSHL_RegIdx_Reg_Quad(
10108 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10109 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10110
10111 } else {
10112 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10113 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10114 emitSHL_RegInd_Reg_Quad(
10115 getBase(MIR_BinaryAcc.getResult(inst)),
10116 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10117 }
10118 }
10119 }
10120 }
10121 }
10122
10123 } else {
10124 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
10125 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10126 emitSHL_Reg_Reg(
10127 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
10128 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10129
10130 } else {
10131 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
10132 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10133 emitSHL_Abs_Reg(
10134 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
10135 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10136
10137 } else {
10138 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
10139 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10140 emitSHL_RegDisp_Reg(
10141 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10142 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10143
10144 } else {
10145 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
10146 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10147 emitSHL_RegOff_Reg(
10148 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10149 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10150
10151 } else {
10152 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
10153 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10154 emitSHL_RegIdx_Reg(
10155 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10156 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10157
10158 } else {
10159 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10160 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10161 emitSHL_RegInd_Reg(
10162 getBase(MIR_BinaryAcc.getResult(inst)),
10163 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10164 }
10165 }
10166 }
10167 }
10168 }
10169 }
10170 }
10171 }
10172 }
10173 }
10174
10175 /**
10176 * Emit the given instruction, assuming that
10177 * it is a MIR_Unary instruction
10178 * and has a CVTSD2SIQ operator
10179 *
10180 * @param inst the instruction to assemble
10181 */
10182 private void doCVTSD2SIQ(Instruction inst) {
10183 if (isXMM_Reg(MIR_Unary.getVal(inst))) {
10184 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10185 if (VM.VerifyAssertions && !isQuad(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
10186 emitCVTSD2SIQ_Reg_Reg_Quad(
10187 getGPR_Reg(MIR_Unary.getResult(inst)),
10188 getXMM_Reg(MIR_Unary.getVal(inst)));
10189
10190 } else {
10191 if (isAbs(MIR_Unary.getVal(inst))) {
10192 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10193 if (VM.VerifyAssertions && !isQuad(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
10194 emitCVTSD2SIQ_Reg_Abs_Quad(
10195 getGPR_Reg(MIR_Unary.getResult(inst)),
10196 getDisp(MIR_Unary.getVal(inst)).toWord().toAddress());
10197
10198 } else {
10199 if (isRegDisp(MIR_Unary.getVal(inst))) {
10200 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10201 if (VM.VerifyAssertions && !isQuad(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
10202 emitCVTSD2SIQ_Reg_RegDisp_Quad(
10203 getGPR_Reg(MIR_Unary.getResult(inst)),
10204 getBase(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
10205
10206 } else {
10207 if (isRegOff(MIR_Unary.getVal(inst))) {
10208 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10209 if (VM.VerifyAssertions && !isQuad(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
10210 emitCVTSD2SIQ_Reg_RegOff_Quad(
10211 getGPR_Reg(MIR_Unary.getResult(inst)),
10212 getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
10213
10214 } else {
10215 if (isRegIdx(MIR_Unary.getVal(inst))) {
10216 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10217 if (VM.VerifyAssertions && !isQuad(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
10218 emitCVTSD2SIQ_Reg_RegIdx_Quad(
10219 getGPR_Reg(MIR_Unary.getResult(inst)),
10220 getBase(MIR_Unary.getVal(inst)), getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
10221
10222 } else {
10223 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10224 if (VM.VerifyAssertions && !isRegInd(MIR_Unary.getVal(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10225 if (VM.VerifyAssertions && !isQuad(inst)) VM._assert(VM.NOT_REACHED, inst.toString());
10226 emitCVTSD2SIQ_Reg_RegInd_Quad(
10227 getGPR_Reg(MIR_Unary.getResult(inst)),
10228 getBase(MIR_Unary.getVal(inst)));
10229 }
10230 }
10231 }
10232 }
10233 }
10234 }
10235
10236 /**
10237 * Emit the given instruction, assuming that
10238 * it is a MIR_BinaryAcc instruction
10239 * and has a SHR operator
10240 *
10241 * @param inst the instruction to assemble
10242 */
10243 private void doSHR(Instruction inst) {
10244 if (isImm(MIR_BinaryAcc.getValue(inst))) {
10245 if (isByte(inst)) {
10246 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
10247 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
10248 emitSHR_Reg_Imm_Byte(
10249 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
10250 getImm(MIR_BinaryAcc.getValue(inst)));
10251
10252 } else {
10253 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
10254 emitSHR_Abs_Imm_Byte(
10255 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
10256 getImm(MIR_BinaryAcc.getValue(inst)));
10257
10258 } else {
10259 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
10260 emitSHR_RegDisp_Imm_Byte(
10261 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10262 getImm(MIR_BinaryAcc.getValue(inst)));
10263
10264 } else {
10265 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
10266 emitSHR_RegOff_Imm_Byte(
10267 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10268 getImm(MIR_BinaryAcc.getValue(inst)));
10269
10270 } else {
10271 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
10272 emitSHR_RegIdx_Imm_Byte(
10273 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10274 getImm(MIR_BinaryAcc.getValue(inst)));
10275
10276 } else {
10277 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10278 emitSHR_RegInd_Imm_Byte(
10279 getBase(MIR_BinaryAcc.getResult(inst)),
10280 getImm(MIR_BinaryAcc.getValue(inst)));
10281 }
10282 }
10283 }
10284 }
10285 }
10286
10287 } else {
10288 if (isWord(inst)) {
10289 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
10290 emitSHR_Reg_Imm_Word(
10291 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
10292 getImm(MIR_BinaryAcc.getValue(inst)));
10293
10294 } else {
10295 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
10296 emitSHR_Abs_Imm_Word(
10297 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
10298 getImm(MIR_BinaryAcc.getValue(inst)));
10299
10300 } else {
10301 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
10302 emitSHR_RegDisp_Imm_Word(
10303 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10304 getImm(MIR_BinaryAcc.getValue(inst)));
10305
10306 } else {
10307 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
10308 emitSHR_RegOff_Imm_Word(
10309 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10310 getImm(MIR_BinaryAcc.getValue(inst)));
10311
10312 } else {
10313 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
10314 emitSHR_RegIdx_Imm_Word(
10315 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10316 getImm(MIR_BinaryAcc.getValue(inst)));
10317
10318 } else {
10319 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10320 emitSHR_RegInd_Imm_Word(
10321 getBase(MIR_BinaryAcc.getResult(inst)),
10322 getImm(MIR_BinaryAcc.getValue(inst)));
10323 }
10324 }
10325 }
10326 }
10327 }
10328
10329 } else {
10330 if (isQuad(inst)) {
10331 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
10332 emitSHR_Reg_Imm_Quad(
10333 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
10334 getImm(MIR_BinaryAcc.getValue(inst)));
10335
10336 } else {
10337 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
10338 emitSHR_Abs_Imm_Quad(
10339 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
10340 getImm(MIR_BinaryAcc.getValue(inst)));
10341
10342 } else {
10343 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
10344 emitSHR_RegDisp_Imm_Quad(
10345 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10346 getImm(MIR_BinaryAcc.getValue(inst)));
10347
10348 } else {
10349 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
10350 emitSHR_RegOff_Imm_Quad(
10351 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10352 getImm(MIR_BinaryAcc.getValue(inst)));
10353
10354 } else {
10355 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
10356 emitSHR_RegIdx_Imm_Quad(
10357 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10358 getImm(MIR_BinaryAcc.getValue(inst)));
10359
10360 } else {
10361 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10362 emitSHR_RegInd_Imm_Quad(
10363 getBase(MIR_BinaryAcc.getResult(inst)),
10364 getImm(MIR_BinaryAcc.getValue(inst)));
10365 }
10366 }
10367 }
10368 }
10369 }
10370
10371 } else {
10372 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
10373 emitSHR_Reg_Imm(
10374 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
10375 getImm(MIR_BinaryAcc.getValue(inst)));
10376
10377 } else {
10378 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
10379 emitSHR_Abs_Imm(
10380 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
10381 getImm(MIR_BinaryAcc.getValue(inst)));
10382
10383 } else {
10384 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
10385 emitSHR_RegDisp_Imm(
10386 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10387 getImm(MIR_BinaryAcc.getValue(inst)));
10388
10389 } else {
10390 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
10391 emitSHR_RegOff_Imm(
10392 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10393 getImm(MIR_BinaryAcc.getValue(inst)));
10394
10395 } else {
10396 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
10397 emitSHR_RegIdx_Imm(
10398 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10399 getImm(MIR_BinaryAcc.getValue(inst)));
10400
10401 } else {
10402 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10403 emitSHR_RegInd_Imm(
10404 getBase(MIR_BinaryAcc.getResult(inst)),
10405 getImm(MIR_BinaryAcc.getValue(inst)));
10406 }
10407 }
10408 }
10409 }
10410 }
10411 }
10412 }
10413 }
10414
10415 } else {
10416 if (isByte(inst)) {
10417 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
10418 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10419 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
10420 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
10421 emitSHR_Reg_Reg_Byte(
10422 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
10423 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10424
10425 } else {
10426 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
10427 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10428 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
10429 emitSHR_Abs_Reg_Byte(
10430 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
10431 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10432
10433 } else {
10434 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
10435 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10436 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
10437 emitSHR_RegDisp_Reg_Byte(
10438 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10439 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10440
10441 } else {
10442 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
10443 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10444 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
10445 emitSHR_RegOff_Reg_Byte(
10446 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10447 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10448
10449 } else {
10450 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
10451 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10452 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
10453 emitSHR_RegIdx_Reg_Byte(
10454 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10455 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10456
10457 } else {
10458 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10459 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10460 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
10461 emitSHR_RegInd_Reg_Byte(
10462 getBase(MIR_BinaryAcc.getResult(inst)),
10463 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10464 }
10465 }
10466 }
10467 }
10468 }
10469
10470 } else {
10471 if (isWord(inst)) {
10472 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
10473 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10474 emitSHR_Reg_Reg_Word(
10475 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
10476 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10477
10478 } else {
10479 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
10480 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10481 emitSHR_Abs_Reg_Word(
10482 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
10483 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10484
10485 } else {
10486 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
10487 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10488 emitSHR_RegDisp_Reg_Word(
10489 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10490 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10491
10492 } else {
10493 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
10494 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10495 emitSHR_RegOff_Reg_Word(
10496 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10497 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10498
10499 } else {
10500 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
10501 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10502 emitSHR_RegIdx_Reg_Word(
10503 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10504 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10505
10506 } else {
10507 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10508 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10509 emitSHR_RegInd_Reg_Word(
10510 getBase(MIR_BinaryAcc.getResult(inst)),
10511 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10512 }
10513 }
10514 }
10515 }
10516 }
10517
10518 } else {
10519 if (isQuad(inst)) {
10520 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
10521 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10522 emitSHR_Reg_Reg_Quad(
10523 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
10524 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10525
10526 } else {
10527 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
10528 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10529 emitSHR_Abs_Reg_Quad(
10530 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
10531 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10532
10533 } else {
10534 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
10535 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10536 emitSHR_RegDisp_Reg_Quad(
10537 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10538 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10539
10540 } else {
10541 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
10542 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10543 emitSHR_RegOff_Reg_Quad(
10544 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10545 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10546
10547 } else {
10548 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
10549 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10550 emitSHR_RegIdx_Reg_Quad(
10551 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10552 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10553
10554 } else {
10555 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10556 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10557 emitSHR_RegInd_Reg_Quad(
10558 getBase(MIR_BinaryAcc.getResult(inst)),
10559 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10560 }
10561 }
10562 }
10563 }
10564 }
10565
10566 } else {
10567 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
10568 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10569 emitSHR_Reg_Reg(
10570 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
10571 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10572
10573 } else {
10574 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
10575 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10576 emitSHR_Abs_Reg(
10577 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
10578 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10579
10580 } else {
10581 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
10582 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10583 emitSHR_RegDisp_Reg(
10584 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10585 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10586
10587 } else {
10588 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
10589 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10590 emitSHR_RegOff_Reg(
10591 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10592 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10593
10594 } else {
10595 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
10596 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10597 emitSHR_RegIdx_Reg(
10598 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10599 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10600
10601 } else {
10602 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10603 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10604 emitSHR_RegInd_Reg(
10605 getBase(MIR_BinaryAcc.getResult(inst)),
10606 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
10607 }
10608 }
10609 }
10610 }
10611 }
10612 }
10613 }
10614 }
10615 }
10616 }
10617
10618 /**
10619 * Emit the given instruction, assuming that
10620 * it is a MIR_BinaryAcc instruction
10621 * and has a FMUL operator
10622 *
10623 * @param inst the instruction to assemble
10624 */
10625 private void doFMUL(Instruction inst) {
10626 if (isQuad(inst)) {
10627 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
10628 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10629 emitFMUL_Reg_Abs_Quad(
10630 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
10631 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
10632
10633 } else {
10634 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
10635 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10636 emitFMUL_Reg_RegDisp_Quad(
10637 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
10638 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
10639
10640 } else {
10641 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
10642 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10643 emitFMUL_Reg_RegOff_Quad(
10644 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
10645 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
10646
10647 } else {
10648 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
10649 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10650 emitFMUL_Reg_RegIdx_Quad(
10651 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
10652 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
10653
10654 } else {
10655 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10656 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10657 emitFMUL_Reg_RegInd_Quad(
10658 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
10659 getBase(MIR_BinaryAcc.getValue(inst)));
10660 }
10661 }
10662 }
10663 }
10664
10665 } else {
10666 if (isFPR_Reg(MIR_BinaryAcc.getValue(inst))) {
10667 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10668 emitFMUL_Reg_Reg(
10669 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
10670 getFPR_Reg(MIR_BinaryAcc.getValue(inst)));
10671
10672 } else {
10673 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
10674 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10675 emitFMUL_Reg_Abs(
10676 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
10677 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
10678
10679 } else {
10680 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
10681 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10682 emitFMUL_Reg_RegDisp(
10683 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
10684 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
10685
10686 } else {
10687 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
10688 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10689 emitFMUL_Reg_RegOff(
10690 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
10691 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
10692
10693 } else {
10694 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
10695 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10696 emitFMUL_Reg_RegIdx(
10697 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
10698 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
10699
10700 } else {
10701 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10702 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10703 emitFMUL_Reg_RegInd(
10704 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
10705 getBase(MIR_BinaryAcc.getValue(inst)));
10706 }
10707 }
10708 }
10709 }
10710 }
10711 }
10712 }
10713
10714 /**
10715 * Emit the given instruction, assuming that
10716 * it is a MIR_Nullary instruction
10717 * and has a FLDL2E operator
10718 *
10719 * @param inst the instruction to assemble
10720 */
10721 private void doFLDL2E(Instruction inst) {
10722 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Nullary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10723 emitFLDL2E_Reg(
10724 getFPR_Reg(MIR_Nullary.getResult(inst)));
10725 }
10726
10727 /**
10728 * Emit the given instruction, assuming that
10729 * it is a MIR_BinaryAcc instruction
10730 * and has a ADDSS operator
10731 *
10732 * @param inst the instruction to assemble
10733 */
10734 private void doADDSS(Instruction inst) {
10735 if (isXMM_Reg(MIR_BinaryAcc.getValue(inst))) {
10736 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10737 emitADDSS_Reg_Reg(
10738 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
10739 getXMM_Reg(MIR_BinaryAcc.getValue(inst)));
10740
10741 } else {
10742 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
10743 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10744 emitADDSS_Reg_Abs(
10745 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
10746 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
10747
10748 } else {
10749 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
10750 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10751 emitADDSS_Reg_RegDisp(
10752 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
10753 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
10754
10755 } else {
10756 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
10757 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10758 emitADDSS_Reg_RegOff(
10759 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
10760 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
10761
10762 } else {
10763 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
10764 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10765 emitADDSS_Reg_RegIdx(
10766 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
10767 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
10768
10769 } else {
10770 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10771 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10772 emitADDSS_Reg_RegInd(
10773 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
10774 getBase(MIR_BinaryAcc.getValue(inst)));
10775 }
10776 }
10777 }
10778 }
10779 }
10780 }
10781
10782 /**
10783 * Emit the given instruction, assuming that
10784 * it is a MIR_Multiply instruction
10785 * and has a MUL operator
10786 *
10787 * @param inst the instruction to assemble
10788 */
10789 private void doMUL(Instruction inst) {
10790 if (isQuad(inst)) {
10791 if (isGPR_Reg(MIR_Multiply.getValue(inst))) {
10792 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Multiply.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10793 emitMUL_Reg_Reg_Quad(
10794 getGPR_Reg(MIR_Multiply.getResult2(inst)),
10795 getGPR_Reg(MIR_Multiply.getValue(inst)));
10796
10797 } else {
10798 if (isAbs(MIR_Multiply.getValue(inst))) {
10799 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Multiply.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10800 emitMUL_Reg_Abs_Quad(
10801 getGPR_Reg(MIR_Multiply.getResult2(inst)),
10802 getDisp(MIR_Multiply.getValue(inst)).toWord().toAddress());
10803
10804 } else {
10805 if (isRegDisp(MIR_Multiply.getValue(inst))) {
10806 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Multiply.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10807 emitMUL_Reg_RegDisp_Quad(
10808 getGPR_Reg(MIR_Multiply.getResult2(inst)),
10809 getBase(MIR_Multiply.getValue(inst)), getDisp(MIR_Multiply.getValue(inst)));
10810
10811 } else {
10812 if (isRegOff(MIR_Multiply.getValue(inst))) {
10813 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Multiply.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10814 emitMUL_Reg_RegOff_Quad(
10815 getGPR_Reg(MIR_Multiply.getResult2(inst)),
10816 getIndex(MIR_Multiply.getValue(inst)), getScale(MIR_Multiply.getValue(inst)), getDisp(MIR_Multiply.getValue(inst)));
10817
10818 } else {
10819 if (isRegIdx(MIR_Multiply.getValue(inst))) {
10820 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Multiply.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10821 emitMUL_Reg_RegIdx_Quad(
10822 getGPR_Reg(MIR_Multiply.getResult2(inst)),
10823 getBase(MIR_Multiply.getValue(inst)), getIndex(MIR_Multiply.getValue(inst)), getScale(MIR_Multiply.getValue(inst)), getDisp(MIR_Multiply.getValue(inst)));
10824
10825 } else {
10826 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Multiply.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10827 if (VM.VerifyAssertions && !isRegInd(MIR_Multiply.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10828 emitMUL_Reg_RegInd_Quad(
10829 getGPR_Reg(MIR_Multiply.getResult2(inst)),
10830 getBase(MIR_Multiply.getValue(inst)));
10831 }
10832 }
10833 }
10834 }
10835 }
10836
10837 } else {
10838 if (isGPR_Reg(MIR_Multiply.getValue(inst))) {
10839 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Multiply.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10840 emitMUL_Reg_Reg(
10841 getGPR_Reg(MIR_Multiply.getResult2(inst)),
10842 getGPR_Reg(MIR_Multiply.getValue(inst)));
10843
10844 } else {
10845 if (isAbs(MIR_Multiply.getValue(inst))) {
10846 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Multiply.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10847 emitMUL_Reg_Abs(
10848 getGPR_Reg(MIR_Multiply.getResult2(inst)),
10849 getDisp(MIR_Multiply.getValue(inst)).toWord().toAddress());
10850
10851 } else {
10852 if (isRegDisp(MIR_Multiply.getValue(inst))) {
10853 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Multiply.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10854 emitMUL_Reg_RegDisp(
10855 getGPR_Reg(MIR_Multiply.getResult2(inst)),
10856 getBase(MIR_Multiply.getValue(inst)), getDisp(MIR_Multiply.getValue(inst)));
10857
10858 } else {
10859 if (isRegOff(MIR_Multiply.getValue(inst))) {
10860 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Multiply.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10861 emitMUL_Reg_RegOff(
10862 getGPR_Reg(MIR_Multiply.getResult2(inst)),
10863 getIndex(MIR_Multiply.getValue(inst)), getScale(MIR_Multiply.getValue(inst)), getDisp(MIR_Multiply.getValue(inst)));
10864
10865 } else {
10866 if (isRegIdx(MIR_Multiply.getValue(inst))) {
10867 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Multiply.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10868 emitMUL_Reg_RegIdx(
10869 getGPR_Reg(MIR_Multiply.getResult2(inst)),
10870 getBase(MIR_Multiply.getValue(inst)), getIndex(MIR_Multiply.getValue(inst)), getScale(MIR_Multiply.getValue(inst)), getDisp(MIR_Multiply.getValue(inst)));
10871
10872 } else {
10873 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Multiply.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10874 if (VM.VerifyAssertions && !isRegInd(MIR_Multiply.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10875 emitMUL_Reg_RegInd(
10876 getGPR_Reg(MIR_Multiply.getResult2(inst)),
10877 getBase(MIR_Multiply.getValue(inst)));
10878 }
10879 }
10880 }
10881 }
10882 }
10883 }
10884 }
10885
10886 /**
10887 * Emit the given instruction, assuming that
10888 * it is a MIR_BinaryAcc instruction
10889 * and has a ANDNPD operator
10890 *
10891 * @param inst the instruction to assemble
10892 */
10893 private void doANDNPD(Instruction inst) {
10894 if (isXMM_Reg(MIR_BinaryAcc.getValue(inst))) {
10895 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10896 emitANDNPD_Reg_Reg(
10897 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
10898 getXMM_Reg(MIR_BinaryAcc.getValue(inst)));
10899
10900 } else {
10901 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
10902 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10903 emitANDNPD_Reg_Abs(
10904 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
10905 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
10906
10907 } else {
10908 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
10909 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10910 emitANDNPD_Reg_RegDisp(
10911 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
10912 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
10913
10914 } else {
10915 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
10916 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10917 emitANDNPD_Reg_RegOff(
10918 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
10919 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
10920
10921 } else {
10922 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
10923 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10924 emitANDNPD_Reg_RegIdx(
10925 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
10926 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
10927
10928 } else {
10929 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10930 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10931 emitANDNPD_Reg_RegInd(
10932 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
10933 getBase(MIR_BinaryAcc.getValue(inst)));
10934 }
10935 }
10936 }
10937 }
10938 }
10939 }
10940
10941 /**
10942 * Emit the given instruction, assuming that
10943 * it is a MIR_BinaryAcc instruction
10944 * and has a ROL operator
10945 *
10946 * @param inst the instruction to assemble
10947 */
10948 private void doROL(Instruction inst) {
10949 if (isImm(MIR_BinaryAcc.getValue(inst))) {
10950 if (isByte(inst)) {
10951 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
10952 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
10953 emitROL_Reg_Imm_Byte(
10954 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
10955 getImm(MIR_BinaryAcc.getValue(inst)));
10956
10957 } else {
10958 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
10959 emitROL_Abs_Imm_Byte(
10960 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
10961 getImm(MIR_BinaryAcc.getValue(inst)));
10962
10963 } else {
10964 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
10965 emitROL_RegDisp_Imm_Byte(
10966 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10967 getImm(MIR_BinaryAcc.getValue(inst)));
10968
10969 } else {
10970 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
10971 emitROL_RegOff_Imm_Byte(
10972 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10973 getImm(MIR_BinaryAcc.getValue(inst)));
10974
10975 } else {
10976 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
10977 emitROL_RegIdx_Imm_Byte(
10978 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
10979 getImm(MIR_BinaryAcc.getValue(inst)));
10980
10981 } else {
10982 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
10983 emitROL_RegInd_Imm_Byte(
10984 getBase(MIR_BinaryAcc.getResult(inst)),
10985 getImm(MIR_BinaryAcc.getValue(inst)));
10986 }
10987 }
10988 }
10989 }
10990 }
10991
10992 } else {
10993 if (isWord(inst)) {
10994 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
10995 emitROL_Reg_Imm_Word(
10996 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
10997 getImm(MIR_BinaryAcc.getValue(inst)));
10998
10999 } else {
11000 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
11001 emitROL_Abs_Imm_Word(
11002 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
11003 getImm(MIR_BinaryAcc.getValue(inst)));
11004
11005 } else {
11006 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
11007 emitROL_RegDisp_Imm_Word(
11008 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11009 getImm(MIR_BinaryAcc.getValue(inst)));
11010
11011 } else {
11012 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
11013 emitROL_RegOff_Imm_Word(
11014 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11015 getImm(MIR_BinaryAcc.getValue(inst)));
11016
11017 } else {
11018 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
11019 emitROL_RegIdx_Imm_Word(
11020 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11021 getImm(MIR_BinaryAcc.getValue(inst)));
11022
11023 } else {
11024 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11025 emitROL_RegInd_Imm_Word(
11026 getBase(MIR_BinaryAcc.getResult(inst)),
11027 getImm(MIR_BinaryAcc.getValue(inst)));
11028 }
11029 }
11030 }
11031 }
11032 }
11033
11034 } else {
11035 if (isQuad(inst)) {
11036 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
11037 emitROL_Reg_Imm_Quad(
11038 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
11039 getImm(MIR_BinaryAcc.getValue(inst)));
11040
11041 } else {
11042 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
11043 emitROL_Abs_Imm_Quad(
11044 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
11045 getImm(MIR_BinaryAcc.getValue(inst)));
11046
11047 } else {
11048 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
11049 emitROL_RegDisp_Imm_Quad(
11050 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11051 getImm(MIR_BinaryAcc.getValue(inst)));
11052
11053 } else {
11054 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
11055 emitROL_RegOff_Imm_Quad(
11056 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11057 getImm(MIR_BinaryAcc.getValue(inst)));
11058
11059 } else {
11060 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
11061 emitROL_RegIdx_Imm_Quad(
11062 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11063 getImm(MIR_BinaryAcc.getValue(inst)));
11064
11065 } else {
11066 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11067 emitROL_RegInd_Imm_Quad(
11068 getBase(MIR_BinaryAcc.getResult(inst)),
11069 getImm(MIR_BinaryAcc.getValue(inst)));
11070 }
11071 }
11072 }
11073 }
11074 }
11075
11076 } else {
11077 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
11078 emitROL_Reg_Imm(
11079 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
11080 getImm(MIR_BinaryAcc.getValue(inst)));
11081
11082 } else {
11083 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
11084 emitROL_Abs_Imm(
11085 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
11086 getImm(MIR_BinaryAcc.getValue(inst)));
11087
11088 } else {
11089 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
11090 emitROL_RegDisp_Imm(
11091 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11092 getImm(MIR_BinaryAcc.getValue(inst)));
11093
11094 } else {
11095 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
11096 emitROL_RegOff_Imm(
11097 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11098 getImm(MIR_BinaryAcc.getValue(inst)));
11099
11100 } else {
11101 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
11102 emitROL_RegIdx_Imm(
11103 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11104 getImm(MIR_BinaryAcc.getValue(inst)));
11105
11106 } else {
11107 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11108 emitROL_RegInd_Imm(
11109 getBase(MIR_BinaryAcc.getResult(inst)),
11110 getImm(MIR_BinaryAcc.getValue(inst)));
11111 }
11112 }
11113 }
11114 }
11115 }
11116 }
11117 }
11118 }
11119
11120 } else {
11121 if (isByte(inst)) {
11122 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
11123 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11124 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
11125 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
11126 emitROL_Reg_Reg_Byte(
11127 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
11128 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11129
11130 } else {
11131 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
11132 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11133 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
11134 emitROL_Abs_Reg_Byte(
11135 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
11136 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11137
11138 } else {
11139 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
11140 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11141 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
11142 emitROL_RegDisp_Reg_Byte(
11143 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11144 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11145
11146 } else {
11147 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
11148 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11149 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
11150 emitROL_RegOff_Reg_Byte(
11151 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11152 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11153
11154 } else {
11155 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
11156 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11157 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
11158 emitROL_RegIdx_Reg_Byte(
11159 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11160 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11161
11162 } else {
11163 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11164 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11165 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
11166 emitROL_RegInd_Reg_Byte(
11167 getBase(MIR_BinaryAcc.getResult(inst)),
11168 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11169 }
11170 }
11171 }
11172 }
11173 }
11174
11175 } else {
11176 if (isWord(inst)) {
11177 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
11178 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11179 emitROL_Reg_Reg_Word(
11180 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
11181 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11182
11183 } else {
11184 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
11185 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11186 emitROL_Abs_Reg_Word(
11187 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
11188 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11189
11190 } else {
11191 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
11192 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11193 emitROL_RegDisp_Reg_Word(
11194 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11195 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11196
11197 } else {
11198 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
11199 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11200 emitROL_RegOff_Reg_Word(
11201 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11202 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11203
11204 } else {
11205 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
11206 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11207 emitROL_RegIdx_Reg_Word(
11208 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11209 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11210
11211 } else {
11212 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11213 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11214 emitROL_RegInd_Reg_Word(
11215 getBase(MIR_BinaryAcc.getResult(inst)),
11216 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11217 }
11218 }
11219 }
11220 }
11221 }
11222
11223 } else {
11224 if (isQuad(inst)) {
11225 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
11226 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11227 emitROL_Reg_Reg_Quad(
11228 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
11229 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11230
11231 } else {
11232 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
11233 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11234 emitROL_Abs_Reg_Quad(
11235 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
11236 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11237
11238 } else {
11239 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
11240 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11241 emitROL_RegDisp_Reg_Quad(
11242 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11243 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11244
11245 } else {
11246 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
11247 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11248 emitROL_RegOff_Reg_Quad(
11249 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11250 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11251
11252 } else {
11253 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
11254 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11255 emitROL_RegIdx_Reg_Quad(
11256 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11257 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11258
11259 } else {
11260 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11261 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11262 emitROL_RegInd_Reg_Quad(
11263 getBase(MIR_BinaryAcc.getResult(inst)),
11264 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11265 }
11266 }
11267 }
11268 }
11269 }
11270
11271 } else {
11272 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
11273 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11274 emitROL_Reg_Reg(
11275 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
11276 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11277
11278 } else {
11279 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
11280 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11281 emitROL_Abs_Reg(
11282 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
11283 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11284
11285 } else {
11286 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
11287 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11288 emitROL_RegDisp_Reg(
11289 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11290 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11291
11292 } else {
11293 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
11294 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11295 emitROL_RegOff_Reg(
11296 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11297 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11298
11299 } else {
11300 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
11301 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11302 emitROL_RegIdx_Reg(
11303 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11304 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11305
11306 } else {
11307 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11308 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11309 emitROL_RegInd_Reg(
11310 getBase(MIR_BinaryAcc.getResult(inst)),
11311 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11312 }
11313 }
11314 }
11315 }
11316 }
11317 }
11318 }
11319 }
11320 }
11321 }
11322
11323 /**
11324 * Emit the given instruction, assuming that
11325 * it is a MIR_Nullary instruction
11326 * and has a FLDL2T operator
11327 *
11328 * @param inst the instruction to assemble
11329 */
11330 private void doFLDL2T(Instruction inst) {
11331 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Nullary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11332 emitFLDL2T_Reg(
11333 getFPR_Reg(MIR_Nullary.getResult(inst)));
11334 }
11335
11336 /**
11337 * Emit the given instruction, assuming that
11338 * it is a MIR_BinaryAcc instruction
11339 * and has a CMPLESD operator
11340 *
11341 * @param inst the instruction to assemble
11342 */
11343 private void doCMPLESD(Instruction inst) {
11344 if (isXMM_Reg(MIR_BinaryAcc.getValue(inst))) {
11345 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11346 emitCMPLESD_Reg_Reg(
11347 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
11348 getXMM_Reg(MIR_BinaryAcc.getValue(inst)));
11349
11350 } else {
11351 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
11352 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11353 emitCMPLESD_Reg_Abs(
11354 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
11355 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
11356
11357 } else {
11358 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
11359 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11360 emitCMPLESD_Reg_RegDisp(
11361 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
11362 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
11363
11364 } else {
11365 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
11366 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11367 emitCMPLESD_Reg_RegOff(
11368 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
11369 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
11370
11371 } else {
11372 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
11373 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11374 emitCMPLESD_Reg_RegIdx(
11375 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
11376 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
11377
11378 } else {
11379 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11380 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11381 emitCMPLESD_Reg_RegInd(
11382 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
11383 getBase(MIR_BinaryAcc.getValue(inst)));
11384 }
11385 }
11386 }
11387 }
11388 }
11389 }
11390
11391 /**
11392 * Emit the given instruction, assuming that
11393 * it is a MIR_Nullary instruction
11394 * and has a FFREE operator
11395 *
11396 * @param inst the instruction to assemble
11397 */
11398 private void doFFREE(Instruction inst) {
11399 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Nullary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11400 emitFFREE_Reg(
11401 getFPR_Reg(MIR_Nullary.getResult(inst)));
11402 }
11403
11404 /**
11405 * Emit the given instruction, assuming that
11406 * it is a MIR_Nullary instruction
11407 * and has a FLD1 operator
11408 *
11409 * @param inst the instruction to assemble
11410 */
11411 private void doFLD1(Instruction inst) {
11412 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Nullary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11413 emitFLD1_Reg(
11414 getFPR_Reg(MIR_Nullary.getResult(inst)));
11415 }
11416
11417 /**
11418 * Emit the given instruction, assuming that
11419 * it is a MIR_UnaryAcc instruction
11420 * and has a NOT operator
11421 *
11422 * @param inst the instruction to assemble
11423 */
11424 private void doNOT(Instruction inst) {
11425 if (isByte(inst)) {
11426 if (isGPR_Reg(MIR_UnaryAcc.getResult(inst))) {
11427 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_UnaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
11428 emitNOT_Reg_Byte(
11429 getGPR_Reg(MIR_UnaryAcc.getResult(inst)));
11430
11431 } else {
11432 if (isAbs(MIR_UnaryAcc.getResult(inst))) {
11433 emitNOT_Abs_Byte(
11434 getDisp(MIR_UnaryAcc.getResult(inst)).toWord().toAddress());
11435
11436 } else {
11437 if (isRegDisp(MIR_UnaryAcc.getResult(inst))) {
11438 emitNOT_RegDisp_Byte(
11439 getBase(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
11440
11441 } else {
11442 if (isRegOff(MIR_UnaryAcc.getResult(inst))) {
11443 emitNOT_RegOff_Byte(
11444 getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
11445
11446 } else {
11447 if (isRegIdx(MIR_UnaryAcc.getResult(inst))) {
11448 emitNOT_RegIdx_Byte(
11449 getBase(MIR_UnaryAcc.getResult(inst)), getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
11450
11451 } else {
11452 if (VM.VerifyAssertions && !isRegInd(MIR_UnaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11453 emitNOT_RegInd_Byte(
11454 getBase(MIR_UnaryAcc.getResult(inst)));
11455 }
11456 }
11457 }
11458 }
11459 }
11460
11461 } else {
11462 if (isWord(inst)) {
11463 if (isGPR_Reg(MIR_UnaryAcc.getResult(inst))) {
11464 emitNOT_Reg_Word(
11465 getGPR_Reg(MIR_UnaryAcc.getResult(inst)));
11466
11467 } else {
11468 if (isAbs(MIR_UnaryAcc.getResult(inst))) {
11469 emitNOT_Abs_Word(
11470 getDisp(MIR_UnaryAcc.getResult(inst)).toWord().toAddress());
11471
11472 } else {
11473 if (isRegDisp(MIR_UnaryAcc.getResult(inst))) {
11474 emitNOT_RegDisp_Word(
11475 getBase(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
11476
11477 } else {
11478 if (isRegOff(MIR_UnaryAcc.getResult(inst))) {
11479 emitNOT_RegOff_Word(
11480 getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
11481
11482 } else {
11483 if (isRegIdx(MIR_UnaryAcc.getResult(inst))) {
11484 emitNOT_RegIdx_Word(
11485 getBase(MIR_UnaryAcc.getResult(inst)), getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
11486
11487 } else {
11488 if (VM.VerifyAssertions && !isRegInd(MIR_UnaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11489 emitNOT_RegInd_Word(
11490 getBase(MIR_UnaryAcc.getResult(inst)));
11491 }
11492 }
11493 }
11494 }
11495 }
11496
11497 } else {
11498 if (isQuad(inst)) {
11499 if (isGPR_Reg(MIR_UnaryAcc.getResult(inst))) {
11500 emitNOT_Reg_Quad(
11501 getGPR_Reg(MIR_UnaryAcc.getResult(inst)));
11502
11503 } else {
11504 if (isAbs(MIR_UnaryAcc.getResult(inst))) {
11505 emitNOT_Abs_Quad(
11506 getDisp(MIR_UnaryAcc.getResult(inst)).toWord().toAddress());
11507
11508 } else {
11509 if (isRegDisp(MIR_UnaryAcc.getResult(inst))) {
11510 emitNOT_RegDisp_Quad(
11511 getBase(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
11512
11513 } else {
11514 if (isRegOff(MIR_UnaryAcc.getResult(inst))) {
11515 emitNOT_RegOff_Quad(
11516 getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
11517
11518 } else {
11519 if (isRegIdx(MIR_UnaryAcc.getResult(inst))) {
11520 emitNOT_RegIdx_Quad(
11521 getBase(MIR_UnaryAcc.getResult(inst)), getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
11522
11523 } else {
11524 if (VM.VerifyAssertions && !isRegInd(MIR_UnaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11525 emitNOT_RegInd_Quad(
11526 getBase(MIR_UnaryAcc.getResult(inst)));
11527 }
11528 }
11529 }
11530 }
11531 }
11532
11533 } else {
11534 if (isGPR_Reg(MIR_UnaryAcc.getResult(inst))) {
11535 emitNOT_Reg(
11536 getGPR_Reg(MIR_UnaryAcc.getResult(inst)));
11537
11538 } else {
11539 if (isAbs(MIR_UnaryAcc.getResult(inst))) {
11540 emitNOT_Abs(
11541 getDisp(MIR_UnaryAcc.getResult(inst)).toWord().toAddress());
11542
11543 } else {
11544 if (isRegDisp(MIR_UnaryAcc.getResult(inst))) {
11545 emitNOT_RegDisp(
11546 getBase(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
11547
11548 } else {
11549 if (isRegOff(MIR_UnaryAcc.getResult(inst))) {
11550 emitNOT_RegOff(
11551 getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
11552
11553 } else {
11554 if (isRegIdx(MIR_UnaryAcc.getResult(inst))) {
11555 emitNOT_RegIdx(
11556 getBase(MIR_UnaryAcc.getResult(inst)), getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
11557
11558 } else {
11559 if (VM.VerifyAssertions && !isRegInd(MIR_UnaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11560 emitNOT_RegInd(
11561 getBase(MIR_UnaryAcc.getResult(inst)));
11562 }
11563 }
11564 }
11565 }
11566 }
11567 }
11568 }
11569 }
11570 }
11571
11572 /**
11573 * Emit the given instruction, assuming that
11574 * it is a MIR_BinaryAcc instruction
11575 * and has a ROR operator
11576 *
11577 * @param inst the instruction to assemble
11578 */
11579 private void doROR(Instruction inst) {
11580 if (isImm(MIR_BinaryAcc.getValue(inst))) {
11581 if (isByte(inst)) {
11582 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
11583 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
11584 emitROR_Reg_Imm_Byte(
11585 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
11586 getImm(MIR_BinaryAcc.getValue(inst)));
11587
11588 } else {
11589 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
11590 emitROR_Abs_Imm_Byte(
11591 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
11592 getImm(MIR_BinaryAcc.getValue(inst)));
11593
11594 } else {
11595 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
11596 emitROR_RegDisp_Imm_Byte(
11597 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11598 getImm(MIR_BinaryAcc.getValue(inst)));
11599
11600 } else {
11601 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
11602 emitROR_RegOff_Imm_Byte(
11603 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11604 getImm(MIR_BinaryAcc.getValue(inst)));
11605
11606 } else {
11607 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
11608 emitROR_RegIdx_Imm_Byte(
11609 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11610 getImm(MIR_BinaryAcc.getValue(inst)));
11611
11612 } else {
11613 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11614 emitROR_RegInd_Imm_Byte(
11615 getBase(MIR_BinaryAcc.getResult(inst)),
11616 getImm(MIR_BinaryAcc.getValue(inst)));
11617 }
11618 }
11619 }
11620 }
11621 }
11622
11623 } else {
11624 if (isWord(inst)) {
11625 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
11626 emitROR_Reg_Imm_Word(
11627 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
11628 getImm(MIR_BinaryAcc.getValue(inst)));
11629
11630 } else {
11631 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
11632 emitROR_Abs_Imm_Word(
11633 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
11634 getImm(MIR_BinaryAcc.getValue(inst)));
11635
11636 } else {
11637 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
11638 emitROR_RegDisp_Imm_Word(
11639 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11640 getImm(MIR_BinaryAcc.getValue(inst)));
11641
11642 } else {
11643 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
11644 emitROR_RegOff_Imm_Word(
11645 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11646 getImm(MIR_BinaryAcc.getValue(inst)));
11647
11648 } else {
11649 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
11650 emitROR_RegIdx_Imm_Word(
11651 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11652 getImm(MIR_BinaryAcc.getValue(inst)));
11653
11654 } else {
11655 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11656 emitROR_RegInd_Imm_Word(
11657 getBase(MIR_BinaryAcc.getResult(inst)),
11658 getImm(MIR_BinaryAcc.getValue(inst)));
11659 }
11660 }
11661 }
11662 }
11663 }
11664
11665 } else {
11666 if (isQuad(inst)) {
11667 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
11668 emitROR_Reg_Imm_Quad(
11669 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
11670 getImm(MIR_BinaryAcc.getValue(inst)));
11671
11672 } else {
11673 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
11674 emitROR_Abs_Imm_Quad(
11675 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
11676 getImm(MIR_BinaryAcc.getValue(inst)));
11677
11678 } else {
11679 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
11680 emitROR_RegDisp_Imm_Quad(
11681 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11682 getImm(MIR_BinaryAcc.getValue(inst)));
11683
11684 } else {
11685 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
11686 emitROR_RegOff_Imm_Quad(
11687 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11688 getImm(MIR_BinaryAcc.getValue(inst)));
11689
11690 } else {
11691 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
11692 emitROR_RegIdx_Imm_Quad(
11693 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11694 getImm(MIR_BinaryAcc.getValue(inst)));
11695
11696 } else {
11697 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11698 emitROR_RegInd_Imm_Quad(
11699 getBase(MIR_BinaryAcc.getResult(inst)),
11700 getImm(MIR_BinaryAcc.getValue(inst)));
11701 }
11702 }
11703 }
11704 }
11705 }
11706
11707 } else {
11708 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
11709 emitROR_Reg_Imm(
11710 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
11711 getImm(MIR_BinaryAcc.getValue(inst)));
11712
11713 } else {
11714 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
11715 emitROR_Abs_Imm(
11716 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
11717 getImm(MIR_BinaryAcc.getValue(inst)));
11718
11719 } else {
11720 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
11721 emitROR_RegDisp_Imm(
11722 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11723 getImm(MIR_BinaryAcc.getValue(inst)));
11724
11725 } else {
11726 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
11727 emitROR_RegOff_Imm(
11728 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11729 getImm(MIR_BinaryAcc.getValue(inst)));
11730
11731 } else {
11732 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
11733 emitROR_RegIdx_Imm(
11734 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11735 getImm(MIR_BinaryAcc.getValue(inst)));
11736
11737 } else {
11738 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11739 emitROR_RegInd_Imm(
11740 getBase(MIR_BinaryAcc.getResult(inst)),
11741 getImm(MIR_BinaryAcc.getValue(inst)));
11742 }
11743 }
11744 }
11745 }
11746 }
11747 }
11748 }
11749 }
11750
11751 } else {
11752 if (isByte(inst)) {
11753 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
11754 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11755 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
11756 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
11757 emitROR_Reg_Reg_Byte(
11758 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
11759 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11760
11761 } else {
11762 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
11763 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11764 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
11765 emitROR_Abs_Reg_Byte(
11766 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
11767 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11768
11769 } else {
11770 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
11771 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11772 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
11773 emitROR_RegDisp_Reg_Byte(
11774 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11775 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11776
11777 } else {
11778 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
11779 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11780 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
11781 emitROR_RegOff_Reg_Byte(
11782 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11783 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11784
11785 } else {
11786 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
11787 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11788 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
11789 emitROR_RegIdx_Reg_Byte(
11790 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11791 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11792
11793 } else {
11794 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11795 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11796 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
11797 emitROR_RegInd_Reg_Byte(
11798 getBase(MIR_BinaryAcc.getResult(inst)),
11799 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11800 }
11801 }
11802 }
11803 }
11804 }
11805
11806 } else {
11807 if (isWord(inst)) {
11808 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
11809 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11810 emitROR_Reg_Reg_Word(
11811 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
11812 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11813
11814 } else {
11815 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
11816 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11817 emitROR_Abs_Reg_Word(
11818 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
11819 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11820
11821 } else {
11822 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
11823 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11824 emitROR_RegDisp_Reg_Word(
11825 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11826 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11827
11828 } else {
11829 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
11830 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11831 emitROR_RegOff_Reg_Word(
11832 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11833 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11834
11835 } else {
11836 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
11837 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11838 emitROR_RegIdx_Reg_Word(
11839 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11840 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11841
11842 } else {
11843 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11844 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11845 emitROR_RegInd_Reg_Word(
11846 getBase(MIR_BinaryAcc.getResult(inst)),
11847 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11848 }
11849 }
11850 }
11851 }
11852 }
11853
11854 } else {
11855 if (isQuad(inst)) {
11856 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
11857 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11858 emitROR_Reg_Reg_Quad(
11859 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
11860 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11861
11862 } else {
11863 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
11864 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11865 emitROR_Abs_Reg_Quad(
11866 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
11867 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11868
11869 } else {
11870 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
11871 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11872 emitROR_RegDisp_Reg_Quad(
11873 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11874 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11875
11876 } else {
11877 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
11878 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11879 emitROR_RegOff_Reg_Quad(
11880 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11881 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11882
11883 } else {
11884 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
11885 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11886 emitROR_RegIdx_Reg_Quad(
11887 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11888 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11889
11890 } else {
11891 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11892 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11893 emitROR_RegInd_Reg_Quad(
11894 getBase(MIR_BinaryAcc.getResult(inst)),
11895 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11896 }
11897 }
11898 }
11899 }
11900 }
11901
11902 } else {
11903 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
11904 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11905 emitROR_Reg_Reg(
11906 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
11907 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11908
11909 } else {
11910 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
11911 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11912 emitROR_Abs_Reg(
11913 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
11914 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11915
11916 } else {
11917 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
11918 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11919 emitROR_RegDisp_Reg(
11920 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11921 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11922
11923 } else {
11924 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
11925 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11926 emitROR_RegOff_Reg(
11927 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11928 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11929
11930 } else {
11931 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
11932 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11933 emitROR_RegIdx_Reg(
11934 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
11935 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11936
11937 } else {
11938 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11939 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11940 emitROR_RegInd_Reg(
11941 getBase(MIR_BinaryAcc.getResult(inst)),
11942 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11943 }
11944 }
11945 }
11946 }
11947 }
11948 }
11949 }
11950 }
11951 }
11952 }
11953
11954 /**
11955 * Emit the given instruction, assuming that
11956 * it is a MIR_Nullary instruction
11957 * and has a FLDPI operator
11958 *
11959 * @param inst the instruction to assemble
11960 */
11961 private void doFLDPI(Instruction inst) {
11962 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Nullary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
11963 emitFLDPI_Reg(
11964 getFPR_Reg(MIR_Nullary.getResult(inst)));
11965 }
11966
11967 /**
11968 * Emit the given instruction, assuming that
11969 * it is a MIR_BinaryAcc instruction
11970 * and has a AND operator
11971 *
11972 * @param inst the instruction to assemble
11973 */
11974 private void doAND(Instruction inst) {
11975 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
11976 if (isByte(inst)) {
11977 if (isImm(MIR_BinaryAcc.getValue(inst))) {
11978 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
11979 emitAND_Reg_Imm_Byte(
11980 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
11981 getImm(MIR_BinaryAcc.getValue(inst)));
11982
11983 } else {
11984 if (isGPR_Reg(MIR_BinaryAcc.getValue(inst))) {
11985 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
11986 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
11987 emitAND_Reg_Reg_Byte(
11988 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
11989 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
11990
11991 } else {
11992 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
11993 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
11994 emitAND_Reg_Abs_Byte(
11995 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
11996 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
11997
11998 } else {
11999 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
12000 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
12001 emitAND_Reg_RegDisp_Byte(
12002 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
12003 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
12004
12005 } else {
12006 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
12007 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
12008 emitAND_Reg_RegOff_Byte(
12009 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
12010 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
12011
12012 } else {
12013 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
12014 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
12015 emitAND_Reg_RegIdx_Byte(
12016 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
12017 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
12018
12019 } else {
12020 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12021 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
12022 emitAND_Reg_RegInd_Byte(
12023 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
12024 getBase(MIR_BinaryAcc.getValue(inst)));
12025 }
12026 }
12027 }
12028 }
12029 }
12030 }
12031
12032 } else {
12033 if (isWord(inst)) {
12034 if (isImm(MIR_BinaryAcc.getValue(inst))) {
12035 emitAND_Reg_Imm_Word(
12036 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
12037 getImm(MIR_BinaryAcc.getValue(inst)));
12038
12039 } else {
12040 if (isGPR_Reg(MIR_BinaryAcc.getValue(inst))) {
12041 emitAND_Reg_Reg_Word(
12042 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
12043 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
12044
12045 } else {
12046 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
12047 emitAND_Reg_Abs_Word(
12048 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
12049 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
12050
12051 } else {
12052 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
12053 emitAND_Reg_RegDisp_Word(
12054 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
12055 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
12056
12057 } else {
12058 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
12059 emitAND_Reg_RegOff_Word(
12060 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
12061 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
12062
12063 } else {
12064 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
12065 emitAND_Reg_RegIdx_Word(
12066 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
12067 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
12068
12069 } else {
12070 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12071 emitAND_Reg_RegInd_Word(
12072 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
12073 getBase(MIR_BinaryAcc.getValue(inst)));
12074 }
12075 }
12076 }
12077 }
12078 }
12079 }
12080
12081 } else {
12082 if (isQuad(inst)) {
12083 if (isImm(MIR_BinaryAcc.getValue(inst))) {
12084 emitAND_Reg_Imm_Quad(
12085 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
12086 getImm(MIR_BinaryAcc.getValue(inst)));
12087
12088 } else {
12089 if (isGPR_Reg(MIR_BinaryAcc.getValue(inst))) {
12090 emitAND_Reg_Reg_Quad(
12091 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
12092 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
12093
12094 } else {
12095 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
12096 emitAND_Reg_Abs_Quad(
12097 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
12098 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
12099
12100 } else {
12101 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
12102 emitAND_Reg_RegDisp_Quad(
12103 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
12104 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
12105
12106 } else {
12107 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
12108 emitAND_Reg_RegOff_Quad(
12109 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
12110 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
12111
12112 } else {
12113 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
12114 emitAND_Reg_RegIdx_Quad(
12115 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
12116 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
12117
12118 } else {
12119 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12120 emitAND_Reg_RegInd_Quad(
12121 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
12122 getBase(MIR_BinaryAcc.getValue(inst)));
12123 }
12124 }
12125 }
12126 }
12127 }
12128 }
12129
12130 } else {
12131 if (isImm(MIR_BinaryAcc.getValue(inst))) {
12132 emitAND_Reg_Imm(
12133 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
12134 getImm(MIR_BinaryAcc.getValue(inst)));
12135
12136 } else {
12137 if (isGPR_Reg(MIR_BinaryAcc.getValue(inst))) {
12138 emitAND_Reg_Reg(
12139 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
12140 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
12141
12142 } else {
12143 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
12144 emitAND_Reg_Abs(
12145 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
12146 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
12147
12148 } else {
12149 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
12150 emitAND_Reg_RegDisp(
12151 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
12152 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
12153
12154 } else {
12155 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
12156 emitAND_Reg_RegOff(
12157 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
12158 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
12159
12160 } else {
12161 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
12162 emitAND_Reg_RegIdx(
12163 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
12164 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
12165
12166 } else {
12167 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12168 emitAND_Reg_RegInd(
12169 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
12170 getBase(MIR_BinaryAcc.getValue(inst)));
12171 }
12172 }
12173 }
12174 }
12175 }
12176 }
12177 }
12178 }
12179 }
12180
12181 } else {
12182 if (isImm(MIR_BinaryAcc.getValue(inst))) {
12183 if (isByte(inst)) {
12184 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
12185 emitAND_Abs_Imm_Byte(
12186 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
12187 getImm(MIR_BinaryAcc.getValue(inst)));
12188
12189 } else {
12190 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
12191 emitAND_RegDisp_Imm_Byte(
12192 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12193 getImm(MIR_BinaryAcc.getValue(inst)));
12194
12195 } else {
12196 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
12197 emitAND_RegOff_Imm_Byte(
12198 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12199 getImm(MIR_BinaryAcc.getValue(inst)));
12200
12201 } else {
12202 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
12203 emitAND_RegIdx_Imm_Byte(
12204 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12205 getImm(MIR_BinaryAcc.getValue(inst)));
12206
12207 } else {
12208 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12209 emitAND_RegInd_Imm_Byte(
12210 getBase(MIR_BinaryAcc.getResult(inst)),
12211 getImm(MIR_BinaryAcc.getValue(inst)));
12212 }
12213 }
12214 }
12215 }
12216
12217 } else {
12218 if (isWord(inst)) {
12219 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
12220 emitAND_Abs_Imm_Word(
12221 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
12222 getImm(MIR_BinaryAcc.getValue(inst)));
12223
12224 } else {
12225 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
12226 emitAND_RegDisp_Imm_Word(
12227 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12228 getImm(MIR_BinaryAcc.getValue(inst)));
12229
12230 } else {
12231 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
12232 emitAND_RegOff_Imm_Word(
12233 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12234 getImm(MIR_BinaryAcc.getValue(inst)));
12235
12236 } else {
12237 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
12238 emitAND_RegIdx_Imm_Word(
12239 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12240 getImm(MIR_BinaryAcc.getValue(inst)));
12241
12242 } else {
12243 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12244 emitAND_RegInd_Imm_Word(
12245 getBase(MIR_BinaryAcc.getResult(inst)),
12246 getImm(MIR_BinaryAcc.getValue(inst)));
12247 }
12248 }
12249 }
12250 }
12251
12252 } else {
12253 if (isQuad(inst)) {
12254 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
12255 emitAND_Abs_Imm_Quad(
12256 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
12257 getImm(MIR_BinaryAcc.getValue(inst)));
12258
12259 } else {
12260 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
12261 emitAND_RegDisp_Imm_Quad(
12262 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12263 getImm(MIR_BinaryAcc.getValue(inst)));
12264
12265 } else {
12266 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
12267 emitAND_RegOff_Imm_Quad(
12268 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12269 getImm(MIR_BinaryAcc.getValue(inst)));
12270
12271 } else {
12272 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
12273 emitAND_RegIdx_Imm_Quad(
12274 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12275 getImm(MIR_BinaryAcc.getValue(inst)));
12276
12277 } else {
12278 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12279 emitAND_RegInd_Imm_Quad(
12280 getBase(MIR_BinaryAcc.getResult(inst)),
12281 getImm(MIR_BinaryAcc.getValue(inst)));
12282 }
12283 }
12284 }
12285 }
12286
12287 } else {
12288 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
12289 emitAND_Abs_Imm(
12290 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
12291 getImm(MIR_BinaryAcc.getValue(inst)));
12292
12293 } else {
12294 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
12295 emitAND_RegDisp_Imm(
12296 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12297 getImm(MIR_BinaryAcc.getValue(inst)));
12298
12299 } else {
12300 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
12301 emitAND_RegOff_Imm(
12302 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12303 getImm(MIR_BinaryAcc.getValue(inst)));
12304
12305 } else {
12306 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
12307 emitAND_RegIdx_Imm(
12308 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12309 getImm(MIR_BinaryAcc.getValue(inst)));
12310
12311 } else {
12312 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12313 emitAND_RegInd_Imm(
12314 getBase(MIR_BinaryAcc.getResult(inst)),
12315 getImm(MIR_BinaryAcc.getValue(inst)));
12316 }
12317 }
12318 }
12319 }
12320 }
12321 }
12322 }
12323
12324 } else {
12325 if (isByte(inst)) {
12326 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
12327 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12328 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
12329 emitAND_Abs_Reg_Byte(
12330 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
12331 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
12332
12333 } else {
12334 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
12335 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12336 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
12337 emitAND_RegDisp_Reg_Byte(
12338 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12339 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
12340
12341 } else {
12342 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
12343 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12344 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
12345 emitAND_RegOff_Reg_Byte(
12346 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12347 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
12348
12349 } else {
12350 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
12351 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12352 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
12353 emitAND_RegIdx_Reg_Byte(
12354 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12355 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
12356
12357 } else {
12358 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12359 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12360 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
12361 emitAND_RegInd_Reg_Byte(
12362 getBase(MIR_BinaryAcc.getResult(inst)),
12363 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
12364 }
12365 }
12366 }
12367 }
12368
12369 } else {
12370 if (isWord(inst)) {
12371 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
12372 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12373 emitAND_Abs_Reg_Word(
12374 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
12375 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
12376
12377 } else {
12378 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
12379 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12380 emitAND_RegDisp_Reg_Word(
12381 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12382 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
12383
12384 } else {
12385 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
12386 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12387 emitAND_RegOff_Reg_Word(
12388 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12389 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
12390
12391 } else {
12392 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
12393 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12394 emitAND_RegIdx_Reg_Word(
12395 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12396 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
12397
12398 } else {
12399 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12400 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12401 emitAND_RegInd_Reg_Word(
12402 getBase(MIR_BinaryAcc.getResult(inst)),
12403 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
12404 }
12405 }
12406 }
12407 }
12408
12409 } else {
12410 if (isQuad(inst)) {
12411 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
12412 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12413 emitAND_Abs_Reg_Quad(
12414 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
12415 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
12416
12417 } else {
12418 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
12419 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12420 emitAND_RegDisp_Reg_Quad(
12421 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12422 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
12423
12424 } else {
12425 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
12426 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12427 emitAND_RegOff_Reg_Quad(
12428 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12429 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
12430
12431 } else {
12432 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
12433 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12434 emitAND_RegIdx_Reg_Quad(
12435 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12436 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
12437
12438 } else {
12439 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12440 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12441 emitAND_RegInd_Reg_Quad(
12442 getBase(MIR_BinaryAcc.getResult(inst)),
12443 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
12444 }
12445 }
12446 }
12447 }
12448
12449 } else {
12450 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
12451 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12452 emitAND_Abs_Reg(
12453 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
12454 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
12455
12456 } else {
12457 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
12458 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12459 emitAND_RegDisp_Reg(
12460 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12461 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
12462
12463 } else {
12464 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
12465 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12466 emitAND_RegOff_Reg(
12467 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12468 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
12469
12470 } else {
12471 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
12472 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12473 emitAND_RegIdx_Reg(
12474 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12475 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
12476
12477 } else {
12478 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12479 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12480 emitAND_RegInd_Reg(
12481 getBase(MIR_BinaryAcc.getResult(inst)),
12482 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
12483 }
12484 }
12485 }
12486 }
12487 }
12488 }
12489 }
12490 }
12491 }
12492 }
12493
12494 /**
12495 * Emit the given instruction, assuming that
12496 * it is a MIR_XChng instruction
12497 * and has a FXCH operator
12498 *
12499 * @param inst the instruction to assemble
12500 */
12501 private void doFXCH(Instruction inst) {
12502 if (VM.VerifyAssertions && !isFPR_Reg(MIR_XChng.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12503 if (VM.VerifyAssertions && !isFPR_Reg(MIR_XChng.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12504 emitFXCH_Reg_Reg(
12505 getFPR_Reg(MIR_XChng.getVal1(inst)),
12506 getFPR_Reg(MIR_XChng.getVal2(inst)));
12507 }
12508
12509 /**
12510 * Emit the given instruction, assuming that
12511 * it is a MIR_BinaryAcc instruction
12512 * and has a ANDNPS operator
12513 *
12514 * @param inst the instruction to assemble
12515 */
12516 private void doANDNPS(Instruction inst) {
12517 if (isXMM_Reg(MIR_BinaryAcc.getValue(inst))) {
12518 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12519 emitANDNPS_Reg_Reg(
12520 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
12521 getXMM_Reg(MIR_BinaryAcc.getValue(inst)));
12522
12523 } else {
12524 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
12525 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12526 emitANDNPS_Reg_Abs(
12527 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
12528 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
12529
12530 } else {
12531 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
12532 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12533 emitANDNPS_Reg_RegDisp(
12534 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
12535 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
12536
12537 } else {
12538 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
12539 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12540 emitANDNPS_Reg_RegOff(
12541 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
12542 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
12543
12544 } else {
12545 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
12546 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12547 emitANDNPS_Reg_RegIdx(
12548 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
12549 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
12550
12551 } else {
12552 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12553 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12554 emitANDNPS_Reg_RegInd(
12555 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
12556 getBase(MIR_BinaryAcc.getValue(inst)));
12557 }
12558 }
12559 }
12560 }
12561 }
12562 }
12563
12564 /**
12565 * Emit the given instruction, assuming that
12566 * it is a MIR_UnaryAcc instruction
12567 * and has a INC operator
12568 *
12569 * @param inst the instruction to assemble
12570 */
12571 private void doINC(Instruction inst) {
12572 if (isByte(inst)) {
12573 if (isGPR_Reg(MIR_UnaryAcc.getResult(inst))) {
12574 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_UnaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
12575 emitINC_Reg_Byte(
12576 getGPR_Reg(MIR_UnaryAcc.getResult(inst)));
12577
12578 } else {
12579 if (isAbs(MIR_UnaryAcc.getResult(inst))) {
12580 emitINC_Abs_Byte(
12581 getDisp(MIR_UnaryAcc.getResult(inst)).toWord().toAddress());
12582
12583 } else {
12584 if (isRegDisp(MIR_UnaryAcc.getResult(inst))) {
12585 emitINC_RegDisp_Byte(
12586 getBase(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
12587
12588 } else {
12589 if (isRegOff(MIR_UnaryAcc.getResult(inst))) {
12590 emitINC_RegOff_Byte(
12591 getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
12592
12593 } else {
12594 if (isRegIdx(MIR_UnaryAcc.getResult(inst))) {
12595 emitINC_RegIdx_Byte(
12596 getBase(MIR_UnaryAcc.getResult(inst)), getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
12597
12598 } else {
12599 if (VM.VerifyAssertions && !isRegInd(MIR_UnaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12600 emitINC_RegInd_Byte(
12601 getBase(MIR_UnaryAcc.getResult(inst)));
12602 }
12603 }
12604 }
12605 }
12606 }
12607
12608 } else {
12609 if (isWord(inst)) {
12610 if (isGPR_Reg(MIR_UnaryAcc.getResult(inst))) {
12611 emitINC_Reg_Word(
12612 getGPR_Reg(MIR_UnaryAcc.getResult(inst)));
12613
12614 } else {
12615 if (isAbs(MIR_UnaryAcc.getResult(inst))) {
12616 emitINC_Abs_Word(
12617 getDisp(MIR_UnaryAcc.getResult(inst)).toWord().toAddress());
12618
12619 } else {
12620 if (isRegDisp(MIR_UnaryAcc.getResult(inst))) {
12621 emitINC_RegDisp_Word(
12622 getBase(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
12623
12624 } else {
12625 if (isRegOff(MIR_UnaryAcc.getResult(inst))) {
12626 emitINC_RegOff_Word(
12627 getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
12628
12629 } else {
12630 if (isRegIdx(MIR_UnaryAcc.getResult(inst))) {
12631 emitINC_RegIdx_Word(
12632 getBase(MIR_UnaryAcc.getResult(inst)), getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
12633
12634 } else {
12635 if (VM.VerifyAssertions && !isRegInd(MIR_UnaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12636 emitINC_RegInd_Word(
12637 getBase(MIR_UnaryAcc.getResult(inst)));
12638 }
12639 }
12640 }
12641 }
12642 }
12643
12644 } else {
12645 if (isQuad(inst)) {
12646 if (isGPR_Reg(MIR_UnaryAcc.getResult(inst))) {
12647 emitINC_Reg_Quad(
12648 getGPR_Reg(MIR_UnaryAcc.getResult(inst)));
12649
12650 } else {
12651 if (isAbs(MIR_UnaryAcc.getResult(inst))) {
12652 emitINC_Abs_Quad(
12653 getDisp(MIR_UnaryAcc.getResult(inst)).toWord().toAddress());
12654
12655 } else {
12656 if (isRegDisp(MIR_UnaryAcc.getResult(inst))) {
12657 emitINC_RegDisp_Quad(
12658 getBase(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
12659
12660 } else {
12661 if (isRegOff(MIR_UnaryAcc.getResult(inst))) {
12662 emitINC_RegOff_Quad(
12663 getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
12664
12665 } else {
12666 if (isRegIdx(MIR_UnaryAcc.getResult(inst))) {
12667 emitINC_RegIdx_Quad(
12668 getBase(MIR_UnaryAcc.getResult(inst)), getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
12669
12670 } else {
12671 if (VM.VerifyAssertions && !isRegInd(MIR_UnaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12672 emitINC_RegInd_Quad(
12673 getBase(MIR_UnaryAcc.getResult(inst)));
12674 }
12675 }
12676 }
12677 }
12678 }
12679
12680 } else {
12681 if (isGPR_Reg(MIR_UnaryAcc.getResult(inst))) {
12682 emitINC_Reg(
12683 getGPR_Reg(MIR_UnaryAcc.getResult(inst)));
12684
12685 } else {
12686 if (isAbs(MIR_UnaryAcc.getResult(inst))) {
12687 emitINC_Abs(
12688 getDisp(MIR_UnaryAcc.getResult(inst)).toWord().toAddress());
12689
12690 } else {
12691 if (isRegDisp(MIR_UnaryAcc.getResult(inst))) {
12692 emitINC_RegDisp(
12693 getBase(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
12694
12695 } else {
12696 if (isRegOff(MIR_UnaryAcc.getResult(inst))) {
12697 emitINC_RegOff(
12698 getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
12699
12700 } else {
12701 if (isRegIdx(MIR_UnaryAcc.getResult(inst))) {
12702 emitINC_RegIdx(
12703 getBase(MIR_UnaryAcc.getResult(inst)), getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
12704
12705 } else {
12706 if (VM.VerifyAssertions && !isRegInd(MIR_UnaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12707 emitINC_RegInd(
12708 getBase(MIR_UnaryAcc.getResult(inst)));
12709 }
12710 }
12711 }
12712 }
12713 }
12714 }
12715 }
12716 }
12717 }
12718
12719 /**
12720 * Emit the given instruction, assuming that
12721 * it is a MIR_BinaryAcc instruction
12722 * and has a SAL operator
12723 *
12724 * @param inst the instruction to assemble
12725 */
12726 private void doSAL(Instruction inst) {
12727 if (isImm(MIR_BinaryAcc.getValue(inst))) {
12728 if (isByte(inst)) {
12729 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
12730 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
12731 emitSAL_Reg_Imm_Byte(
12732 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
12733 getImm(MIR_BinaryAcc.getValue(inst)));
12734
12735 } else {
12736 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
12737 emitSAL_Abs_Imm_Byte(
12738 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
12739 getImm(MIR_BinaryAcc.getValue(inst)));
12740
12741 } else {
12742 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
12743 emitSAL_RegDisp_Imm_Byte(
12744 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12745 getImm(MIR_BinaryAcc.getValue(inst)));
12746
12747 } else {
12748 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
12749 emitSAL_RegOff_Imm_Byte(
12750 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12751 getImm(MIR_BinaryAcc.getValue(inst)));
12752
12753 } else {
12754 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
12755 emitSAL_RegIdx_Imm_Byte(
12756 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12757 getImm(MIR_BinaryAcc.getValue(inst)));
12758
12759 } else {
12760 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12761 emitSAL_RegInd_Imm_Byte(
12762 getBase(MIR_BinaryAcc.getResult(inst)),
12763 getImm(MIR_BinaryAcc.getValue(inst)));
12764 }
12765 }
12766 }
12767 }
12768 }
12769
12770 } else {
12771 if (isWord(inst)) {
12772 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
12773 emitSAL_Reg_Imm_Word(
12774 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
12775 getImm(MIR_BinaryAcc.getValue(inst)));
12776
12777 } else {
12778 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
12779 emitSAL_Abs_Imm_Word(
12780 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
12781 getImm(MIR_BinaryAcc.getValue(inst)));
12782
12783 } else {
12784 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
12785 emitSAL_RegDisp_Imm_Word(
12786 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12787 getImm(MIR_BinaryAcc.getValue(inst)));
12788
12789 } else {
12790 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
12791 emitSAL_RegOff_Imm_Word(
12792 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12793 getImm(MIR_BinaryAcc.getValue(inst)));
12794
12795 } else {
12796 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
12797 emitSAL_RegIdx_Imm_Word(
12798 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12799 getImm(MIR_BinaryAcc.getValue(inst)));
12800
12801 } else {
12802 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12803 emitSAL_RegInd_Imm_Word(
12804 getBase(MIR_BinaryAcc.getResult(inst)),
12805 getImm(MIR_BinaryAcc.getValue(inst)));
12806 }
12807 }
12808 }
12809 }
12810 }
12811
12812 } else {
12813 if (isQuad(inst)) {
12814 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
12815 emitSAL_Reg_Imm_Quad(
12816 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
12817 getImm(MIR_BinaryAcc.getValue(inst)));
12818
12819 } else {
12820 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
12821 emitSAL_Abs_Imm_Quad(
12822 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
12823 getImm(MIR_BinaryAcc.getValue(inst)));
12824
12825 } else {
12826 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
12827 emitSAL_RegDisp_Imm_Quad(
12828 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12829 getImm(MIR_BinaryAcc.getValue(inst)));
12830
12831 } else {
12832 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
12833 emitSAL_RegOff_Imm_Quad(
12834 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12835 getImm(MIR_BinaryAcc.getValue(inst)));
12836
12837 } else {
12838 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
12839 emitSAL_RegIdx_Imm_Quad(
12840 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12841 getImm(MIR_BinaryAcc.getValue(inst)));
12842
12843 } else {
12844 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12845 emitSAL_RegInd_Imm_Quad(
12846 getBase(MIR_BinaryAcc.getResult(inst)),
12847 getImm(MIR_BinaryAcc.getValue(inst)));
12848 }
12849 }
12850 }
12851 }
12852 }
12853
12854 } else {
12855 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
12856 emitSAL_Reg_Imm(
12857 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
12858 getImm(MIR_BinaryAcc.getValue(inst)));
12859
12860 } else {
12861 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
12862 emitSAL_Abs_Imm(
12863 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
12864 getImm(MIR_BinaryAcc.getValue(inst)));
12865
12866 } else {
12867 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
12868 emitSAL_RegDisp_Imm(
12869 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12870 getImm(MIR_BinaryAcc.getValue(inst)));
12871
12872 } else {
12873 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
12874 emitSAL_RegOff_Imm(
12875 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12876 getImm(MIR_BinaryAcc.getValue(inst)));
12877
12878 } else {
12879 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
12880 emitSAL_RegIdx_Imm(
12881 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12882 getImm(MIR_BinaryAcc.getValue(inst)));
12883
12884 } else {
12885 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12886 emitSAL_RegInd_Imm(
12887 getBase(MIR_BinaryAcc.getResult(inst)),
12888 getImm(MIR_BinaryAcc.getValue(inst)));
12889 }
12890 }
12891 }
12892 }
12893 }
12894 }
12895 }
12896 }
12897
12898 } else {
12899 if (isByte(inst)) {
12900 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
12901 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12902 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
12903 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
12904 emitSAL_Reg_Reg_Byte(
12905 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
12906 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
12907
12908 } else {
12909 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
12910 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12911 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
12912 emitSAL_Abs_Reg_Byte(
12913 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
12914 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
12915
12916 } else {
12917 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
12918 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12919 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
12920 emitSAL_RegDisp_Reg_Byte(
12921 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12922 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
12923
12924 } else {
12925 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
12926 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12927 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
12928 emitSAL_RegOff_Reg_Byte(
12929 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12930 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
12931
12932 } else {
12933 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
12934 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12935 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
12936 emitSAL_RegIdx_Reg_Byte(
12937 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12938 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
12939
12940 } else {
12941 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12942 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12943 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
12944 emitSAL_RegInd_Reg_Byte(
12945 getBase(MIR_BinaryAcc.getResult(inst)),
12946 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
12947 }
12948 }
12949 }
12950 }
12951 }
12952
12953 } else {
12954 if (isWord(inst)) {
12955 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
12956 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12957 emitSAL_Reg_Reg_Word(
12958 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
12959 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
12960
12961 } else {
12962 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
12963 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12964 emitSAL_Abs_Reg_Word(
12965 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
12966 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
12967
12968 } else {
12969 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
12970 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12971 emitSAL_RegDisp_Reg_Word(
12972 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12973 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
12974
12975 } else {
12976 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
12977 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12978 emitSAL_RegOff_Reg_Word(
12979 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12980 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
12981
12982 } else {
12983 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
12984 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12985 emitSAL_RegIdx_Reg_Word(
12986 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
12987 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
12988
12989 } else {
12990 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12991 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
12992 emitSAL_RegInd_Reg_Word(
12993 getBase(MIR_BinaryAcc.getResult(inst)),
12994 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
12995 }
12996 }
12997 }
12998 }
12999 }
13000
13001 } else {
13002 if (isQuad(inst)) {
13003 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
13004 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13005 emitSAL_Reg_Reg_Quad(
13006 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
13007 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
13008
13009 } else {
13010 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
13011 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13012 emitSAL_Abs_Reg_Quad(
13013 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
13014 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
13015
13016 } else {
13017 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
13018 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13019 emitSAL_RegDisp_Reg_Quad(
13020 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
13021 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
13022
13023 } else {
13024 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
13025 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13026 emitSAL_RegOff_Reg_Quad(
13027 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
13028 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
13029
13030 } else {
13031 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
13032 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13033 emitSAL_RegIdx_Reg_Quad(
13034 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
13035 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
13036
13037 } else {
13038 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13039 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13040 emitSAL_RegInd_Reg_Quad(
13041 getBase(MIR_BinaryAcc.getResult(inst)),
13042 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
13043 }
13044 }
13045 }
13046 }
13047 }
13048
13049 } else {
13050 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
13051 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13052 emitSAL_Reg_Reg(
13053 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
13054 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
13055
13056 } else {
13057 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
13058 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13059 emitSAL_Abs_Reg(
13060 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
13061 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
13062
13063 } else {
13064 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
13065 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13066 emitSAL_RegDisp_Reg(
13067 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
13068 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
13069
13070 } else {
13071 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
13072 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13073 emitSAL_RegOff_Reg(
13074 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
13075 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
13076
13077 } else {
13078 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
13079 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13080 emitSAL_RegIdx_Reg(
13081 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
13082 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
13083
13084 } else {
13085 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13086 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13087 emitSAL_RegInd_Reg(
13088 getBase(MIR_BinaryAcc.getResult(inst)),
13089 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
13090 }
13091 }
13092 }
13093 }
13094 }
13095 }
13096 }
13097 }
13098 }
13099 }
13100
13101 /**
13102 * Emit the given instruction, assuming that
13103 * it is a MIR_BinaryAcc instruction
13104 * and has a CMPLESS operator
13105 *
13106 * @param inst the instruction to assemble
13107 */
13108 private void doCMPLESS(Instruction inst) {
13109 if (isXMM_Reg(MIR_BinaryAcc.getValue(inst))) {
13110 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13111 emitCMPLESS_Reg_Reg(
13112 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
13113 getXMM_Reg(MIR_BinaryAcc.getValue(inst)));
13114
13115 } else {
13116 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
13117 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13118 emitCMPLESS_Reg_Abs(
13119 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
13120 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
13121
13122 } else {
13123 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
13124 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13125 emitCMPLESS_Reg_RegDisp(
13126 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
13127 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
13128
13129 } else {
13130 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
13131 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13132 emitCMPLESS_Reg_RegOff(
13133 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
13134 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
13135
13136 } else {
13137 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
13138 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13139 emitCMPLESS_Reg_RegIdx(
13140 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
13141 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
13142
13143 } else {
13144 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13145 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13146 emitCMPLESS_Reg_RegInd(
13147 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
13148 getBase(MIR_BinaryAcc.getValue(inst)));
13149 }
13150 }
13151 }
13152 }
13153 }
13154 }
13155
13156 /**
13157 * Emit the given instruction, assuming that
13158 * it is a MIR_BinaryAcc instruction
13159 * and has a CMPNLTSD operator
13160 *
13161 * @param inst the instruction to assemble
13162 */
13163 private void doCMPNLTSD(Instruction inst) {
13164 if (isXMM_Reg(MIR_BinaryAcc.getValue(inst))) {
13165 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13166 emitCMPNLTSD_Reg_Reg(
13167 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
13168 getXMM_Reg(MIR_BinaryAcc.getValue(inst)));
13169
13170 } else {
13171 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
13172 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13173 emitCMPNLTSD_Reg_Abs(
13174 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
13175 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
13176
13177 } else {
13178 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
13179 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13180 emitCMPNLTSD_Reg_RegDisp(
13181 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
13182 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
13183
13184 } else {
13185 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
13186 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13187 emitCMPNLTSD_Reg_RegOff(
13188 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
13189 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
13190
13191 } else {
13192 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
13193 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13194 emitCMPNLTSD_Reg_RegIdx(
13195 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
13196 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
13197
13198 } else {
13199 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13200 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13201 emitCMPNLTSD_Reg_RegInd(
13202 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
13203 getBase(MIR_BinaryAcc.getValue(inst)));
13204 }
13205 }
13206 }
13207 }
13208 }
13209 }
13210
13211 /**
13212 * Emit the given instruction, assuming that
13213 * it is a MIR_Compare instruction
13214 * and has a FCOMIP operator
13215 *
13216 * @param inst the instruction to assemble
13217 */
13218 private void doFCOMIP(Instruction inst) {
13219 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Compare.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13220 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Compare.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13221 emitFCOMIP_Reg_Reg(
13222 getFPR_Reg(MIR_Compare.getVal1(inst)),
13223 getFPR_Reg(MIR_Compare.getVal2(inst)));
13224 }
13225
13226 /**
13227 * Emit the given instruction, assuming that
13228 * it is a MIR_Unary instruction
13229 * and has a CVTTSD2SI operator
13230 *
13231 * @param inst the instruction to assemble
13232 */
13233 private void doCVTTSD2SI(Instruction inst) {
13234 if (isXMM_Reg(MIR_Unary.getVal(inst))) {
13235 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13236 emitCVTTSD2SI_Reg_Reg(
13237 getGPR_Reg(MIR_Unary.getResult(inst)),
13238 getXMM_Reg(MIR_Unary.getVal(inst)));
13239
13240 } else {
13241 if (isAbs(MIR_Unary.getVal(inst))) {
13242 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13243 emitCVTTSD2SI_Reg_Abs(
13244 getGPR_Reg(MIR_Unary.getResult(inst)),
13245 getDisp(MIR_Unary.getVal(inst)).toWord().toAddress());
13246
13247 } else {
13248 if (isRegDisp(MIR_Unary.getVal(inst))) {
13249 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13250 emitCVTTSD2SI_Reg_RegDisp(
13251 getGPR_Reg(MIR_Unary.getResult(inst)),
13252 getBase(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
13253
13254 } else {
13255 if (isRegOff(MIR_Unary.getVal(inst))) {
13256 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13257 emitCVTTSD2SI_Reg_RegOff(
13258 getGPR_Reg(MIR_Unary.getResult(inst)),
13259 getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
13260
13261 } else {
13262 if (isRegIdx(MIR_Unary.getVal(inst))) {
13263 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13264 emitCVTTSD2SI_Reg_RegIdx(
13265 getGPR_Reg(MIR_Unary.getResult(inst)),
13266 getBase(MIR_Unary.getVal(inst)), getIndex(MIR_Unary.getVal(inst)), getScale(MIR_Unary.getVal(inst)), getDisp(MIR_Unary.getVal(inst)));
13267
13268 } else {
13269 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Unary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13270 if (VM.VerifyAssertions && !isRegInd(MIR_Unary.getVal(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13271 emitCVTTSD2SI_Reg_RegInd(
13272 getGPR_Reg(MIR_Unary.getResult(inst)),
13273 getBase(MIR_Unary.getVal(inst)));
13274 }
13275 }
13276 }
13277 }
13278 }
13279 }
13280
13281 /**
13282 * Emit the given instruction, assuming that
13283 * it is a MIR_BinaryAcc instruction
13284 * and has a SAR operator
13285 *
13286 * @param inst the instruction to assemble
13287 */
13288 private void doSAR(Instruction inst) {
13289 if (isImm(MIR_BinaryAcc.getValue(inst))) {
13290 if (isByte(inst)) {
13291 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
13292 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
13293 emitSAR_Reg_Imm_Byte(
13294 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
13295 getImm(MIR_BinaryAcc.getValue(inst)));
13296
13297 } else {
13298 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
13299 emitSAR_Abs_Imm_Byte(
13300 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
13301 getImm(MIR_BinaryAcc.getValue(inst)));
13302
13303 } else {
13304 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
13305 emitSAR_RegDisp_Imm_Byte(
13306 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
13307 getImm(MIR_BinaryAcc.getValue(inst)));
13308
13309 } else {
13310 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
13311 emitSAR_RegOff_Imm_Byte(
13312 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
13313 getImm(MIR_BinaryAcc.getValue(inst)));
13314
13315 } else {
13316 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
13317 emitSAR_RegIdx_Imm_Byte(
13318 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
13319 getImm(MIR_BinaryAcc.getValue(inst)));
13320
13321 } else {
13322 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13323 emitSAR_RegInd_Imm_Byte(
13324 getBase(MIR_BinaryAcc.getResult(inst)),
13325 getImm(MIR_BinaryAcc.getValue(inst)));
13326 }
13327 }
13328 }
13329 }
13330 }
13331
13332 } else {
13333 if (isWord(inst)) {
13334 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
13335 emitSAR_Reg_Imm_Word(
13336 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
13337 getImm(MIR_BinaryAcc.getValue(inst)));
13338
13339 } else {
13340 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
13341 emitSAR_Abs_Imm_Word(
13342 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
13343 getImm(MIR_BinaryAcc.getValue(inst)));
13344
13345 } else {
13346 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
13347 emitSAR_RegDisp_Imm_Word(
13348 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
13349 getImm(MIR_BinaryAcc.getValue(inst)));
13350
13351 } else {
13352 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
13353 emitSAR_RegOff_Imm_Word(
13354 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
13355 getImm(MIR_BinaryAcc.getValue(inst)));
13356
13357 } else {
13358 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
13359 emitSAR_RegIdx_Imm_Word(
13360 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
13361 getImm(MIR_BinaryAcc.getValue(inst)));
13362
13363 } else {
13364 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13365 emitSAR_RegInd_Imm_Word(
13366 getBase(MIR_BinaryAcc.getResult(inst)),
13367 getImm(MIR_BinaryAcc.getValue(inst)));
13368 }
13369 }
13370 }
13371 }
13372 }
13373
13374 } else {
13375 if (isQuad(inst)) {
13376 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
13377 emitSAR_Reg_Imm_Quad(
13378 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
13379 getImm(MIR_BinaryAcc.getValue(inst)));
13380
13381 } else {
13382 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
13383 emitSAR_Abs_Imm_Quad(
13384 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
13385 getImm(MIR_BinaryAcc.getValue(inst)));
13386
13387 } else {
13388 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
13389 emitSAR_RegDisp_Imm_Quad(
13390 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
13391 getImm(MIR_BinaryAcc.getValue(inst)));
13392
13393 } else {
13394 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
13395 emitSAR_RegOff_Imm_Quad(
13396 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
13397 getImm(MIR_BinaryAcc.getValue(inst)));
13398
13399 } else {
13400 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
13401 emitSAR_RegIdx_Imm_Quad(
13402 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
13403 getImm(MIR_BinaryAcc.getValue(inst)));
13404
13405 } else {
13406 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13407 emitSAR_RegInd_Imm_Quad(
13408 getBase(MIR_BinaryAcc.getResult(inst)),
13409 getImm(MIR_BinaryAcc.getValue(inst)));
13410 }
13411 }
13412 }
13413 }
13414 }
13415
13416 } else {
13417 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
13418 emitSAR_Reg_Imm(
13419 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
13420 getImm(MIR_BinaryAcc.getValue(inst)));
13421
13422 } else {
13423 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
13424 emitSAR_Abs_Imm(
13425 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
13426 getImm(MIR_BinaryAcc.getValue(inst)));
13427
13428 } else {
13429 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
13430 emitSAR_RegDisp_Imm(
13431 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
13432 getImm(MIR_BinaryAcc.getValue(inst)));
13433
13434 } else {
13435 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
13436 emitSAR_RegOff_Imm(
13437 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
13438 getImm(MIR_BinaryAcc.getValue(inst)));
13439
13440 } else {
13441 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
13442 emitSAR_RegIdx_Imm(
13443 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
13444 getImm(MIR_BinaryAcc.getValue(inst)));
13445
13446 } else {
13447 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13448 emitSAR_RegInd_Imm(
13449 getBase(MIR_BinaryAcc.getResult(inst)),
13450 getImm(MIR_BinaryAcc.getValue(inst)));
13451 }
13452 }
13453 }
13454 }
13455 }
13456 }
13457 }
13458 }
13459
13460 } else {
13461 if (isByte(inst)) {
13462 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
13463 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13464 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
13465 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
13466 emitSAR_Reg_Reg_Byte(
13467 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
13468 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
13469
13470 } else {
13471 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
13472 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13473 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
13474 emitSAR_Abs_Reg_Byte(
13475 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
13476 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
13477
13478 } else {
13479 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
13480 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13481 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
13482 emitSAR_RegDisp_Reg_Byte(
13483 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
13484 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
13485
13486 } else {
13487 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
13488 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13489 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
13490 emitSAR_RegOff_Reg_Byte(
13491 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
13492 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
13493
13494 } else {
13495 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
13496 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13497 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
13498 emitSAR_RegIdx_Reg_Byte(
13499 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
13500 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
13501
13502 } else {
13503 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13504 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13505 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
13506 emitSAR_RegInd_Reg_Byte(
13507 getBase(MIR_BinaryAcc.getResult(inst)),
13508 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
13509 }
13510 }
13511 }
13512 }
13513 }
13514
13515 } else {
13516 if (isWord(inst)) {
13517 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
13518 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13519 emitSAR_Reg_Reg_Word(
13520 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
13521 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
13522
13523 } else {
13524 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
13525 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13526 emitSAR_Abs_Reg_Word(
13527 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
13528 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
13529
13530 } else {
13531 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
13532 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13533 emitSAR_RegDisp_Reg_Word(
13534 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
13535 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
13536
13537 } else {
13538 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
13539 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13540 emitSAR_RegOff_Reg_Word(
13541 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
13542 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
13543
13544 } else {
13545 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
13546 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13547 emitSAR_RegIdx_Reg_Word(
13548 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
13549 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
13550
13551 } else {
13552 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13553 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13554 emitSAR_RegInd_Reg_Word(
13555 getBase(MIR_BinaryAcc.getResult(inst)),
13556 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
13557 }
13558 }
13559 }
13560 }
13561 }
13562
13563 } else {
13564 if (isQuad(inst)) {
13565 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
13566 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13567 emitSAR_Reg_Reg_Quad(
13568 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
13569 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
13570
13571 } else {
13572 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
13573 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13574 emitSAR_Abs_Reg_Quad(
13575 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
13576 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
13577
13578 } else {
13579 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
13580 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13581 emitSAR_RegDisp_Reg_Quad(
13582 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
13583 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
13584
13585 } else {
13586 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
13587 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13588 emitSAR_RegOff_Reg_Quad(
13589 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
13590 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
13591
13592 } else {
13593 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
13594 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13595 emitSAR_RegIdx_Reg_Quad(
13596 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
13597 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
13598
13599 } else {
13600 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13601 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13602 emitSAR_RegInd_Reg_Quad(
13603 getBase(MIR_BinaryAcc.getResult(inst)),
13604 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
13605 }
13606 }
13607 }
13608 }
13609 }
13610
13611 } else {
13612 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
13613 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13614 emitSAR_Reg_Reg(
13615 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
13616 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
13617
13618 } else {
13619 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
13620 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13621 emitSAR_Abs_Reg(
13622 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
13623 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
13624
13625 } else {
13626 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
13627 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13628 emitSAR_RegDisp_Reg(
13629 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
13630 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
13631
13632 } else {
13633 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
13634 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13635 emitSAR_RegOff_Reg(
13636 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
13637 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
13638
13639 } else {
13640 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
13641 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13642 emitSAR_RegIdx_Reg(
13643 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
13644 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
13645
13646 } else {
13647 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13648 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13649 emitSAR_RegInd_Reg(
13650 getBase(MIR_BinaryAcc.getResult(inst)),
13651 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
13652 }
13653 }
13654 }
13655 }
13656 }
13657 }
13658 }
13659 }
13660 }
13661 }
13662
13663 /**
13664 * Emit the given instruction, assuming that
13665 * it is a MIR_Move instruction
13666 * and has a MOVLPD operator
13667 *
13668 * @param inst the instruction to assemble
13669 */
13670 private void doMOVLPD(Instruction inst) {
13671 if (isXMM_Reg(MIR_Move.getResult(inst))) {
13672 if (isXMM_Reg(MIR_Move.getValue(inst))) {
13673 emitMOVLPD_Reg_Reg(
13674 getXMM_Reg(MIR_Move.getResult(inst)),
13675 getXMM_Reg(MIR_Move.getValue(inst)));
13676
13677 } else {
13678 if (isAbs(MIR_Move.getValue(inst))) {
13679 emitMOVLPD_Reg_Abs(
13680 getXMM_Reg(MIR_Move.getResult(inst)),
13681 getDisp(MIR_Move.getValue(inst)).toWord().toAddress());
13682
13683 } else {
13684 if (isRegDisp(MIR_Move.getValue(inst))) {
13685 emitMOVLPD_Reg_RegDisp(
13686 getXMM_Reg(MIR_Move.getResult(inst)),
13687 getBase(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
13688
13689 } else {
13690 if (isRegOff(MIR_Move.getValue(inst))) {
13691 emitMOVLPD_Reg_RegOff(
13692 getXMM_Reg(MIR_Move.getResult(inst)),
13693 getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
13694
13695 } else {
13696 if (isRegIdx(MIR_Move.getValue(inst))) {
13697 emitMOVLPD_Reg_RegIdx(
13698 getXMM_Reg(MIR_Move.getResult(inst)),
13699 getBase(MIR_Move.getValue(inst)), getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
13700
13701 } else {
13702 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13703 emitMOVLPD_Reg_RegInd(
13704 getXMM_Reg(MIR_Move.getResult(inst)),
13705 getBase(MIR_Move.getValue(inst)));
13706 }
13707 }
13708 }
13709 }
13710 }
13711
13712 } else {
13713 if (isAbs(MIR_Move.getResult(inst))) {
13714 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13715 emitMOVLPD_Abs_Reg(
13716 getDisp(MIR_Move.getResult(inst)).toWord().toAddress(),
13717 getXMM_Reg(MIR_Move.getValue(inst)));
13718
13719 } else {
13720 if (isRegDisp(MIR_Move.getResult(inst))) {
13721 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13722 emitMOVLPD_RegDisp_Reg(
13723 getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
13724 getXMM_Reg(MIR_Move.getValue(inst)));
13725
13726 } else {
13727 if (isRegOff(MIR_Move.getResult(inst))) {
13728 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13729 emitMOVLPD_RegOff_Reg(
13730 getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
13731 getXMM_Reg(MIR_Move.getValue(inst)));
13732
13733 } else {
13734 if (isRegIdx(MIR_Move.getResult(inst))) {
13735 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13736 emitMOVLPD_RegIdx_Reg(
13737 getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
13738 getXMM_Reg(MIR_Move.getValue(inst)));
13739
13740 } else {
13741 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13742 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13743 emitMOVLPD_RegInd_Reg(
13744 getBase(MIR_Move.getResult(inst)),
13745 getXMM_Reg(MIR_Move.getValue(inst)));
13746 }
13747 }
13748 }
13749 }
13750 }
13751 }
13752
13753 /**
13754 * Emit the given instruction, assuming that
13755 * it is a MIR_BinaryAcc instruction
13756 * and has a FIDIV operator
13757 *
13758 * @param inst the instruction to assemble
13759 */
13760 private void doFIDIV(Instruction inst) {
13761 if (isWord(inst)) {
13762 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
13763 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13764 emitFIDIV_Reg_Abs_Word(
13765 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
13766 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
13767
13768 } else {
13769 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
13770 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13771 emitFIDIV_Reg_RegDisp_Word(
13772 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
13773 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
13774
13775 } else {
13776 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
13777 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13778 emitFIDIV_Reg_RegOff_Word(
13779 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
13780 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
13781
13782 } else {
13783 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
13784 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13785 emitFIDIV_Reg_RegIdx_Word(
13786 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
13787 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
13788
13789 } else {
13790 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13791 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13792 emitFIDIV_Reg_RegInd_Word(
13793 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
13794 getBase(MIR_BinaryAcc.getValue(inst)));
13795 }
13796 }
13797 }
13798 }
13799
13800 } else {
13801 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
13802 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13803 emitFIDIV_Reg_Abs(
13804 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
13805 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
13806
13807 } else {
13808 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
13809 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13810 emitFIDIV_Reg_RegDisp(
13811 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
13812 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
13813
13814 } else {
13815 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
13816 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13817 emitFIDIV_Reg_RegOff(
13818 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
13819 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
13820
13821 } else {
13822 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
13823 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13824 emitFIDIV_Reg_RegIdx(
13825 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
13826 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
13827
13828 } else {
13829 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13830 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13831 emitFIDIV_Reg_RegInd(
13832 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
13833 getBase(MIR_BinaryAcc.getValue(inst)));
13834 }
13835 }
13836 }
13837 }
13838 }
13839 }
13840
13841 /**
13842 * Emit the given instruction, assuming that
13843 * it is a MIR_Trap instruction
13844 * and has a INT operator
13845 *
13846 * @param inst the instruction to assemble
13847 */
13848 private void doINT(Instruction inst) {
13849 if (VM.VerifyAssertions && !isImm(MIR_Trap.getTrapCode(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13850 emitINT_Imm(
13851 getImm(MIR_Trap.getTrapCode(inst)));
13852 }
13853
13854 /**
13855 * Emit the given instruction, assuming that
13856 * it is a MIR_FSave instruction
13857 * and has a FRSTOR operator
13858 *
13859 * @param inst the instruction to assemble
13860 */
13861 private void doFRSTOR(Instruction inst) {
13862 if (isAbs(MIR_FSave.getDestination(inst))) {
13863 emitFRSTOR_Abs(
13864 getDisp(MIR_FSave.getDestination(inst)).toWord().toAddress());
13865
13866 } else {
13867 if (isRegDisp(MIR_FSave.getDestination(inst))) {
13868 emitFRSTOR_RegDisp(
13869 getBase(MIR_FSave.getDestination(inst)), getDisp(MIR_FSave.getDestination(inst)));
13870
13871 } else {
13872 if (isRegOff(MIR_FSave.getDestination(inst))) {
13873 emitFRSTOR_RegOff(
13874 getIndex(MIR_FSave.getDestination(inst)), getScale(MIR_FSave.getDestination(inst)), getDisp(MIR_FSave.getDestination(inst)));
13875
13876 } else {
13877 if (isRegIdx(MIR_FSave.getDestination(inst))) {
13878 emitFRSTOR_RegIdx(
13879 getBase(MIR_FSave.getDestination(inst)), getIndex(MIR_FSave.getDestination(inst)), getScale(MIR_FSave.getDestination(inst)), getDisp(MIR_FSave.getDestination(inst)));
13880
13881 } else {
13882 if (VM.VerifyAssertions && !isRegInd(MIR_FSave.getDestination(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13883 emitFRSTOR_RegInd(
13884 getBase(MIR_FSave.getDestination(inst)));
13885 }
13886 }
13887 }
13888 }
13889 }
13890
13891 /**
13892 * Emit the given instruction, assuming that
13893 * it is a MIR_BinaryAcc instruction
13894 * and has a CMPNLTSS operator
13895 *
13896 * @param inst the instruction to assemble
13897 */
13898 private void doCMPNLTSS(Instruction inst) {
13899 if (isXMM_Reg(MIR_BinaryAcc.getValue(inst))) {
13900 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13901 emitCMPNLTSS_Reg_Reg(
13902 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
13903 getXMM_Reg(MIR_BinaryAcc.getValue(inst)));
13904
13905 } else {
13906 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
13907 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13908 emitCMPNLTSS_Reg_Abs(
13909 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
13910 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
13911
13912 } else {
13913 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
13914 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13915 emitCMPNLTSS_Reg_RegDisp(
13916 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
13917 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
13918
13919 } else {
13920 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
13921 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13922 emitCMPNLTSS_Reg_RegOff(
13923 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
13924 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
13925
13926 } else {
13927 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
13928 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13929 emitCMPNLTSS_Reg_RegIdx(
13930 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
13931 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
13932
13933 } else {
13934 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13935 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13936 emitCMPNLTSS_Reg_RegInd(
13937 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
13938 getBase(MIR_BinaryAcc.getValue(inst)));
13939 }
13940 }
13941 }
13942 }
13943 }
13944 }
13945
13946 /**
13947 * Emit the given instruction, assuming that
13948 * it is a MIR_Move instruction
13949 * and has a MOVD operator
13950 *
13951 * @param inst the instruction to assemble
13952 */
13953 private void doMOVD(Instruction inst) {
13954 if (isMM_Reg(MIR_Move.getResult(inst))) {
13955 if (isGPR_Reg(MIR_Move.getValue(inst))) {
13956 emitMOVD_Reg_Reg(
13957 getMM_Reg(MIR_Move.getResult(inst)),
13958 getGPR_Reg(MIR_Move.getValue(inst)));
13959
13960 } else {
13961 if (isAbs(MIR_Move.getValue(inst))) {
13962 emitMOVD_Reg_Abs(
13963 getMM_Reg(MIR_Move.getResult(inst)),
13964 getDisp(MIR_Move.getValue(inst)).toWord().toAddress());
13965
13966 } else {
13967 if (isRegDisp(MIR_Move.getValue(inst))) {
13968 emitMOVD_Reg_RegDisp(
13969 getMM_Reg(MIR_Move.getResult(inst)),
13970 getBase(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
13971
13972 } else {
13973 if (isRegOff(MIR_Move.getValue(inst))) {
13974 emitMOVD_Reg_RegOff(
13975 getMM_Reg(MIR_Move.getResult(inst)),
13976 getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
13977
13978 } else {
13979 if (isRegIdx(MIR_Move.getValue(inst))) {
13980 emitMOVD_Reg_RegIdx(
13981 getMM_Reg(MIR_Move.getResult(inst)),
13982 getBase(MIR_Move.getValue(inst)), getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
13983
13984 } else {
13985 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
13986 emitMOVD_Reg_RegInd(
13987 getMM_Reg(MIR_Move.getResult(inst)),
13988 getBase(MIR_Move.getValue(inst)));
13989 }
13990 }
13991 }
13992 }
13993 }
13994
13995 } else {
13996 if (isXMM_Reg(MIR_Move.getResult(inst))) {
13997 if (isGPR_Reg(MIR_Move.getValue(inst))) {
13998 emitMOVD_Reg_Reg(
13999 getXMM_Reg(MIR_Move.getResult(inst)),
14000 getGPR_Reg(MIR_Move.getValue(inst)));
14001
14002 } else {
14003 if (isAbs(MIR_Move.getValue(inst))) {
14004 emitMOVD_Reg_Abs(
14005 getXMM_Reg(MIR_Move.getResult(inst)),
14006 getDisp(MIR_Move.getValue(inst)).toWord().toAddress());
14007
14008 } else {
14009 if (isRegDisp(MIR_Move.getValue(inst))) {
14010 emitMOVD_Reg_RegDisp(
14011 getXMM_Reg(MIR_Move.getResult(inst)),
14012 getBase(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
14013
14014 } else {
14015 if (isRegOff(MIR_Move.getValue(inst))) {
14016 emitMOVD_Reg_RegOff(
14017 getXMM_Reg(MIR_Move.getResult(inst)),
14018 getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
14019
14020 } else {
14021 if (isRegIdx(MIR_Move.getValue(inst))) {
14022 emitMOVD_Reg_RegIdx(
14023 getXMM_Reg(MIR_Move.getResult(inst)),
14024 getBase(MIR_Move.getValue(inst)), getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
14025
14026 } else {
14027 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14028 emitMOVD_Reg_RegInd(
14029 getXMM_Reg(MIR_Move.getResult(inst)),
14030 getBase(MIR_Move.getValue(inst)));
14031 }
14032 }
14033 }
14034 }
14035 }
14036
14037 } else {
14038 if (isMM_Reg(MIR_Move.getValue(inst))) {
14039 if (isGPR_Reg(MIR_Move.getResult(inst))) {
14040 emitMOVD_Reg_Reg(
14041 getGPR_Reg(MIR_Move.getResult(inst)),
14042 getMM_Reg(MIR_Move.getValue(inst)));
14043
14044 } else {
14045 if (isAbs(MIR_Move.getResult(inst))) {
14046 emitMOVD_Abs_Reg(
14047 getDisp(MIR_Move.getResult(inst)).toWord().toAddress(),
14048 getMM_Reg(MIR_Move.getValue(inst)));
14049
14050 } else {
14051 if (isRegDisp(MIR_Move.getResult(inst))) {
14052 emitMOVD_RegDisp_Reg(
14053 getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
14054 getMM_Reg(MIR_Move.getValue(inst)));
14055
14056 } else {
14057 if (isRegOff(MIR_Move.getResult(inst))) {
14058 emitMOVD_RegOff_Reg(
14059 getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
14060 getMM_Reg(MIR_Move.getValue(inst)));
14061
14062 } else {
14063 if (isRegIdx(MIR_Move.getResult(inst))) {
14064 emitMOVD_RegIdx_Reg(
14065 getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
14066 getMM_Reg(MIR_Move.getValue(inst)));
14067
14068 } else {
14069 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14070 emitMOVD_RegInd_Reg(
14071 getBase(MIR_Move.getResult(inst)),
14072 getMM_Reg(MIR_Move.getValue(inst)));
14073 }
14074 }
14075 }
14076 }
14077 }
14078
14079 } else {
14080 if (isGPR_Reg(MIR_Move.getResult(inst))) {
14081 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14082 emitMOVD_Reg_Reg(
14083 getGPR_Reg(MIR_Move.getResult(inst)),
14084 getXMM_Reg(MIR_Move.getValue(inst)));
14085
14086 } else {
14087 if (isAbs(MIR_Move.getResult(inst))) {
14088 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14089 emitMOVD_Abs_Reg(
14090 getDisp(MIR_Move.getResult(inst)).toWord().toAddress(),
14091 getXMM_Reg(MIR_Move.getValue(inst)));
14092
14093 } else {
14094 if (isRegDisp(MIR_Move.getResult(inst))) {
14095 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14096 emitMOVD_RegDisp_Reg(
14097 getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
14098 getXMM_Reg(MIR_Move.getValue(inst)));
14099
14100 } else {
14101 if (isRegOff(MIR_Move.getResult(inst))) {
14102 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14103 emitMOVD_RegOff_Reg(
14104 getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
14105 getXMM_Reg(MIR_Move.getValue(inst)));
14106
14107 } else {
14108 if (isRegIdx(MIR_Move.getResult(inst))) {
14109 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14110 emitMOVD_RegIdx_Reg(
14111 getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
14112 getXMM_Reg(MIR_Move.getValue(inst)));
14113
14114 } else {
14115 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14116 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14117 emitMOVD_RegInd_Reg(
14118 getBase(MIR_Move.getResult(inst)),
14119 getXMM_Reg(MIR_Move.getValue(inst)));
14120 }
14121 }
14122 }
14123 }
14124 }
14125 }
14126 }
14127 }
14128 }
14129
14130 /**
14131 * Emit the given instruction, assuming that
14132 * it is a MIR_CondMove instruction
14133 * and has a CMOV operator
14134 *
14135 * @param inst the instruction to assemble
14136 */
14137 private void doCMOV(Instruction inst) {
14138 if (isGPR_Reg(MIR_CondMove.getValue(inst))) {
14139 if (VM.VerifyAssertions && !isCond(MIR_CondMove.getCond(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14140 if (VM.VerifyAssertions && !isGPR_Reg(MIR_CondMove.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14141 emitCMOV_Cond_Reg_Reg(
14142 getCond(MIR_CondMove.getCond(inst)),
14143 getGPR_Reg(MIR_CondMove.getResult(inst)),
14144 getGPR_Reg(MIR_CondMove.getValue(inst)));
14145
14146 } else {
14147 if (isAbs(MIR_CondMove.getValue(inst))) {
14148 if (VM.VerifyAssertions && !isCond(MIR_CondMove.getCond(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14149 if (VM.VerifyAssertions && !isGPR_Reg(MIR_CondMove.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14150 emitCMOV_Cond_Reg_Abs(
14151 getCond(MIR_CondMove.getCond(inst)),
14152 getGPR_Reg(MIR_CondMove.getResult(inst)),
14153 getDisp(MIR_CondMove.getValue(inst)).toWord().toAddress());
14154
14155 } else {
14156 if (isRegDisp(MIR_CondMove.getValue(inst))) {
14157 if (VM.VerifyAssertions && !isCond(MIR_CondMove.getCond(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14158 if (VM.VerifyAssertions && !isGPR_Reg(MIR_CondMove.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14159 emitCMOV_Cond_Reg_RegDisp(
14160 getCond(MIR_CondMove.getCond(inst)),
14161 getGPR_Reg(MIR_CondMove.getResult(inst)),
14162 getBase(MIR_CondMove.getValue(inst)), getDisp(MIR_CondMove.getValue(inst)));
14163
14164 } else {
14165 if (isRegOff(MIR_CondMove.getValue(inst))) {
14166 if (VM.VerifyAssertions && !isCond(MIR_CondMove.getCond(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14167 if (VM.VerifyAssertions && !isGPR_Reg(MIR_CondMove.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14168 emitCMOV_Cond_Reg_RegOff(
14169 getCond(MIR_CondMove.getCond(inst)),
14170 getGPR_Reg(MIR_CondMove.getResult(inst)),
14171 getIndex(MIR_CondMove.getValue(inst)), getScale(MIR_CondMove.getValue(inst)), getDisp(MIR_CondMove.getValue(inst)));
14172
14173 } else {
14174 if (isRegIdx(MIR_CondMove.getValue(inst))) {
14175 if (VM.VerifyAssertions && !isCond(MIR_CondMove.getCond(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14176 if (VM.VerifyAssertions && !isGPR_Reg(MIR_CondMove.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14177 emitCMOV_Cond_Reg_RegIdx(
14178 getCond(MIR_CondMove.getCond(inst)),
14179 getGPR_Reg(MIR_CondMove.getResult(inst)),
14180 getBase(MIR_CondMove.getValue(inst)), getIndex(MIR_CondMove.getValue(inst)), getScale(MIR_CondMove.getValue(inst)), getDisp(MIR_CondMove.getValue(inst)));
14181
14182 } else {
14183 if (VM.VerifyAssertions && !isCond(MIR_CondMove.getCond(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14184 if (VM.VerifyAssertions && !isGPR_Reg(MIR_CondMove.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14185 if (VM.VerifyAssertions && !isRegInd(MIR_CondMove.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14186 emitCMOV_Cond_Reg_RegInd(
14187 getCond(MIR_CondMove.getCond(inst)),
14188 getGPR_Reg(MIR_CondMove.getResult(inst)),
14189 getBase(MIR_CondMove.getValue(inst)));
14190 }
14191 }
14192 }
14193 }
14194 }
14195 }
14196
14197 /**
14198 * Emit the given instruction, assuming that
14199 * it is a MIR_BinaryAcc instruction
14200 * and has a SBB operator
14201 *
14202 * @param inst the instruction to assemble
14203 */
14204 private void doSBB(Instruction inst) {
14205 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
14206 if (isByte(inst)) {
14207 if (isImm(MIR_BinaryAcc.getValue(inst))) {
14208 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
14209 emitSBB_Reg_Imm_Byte(
14210 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14211 getImm(MIR_BinaryAcc.getValue(inst)));
14212
14213 } else {
14214 if (isGPR_Reg(MIR_BinaryAcc.getValue(inst))) {
14215 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
14216 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
14217 emitSBB_Reg_Reg_Byte(
14218 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14219 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
14220
14221 } else {
14222 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
14223 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
14224 emitSBB_Reg_Abs_Byte(
14225 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14226 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
14227
14228 } else {
14229 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
14230 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
14231 emitSBB_Reg_RegDisp_Byte(
14232 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14233 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
14234
14235 } else {
14236 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
14237 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
14238 emitSBB_Reg_RegOff_Byte(
14239 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14240 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
14241
14242 } else {
14243 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
14244 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
14245 emitSBB_Reg_RegIdx_Byte(
14246 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14247 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
14248
14249 } else {
14250 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14251 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
14252 emitSBB_Reg_RegInd_Byte(
14253 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14254 getBase(MIR_BinaryAcc.getValue(inst)));
14255 }
14256 }
14257 }
14258 }
14259 }
14260 }
14261
14262 } else {
14263 if (isWord(inst)) {
14264 if (isImm(MIR_BinaryAcc.getValue(inst))) {
14265 emitSBB_Reg_Imm_Word(
14266 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14267 getImm(MIR_BinaryAcc.getValue(inst)));
14268
14269 } else {
14270 if (isGPR_Reg(MIR_BinaryAcc.getValue(inst))) {
14271 emitSBB_Reg_Reg_Word(
14272 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14273 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
14274
14275 } else {
14276 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
14277 emitSBB_Reg_Abs_Word(
14278 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14279 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
14280
14281 } else {
14282 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
14283 emitSBB_Reg_RegDisp_Word(
14284 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14285 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
14286
14287 } else {
14288 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
14289 emitSBB_Reg_RegOff_Word(
14290 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14291 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
14292
14293 } else {
14294 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
14295 emitSBB_Reg_RegIdx_Word(
14296 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14297 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
14298
14299 } else {
14300 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14301 emitSBB_Reg_RegInd_Word(
14302 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14303 getBase(MIR_BinaryAcc.getValue(inst)));
14304 }
14305 }
14306 }
14307 }
14308 }
14309 }
14310
14311 } else {
14312 if (isQuad(inst)) {
14313 if (isImm(MIR_BinaryAcc.getValue(inst))) {
14314 emitSBB_Reg_Imm_Quad(
14315 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14316 getImm(MIR_BinaryAcc.getValue(inst)));
14317
14318 } else {
14319 if (isGPR_Reg(MIR_BinaryAcc.getValue(inst))) {
14320 emitSBB_Reg_Reg_Quad(
14321 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14322 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
14323
14324 } else {
14325 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
14326 emitSBB_Reg_Abs_Quad(
14327 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14328 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
14329
14330 } else {
14331 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
14332 emitSBB_Reg_RegDisp_Quad(
14333 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14334 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
14335
14336 } else {
14337 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
14338 emitSBB_Reg_RegOff_Quad(
14339 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14340 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
14341
14342 } else {
14343 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
14344 emitSBB_Reg_RegIdx_Quad(
14345 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14346 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
14347
14348 } else {
14349 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14350 emitSBB_Reg_RegInd_Quad(
14351 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14352 getBase(MIR_BinaryAcc.getValue(inst)));
14353 }
14354 }
14355 }
14356 }
14357 }
14358 }
14359
14360 } else {
14361 if (isImm(MIR_BinaryAcc.getValue(inst))) {
14362 emitSBB_Reg_Imm(
14363 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14364 getImm(MIR_BinaryAcc.getValue(inst)));
14365
14366 } else {
14367 if (isGPR_Reg(MIR_BinaryAcc.getValue(inst))) {
14368 emitSBB_Reg_Reg(
14369 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14370 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
14371
14372 } else {
14373 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
14374 emitSBB_Reg_Abs(
14375 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14376 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
14377
14378 } else {
14379 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
14380 emitSBB_Reg_RegDisp(
14381 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14382 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
14383
14384 } else {
14385 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
14386 emitSBB_Reg_RegOff(
14387 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14388 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
14389
14390 } else {
14391 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
14392 emitSBB_Reg_RegIdx(
14393 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14394 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
14395
14396 } else {
14397 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14398 emitSBB_Reg_RegInd(
14399 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14400 getBase(MIR_BinaryAcc.getValue(inst)));
14401 }
14402 }
14403 }
14404 }
14405 }
14406 }
14407 }
14408 }
14409 }
14410
14411 } else {
14412 if (isImm(MIR_BinaryAcc.getValue(inst))) {
14413 if (isByte(inst)) {
14414 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
14415 emitSBB_Abs_Imm_Byte(
14416 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
14417 getImm(MIR_BinaryAcc.getValue(inst)));
14418
14419 } else {
14420 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
14421 emitSBB_RegDisp_Imm_Byte(
14422 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
14423 getImm(MIR_BinaryAcc.getValue(inst)));
14424
14425 } else {
14426 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
14427 emitSBB_RegOff_Imm_Byte(
14428 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
14429 getImm(MIR_BinaryAcc.getValue(inst)));
14430
14431 } else {
14432 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
14433 emitSBB_RegIdx_Imm_Byte(
14434 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
14435 getImm(MIR_BinaryAcc.getValue(inst)));
14436
14437 } else {
14438 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14439 emitSBB_RegInd_Imm_Byte(
14440 getBase(MIR_BinaryAcc.getResult(inst)),
14441 getImm(MIR_BinaryAcc.getValue(inst)));
14442 }
14443 }
14444 }
14445 }
14446
14447 } else {
14448 if (isWord(inst)) {
14449 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
14450 emitSBB_Abs_Imm_Word(
14451 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
14452 getImm(MIR_BinaryAcc.getValue(inst)));
14453
14454 } else {
14455 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
14456 emitSBB_RegDisp_Imm_Word(
14457 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
14458 getImm(MIR_BinaryAcc.getValue(inst)));
14459
14460 } else {
14461 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
14462 emitSBB_RegOff_Imm_Word(
14463 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
14464 getImm(MIR_BinaryAcc.getValue(inst)));
14465
14466 } else {
14467 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
14468 emitSBB_RegIdx_Imm_Word(
14469 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
14470 getImm(MIR_BinaryAcc.getValue(inst)));
14471
14472 } else {
14473 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14474 emitSBB_RegInd_Imm_Word(
14475 getBase(MIR_BinaryAcc.getResult(inst)),
14476 getImm(MIR_BinaryAcc.getValue(inst)));
14477 }
14478 }
14479 }
14480 }
14481
14482 } else {
14483 if (isQuad(inst)) {
14484 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
14485 emitSBB_Abs_Imm_Quad(
14486 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
14487 getImm(MIR_BinaryAcc.getValue(inst)));
14488
14489 } else {
14490 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
14491 emitSBB_RegDisp_Imm_Quad(
14492 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
14493 getImm(MIR_BinaryAcc.getValue(inst)));
14494
14495 } else {
14496 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
14497 emitSBB_RegOff_Imm_Quad(
14498 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
14499 getImm(MIR_BinaryAcc.getValue(inst)));
14500
14501 } else {
14502 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
14503 emitSBB_RegIdx_Imm_Quad(
14504 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
14505 getImm(MIR_BinaryAcc.getValue(inst)));
14506
14507 } else {
14508 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14509 emitSBB_RegInd_Imm_Quad(
14510 getBase(MIR_BinaryAcc.getResult(inst)),
14511 getImm(MIR_BinaryAcc.getValue(inst)));
14512 }
14513 }
14514 }
14515 }
14516
14517 } else {
14518 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
14519 emitSBB_Abs_Imm(
14520 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
14521 getImm(MIR_BinaryAcc.getValue(inst)));
14522
14523 } else {
14524 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
14525 emitSBB_RegDisp_Imm(
14526 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
14527 getImm(MIR_BinaryAcc.getValue(inst)));
14528
14529 } else {
14530 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
14531 emitSBB_RegOff_Imm(
14532 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
14533 getImm(MIR_BinaryAcc.getValue(inst)));
14534
14535 } else {
14536 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
14537 emitSBB_RegIdx_Imm(
14538 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
14539 getImm(MIR_BinaryAcc.getValue(inst)));
14540
14541 } else {
14542 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14543 emitSBB_RegInd_Imm(
14544 getBase(MIR_BinaryAcc.getResult(inst)),
14545 getImm(MIR_BinaryAcc.getValue(inst)));
14546 }
14547 }
14548 }
14549 }
14550 }
14551 }
14552 }
14553
14554 } else {
14555 if (isByte(inst)) {
14556 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
14557 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14558 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
14559 emitSBB_Abs_Reg_Byte(
14560 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
14561 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
14562
14563 } else {
14564 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
14565 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14566 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
14567 emitSBB_RegDisp_Reg_Byte(
14568 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
14569 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
14570
14571 } else {
14572 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
14573 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14574 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
14575 emitSBB_RegOff_Reg_Byte(
14576 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
14577 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
14578
14579 } else {
14580 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
14581 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14582 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
14583 emitSBB_RegIdx_Reg_Byte(
14584 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
14585 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
14586
14587 } else {
14588 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14589 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14590 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
14591 emitSBB_RegInd_Reg_Byte(
14592 getBase(MIR_BinaryAcc.getResult(inst)),
14593 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
14594 }
14595 }
14596 }
14597 }
14598
14599 } else {
14600 if (isWord(inst)) {
14601 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
14602 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14603 emitSBB_Abs_Reg_Word(
14604 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
14605 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
14606
14607 } else {
14608 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
14609 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14610 emitSBB_RegDisp_Reg_Word(
14611 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
14612 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
14613
14614 } else {
14615 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
14616 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14617 emitSBB_RegOff_Reg_Word(
14618 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
14619 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
14620
14621 } else {
14622 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
14623 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14624 emitSBB_RegIdx_Reg_Word(
14625 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
14626 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
14627
14628 } else {
14629 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14630 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14631 emitSBB_RegInd_Reg_Word(
14632 getBase(MIR_BinaryAcc.getResult(inst)),
14633 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
14634 }
14635 }
14636 }
14637 }
14638
14639 } else {
14640 if (isQuad(inst)) {
14641 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
14642 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14643 emitSBB_Abs_Reg_Quad(
14644 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
14645 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
14646
14647 } else {
14648 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
14649 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14650 emitSBB_RegDisp_Reg_Quad(
14651 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
14652 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
14653
14654 } else {
14655 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
14656 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14657 emitSBB_RegOff_Reg_Quad(
14658 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
14659 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
14660
14661 } else {
14662 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
14663 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14664 emitSBB_RegIdx_Reg_Quad(
14665 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
14666 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
14667
14668 } else {
14669 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14670 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14671 emitSBB_RegInd_Reg_Quad(
14672 getBase(MIR_BinaryAcc.getResult(inst)),
14673 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
14674 }
14675 }
14676 }
14677 }
14678
14679 } else {
14680 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
14681 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14682 emitSBB_Abs_Reg(
14683 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
14684 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
14685
14686 } else {
14687 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
14688 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14689 emitSBB_RegDisp_Reg(
14690 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
14691 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
14692
14693 } else {
14694 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
14695 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14696 emitSBB_RegOff_Reg(
14697 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
14698 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
14699
14700 } else {
14701 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
14702 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14703 emitSBB_RegIdx_Reg(
14704 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
14705 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
14706
14707 } else {
14708 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14709 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14710 emitSBB_RegInd_Reg(
14711 getBase(MIR_BinaryAcc.getResult(inst)),
14712 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
14713 }
14714 }
14715 }
14716 }
14717 }
14718 }
14719 }
14720 }
14721 }
14722 }
14723
14724 /**
14725 * Emit the given instruction, assuming that
14726 * it is a MIR_UnaryAcc instruction
14727 * and has a BSWAP operator
14728 *
14729 * @param inst the instruction to assemble
14730 */
14731 private void doBSWAP(Instruction inst) {
14732 if (isQuad(inst)) {
14733 if (VM.VerifyAssertions && !isGPR_Reg(MIR_UnaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14734 emitBSWAP_Reg_Quad(
14735 getGPR_Reg(MIR_UnaryAcc.getResult(inst)));
14736
14737 } else {
14738 if (VM.VerifyAssertions && !isGPR_Reg(MIR_UnaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14739 emitBSWAP_Reg(
14740 getGPR_Reg(MIR_UnaryAcc.getResult(inst)));
14741 }
14742 }
14743
14744 /**
14745 * Emit the given instruction, assuming that
14746 * it is a MIR_Multiply instruction
14747 * and has a IMUL1 operator
14748 *
14749 * @param inst the instruction to assemble
14750 */
14751 private void doIMUL1(Instruction inst) {
14752 if (isQuad(inst)) {
14753 if (isGPR_Reg(MIR_Multiply.getValue(inst))) {
14754 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Multiply.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14755 emitIMUL1_Reg_Reg_Quad(
14756 getGPR_Reg(MIR_Multiply.getResult2(inst)),
14757 getGPR_Reg(MIR_Multiply.getValue(inst)));
14758
14759 } else {
14760 if (isAbs(MIR_Multiply.getValue(inst))) {
14761 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Multiply.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14762 emitIMUL1_Reg_Abs_Quad(
14763 getGPR_Reg(MIR_Multiply.getResult2(inst)),
14764 getDisp(MIR_Multiply.getValue(inst)).toWord().toAddress());
14765
14766 } else {
14767 if (isRegDisp(MIR_Multiply.getValue(inst))) {
14768 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Multiply.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14769 emitIMUL1_Reg_RegDisp_Quad(
14770 getGPR_Reg(MIR_Multiply.getResult2(inst)),
14771 getBase(MIR_Multiply.getValue(inst)), getDisp(MIR_Multiply.getValue(inst)));
14772
14773 } else {
14774 if (isRegOff(MIR_Multiply.getValue(inst))) {
14775 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Multiply.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14776 emitIMUL1_Reg_RegOff_Quad(
14777 getGPR_Reg(MIR_Multiply.getResult2(inst)),
14778 getIndex(MIR_Multiply.getValue(inst)), getScale(MIR_Multiply.getValue(inst)), getDisp(MIR_Multiply.getValue(inst)));
14779
14780 } else {
14781 if (isRegIdx(MIR_Multiply.getValue(inst))) {
14782 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Multiply.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14783 emitIMUL1_Reg_RegIdx_Quad(
14784 getGPR_Reg(MIR_Multiply.getResult2(inst)),
14785 getBase(MIR_Multiply.getValue(inst)), getIndex(MIR_Multiply.getValue(inst)), getScale(MIR_Multiply.getValue(inst)), getDisp(MIR_Multiply.getValue(inst)));
14786
14787 } else {
14788 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Multiply.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14789 if (VM.VerifyAssertions && !isRegInd(MIR_Multiply.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14790 emitIMUL1_Reg_RegInd_Quad(
14791 getGPR_Reg(MIR_Multiply.getResult2(inst)),
14792 getBase(MIR_Multiply.getValue(inst)));
14793 }
14794 }
14795 }
14796 }
14797 }
14798
14799 } else {
14800 if (isGPR_Reg(MIR_Multiply.getValue(inst))) {
14801 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Multiply.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14802 emitIMUL1_Reg_Reg(
14803 getGPR_Reg(MIR_Multiply.getResult2(inst)),
14804 getGPR_Reg(MIR_Multiply.getValue(inst)));
14805
14806 } else {
14807 if (isAbs(MIR_Multiply.getValue(inst))) {
14808 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Multiply.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14809 emitIMUL1_Reg_Abs(
14810 getGPR_Reg(MIR_Multiply.getResult2(inst)),
14811 getDisp(MIR_Multiply.getValue(inst)).toWord().toAddress());
14812
14813 } else {
14814 if (isRegDisp(MIR_Multiply.getValue(inst))) {
14815 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Multiply.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14816 emitIMUL1_Reg_RegDisp(
14817 getGPR_Reg(MIR_Multiply.getResult2(inst)),
14818 getBase(MIR_Multiply.getValue(inst)), getDisp(MIR_Multiply.getValue(inst)));
14819
14820 } else {
14821 if (isRegOff(MIR_Multiply.getValue(inst))) {
14822 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Multiply.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14823 emitIMUL1_Reg_RegOff(
14824 getGPR_Reg(MIR_Multiply.getResult2(inst)),
14825 getIndex(MIR_Multiply.getValue(inst)), getScale(MIR_Multiply.getValue(inst)), getDisp(MIR_Multiply.getValue(inst)));
14826
14827 } else {
14828 if (isRegIdx(MIR_Multiply.getValue(inst))) {
14829 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Multiply.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14830 emitIMUL1_Reg_RegIdx(
14831 getGPR_Reg(MIR_Multiply.getResult2(inst)),
14832 getBase(MIR_Multiply.getValue(inst)), getIndex(MIR_Multiply.getValue(inst)), getScale(MIR_Multiply.getValue(inst)), getDisp(MIR_Multiply.getValue(inst)));
14833
14834 } else {
14835 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Multiply.getResult2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14836 if (VM.VerifyAssertions && !isRegInd(MIR_Multiply.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14837 emitIMUL1_Reg_RegInd(
14838 getGPR_Reg(MIR_Multiply.getResult2(inst)),
14839 getBase(MIR_Multiply.getValue(inst)));
14840 }
14841 }
14842 }
14843 }
14844 }
14845 }
14846 }
14847
14848 /**
14849 * Emit the given instruction, assuming that
14850 * it is a MIR_Empty instruction
14851 * and has a PAUSE operator
14852 *
14853 * @param inst the instruction to assemble
14854 */
14855 private void doPAUSE(Instruction inst) {
14856 emitPAUSE();
14857 }
14858
14859 /**
14860 * Emit the given instruction, assuming that
14861 * it is a MIR_BinaryAcc instruction
14862 * and has a IMUL2 operator
14863 *
14864 * @param inst the instruction to assemble
14865 */
14866 private void doIMUL2(Instruction inst) {
14867 if (isQuad(inst)) {
14868 if (isImm(MIR_BinaryAcc.getValue(inst))) {
14869 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14870 emitIMUL2_Reg_Imm_Quad(
14871 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14872 getImm(MIR_BinaryAcc.getValue(inst)));
14873
14874 } else {
14875 if (isGPR_Reg(MIR_BinaryAcc.getValue(inst))) {
14876 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14877 emitIMUL2_Reg_Reg_Quad(
14878 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14879 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
14880
14881 } else {
14882 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
14883 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14884 emitIMUL2_Reg_Abs_Quad(
14885 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14886 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
14887
14888 } else {
14889 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
14890 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14891 emitIMUL2_Reg_RegDisp_Quad(
14892 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14893 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
14894
14895 } else {
14896 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
14897 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14898 emitIMUL2_Reg_RegOff_Quad(
14899 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14900 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
14901
14902 } else {
14903 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
14904 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14905 emitIMUL2_Reg_RegIdx_Quad(
14906 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14907 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
14908
14909 } else {
14910 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14911 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14912 emitIMUL2_Reg_RegInd_Quad(
14913 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14914 getBase(MIR_BinaryAcc.getValue(inst)));
14915 }
14916 }
14917 }
14918 }
14919 }
14920 }
14921
14922 } else {
14923 if (isImm(MIR_BinaryAcc.getValue(inst))) {
14924 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14925 emitIMUL2_Reg_Imm(
14926 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14927 getImm(MIR_BinaryAcc.getValue(inst)));
14928
14929 } else {
14930 if (isGPR_Reg(MIR_BinaryAcc.getValue(inst))) {
14931 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14932 emitIMUL2_Reg_Reg(
14933 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14934 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
14935
14936 } else {
14937 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
14938 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14939 emitIMUL2_Reg_Abs(
14940 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14941 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
14942
14943 } else {
14944 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
14945 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14946 emitIMUL2_Reg_RegDisp(
14947 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14948 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
14949
14950 } else {
14951 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
14952 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14953 emitIMUL2_Reg_RegOff(
14954 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14955 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
14956
14957 } else {
14958 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
14959 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14960 emitIMUL2_Reg_RegIdx(
14961 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14962 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
14963
14964 } else {
14965 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14966 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14967 emitIMUL2_Reg_RegInd(
14968 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
14969 getBase(MIR_BinaryAcc.getValue(inst)));
14970 }
14971 }
14972 }
14973 }
14974 }
14975 }
14976 }
14977 }
14978
14979 /**
14980 * Emit the given instruction, assuming that
14981 * it is a MIR_BinaryAcc instruction
14982 * and has a FSUBRP operator
14983 *
14984 * @param inst the instruction to assemble
14985 */
14986 private void doFSUBRP(Instruction inst) {
14987 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14988 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
14989 emitFSUBRP_Reg_Reg(
14990 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
14991 getFPR_Reg(MIR_BinaryAcc.getValue(inst)));
14992 }
14993
14994 /**
14995 * Emit the given instruction, assuming that
14996 * it is a MIR_Empty instruction
14997 * and has a FNINIT operator
14998 *
14999 * @param inst the instruction to assemble
15000 */
15001 private void doFNINIT(Instruction inst) {
15002 emitFNINIT();
15003 }
15004
15005 /**
15006 * Emit the given instruction, assuming that
15007 * it is a MIR_Compare instruction
15008 * and has a FUCOMIP operator
15009 *
15010 * @param inst the instruction to assemble
15011 */
15012 private void doFUCOMIP(Instruction inst) {
15013 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Compare.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15014 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Compare.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15015 emitFUCOMIP_Reg_Reg(
15016 getFPR_Reg(MIR_Compare.getVal1(inst)),
15017 getFPR_Reg(MIR_Compare.getVal2(inst)));
15018 }
15019
15020 /**
15021 * Emit the given instruction, assuming that
15022 * it is a MIR_UnaryNoRes instruction
15023 * and has a FSTCW operator
15024 *
15025 * @param inst the instruction to assemble
15026 */
15027 private void doFSTCW(Instruction inst) {
15028 if (isAbs(MIR_UnaryNoRes.getVal(inst))) {
15029 emitFSTCW_Abs(
15030 getDisp(MIR_UnaryNoRes.getVal(inst)).toWord().toAddress());
15031
15032 } else {
15033 if (isRegDisp(MIR_UnaryNoRes.getVal(inst))) {
15034 emitFSTCW_RegDisp(
15035 getBase(MIR_UnaryNoRes.getVal(inst)), getDisp(MIR_UnaryNoRes.getVal(inst)));
15036
15037 } else {
15038 if (isRegOff(MIR_UnaryNoRes.getVal(inst))) {
15039 emitFSTCW_RegOff(
15040 getIndex(MIR_UnaryNoRes.getVal(inst)), getScale(MIR_UnaryNoRes.getVal(inst)), getDisp(MIR_UnaryNoRes.getVal(inst)));
15041
15042 } else {
15043 if (isRegIdx(MIR_UnaryNoRes.getVal(inst))) {
15044 emitFSTCW_RegIdx(
15045 getBase(MIR_UnaryNoRes.getVal(inst)), getIndex(MIR_UnaryNoRes.getVal(inst)), getScale(MIR_UnaryNoRes.getVal(inst)), getDisp(MIR_UnaryNoRes.getVal(inst)));
15046
15047 } else {
15048 if (VM.VerifyAssertions && !isRegInd(MIR_UnaryNoRes.getVal(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15049 emitFSTCW_RegInd(
15050 getBase(MIR_UnaryNoRes.getVal(inst)));
15051 }
15052 }
15053 }
15054 }
15055 }
15056
15057 /**
15058 * Emit the given instruction, assuming that
15059 * it is a MIR_Move instruction
15060 * and has a MOVLPS operator
15061 *
15062 * @param inst the instruction to assemble
15063 */
15064 private void doMOVLPS(Instruction inst) {
15065 if (isXMM_Reg(MIR_Move.getResult(inst))) {
15066 if (isXMM_Reg(MIR_Move.getValue(inst))) {
15067 emitMOVLPS_Reg_Reg(
15068 getXMM_Reg(MIR_Move.getResult(inst)),
15069 getXMM_Reg(MIR_Move.getValue(inst)));
15070
15071 } else {
15072 if (isAbs(MIR_Move.getValue(inst))) {
15073 emitMOVLPS_Reg_Abs(
15074 getXMM_Reg(MIR_Move.getResult(inst)),
15075 getDisp(MIR_Move.getValue(inst)).toWord().toAddress());
15076
15077 } else {
15078 if (isRegDisp(MIR_Move.getValue(inst))) {
15079 emitMOVLPS_Reg_RegDisp(
15080 getXMM_Reg(MIR_Move.getResult(inst)),
15081 getBase(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
15082
15083 } else {
15084 if (isRegOff(MIR_Move.getValue(inst))) {
15085 emitMOVLPS_Reg_RegOff(
15086 getXMM_Reg(MIR_Move.getResult(inst)),
15087 getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
15088
15089 } else {
15090 if (isRegIdx(MIR_Move.getValue(inst))) {
15091 emitMOVLPS_Reg_RegIdx(
15092 getXMM_Reg(MIR_Move.getResult(inst)),
15093 getBase(MIR_Move.getValue(inst)), getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
15094
15095 } else {
15096 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15097 emitMOVLPS_Reg_RegInd(
15098 getXMM_Reg(MIR_Move.getResult(inst)),
15099 getBase(MIR_Move.getValue(inst)));
15100 }
15101 }
15102 }
15103 }
15104 }
15105
15106 } else {
15107 if (isAbs(MIR_Move.getResult(inst))) {
15108 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15109 emitMOVLPS_Abs_Reg(
15110 getDisp(MIR_Move.getResult(inst)).toWord().toAddress(),
15111 getXMM_Reg(MIR_Move.getValue(inst)));
15112
15113 } else {
15114 if (isRegDisp(MIR_Move.getResult(inst))) {
15115 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15116 emitMOVLPS_RegDisp_Reg(
15117 getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
15118 getXMM_Reg(MIR_Move.getValue(inst)));
15119
15120 } else {
15121 if (isRegOff(MIR_Move.getResult(inst))) {
15122 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15123 emitMOVLPS_RegOff_Reg(
15124 getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
15125 getXMM_Reg(MIR_Move.getValue(inst)));
15126
15127 } else {
15128 if (isRegIdx(MIR_Move.getResult(inst))) {
15129 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15130 emitMOVLPS_RegIdx_Reg(
15131 getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
15132 getXMM_Reg(MIR_Move.getValue(inst)));
15133
15134 } else {
15135 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15136 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15137 emitMOVLPS_RegInd_Reg(
15138 getBase(MIR_Move.getResult(inst)),
15139 getXMM_Reg(MIR_Move.getValue(inst)));
15140 }
15141 }
15142 }
15143 }
15144 }
15145 }
15146
15147 /**
15148 * Emit the given instruction, assuming that
15149 * it is a MIR_Nullary instruction
15150 * and has a FLDZ operator
15151 *
15152 * @param inst the instruction to assemble
15153 */
15154 private void doFLDZ(Instruction inst) {
15155 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Nullary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15156 emitFLDZ_Reg(
15157 getFPR_Reg(MIR_Nullary.getResult(inst)));
15158 }
15159
15160 /**
15161 * Emit the given instruction, assuming that
15162 * it is a MIR_Move instruction
15163 * and has a MOVQ operator
15164 *
15165 * @param inst the instruction to assemble
15166 */
15167 private void doMOVQ(Instruction inst) {
15168 if (isMM_Reg(MIR_Move.getResult(inst))) {
15169 if (isMM_Reg(MIR_Move.getValue(inst))) {
15170 emitMOVQ_Reg_Reg(
15171 getMM_Reg(MIR_Move.getResult(inst)),
15172 getMM_Reg(MIR_Move.getValue(inst)));
15173
15174 } else {
15175 if (isAbs(MIR_Move.getValue(inst))) {
15176 emitMOVQ_Reg_Abs(
15177 getMM_Reg(MIR_Move.getResult(inst)),
15178 getDisp(MIR_Move.getValue(inst)).toWord().toAddress());
15179
15180 } else {
15181 if (isRegDisp(MIR_Move.getValue(inst))) {
15182 emitMOVQ_Reg_RegDisp(
15183 getMM_Reg(MIR_Move.getResult(inst)),
15184 getBase(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
15185
15186 } else {
15187 if (isRegOff(MIR_Move.getValue(inst))) {
15188 emitMOVQ_Reg_RegOff(
15189 getMM_Reg(MIR_Move.getResult(inst)),
15190 getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
15191
15192 } else {
15193 if (isRegIdx(MIR_Move.getValue(inst))) {
15194 emitMOVQ_Reg_RegIdx(
15195 getMM_Reg(MIR_Move.getResult(inst)),
15196 getBase(MIR_Move.getValue(inst)), getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
15197
15198 } else {
15199 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15200 emitMOVQ_Reg_RegInd(
15201 getMM_Reg(MIR_Move.getResult(inst)),
15202 getBase(MIR_Move.getValue(inst)));
15203 }
15204 }
15205 }
15206 }
15207 }
15208
15209 } else {
15210 if (isXMM_Reg(MIR_Move.getResult(inst))) {
15211 if (isXMM_Reg(MIR_Move.getValue(inst))) {
15212 emitMOVQ_Reg_Reg(
15213 getXMM_Reg(MIR_Move.getResult(inst)),
15214 getXMM_Reg(MIR_Move.getValue(inst)));
15215
15216 } else {
15217 if (isAbs(MIR_Move.getValue(inst))) {
15218 emitMOVQ_Reg_Abs(
15219 getXMM_Reg(MIR_Move.getResult(inst)),
15220 getDisp(MIR_Move.getValue(inst)).toWord().toAddress());
15221
15222 } else {
15223 if (isRegDisp(MIR_Move.getValue(inst))) {
15224 emitMOVQ_Reg_RegDisp(
15225 getXMM_Reg(MIR_Move.getResult(inst)),
15226 getBase(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
15227
15228 } else {
15229 if (isRegOff(MIR_Move.getValue(inst))) {
15230 emitMOVQ_Reg_RegOff(
15231 getXMM_Reg(MIR_Move.getResult(inst)),
15232 getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
15233
15234 } else {
15235 if (isRegIdx(MIR_Move.getValue(inst))) {
15236 emitMOVQ_Reg_RegIdx(
15237 getXMM_Reg(MIR_Move.getResult(inst)),
15238 getBase(MIR_Move.getValue(inst)), getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
15239
15240 } else {
15241 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15242 emitMOVQ_Reg_RegInd(
15243 getXMM_Reg(MIR_Move.getResult(inst)),
15244 getBase(MIR_Move.getValue(inst)));
15245 }
15246 }
15247 }
15248 }
15249 }
15250
15251 } else {
15252 if (isMM_Reg(MIR_Move.getValue(inst))) {
15253 if (isAbs(MIR_Move.getResult(inst))) {
15254 emitMOVQ_Abs_Reg(
15255 getDisp(MIR_Move.getResult(inst)).toWord().toAddress(),
15256 getMM_Reg(MIR_Move.getValue(inst)));
15257
15258 } else {
15259 if (isRegDisp(MIR_Move.getResult(inst))) {
15260 emitMOVQ_RegDisp_Reg(
15261 getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
15262 getMM_Reg(MIR_Move.getValue(inst)));
15263
15264 } else {
15265 if (isRegOff(MIR_Move.getResult(inst))) {
15266 emitMOVQ_RegOff_Reg(
15267 getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
15268 getMM_Reg(MIR_Move.getValue(inst)));
15269
15270 } else {
15271 if (isRegIdx(MIR_Move.getResult(inst))) {
15272 emitMOVQ_RegIdx_Reg(
15273 getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
15274 getMM_Reg(MIR_Move.getValue(inst)));
15275
15276 } else {
15277 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15278 emitMOVQ_RegInd_Reg(
15279 getBase(MIR_Move.getResult(inst)),
15280 getMM_Reg(MIR_Move.getValue(inst)));
15281 }
15282 }
15283 }
15284 }
15285
15286 } else {
15287 if (isAbs(MIR_Move.getResult(inst))) {
15288 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15289 emitMOVQ_Abs_Reg(
15290 getDisp(MIR_Move.getResult(inst)).toWord().toAddress(),
15291 getXMM_Reg(MIR_Move.getValue(inst)));
15292
15293 } else {
15294 if (isRegDisp(MIR_Move.getResult(inst))) {
15295 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15296 emitMOVQ_RegDisp_Reg(
15297 getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
15298 getXMM_Reg(MIR_Move.getValue(inst)));
15299
15300 } else {
15301 if (isRegOff(MIR_Move.getResult(inst))) {
15302 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15303 emitMOVQ_RegOff_Reg(
15304 getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
15305 getXMM_Reg(MIR_Move.getValue(inst)));
15306
15307 } else {
15308 if (isRegIdx(MIR_Move.getResult(inst))) {
15309 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15310 emitMOVQ_RegIdx_Reg(
15311 getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
15312 getXMM_Reg(MIR_Move.getValue(inst)));
15313
15314 } else {
15315 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15316 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15317 emitMOVQ_RegInd_Reg(
15318 getBase(MIR_Move.getResult(inst)),
15319 getXMM_Reg(MIR_Move.getValue(inst)));
15320 }
15321 }
15322 }
15323 }
15324 }
15325 }
15326 }
15327 }
15328
15329 /**
15330 * Emit the given instruction, assuming that
15331 * it is a MIR_BinaryAcc instruction
15332 * and has a FIADD operator
15333 *
15334 * @param inst the instruction to assemble
15335 */
15336 private void doFIADD(Instruction inst) {
15337 if (isWord(inst)) {
15338 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
15339 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15340 emitFIADD_Reg_Abs_Word(
15341 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
15342 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
15343
15344 } else {
15345 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
15346 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15347 emitFIADD_Reg_RegDisp_Word(
15348 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
15349 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
15350
15351 } else {
15352 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
15353 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15354 emitFIADD_Reg_RegOff_Word(
15355 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
15356 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
15357
15358 } else {
15359 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
15360 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15361 emitFIADD_Reg_RegIdx_Word(
15362 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
15363 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
15364
15365 } else {
15366 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15367 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15368 emitFIADD_Reg_RegInd_Word(
15369 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
15370 getBase(MIR_BinaryAcc.getValue(inst)));
15371 }
15372 }
15373 }
15374 }
15375
15376 } else {
15377 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
15378 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15379 emitFIADD_Reg_Abs(
15380 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
15381 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
15382
15383 } else {
15384 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
15385 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15386 emitFIADD_Reg_RegDisp(
15387 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
15388 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
15389
15390 } else {
15391 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
15392 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15393 emitFIADD_Reg_RegOff(
15394 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
15395 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
15396
15397 } else {
15398 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
15399 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15400 emitFIADD_Reg_RegIdx(
15401 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
15402 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
15403
15404 } else {
15405 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15406 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15407 emitFIADD_Reg_RegInd(
15408 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
15409 getBase(MIR_BinaryAcc.getValue(inst)));
15410 }
15411 }
15412 }
15413 }
15414 }
15415 }
15416
15417 /**
15418 * Emit the given instruction, assuming that
15419 * it is a MIR_UnaryAcc instruction
15420 * and has a DEC operator
15421 *
15422 * @param inst the instruction to assemble
15423 */
15424 private void doDEC(Instruction inst) {
15425 if (isByte(inst)) {
15426 if (isGPR_Reg(MIR_UnaryAcc.getResult(inst))) {
15427 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_UnaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
15428 emitDEC_Reg_Byte(
15429 getGPR_Reg(MIR_UnaryAcc.getResult(inst)));
15430
15431 } else {
15432 if (isAbs(MIR_UnaryAcc.getResult(inst))) {
15433 emitDEC_Abs_Byte(
15434 getDisp(MIR_UnaryAcc.getResult(inst)).toWord().toAddress());
15435
15436 } else {
15437 if (isRegDisp(MIR_UnaryAcc.getResult(inst))) {
15438 emitDEC_RegDisp_Byte(
15439 getBase(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
15440
15441 } else {
15442 if (isRegOff(MIR_UnaryAcc.getResult(inst))) {
15443 emitDEC_RegOff_Byte(
15444 getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
15445
15446 } else {
15447 if (isRegIdx(MIR_UnaryAcc.getResult(inst))) {
15448 emitDEC_RegIdx_Byte(
15449 getBase(MIR_UnaryAcc.getResult(inst)), getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
15450
15451 } else {
15452 if (VM.VerifyAssertions && !isRegInd(MIR_UnaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15453 emitDEC_RegInd_Byte(
15454 getBase(MIR_UnaryAcc.getResult(inst)));
15455 }
15456 }
15457 }
15458 }
15459 }
15460
15461 } else {
15462 if (isWord(inst)) {
15463 if (isGPR_Reg(MIR_UnaryAcc.getResult(inst))) {
15464 emitDEC_Reg_Word(
15465 getGPR_Reg(MIR_UnaryAcc.getResult(inst)));
15466
15467 } else {
15468 if (isAbs(MIR_UnaryAcc.getResult(inst))) {
15469 emitDEC_Abs_Word(
15470 getDisp(MIR_UnaryAcc.getResult(inst)).toWord().toAddress());
15471
15472 } else {
15473 if (isRegDisp(MIR_UnaryAcc.getResult(inst))) {
15474 emitDEC_RegDisp_Word(
15475 getBase(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
15476
15477 } else {
15478 if (isRegOff(MIR_UnaryAcc.getResult(inst))) {
15479 emitDEC_RegOff_Word(
15480 getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
15481
15482 } else {
15483 if (isRegIdx(MIR_UnaryAcc.getResult(inst))) {
15484 emitDEC_RegIdx_Word(
15485 getBase(MIR_UnaryAcc.getResult(inst)), getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
15486
15487 } else {
15488 if (VM.VerifyAssertions && !isRegInd(MIR_UnaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15489 emitDEC_RegInd_Word(
15490 getBase(MIR_UnaryAcc.getResult(inst)));
15491 }
15492 }
15493 }
15494 }
15495 }
15496
15497 } else {
15498 if (isQuad(inst)) {
15499 if (isGPR_Reg(MIR_UnaryAcc.getResult(inst))) {
15500 emitDEC_Reg_Quad(
15501 getGPR_Reg(MIR_UnaryAcc.getResult(inst)));
15502
15503 } else {
15504 if (isAbs(MIR_UnaryAcc.getResult(inst))) {
15505 emitDEC_Abs_Quad(
15506 getDisp(MIR_UnaryAcc.getResult(inst)).toWord().toAddress());
15507
15508 } else {
15509 if (isRegDisp(MIR_UnaryAcc.getResult(inst))) {
15510 emitDEC_RegDisp_Quad(
15511 getBase(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
15512
15513 } else {
15514 if (isRegOff(MIR_UnaryAcc.getResult(inst))) {
15515 emitDEC_RegOff_Quad(
15516 getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
15517
15518 } else {
15519 if (isRegIdx(MIR_UnaryAcc.getResult(inst))) {
15520 emitDEC_RegIdx_Quad(
15521 getBase(MIR_UnaryAcc.getResult(inst)), getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
15522
15523 } else {
15524 if (VM.VerifyAssertions && !isRegInd(MIR_UnaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15525 emitDEC_RegInd_Quad(
15526 getBase(MIR_UnaryAcc.getResult(inst)));
15527 }
15528 }
15529 }
15530 }
15531 }
15532
15533 } else {
15534 if (isGPR_Reg(MIR_UnaryAcc.getResult(inst))) {
15535 emitDEC_Reg(
15536 getGPR_Reg(MIR_UnaryAcc.getResult(inst)));
15537
15538 } else {
15539 if (isAbs(MIR_UnaryAcc.getResult(inst))) {
15540 emitDEC_Abs(
15541 getDisp(MIR_UnaryAcc.getResult(inst)).toWord().toAddress());
15542
15543 } else {
15544 if (isRegDisp(MIR_UnaryAcc.getResult(inst))) {
15545 emitDEC_RegDisp(
15546 getBase(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
15547
15548 } else {
15549 if (isRegOff(MIR_UnaryAcc.getResult(inst))) {
15550 emitDEC_RegOff(
15551 getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
15552
15553 } else {
15554 if (isRegIdx(MIR_UnaryAcc.getResult(inst))) {
15555 emitDEC_RegIdx(
15556 getBase(MIR_UnaryAcc.getResult(inst)), getIndex(MIR_UnaryAcc.getResult(inst)), getScale(MIR_UnaryAcc.getResult(inst)), getDisp(MIR_UnaryAcc.getResult(inst)));
15557
15558 } else {
15559 if (VM.VerifyAssertions && !isRegInd(MIR_UnaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15560 emitDEC_RegInd(
15561 getBase(MIR_UnaryAcc.getResult(inst)));
15562 }
15563 }
15564 }
15565 }
15566 }
15567 }
15568 }
15569 }
15570 }
15571
15572 /**
15573 * Emit the given instruction, assuming that
15574 * it is a MIR_BinaryAcc instruction
15575 * and has a OR operator
15576 *
15577 * @param inst the instruction to assemble
15578 */
15579 private void doOR(Instruction inst) {
15580 if (isGPR_Reg(MIR_BinaryAcc.getResult(inst))) {
15581 if (isByte(inst)) {
15582 if (isImm(MIR_BinaryAcc.getValue(inst))) {
15583 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
15584 emitOR_Reg_Imm_Byte(
15585 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
15586 getImm(MIR_BinaryAcc.getValue(inst)));
15587
15588 } else {
15589 if (isGPR_Reg(MIR_BinaryAcc.getValue(inst))) {
15590 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
15591 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
15592 emitOR_Reg_Reg_Byte(
15593 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
15594 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
15595
15596 } else {
15597 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
15598 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
15599 emitOR_Reg_Abs_Byte(
15600 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
15601 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
15602
15603 } else {
15604 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
15605 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
15606 emitOR_Reg_RegDisp_Byte(
15607 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
15608 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
15609
15610 } else {
15611 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
15612 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
15613 emitOR_Reg_RegOff_Byte(
15614 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
15615 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
15616
15617 } else {
15618 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
15619 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
15620 emitOR_Reg_RegIdx_Byte(
15621 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
15622 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
15623
15624 } else {
15625 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15626 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
15627 emitOR_Reg_RegInd_Byte(
15628 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
15629 getBase(MIR_BinaryAcc.getValue(inst)));
15630 }
15631 }
15632 }
15633 }
15634 }
15635 }
15636
15637 } else {
15638 if (isWord(inst)) {
15639 if (isImm(MIR_BinaryAcc.getValue(inst))) {
15640 emitOR_Reg_Imm_Word(
15641 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
15642 getImm(MIR_BinaryAcc.getValue(inst)));
15643
15644 } else {
15645 if (isGPR_Reg(MIR_BinaryAcc.getValue(inst))) {
15646 emitOR_Reg_Reg_Word(
15647 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
15648 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
15649
15650 } else {
15651 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
15652 emitOR_Reg_Abs_Word(
15653 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
15654 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
15655
15656 } else {
15657 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
15658 emitOR_Reg_RegDisp_Word(
15659 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
15660 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
15661
15662 } else {
15663 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
15664 emitOR_Reg_RegOff_Word(
15665 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
15666 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
15667
15668 } else {
15669 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
15670 emitOR_Reg_RegIdx_Word(
15671 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
15672 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
15673
15674 } else {
15675 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15676 emitOR_Reg_RegInd_Word(
15677 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
15678 getBase(MIR_BinaryAcc.getValue(inst)));
15679 }
15680 }
15681 }
15682 }
15683 }
15684 }
15685
15686 } else {
15687 if (isQuad(inst)) {
15688 if (isImm(MIR_BinaryAcc.getValue(inst))) {
15689 emitOR_Reg_Imm_Quad(
15690 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
15691 getImm(MIR_BinaryAcc.getValue(inst)));
15692
15693 } else {
15694 if (isGPR_Reg(MIR_BinaryAcc.getValue(inst))) {
15695 emitOR_Reg_Reg_Quad(
15696 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
15697 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
15698
15699 } else {
15700 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
15701 emitOR_Reg_Abs_Quad(
15702 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
15703 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
15704
15705 } else {
15706 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
15707 emitOR_Reg_RegDisp_Quad(
15708 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
15709 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
15710
15711 } else {
15712 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
15713 emitOR_Reg_RegOff_Quad(
15714 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
15715 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
15716
15717 } else {
15718 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
15719 emitOR_Reg_RegIdx_Quad(
15720 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
15721 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
15722
15723 } else {
15724 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15725 emitOR_Reg_RegInd_Quad(
15726 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
15727 getBase(MIR_BinaryAcc.getValue(inst)));
15728 }
15729 }
15730 }
15731 }
15732 }
15733 }
15734
15735 } else {
15736 if (isImm(MIR_BinaryAcc.getValue(inst))) {
15737 emitOR_Reg_Imm(
15738 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
15739 getImm(MIR_BinaryAcc.getValue(inst)));
15740
15741 } else {
15742 if (isGPR_Reg(MIR_BinaryAcc.getValue(inst))) {
15743 emitOR_Reg_Reg(
15744 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
15745 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
15746
15747 } else {
15748 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
15749 emitOR_Reg_Abs(
15750 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
15751 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
15752
15753 } else {
15754 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
15755 emitOR_Reg_RegDisp(
15756 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
15757 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
15758
15759 } else {
15760 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
15761 emitOR_Reg_RegOff(
15762 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
15763 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
15764
15765 } else {
15766 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
15767 emitOR_Reg_RegIdx(
15768 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
15769 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
15770
15771 } else {
15772 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15773 emitOR_Reg_RegInd(
15774 getGPR_Reg(MIR_BinaryAcc.getResult(inst)),
15775 getBase(MIR_BinaryAcc.getValue(inst)));
15776 }
15777 }
15778 }
15779 }
15780 }
15781 }
15782 }
15783 }
15784 }
15785
15786 } else {
15787 if (isImm(MIR_BinaryAcc.getValue(inst))) {
15788 if (isByte(inst)) {
15789 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
15790 emitOR_Abs_Imm_Byte(
15791 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
15792 getImm(MIR_BinaryAcc.getValue(inst)));
15793
15794 } else {
15795 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
15796 emitOR_RegDisp_Imm_Byte(
15797 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
15798 getImm(MIR_BinaryAcc.getValue(inst)));
15799
15800 } else {
15801 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
15802 emitOR_RegOff_Imm_Byte(
15803 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
15804 getImm(MIR_BinaryAcc.getValue(inst)));
15805
15806 } else {
15807 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
15808 emitOR_RegIdx_Imm_Byte(
15809 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
15810 getImm(MIR_BinaryAcc.getValue(inst)));
15811
15812 } else {
15813 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15814 emitOR_RegInd_Imm_Byte(
15815 getBase(MIR_BinaryAcc.getResult(inst)),
15816 getImm(MIR_BinaryAcc.getValue(inst)));
15817 }
15818 }
15819 }
15820 }
15821
15822 } else {
15823 if (isWord(inst)) {
15824 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
15825 emitOR_Abs_Imm_Word(
15826 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
15827 getImm(MIR_BinaryAcc.getValue(inst)));
15828
15829 } else {
15830 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
15831 emitOR_RegDisp_Imm_Word(
15832 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
15833 getImm(MIR_BinaryAcc.getValue(inst)));
15834
15835 } else {
15836 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
15837 emitOR_RegOff_Imm_Word(
15838 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
15839 getImm(MIR_BinaryAcc.getValue(inst)));
15840
15841 } else {
15842 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
15843 emitOR_RegIdx_Imm_Word(
15844 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
15845 getImm(MIR_BinaryAcc.getValue(inst)));
15846
15847 } else {
15848 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15849 emitOR_RegInd_Imm_Word(
15850 getBase(MIR_BinaryAcc.getResult(inst)),
15851 getImm(MIR_BinaryAcc.getValue(inst)));
15852 }
15853 }
15854 }
15855 }
15856
15857 } else {
15858 if (isQuad(inst)) {
15859 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
15860 emitOR_Abs_Imm_Quad(
15861 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
15862 getImm(MIR_BinaryAcc.getValue(inst)));
15863
15864 } else {
15865 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
15866 emitOR_RegDisp_Imm_Quad(
15867 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
15868 getImm(MIR_BinaryAcc.getValue(inst)));
15869
15870 } else {
15871 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
15872 emitOR_RegOff_Imm_Quad(
15873 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
15874 getImm(MIR_BinaryAcc.getValue(inst)));
15875
15876 } else {
15877 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
15878 emitOR_RegIdx_Imm_Quad(
15879 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
15880 getImm(MIR_BinaryAcc.getValue(inst)));
15881
15882 } else {
15883 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15884 emitOR_RegInd_Imm_Quad(
15885 getBase(MIR_BinaryAcc.getResult(inst)),
15886 getImm(MIR_BinaryAcc.getValue(inst)));
15887 }
15888 }
15889 }
15890 }
15891
15892 } else {
15893 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
15894 emitOR_Abs_Imm(
15895 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
15896 getImm(MIR_BinaryAcc.getValue(inst)));
15897
15898 } else {
15899 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
15900 emitOR_RegDisp_Imm(
15901 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
15902 getImm(MIR_BinaryAcc.getValue(inst)));
15903
15904 } else {
15905 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
15906 emitOR_RegOff_Imm(
15907 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
15908 getImm(MIR_BinaryAcc.getValue(inst)));
15909
15910 } else {
15911 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
15912 emitOR_RegIdx_Imm(
15913 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
15914 getImm(MIR_BinaryAcc.getValue(inst)));
15915
15916 } else {
15917 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15918 emitOR_RegInd_Imm(
15919 getBase(MIR_BinaryAcc.getResult(inst)),
15920 getImm(MIR_BinaryAcc.getValue(inst)));
15921 }
15922 }
15923 }
15924 }
15925 }
15926 }
15927 }
15928
15929 } else {
15930 if (isByte(inst)) {
15931 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
15932 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15933 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
15934 emitOR_Abs_Reg_Byte(
15935 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
15936 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
15937
15938 } else {
15939 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
15940 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15941 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
15942 emitOR_RegDisp_Reg_Byte(
15943 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
15944 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
15945
15946 } else {
15947 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
15948 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15949 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
15950 emitOR_RegOff_Reg_Byte(
15951 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
15952 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
15953
15954 } else {
15955 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
15956 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15957 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
15958 emitOR_RegIdx_Reg_Byte(
15959 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
15960 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
15961
15962 } else {
15963 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15964 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15965 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_BinaryAcc.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
15966 emitOR_RegInd_Reg_Byte(
15967 getBase(MIR_BinaryAcc.getResult(inst)),
15968 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
15969 }
15970 }
15971 }
15972 }
15973
15974 } else {
15975 if (isWord(inst)) {
15976 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
15977 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15978 emitOR_Abs_Reg_Word(
15979 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
15980 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
15981
15982 } else {
15983 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
15984 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15985 emitOR_RegDisp_Reg_Word(
15986 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
15987 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
15988
15989 } else {
15990 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
15991 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15992 emitOR_RegOff_Reg_Word(
15993 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
15994 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
15995
15996 } else {
15997 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
15998 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
15999 emitOR_RegIdx_Reg_Word(
16000 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
16001 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
16002
16003 } else {
16004 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16005 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16006 emitOR_RegInd_Reg_Word(
16007 getBase(MIR_BinaryAcc.getResult(inst)),
16008 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
16009 }
16010 }
16011 }
16012 }
16013
16014 } else {
16015 if (isQuad(inst)) {
16016 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
16017 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16018 emitOR_Abs_Reg_Quad(
16019 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
16020 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
16021
16022 } else {
16023 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
16024 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16025 emitOR_RegDisp_Reg_Quad(
16026 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
16027 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
16028
16029 } else {
16030 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
16031 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16032 emitOR_RegOff_Reg_Quad(
16033 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
16034 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
16035
16036 } else {
16037 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
16038 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16039 emitOR_RegIdx_Reg_Quad(
16040 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
16041 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
16042
16043 } else {
16044 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16045 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16046 emitOR_RegInd_Reg_Quad(
16047 getBase(MIR_BinaryAcc.getResult(inst)),
16048 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
16049 }
16050 }
16051 }
16052 }
16053
16054 } else {
16055 if (isAbs(MIR_BinaryAcc.getResult(inst))) {
16056 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16057 emitOR_Abs_Reg(
16058 getDisp(MIR_BinaryAcc.getResult(inst)).toWord().toAddress(),
16059 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
16060
16061 } else {
16062 if (isRegDisp(MIR_BinaryAcc.getResult(inst))) {
16063 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16064 emitOR_RegDisp_Reg(
16065 getBase(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
16066 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
16067
16068 } else {
16069 if (isRegOff(MIR_BinaryAcc.getResult(inst))) {
16070 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16071 emitOR_RegOff_Reg(
16072 getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
16073 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
16074
16075 } else {
16076 if (isRegIdx(MIR_BinaryAcc.getResult(inst))) {
16077 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16078 emitOR_RegIdx_Reg(
16079 getBase(MIR_BinaryAcc.getResult(inst)), getIndex(MIR_BinaryAcc.getResult(inst)), getScale(MIR_BinaryAcc.getResult(inst)), getDisp(MIR_BinaryAcc.getResult(inst)),
16080 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
16081
16082 } else {
16083 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16084 if (VM.VerifyAssertions && !isGPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16085 emitOR_RegInd_Reg(
16086 getBase(MIR_BinaryAcc.getResult(inst)),
16087 getGPR_Reg(MIR_BinaryAcc.getValue(inst)));
16088 }
16089 }
16090 }
16091 }
16092 }
16093 }
16094 }
16095 }
16096 }
16097 }
16098
16099 /**
16100 * Emit the given instruction, assuming that
16101 * it is a MIR_Empty instruction
16102 * and has a MFENCE operator
16103 *
16104 * @param inst the instruction to assemble
16105 */
16106 private void doMFENCE(Instruction inst) {
16107 emitMFENCE();
16108 }
16109
16110 /**
16111 * Emit the given instruction, assuming that
16112 * it is a MIR_CacheOp instruction
16113 * and has a PREFETCHNTA operator
16114 *
16115 * @param inst the instruction to assemble
16116 */
16117 private void doPREFETCHNTA(Instruction inst) {
16118 if (VM.VerifyAssertions && !isGPR_Reg(MIR_CacheOp.getAddress(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16119 emitPREFETCHNTA_Reg(
16120 getGPR_Reg(MIR_CacheOp.getAddress(inst)));
16121 }
16122
16123 /**
16124 * Emit the given instruction, assuming that
16125 * it is a MIR_Lea instruction
16126 * and has a LEA operator
16127 *
16128 * @param inst the instruction to assemble
16129 */
16130 private void doLEA(Instruction inst) {
16131 if (isQuad(inst)) {
16132 if (isAbs(MIR_Lea.getValue(inst))) {
16133 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Lea.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16134 emitLEA_Reg_Abs_Quad(
16135 getGPR_Reg(MIR_Lea.getResult(inst)),
16136 getDisp(MIR_Lea.getValue(inst)).toWord().toAddress());
16137
16138 } else {
16139 if (isRegDisp(MIR_Lea.getValue(inst))) {
16140 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Lea.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16141 emitLEA_Reg_RegDisp_Quad(
16142 getGPR_Reg(MIR_Lea.getResult(inst)),
16143 getBase(MIR_Lea.getValue(inst)), getDisp(MIR_Lea.getValue(inst)));
16144
16145 } else {
16146 if (isRegOff(MIR_Lea.getValue(inst))) {
16147 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Lea.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16148 emitLEA_Reg_RegOff_Quad(
16149 getGPR_Reg(MIR_Lea.getResult(inst)),
16150 getIndex(MIR_Lea.getValue(inst)), getScale(MIR_Lea.getValue(inst)), getDisp(MIR_Lea.getValue(inst)));
16151
16152 } else {
16153 if (isRegIdx(MIR_Lea.getValue(inst))) {
16154 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Lea.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16155 emitLEA_Reg_RegIdx_Quad(
16156 getGPR_Reg(MIR_Lea.getResult(inst)),
16157 getBase(MIR_Lea.getValue(inst)), getIndex(MIR_Lea.getValue(inst)), getScale(MIR_Lea.getValue(inst)), getDisp(MIR_Lea.getValue(inst)));
16158
16159 } else {
16160 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Lea.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16161 if (VM.VerifyAssertions && !isRegInd(MIR_Lea.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16162 emitLEA_Reg_RegInd_Quad(
16163 getGPR_Reg(MIR_Lea.getResult(inst)),
16164 getBase(MIR_Lea.getValue(inst)));
16165 }
16166 }
16167 }
16168 }
16169
16170 } else {
16171 if (isAbs(MIR_Lea.getValue(inst))) {
16172 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Lea.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16173 emitLEA_Reg_Abs(
16174 getGPR_Reg(MIR_Lea.getResult(inst)),
16175 getDisp(MIR_Lea.getValue(inst)).toWord().toAddress());
16176
16177 } else {
16178 if (isRegDisp(MIR_Lea.getValue(inst))) {
16179 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Lea.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16180 emitLEA_Reg_RegDisp(
16181 getGPR_Reg(MIR_Lea.getResult(inst)),
16182 getBase(MIR_Lea.getValue(inst)), getDisp(MIR_Lea.getValue(inst)));
16183
16184 } else {
16185 if (isRegOff(MIR_Lea.getValue(inst))) {
16186 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Lea.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16187 emitLEA_Reg_RegOff(
16188 getGPR_Reg(MIR_Lea.getResult(inst)),
16189 getIndex(MIR_Lea.getValue(inst)), getScale(MIR_Lea.getValue(inst)), getDisp(MIR_Lea.getValue(inst)));
16190
16191 } else {
16192 if (isRegIdx(MIR_Lea.getValue(inst))) {
16193 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Lea.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16194 emitLEA_Reg_RegIdx(
16195 getGPR_Reg(MIR_Lea.getResult(inst)),
16196 getBase(MIR_Lea.getValue(inst)), getIndex(MIR_Lea.getValue(inst)), getScale(MIR_Lea.getValue(inst)), getDisp(MIR_Lea.getValue(inst)));
16197
16198 } else {
16199 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Lea.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16200 if (VM.VerifyAssertions && !isRegInd(MIR_Lea.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16201 emitLEA_Reg_RegInd(
16202 getGPR_Reg(MIR_Lea.getResult(inst)),
16203 getBase(MIR_Lea.getValue(inst)));
16204 }
16205 }
16206 }
16207 }
16208 }
16209 }
16210
16211 /**
16212 * Emit the given instruction, assuming that
16213 * it is a MIR_BinaryAcc instruction
16214 * and has a FDIVRP operator
16215 *
16216 * @param inst the instruction to assemble
16217 */
16218 private void doFDIVRP(Instruction inst) {
16219 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16220 if (VM.VerifyAssertions && !isFPR_Reg(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16221 emitFDIVRP_Reg_Reg(
16222 getFPR_Reg(MIR_BinaryAcc.getResult(inst)),
16223 getFPR_Reg(MIR_BinaryAcc.getValue(inst)));
16224 }
16225
16226 /**
16227 * Emit the given instruction, assuming that
16228 * it is a MIR_BinaryAcc instruction
16229 * and has a ANDPD operator
16230 *
16231 * @param inst the instruction to assemble
16232 */
16233 private void doANDPD(Instruction inst) {
16234 if (isXMM_Reg(MIR_BinaryAcc.getValue(inst))) {
16235 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16236 emitANDPD_Reg_Reg(
16237 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
16238 getXMM_Reg(MIR_BinaryAcc.getValue(inst)));
16239
16240 } else {
16241 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
16242 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16243 emitANDPD_Reg_Abs(
16244 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
16245 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
16246
16247 } else {
16248 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
16249 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16250 emitANDPD_Reg_RegDisp(
16251 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
16252 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
16253
16254 } else {
16255 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
16256 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16257 emitANDPD_Reg_RegOff(
16258 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
16259 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
16260
16261 } else {
16262 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
16263 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16264 emitANDPD_Reg_RegIdx(
16265 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
16266 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
16267
16268 } else {
16269 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16270 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16271 emitANDPD_Reg_RegInd(
16272 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
16273 getBase(MIR_BinaryAcc.getValue(inst)));
16274 }
16275 }
16276 }
16277 }
16278 }
16279 }
16280
16281 /**
16282 * Emit the given instruction, assuming that
16283 * it is a MIR_BinaryAcc instruction
16284 * and has a PSLLQ operator
16285 *
16286 * @param inst the instruction to assemble
16287 */
16288 private void doPSLLQ(Instruction inst) {
16289 if (isMM_Reg(MIR_BinaryAcc.getResult(inst))) {
16290 if (isMM_Reg(MIR_BinaryAcc.getValue(inst))) {
16291 emitPSLLQ_Reg_Reg(
16292 getMM_Reg(MIR_BinaryAcc.getResult(inst)),
16293 getMM_Reg(MIR_BinaryAcc.getValue(inst)));
16294
16295 } else {
16296 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
16297 emitPSLLQ_Reg_Abs(
16298 getMM_Reg(MIR_BinaryAcc.getResult(inst)),
16299 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
16300
16301 } else {
16302 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
16303 emitPSLLQ_Reg_RegDisp(
16304 getMM_Reg(MIR_BinaryAcc.getResult(inst)),
16305 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
16306
16307 } else {
16308 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
16309 emitPSLLQ_Reg_RegOff(
16310 getMM_Reg(MIR_BinaryAcc.getResult(inst)),
16311 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
16312
16313 } else {
16314 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
16315 emitPSLLQ_Reg_RegIdx(
16316 getMM_Reg(MIR_BinaryAcc.getResult(inst)),
16317 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
16318
16319 } else {
16320 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16321 emitPSLLQ_Reg_RegInd(
16322 getMM_Reg(MIR_BinaryAcc.getResult(inst)),
16323 getBase(MIR_BinaryAcc.getValue(inst)));
16324 }
16325 }
16326 }
16327 }
16328 }
16329
16330 } else {
16331 if (isXMM_Reg(MIR_BinaryAcc.getValue(inst))) {
16332 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16333 emitPSLLQ_Reg_Reg(
16334 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
16335 getXMM_Reg(MIR_BinaryAcc.getValue(inst)));
16336
16337 } else {
16338 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
16339 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16340 emitPSLLQ_Reg_Abs(
16341 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
16342 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
16343
16344 } else {
16345 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
16346 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16347 emitPSLLQ_Reg_RegDisp(
16348 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
16349 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
16350
16351 } else {
16352 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
16353 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16354 emitPSLLQ_Reg_RegOff(
16355 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
16356 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
16357
16358 } else {
16359 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
16360 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16361 emitPSLLQ_Reg_RegIdx(
16362 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
16363 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
16364
16365 } else {
16366 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16367 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16368 emitPSLLQ_Reg_RegInd(
16369 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
16370 getBase(MIR_BinaryAcc.getValue(inst)));
16371 }
16372 }
16373 }
16374 }
16375 }
16376 }
16377 }
16378
16379 /**
16380 * Emit the given instruction, assuming that
16381 * it is a MIR_Compare instruction
16382 * and has a UCOMISD operator
16383 *
16384 * @param inst the instruction to assemble
16385 */
16386 private void doUCOMISD(Instruction inst) {
16387 if (isXMM_Reg(MIR_Compare.getVal2(inst))) {
16388 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Compare.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16389 emitUCOMISD_Reg_Reg(
16390 getXMM_Reg(MIR_Compare.getVal1(inst)),
16391 getXMM_Reg(MIR_Compare.getVal2(inst)));
16392
16393 } else {
16394 if (isAbs(MIR_Compare.getVal2(inst))) {
16395 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Compare.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16396 emitUCOMISD_Reg_Abs(
16397 getXMM_Reg(MIR_Compare.getVal1(inst)),
16398 getDisp(MIR_Compare.getVal2(inst)).toWord().toAddress());
16399
16400 } else {
16401 if (isRegDisp(MIR_Compare.getVal2(inst))) {
16402 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Compare.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16403 emitUCOMISD_Reg_RegDisp(
16404 getXMM_Reg(MIR_Compare.getVal1(inst)),
16405 getBase(MIR_Compare.getVal2(inst)), getDisp(MIR_Compare.getVal2(inst)));
16406
16407 } else {
16408 if (isRegOff(MIR_Compare.getVal2(inst))) {
16409 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Compare.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16410 emitUCOMISD_Reg_RegOff(
16411 getXMM_Reg(MIR_Compare.getVal1(inst)),
16412 getIndex(MIR_Compare.getVal2(inst)), getScale(MIR_Compare.getVal2(inst)), getDisp(MIR_Compare.getVal2(inst)));
16413
16414 } else {
16415 if (isRegIdx(MIR_Compare.getVal2(inst))) {
16416 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Compare.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16417 emitUCOMISD_Reg_RegIdx(
16418 getXMM_Reg(MIR_Compare.getVal1(inst)),
16419 getBase(MIR_Compare.getVal2(inst)), getIndex(MIR_Compare.getVal2(inst)), getScale(MIR_Compare.getVal2(inst)), getDisp(MIR_Compare.getVal2(inst)));
16420
16421 } else {
16422 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Compare.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16423 if (VM.VerifyAssertions && !isRegInd(MIR_Compare.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16424 emitUCOMISD_Reg_RegInd(
16425 getXMM_Reg(MIR_Compare.getVal1(inst)),
16426 getBase(MIR_Compare.getVal2(inst)));
16427 }
16428 }
16429 }
16430 }
16431 }
16432 }
16433
16434 /**
16435 * Emit the given instruction, assuming that
16436 * it is a MIR_Nullary instruction
16437 * and has a FLDLN2 operator
16438 *
16439 * @param inst the instruction to assemble
16440 */
16441 private void doFLDLN2(Instruction inst) {
16442 if (VM.VerifyAssertions && !isFPR_Reg(MIR_Nullary.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16443 emitFLDLN2_Reg(
16444 getFPR_Reg(MIR_Nullary.getResult(inst)));
16445 }
16446
16447 /**
16448 * Emit the given instruction, assuming that
16449 * it is a MIR_BinaryAcc instruction
16450 * and has a CMPUNORDSD operator
16451 *
16452 * @param inst the instruction to assemble
16453 */
16454 private void doCMPUNORDSD(Instruction inst) {
16455 if (isXMM_Reg(MIR_BinaryAcc.getValue(inst))) {
16456 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16457 emitCMPUNORDSD_Reg_Reg(
16458 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
16459 getXMM_Reg(MIR_BinaryAcc.getValue(inst)));
16460
16461 } else {
16462 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
16463 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16464 emitCMPUNORDSD_Reg_Abs(
16465 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
16466 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
16467
16468 } else {
16469 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
16470 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16471 emitCMPUNORDSD_Reg_RegDisp(
16472 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
16473 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
16474
16475 } else {
16476 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
16477 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16478 emitCMPUNORDSD_Reg_RegOff(
16479 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
16480 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
16481
16482 } else {
16483 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
16484 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16485 emitCMPUNORDSD_Reg_RegIdx(
16486 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
16487 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
16488
16489 } else {
16490 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16491 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16492 emitCMPUNORDSD_Reg_RegInd(
16493 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
16494 getBase(MIR_BinaryAcc.getValue(inst)));
16495 }
16496 }
16497 }
16498 }
16499 }
16500 }
16501
16502 /**
16503 * Emit the given instruction, assuming that
16504 * it is a MIR_Move instruction
16505 * and has a MOV operator
16506 *
16507 * @param inst the instruction to assemble
16508 */
16509 private void doMOV(Instruction inst) {
16510 if (isGPR_Reg(MIR_Move.getResult(inst))) {
16511 if (isQuad(inst)) {
16512 if (isImm(MIR_Move.getValue(inst))) {
16513 emitMOV_Reg_Imm_Quad(
16514 getGPR_Reg(MIR_Move.getResult(inst)),
16515 getImm(MIR_Move.getValue(inst)));
16516
16517 } else {
16518 if (isGPR_Reg(MIR_Move.getValue(inst))) {
16519 emitMOV_Reg_Reg_Quad(
16520 getGPR_Reg(MIR_Move.getResult(inst)),
16521 getGPR_Reg(MIR_Move.getValue(inst)));
16522
16523 } else {
16524 if (isAbs(MIR_Move.getValue(inst))) {
16525 emitMOV_Reg_Abs_Quad(
16526 getGPR_Reg(MIR_Move.getResult(inst)),
16527 getDisp(MIR_Move.getValue(inst)).toWord().toAddress());
16528
16529 } else {
16530 if (isRegDisp(MIR_Move.getValue(inst))) {
16531 emitMOV_Reg_RegDisp_Quad(
16532 getGPR_Reg(MIR_Move.getResult(inst)),
16533 getBase(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
16534
16535 } else {
16536 if (isRegOff(MIR_Move.getValue(inst))) {
16537 emitMOV_Reg_RegOff_Quad(
16538 getGPR_Reg(MIR_Move.getResult(inst)),
16539 getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
16540
16541 } else {
16542 if (isRegIdx(MIR_Move.getValue(inst))) {
16543 emitMOV_Reg_RegIdx_Quad(
16544 getGPR_Reg(MIR_Move.getResult(inst)),
16545 getBase(MIR_Move.getValue(inst)), getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
16546
16547 } else {
16548 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16549 emitMOV_Reg_RegInd_Quad(
16550 getGPR_Reg(MIR_Move.getResult(inst)),
16551 getBase(MIR_Move.getValue(inst)));
16552 }
16553 }
16554 }
16555 }
16556 }
16557 }
16558
16559 } else {
16560 if (isByte(inst)) {
16561 if (isGPR_Reg(MIR_Move.getValue(inst))) {
16562 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_Move.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
16563 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_Move.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
16564 emitMOV_Reg_Reg_Byte(
16565 getGPR_Reg(MIR_Move.getResult(inst)),
16566 getGPR_Reg(MIR_Move.getValue(inst)));
16567
16568 } else {
16569 if (isAbs(MIR_Move.getValue(inst))) {
16570 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_Move.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
16571 emitMOV_Reg_Abs_Byte(
16572 getGPR_Reg(MIR_Move.getResult(inst)),
16573 getDisp(MIR_Move.getValue(inst)).toWord().toAddress());
16574
16575 } else {
16576 if (isRegDisp(MIR_Move.getValue(inst))) {
16577 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_Move.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
16578 emitMOV_Reg_RegDisp_Byte(
16579 getGPR_Reg(MIR_Move.getResult(inst)),
16580 getBase(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
16581
16582 } else {
16583 if (isRegOff(MIR_Move.getValue(inst))) {
16584 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_Move.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
16585 emitMOV_Reg_RegOff_Byte(
16586 getGPR_Reg(MIR_Move.getResult(inst)),
16587 getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
16588
16589 } else {
16590 if (isRegIdx(MIR_Move.getValue(inst))) {
16591 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_Move.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
16592 emitMOV_Reg_RegIdx_Byte(
16593 getGPR_Reg(MIR_Move.getResult(inst)),
16594 getBase(MIR_Move.getValue(inst)), getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
16595
16596 } else {
16597 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16598 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_Move.getResult(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
16599 emitMOV_Reg_RegInd_Byte(
16600 getGPR_Reg(MIR_Move.getResult(inst)),
16601 getBase(MIR_Move.getValue(inst)));
16602 }
16603 }
16604 }
16605 }
16606 }
16607
16608 } else {
16609 if (isWord(inst)) {
16610 if (isGPR_Reg(MIR_Move.getValue(inst))) {
16611 emitMOV_Reg_Reg_Word(
16612 getGPR_Reg(MIR_Move.getResult(inst)),
16613 getGPR_Reg(MIR_Move.getValue(inst)));
16614
16615 } else {
16616 if (isAbs(MIR_Move.getValue(inst))) {
16617 emitMOV_Reg_Abs_Word(
16618 getGPR_Reg(MIR_Move.getResult(inst)),
16619 getDisp(MIR_Move.getValue(inst)).toWord().toAddress());
16620
16621 } else {
16622 if (isRegDisp(MIR_Move.getValue(inst))) {
16623 emitMOV_Reg_RegDisp_Word(
16624 getGPR_Reg(MIR_Move.getResult(inst)),
16625 getBase(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
16626
16627 } else {
16628 if (isRegOff(MIR_Move.getValue(inst))) {
16629 emitMOV_Reg_RegOff_Word(
16630 getGPR_Reg(MIR_Move.getResult(inst)),
16631 getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
16632
16633 } else {
16634 if (isRegIdx(MIR_Move.getValue(inst))) {
16635 emitMOV_Reg_RegIdx_Word(
16636 getGPR_Reg(MIR_Move.getResult(inst)),
16637 getBase(MIR_Move.getValue(inst)), getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
16638
16639 } else {
16640 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16641 emitMOV_Reg_RegInd_Word(
16642 getGPR_Reg(MIR_Move.getResult(inst)),
16643 getBase(MIR_Move.getValue(inst)));
16644 }
16645 }
16646 }
16647 }
16648 }
16649
16650 } else {
16651 if (isImm(MIR_Move.getValue(inst))) {
16652 emitMOV_Reg_Imm(
16653 getGPR_Reg(MIR_Move.getResult(inst)),
16654 getImm(MIR_Move.getValue(inst)));
16655
16656 } else {
16657 if (isGPR_Reg(MIR_Move.getValue(inst))) {
16658 emitMOV_Reg_Reg(
16659 getGPR_Reg(MIR_Move.getResult(inst)),
16660 getGPR_Reg(MIR_Move.getValue(inst)));
16661
16662 } else {
16663 if (isAbs(MIR_Move.getValue(inst))) {
16664 emitMOV_Reg_Abs(
16665 getGPR_Reg(MIR_Move.getResult(inst)),
16666 getDisp(MIR_Move.getValue(inst)).toWord().toAddress());
16667
16668 } else {
16669 if (isRegDisp(MIR_Move.getValue(inst))) {
16670 emitMOV_Reg_RegDisp(
16671 getGPR_Reg(MIR_Move.getResult(inst)),
16672 getBase(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
16673
16674 } else {
16675 if (isRegOff(MIR_Move.getValue(inst))) {
16676 emitMOV_Reg_RegOff(
16677 getGPR_Reg(MIR_Move.getResult(inst)),
16678 getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
16679
16680 } else {
16681 if (isRegIdx(MIR_Move.getValue(inst))) {
16682 emitMOV_Reg_RegIdx(
16683 getGPR_Reg(MIR_Move.getResult(inst)),
16684 getBase(MIR_Move.getValue(inst)), getIndex(MIR_Move.getValue(inst)), getScale(MIR_Move.getValue(inst)), getDisp(MIR_Move.getValue(inst)));
16685
16686 } else {
16687 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16688 emitMOV_Reg_RegInd(
16689 getGPR_Reg(MIR_Move.getResult(inst)),
16690 getBase(MIR_Move.getValue(inst)));
16691 }
16692 }
16693 }
16694 }
16695 }
16696 }
16697 }
16698 }
16699 }
16700
16701 } else {
16702 if (isImm(MIR_Move.getValue(inst))) {
16703 if (isByte(inst)) {
16704 if (isAbs(MIR_Move.getResult(inst))) {
16705 emitMOV_Abs_Imm_Byte(
16706 getDisp(MIR_Move.getResult(inst)).toWord().toAddress(),
16707 getImm(MIR_Move.getValue(inst)));
16708
16709 } else {
16710 if (isRegDisp(MIR_Move.getResult(inst))) {
16711 emitMOV_RegDisp_Imm_Byte(
16712 getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
16713 getImm(MIR_Move.getValue(inst)));
16714
16715 } else {
16716 if (isRegOff(MIR_Move.getResult(inst))) {
16717 emitMOV_RegOff_Imm_Byte(
16718 getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
16719 getImm(MIR_Move.getValue(inst)));
16720
16721 } else {
16722 if (isRegIdx(MIR_Move.getResult(inst))) {
16723 emitMOV_RegIdx_Imm_Byte(
16724 getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
16725 getImm(MIR_Move.getValue(inst)));
16726
16727 } else {
16728 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16729 emitMOV_RegInd_Imm_Byte(
16730 getBase(MIR_Move.getResult(inst)),
16731 getImm(MIR_Move.getValue(inst)));
16732 }
16733 }
16734 }
16735 }
16736
16737 } else {
16738 if (isWord(inst)) {
16739 if (isAbs(MIR_Move.getResult(inst))) {
16740 emitMOV_Abs_Imm_Word(
16741 getDisp(MIR_Move.getResult(inst)).toWord().toAddress(),
16742 getImm(MIR_Move.getValue(inst)));
16743
16744 } else {
16745 if (isRegDisp(MIR_Move.getResult(inst))) {
16746 emitMOV_RegDisp_Imm_Word(
16747 getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
16748 getImm(MIR_Move.getValue(inst)));
16749
16750 } else {
16751 if (isRegOff(MIR_Move.getResult(inst))) {
16752 emitMOV_RegOff_Imm_Word(
16753 getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
16754 getImm(MIR_Move.getValue(inst)));
16755
16756 } else {
16757 if (isRegIdx(MIR_Move.getResult(inst))) {
16758 emitMOV_RegIdx_Imm_Word(
16759 getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
16760 getImm(MIR_Move.getValue(inst)));
16761
16762 } else {
16763 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16764 emitMOV_RegInd_Imm_Word(
16765 getBase(MIR_Move.getResult(inst)),
16766 getImm(MIR_Move.getValue(inst)));
16767 }
16768 }
16769 }
16770 }
16771
16772 } else {
16773 if (isQuad(inst)) {
16774 if (isAbs(MIR_Move.getResult(inst))) {
16775 emitMOV_Abs_Imm_Quad(
16776 getDisp(MIR_Move.getResult(inst)).toWord().toAddress(),
16777 getImm(MIR_Move.getValue(inst)));
16778
16779 } else {
16780 if (isRegDisp(MIR_Move.getResult(inst))) {
16781 emitMOV_RegDisp_Imm_Quad(
16782 getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
16783 getImm(MIR_Move.getValue(inst)));
16784
16785 } else {
16786 if (isRegOff(MIR_Move.getResult(inst))) {
16787 emitMOV_RegOff_Imm_Quad(
16788 getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
16789 getImm(MIR_Move.getValue(inst)));
16790
16791 } else {
16792 if (isRegIdx(MIR_Move.getResult(inst))) {
16793 emitMOV_RegIdx_Imm_Quad(
16794 getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
16795 getImm(MIR_Move.getValue(inst)));
16796
16797 } else {
16798 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16799 emitMOV_RegInd_Imm_Quad(
16800 getBase(MIR_Move.getResult(inst)),
16801 getImm(MIR_Move.getValue(inst)));
16802 }
16803 }
16804 }
16805 }
16806
16807 } else {
16808 if (isAbs(MIR_Move.getResult(inst))) {
16809 emitMOV_Abs_Imm(
16810 getDisp(MIR_Move.getResult(inst)).toWord().toAddress(),
16811 getImm(MIR_Move.getValue(inst)));
16812
16813 } else {
16814 if (isRegDisp(MIR_Move.getResult(inst))) {
16815 emitMOV_RegDisp_Imm(
16816 getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
16817 getImm(MIR_Move.getValue(inst)));
16818
16819 } else {
16820 if (isRegOff(MIR_Move.getResult(inst))) {
16821 emitMOV_RegOff_Imm(
16822 getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
16823 getImm(MIR_Move.getValue(inst)));
16824
16825 } else {
16826 if (isRegIdx(MIR_Move.getResult(inst))) {
16827 emitMOV_RegIdx_Imm(
16828 getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
16829 getImm(MIR_Move.getValue(inst)));
16830
16831 } else {
16832 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16833 emitMOV_RegInd_Imm(
16834 getBase(MIR_Move.getResult(inst)),
16835 getImm(MIR_Move.getValue(inst)));
16836 }
16837 }
16838 }
16839 }
16840 }
16841 }
16842 }
16843
16844 } else {
16845 if (isByte(inst)) {
16846 if (isAbs(MIR_Move.getResult(inst))) {
16847 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16848 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_Move.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
16849 emitMOV_Abs_Reg_Byte(
16850 getDisp(MIR_Move.getResult(inst)).toWord().toAddress(),
16851 getGPR_Reg(MIR_Move.getValue(inst)));
16852
16853 } else {
16854 if (isRegDisp(MIR_Move.getResult(inst))) {
16855 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16856 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_Move.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
16857 emitMOV_RegDisp_Reg_Byte(
16858 getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
16859 getGPR_Reg(MIR_Move.getValue(inst)));
16860
16861 } else {
16862 if (isRegOff(MIR_Move.getResult(inst))) {
16863 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16864 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_Move.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
16865 emitMOV_RegOff_Reg_Byte(
16866 getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
16867 getGPR_Reg(MIR_Move.getValue(inst)));
16868
16869 } else {
16870 if (isRegIdx(MIR_Move.getResult(inst))) {
16871 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16872 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_Move.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
16873 emitMOV_RegIdx_Reg_Byte(
16874 getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
16875 getGPR_Reg(MIR_Move.getValue(inst)));
16876
16877 } else {
16878 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16879 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16880 if (VM.VerifyAssertions && !(getGPR_Reg(MIR_Move.getValue(inst)).value() < 4)) VM._assert(VM.NOT_REACHED, inst.toString());
16881 emitMOV_RegInd_Reg_Byte(
16882 getBase(MIR_Move.getResult(inst)),
16883 getGPR_Reg(MIR_Move.getValue(inst)));
16884 }
16885 }
16886 }
16887 }
16888
16889 } else {
16890 if (isWord(inst)) {
16891 if (isAbs(MIR_Move.getResult(inst))) {
16892 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16893 emitMOV_Abs_Reg_Word(
16894 getDisp(MIR_Move.getResult(inst)).toWord().toAddress(),
16895 getGPR_Reg(MIR_Move.getValue(inst)));
16896
16897 } else {
16898 if (isRegDisp(MIR_Move.getResult(inst))) {
16899 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16900 emitMOV_RegDisp_Reg_Word(
16901 getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
16902 getGPR_Reg(MIR_Move.getValue(inst)));
16903
16904 } else {
16905 if (isRegOff(MIR_Move.getResult(inst))) {
16906 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16907 emitMOV_RegOff_Reg_Word(
16908 getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
16909 getGPR_Reg(MIR_Move.getValue(inst)));
16910
16911 } else {
16912 if (isRegIdx(MIR_Move.getResult(inst))) {
16913 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16914 emitMOV_RegIdx_Reg_Word(
16915 getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
16916 getGPR_Reg(MIR_Move.getValue(inst)));
16917
16918 } else {
16919 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16920 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16921 emitMOV_RegInd_Reg_Word(
16922 getBase(MIR_Move.getResult(inst)),
16923 getGPR_Reg(MIR_Move.getValue(inst)));
16924 }
16925 }
16926 }
16927 }
16928
16929 } else {
16930 if (isQuad(inst)) {
16931 if (isAbs(MIR_Move.getResult(inst))) {
16932 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16933 emitMOV_Abs_Reg_Quad(
16934 getDisp(MIR_Move.getResult(inst)).toWord().toAddress(),
16935 getGPR_Reg(MIR_Move.getValue(inst)));
16936
16937 } else {
16938 if (isRegDisp(MIR_Move.getResult(inst))) {
16939 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16940 emitMOV_RegDisp_Reg_Quad(
16941 getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
16942 getGPR_Reg(MIR_Move.getValue(inst)));
16943
16944 } else {
16945 if (isRegOff(MIR_Move.getResult(inst))) {
16946 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16947 emitMOV_RegOff_Reg_Quad(
16948 getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
16949 getGPR_Reg(MIR_Move.getValue(inst)));
16950
16951 } else {
16952 if (isRegIdx(MIR_Move.getResult(inst))) {
16953 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16954 emitMOV_RegIdx_Reg_Quad(
16955 getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
16956 getGPR_Reg(MIR_Move.getValue(inst)));
16957
16958 } else {
16959 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16960 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16961 emitMOV_RegInd_Reg_Quad(
16962 getBase(MIR_Move.getResult(inst)),
16963 getGPR_Reg(MIR_Move.getValue(inst)));
16964 }
16965 }
16966 }
16967 }
16968
16969 } else {
16970 if (isAbs(MIR_Move.getResult(inst))) {
16971 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16972 emitMOV_Abs_Reg(
16973 getDisp(MIR_Move.getResult(inst)).toWord().toAddress(),
16974 getGPR_Reg(MIR_Move.getValue(inst)));
16975
16976 } else {
16977 if (isRegDisp(MIR_Move.getResult(inst))) {
16978 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16979 emitMOV_RegDisp_Reg(
16980 getBase(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
16981 getGPR_Reg(MIR_Move.getValue(inst)));
16982
16983 } else {
16984 if (isRegOff(MIR_Move.getResult(inst))) {
16985 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16986 emitMOV_RegOff_Reg(
16987 getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
16988 getGPR_Reg(MIR_Move.getValue(inst)));
16989
16990 } else {
16991 if (isRegIdx(MIR_Move.getResult(inst))) {
16992 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16993 emitMOV_RegIdx_Reg(
16994 getBase(MIR_Move.getResult(inst)), getIndex(MIR_Move.getResult(inst)), getScale(MIR_Move.getResult(inst)), getDisp(MIR_Move.getResult(inst)),
16995 getGPR_Reg(MIR_Move.getValue(inst)));
16996
16997 } else {
16998 if (VM.VerifyAssertions && !isRegInd(MIR_Move.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
16999 if (VM.VerifyAssertions && !isGPR_Reg(MIR_Move.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
17000 emitMOV_RegInd_Reg(
17001 getBase(MIR_Move.getResult(inst)),
17002 getGPR_Reg(MIR_Move.getValue(inst)));
17003 }
17004 }
17005 }
17006 }
17007 }
17008 }
17009 }
17010 }
17011 }
17012 }
17013
17014 /**
17015 * Emit the given instruction, assuming that
17016 * it is a MIR_BinaryAcc instruction
17017 * and has a MULSD operator
17018 *
17019 * @param inst the instruction to assemble
17020 */
17021 private void doMULSD(Instruction inst) {
17022 if (isXMM_Reg(MIR_BinaryAcc.getValue(inst))) {
17023 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
17024 emitMULSD_Reg_Reg(
17025 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
17026 getXMM_Reg(MIR_BinaryAcc.getValue(inst)));
17027
17028 } else {
17029 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
17030 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
17031 emitMULSD_Reg_Abs(
17032 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
17033 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
17034
17035 } else {
17036 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
17037 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
17038 emitMULSD_Reg_RegDisp(
17039 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
17040 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
17041
17042 } else {
17043 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
17044 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
17045 emitMULSD_Reg_RegOff(
17046 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
17047 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
17048
17049 } else {
17050 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
17051 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
17052 emitMULSD_Reg_RegIdx(
17053 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
17054 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
17055
17056 } else {
17057 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
17058 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
17059 emitMULSD_Reg_RegInd(
17060 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
17061 getBase(MIR_BinaryAcc.getValue(inst)));
17062 }
17063 }
17064 }
17065 }
17066 }
17067 }
17068
17069 /**
17070 * Emit the given instruction, assuming that
17071 * it is a MIR_BinaryAcc instruction
17072 * and has a ANDPS operator
17073 *
17074 * @param inst the instruction to assemble
17075 */
17076 private void doANDPS(Instruction inst) {
17077 if (isXMM_Reg(MIR_BinaryAcc.getValue(inst))) {
17078 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
17079 emitANDPS_Reg_Reg(
17080 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
17081 getXMM_Reg(MIR_BinaryAcc.getValue(inst)));
17082
17083 } else {
17084 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
17085 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
17086 emitANDPS_Reg_Abs(
17087 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
17088 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
17089
17090 } else {
17091 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
17092 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
17093 emitANDPS_Reg_RegDisp(
17094 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
17095 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
17096
17097 } else {
17098 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
17099 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
17100 emitANDPS_Reg_RegOff(
17101 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
17102 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
17103
17104 } else {
17105 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
17106 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
17107 emitANDPS_Reg_RegIdx(
17108 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
17109 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
17110
17111 } else {
17112 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
17113 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
17114 emitANDPS_Reg_RegInd(
17115 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
17116 getBase(MIR_BinaryAcc.getValue(inst)));
17117 }
17118 }
17119 }
17120 }
17121 }
17122 }
17123
17124 /**
17125 * Emit the given instruction, assuming that
17126 * it is a MIR_Compare instruction
17127 * and has a UCOMISS operator
17128 *
17129 * @param inst the instruction to assemble
17130 */
17131 private void doUCOMISS(Instruction inst) {
17132 if (isXMM_Reg(MIR_Compare.getVal2(inst))) {
17133 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Compare.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
17134 emitUCOMISS_Reg_Reg(
17135 getXMM_Reg(MIR_Compare.getVal1(inst)),
17136 getXMM_Reg(MIR_Compare.getVal2(inst)));
17137
17138 } else {
17139 if (isAbs(MIR_Compare.getVal2(inst))) {
17140 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Compare.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
17141 emitUCOMISS_Reg_Abs(
17142 getXMM_Reg(MIR_Compare.getVal1(inst)),
17143 getDisp(MIR_Compare.getVal2(inst)).toWord().toAddress());
17144
17145 } else {
17146 if (isRegDisp(MIR_Compare.getVal2(inst))) {
17147 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Compare.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
17148 emitUCOMISS_Reg_RegDisp(
17149 getXMM_Reg(MIR_Compare.getVal1(inst)),
17150 getBase(MIR_Compare.getVal2(inst)), getDisp(MIR_Compare.getVal2(inst)));
17151
17152 } else {
17153 if (isRegOff(MIR_Compare.getVal2(inst))) {
17154 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Compare.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
17155 emitUCOMISS_Reg_RegOff(
17156 getXMM_Reg(MIR_Compare.getVal1(inst)),
17157 getIndex(MIR_Compare.getVal2(inst)), getScale(MIR_Compare.getVal2(inst)), getDisp(MIR_Compare.getVal2(inst)));
17158
17159 } else {
17160 if (isRegIdx(MIR_Compare.getVal2(inst))) {
17161 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Compare.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
17162 emitUCOMISS_Reg_RegIdx(
17163 getXMM_Reg(MIR_Compare.getVal1(inst)),
17164 getBase(MIR_Compare.getVal2(inst)), getIndex(MIR_Compare.getVal2(inst)), getScale(MIR_Compare.getVal2(inst)), getDisp(MIR_Compare.getVal2(inst)));
17165
17166 } else {
17167 if (VM.VerifyAssertions && !isXMM_Reg(MIR_Compare.getVal1(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
17168 if (VM.VerifyAssertions && !isRegInd(MIR_Compare.getVal2(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
17169 emitUCOMISS_Reg_RegInd(
17170 getXMM_Reg(MIR_Compare.getVal1(inst)),
17171 getBase(MIR_Compare.getVal2(inst)));
17172 }
17173 }
17174 }
17175 }
17176 }
17177 }
17178
17179 /**
17180 * Emit the given instruction, assuming that
17181 * it is a MIR_BinaryAcc instruction
17182 * and has a CMPLTSD operator
17183 *
17184 * @param inst the instruction to assemble
17185 */
17186 private void doCMPLTSD(Instruction inst) {
17187 if (isXMM_Reg(MIR_BinaryAcc.getValue(inst))) {
17188 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
17189 emitCMPLTSD_Reg_Reg(
17190 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
17191 getXMM_Reg(MIR_BinaryAcc.getValue(inst)));
17192
17193 } else {
17194 if (isAbs(MIR_BinaryAcc.getValue(inst))) {
17195 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
17196 emitCMPLTSD_Reg_Abs(
17197 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
17198 getDisp(MIR_BinaryAcc.getValue(inst)).toWord().toAddress());
17199
17200 } else {
17201 if (isRegDisp(MIR_BinaryAcc.getValue(inst))) {
17202 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
17203 emitCMPLTSD_Reg_RegDisp(
17204 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
17205 getBase(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
17206
17207 } else {
17208 if (isRegOff(MIR_BinaryAcc.getValue(inst))) {
17209 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
17210 emitCMPLTSD_Reg_RegOff(
17211 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
17212 getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
17213
17214 } else {
17215 if (isRegIdx(MIR_BinaryAcc.getValue(inst))) {
17216 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
17217 emitCMPLTSD_Reg_RegIdx(
17218 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
17219 getBase(MIR_BinaryAcc.getValue(inst)), getIndex(MIR_BinaryAcc.getValue(inst)), getScale(MIR_BinaryAcc.getValue(inst)), getDisp(MIR_BinaryAcc.getValue(inst)));
17220
17221 } else {
17222 if (VM.VerifyAssertions && !isXMM_Reg(MIR_BinaryAcc.getResult(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
17223 if (VM.VerifyAssertions && !isRegInd(MIR_BinaryAcc.getValue(inst))) VM._assert(VM.NOT_REACHED, inst.toString());
17224 emitCMPLTSD_Reg_RegInd(
17225 getXMM_Reg(MIR_BinaryAcc.getResult(inst)),
17226 getBase(MIR_BinaryAcc.getValue(inst)));
17227 }
17228 }
17229 }
17230 }
17231 }
17232 }
17233
17234 /**
17235 * The number of instructions emitted so far
17236 */
17237 private int instructionCount = 0;
17238
17239 /**
17240 * Assemble the given instruction
17241 *
17242 * @param inst the instruction to assemble
17243 */
17244 public void doInst(Instruction inst) {
17245 instructionCount++;
17246 resolveForwardReferences(instructionCount);
17247 switch (inst.getOpcode()) {
17248 case IA32_FIMUL_opcode:
17249 doFIMUL(inst);
17250 break;
17251 case IA32_METHODSTART_opcode:
17252 doMETHODSTART(inst);
17253 break;
17254 case IA32_CVTSS2SD_opcode:
17255 doCVTSS2SD(inst);
17256 break;
17257 case IA32_CMPUNORDSS_opcode:
17258 doCMPUNORDSS(inst);
17259 break;
17260 case IA32_MULSS_opcode:
17261 doMULSS(inst);
17262 break;
17263 case IA32_CVTSS2SI_opcode:
17264 doCVTSS2SI(inst);
17265 break;
17266 case IA32_FSTP_opcode:
17267 doFSTP(inst);
17268 break;
17269 case IA32_CVTTSD2SIQ_opcode:
17270 doCVTTSD2SIQ(inst);
17271 break;
17272 case IA32_CDO_opcode:
17273 doCDO(inst);
17274 break;
17275 case IA32_CMPLTSS_opcode:
17276 doCMPLTSS(inst);
17277 break;
17278 case IA32_CDQ_opcode:
17279 doCDQ(inst);
17280 break;
17281 case IA32_ORPD_opcode:
17282 doORPD(inst);
17283 break;
17284 case IA32_FCMOV_opcode:
17285 doFCMOV(inst);
17286 break;
17287 case IA32_MOVSXQ__B_opcode:
17288 case IA32_MOVSXQ__W_opcode:
17289 doMOVSXQ(inst);
17290 break;
17291 case IA32_FLDLG2_opcode:
17292 doFLDLG2(inst);
17293 break;
17294 case IA32_FSUB_opcode:
17295 doFSUB(inst);
17296 break;
17297 case IA32_PUSH_opcode:
17298 doPUSH(inst);
17299 break;
17300 case IA32_SUB_opcode:
17301 doSUB(inst);
17302 break;
17303 case IA32_CMPEQSD_opcode:
17304 doCMPEQSD(inst);
17305 break;
17306 case IA32_ORPS_opcode:
17307 doORPS(inst);
17308 break;
17309 case IA32_CMP_opcode:
17310 doCMP(inst);
17311 break;
17312 case IA32_FST_opcode:
17313 doFST(inst);
17314 break;
17315 case IA32_BTC_opcode:
17316 doBTC(inst);
17317 break;
17318 case IA32_POP_opcode:
17319 doPOP(inst);
17320 break;
17321 case IA32_FLDCW_opcode:
17322 doFLDCW(inst);
17323 break;
17324 case IA32_RDTSC_opcode:
17325 doRDTSC(inst);
17326 break;
17327 case IA32_MOVZX__B_opcode:
17328 case IA32_MOVZX__W_opcode:
17329 doMOVZX(inst);
17330 break;
17331 case IA32_CMPEQSS_opcode:
17332 doCMPEQSS(inst);
17333 break;
17334 case IA32_FADDP_opcode:
17335 doFADDP(inst);
17336 break;
17337 case IA32_CDQE_opcode:
17338 doCDQE(inst);
17339 break;
17340 case IA32_XOR_opcode:
17341 doXOR(inst);
17342 break;
17343 case IA32_RCL_opcode:
17344 doRCL(inst);
17345 break;
17346 case IA32_FLD_opcode:
17347 doFLD(inst);
17348 break;
17349 case IA32_BTR_opcode:
17350 doBTR(inst);
17351 break;
17352 case IA32_BTS_opcode:
17353 doBTS(inst);
17354 break;
17355 case IA32_RCR_opcode:
17356 doRCR(inst);
17357 break;
17358 case IA32_SET__B_opcode:
17359 doSET(inst);
17360 break;
17361 case IA32_FIDIVR_opcode:
17362 doFIDIVR(inst);
17363 break;
17364 case IA32_FNSAVE_opcode:
17365 doFNSAVE(inst);
17366 break;
17367 case IA32_FDIVP_opcode:
17368 doFDIVP(inst);
17369 break;
17370 case IA32_MOVSD_opcode:
17371 doMOVSD(inst);
17372 break;
17373 case IA32_FDIVR_opcode:
17374 doFDIVR(inst);
17375 break;
17376 case IA32_SHRD_opcode:
17377 doSHRD(inst);
17378 break;
17379 case IA32_CVTSI2SD_opcode:
17380 doCVTSI2SD(inst);
17381 break;
17382 case IA32_FCOMI_opcode:
17383 doFCOMI(inst);
17384 break;
17385 case IA32_CMPXCHG_opcode:
17386 doCMPXCHG(inst);
17387 break;
17388 case IA32_BT_opcode:
17389 doBT(inst);
17390 break;
17391 case IA32_MOVSS_opcode:
17392 doMOVSS(inst);
17393 break;
17394 case IA32_CVTTSS2SI_opcode:
17395 doCVTTSS2SI(inst);
17396 break;
17397 case IA32_FINIT_opcode:
17398 doFINIT(inst);
17399 break;
17400 case IA32_FUCOMI_opcode:
17401 doFUCOMI(inst);
17402 break;
17403 case IA32_MOVSX__B_opcode:
17404 case IA32_MOVSX__W_opcode:
17405 doMOVSX(inst);
17406 break;
17407 case IA32_CMPXCHG8B_opcode:
17408 doCMPXCHG8B(inst);
17409 break;
17410 case IA32_CVTSI2SS_opcode:
17411 doCVTSI2SS(inst);
17412 break;
17413 case IA32_FNSTCW_opcode:
17414 doFNSTCW(inst);
17415 break;
17416 case IA32_CALL_opcode:
17417 doCALL(inst);
17418 break;
17419 case IA32_MOVZXQ__B_opcode:
17420 case IA32_MOVZXQ__W_opcode:
17421 doMOVZXQ(inst);
17422 break;
17423 case IA32_FIST_opcode:
17424 doFIST(inst);
17425 break;
17426 case IA32_FDIV_opcode:
17427 doFDIV(inst);
17428 break;
17429 case IA32_FISTP_opcode:
17430 doFISTP(inst);
17431 break;
17432 case IA32_CMPORDSD_opcode:
17433 doCMPORDSD(inst);
17434 break;
17435 case IA32_CMPNESD_opcode:
17436 doCMPNESD(inst);
17437 break;
17438 case IA32_XORPD_opcode:
17439 doXORPD(inst);
17440 break;
17441 case IA32_NEG_opcode:
17442 doNEG(inst);
17443 break;
17444 case IA32_FPREM_opcode:
17445 doFPREM(inst);
17446 break;
17447 case IA32_DIV_opcode:
17448 doDIV(inst);
17449 break;
17450 case IA32_SUBSD_opcode:
17451 doSUBSD(inst);
17452 break;
17453 case IA32_SQRTSD_opcode:
17454 doSQRTSD(inst);
17455 break;
17456 case IA32_FMULP_opcode:
17457 doFMULP(inst);
17458 break;
17459 case IA32_CMPNLESD_opcode:
17460 doCMPNLESD(inst);
17461 break;
17462 case IA32_PSRLQ_opcode:
17463 doPSRLQ(inst);
17464 break;
17465 case IA32_FISUBR_opcode:
17466 doFISUBR(inst);
17467 break;
17468 case IA32_FSUBP_opcode:
17469 doFSUBP(inst);
17470 break;
17471 case IA32_CVTSD2SI_opcode:
17472 doCVTSD2SI(inst);
17473 break;
17474 case IA32_FSUBR_opcode:
17475 doFSUBR(inst);
17476 break;
17477 case IA32_FILD_opcode:
17478 doFILD(inst);
17479 break;
17480 case IA32_FADD_opcode:
17481 doFADD(inst);
17482 break;
17483 case IA32_CMPORDSS_opcode:
17484 doCMPORDSS(inst);
17485 break;
17486 case IA32_FISUB_opcode:
17487 doFISUB(inst);
17488 break;
17489 case IA32_CMPNESS_opcode:
17490 doCMPNESS(inst);
17491 break;
17492 case IA32_XORPS_opcode:
17493 doXORPS(inst);
17494 break;
17495 case IA32_CVTSD2SS_opcode:
17496 doCVTSD2SS(inst);
17497 break;
17498 case IA32_ADC_opcode:
17499 doADC(inst);
17500 break;
17501 case IA32_SUBSS_opcode:
17502 doSUBSS(inst);
17503 break;
17504 case IA32_SQRTSS_opcode:
17505 doSQRTSS(inst);
17506 break;
17507 case IA32_ADD_opcode:
17508 doADD(inst);
17509 break;
17510 case IA32_RET_opcode:
17511 doRET(inst);
17512 break;
17513 case IA32_CMPNLESS_opcode:
17514 doCMPNLESS(inst);
17515 break;
17516 case IA32_DIVSD_opcode:
17517 doDIVSD(inst);
17518 break;
17519 case IA32_CVTSI2SDQ_opcode:
17520 doCVTSI2SDQ(inst);
17521 break;
17522 case IA32_FCHS_opcode:
17523 doFCHS(inst);
17524 break;
17525 case IA32_IDIV_opcode:
17526 doIDIV(inst);
17527 break;
17528 case IA32_SHLD_opcode:
17529 doSHLD(inst);
17530 break;
17531 case IA32_DIVSS_opcode:
17532 doDIVSS(inst);
17533 break;
17534 case IA32_TEST_opcode:
17535 doTEST(inst);
17536 break;
17537 case IA32_ADDSD_opcode:
17538 doADDSD(inst);
17539 break;
17540 case IA32_OFFSET_opcode:
17541 doOFFSET(inst);
17542 break;
17543 case IA32_SHL_opcode:
17544 doSHL(inst);
17545 break;
17546 case IA32_CVTSD2SIQ_opcode:
17547 doCVTSD2SIQ(inst);
17548 break;
17549 case IA32_SHR_opcode:
17550 doSHR(inst);
17551 break;
17552 case IA32_FMUL_opcode:
17553 doFMUL(inst);
17554 break;
17555 case IA32_FLDL2E_opcode:
17556 doFLDL2E(inst);
17557 break;
17558 case IA32_ADDSS_opcode:
17559 doADDSS(inst);
17560 break;
17561 case IA32_MUL_opcode:
17562 doMUL(inst);
17563 break;
17564 case IA32_ANDNPD_opcode:
17565 doANDNPD(inst);
17566 break;
17567 case IA32_ROL_opcode:
17568 doROL(inst);
17569 break;
17570 case IA32_FLDL2T_opcode:
17571 doFLDL2T(inst);
17572 break;
17573 case IA32_CMPLESD_opcode:
17574 doCMPLESD(inst);
17575 break;
17576 case IA32_FFREE_opcode:
17577 doFFREE(inst);
17578 break;
17579 case IA32_FLD1_opcode:
17580 doFLD1(inst);
17581 break;
17582 case IA32_NOT_opcode:
17583 doNOT(inst);
17584 break;
17585 case IA32_ROR_opcode:
17586 doROR(inst);
17587 break;
17588 case IA32_FLDPI_opcode:
17589 doFLDPI(inst);
17590 break;
17591 case IA32_AND_opcode:
17592 doAND(inst);
17593 break;
17594 case IA32_FXCH_opcode:
17595 doFXCH(inst);
17596 break;
17597 case IA32_ANDNPS_opcode:
17598 doANDNPS(inst);
17599 break;
17600 case IA32_INC_opcode:
17601 doINC(inst);
17602 break;
17603 case IA32_SAL_opcode:
17604 doSAL(inst);
17605 break;
17606 case IA32_CMPLESS_opcode:
17607 doCMPLESS(inst);
17608 break;
17609 case IA32_CMPNLTSD_opcode:
17610 doCMPNLTSD(inst);
17611 break;
17612 case IA32_FCOMIP_opcode:
17613 doFCOMIP(inst);
17614 break;
17615 case IA32_CVTTSD2SI_opcode:
17616 doCVTTSD2SI(inst);
17617 break;
17618 case IA32_SAR_opcode:
17619 doSAR(inst);
17620 break;
17621 case IA32_MOVLPD_opcode:
17622 doMOVLPD(inst);
17623 break;
17624 case IA32_FIDIV_opcode:
17625 doFIDIV(inst);
17626 break;
17627 case IA32_INT_opcode:
17628 doINT(inst);
17629 break;
17630 case IA32_FRSTOR_opcode:
17631 doFRSTOR(inst);
17632 break;
17633 case IA32_CMPNLTSS_opcode:
17634 doCMPNLTSS(inst);
17635 break;
17636 case IA32_MOVD_opcode:
17637 doMOVD(inst);
17638 break;
17639 case IA32_CMOV_opcode:
17640 doCMOV(inst);
17641 break;
17642 case IA32_SBB_opcode:
17643 doSBB(inst);
17644 break;
17645 case IA32_BSWAP_opcode:
17646 doBSWAP(inst);
17647 break;
17648 case IA32_IMUL1_opcode:
17649 doIMUL1(inst);
17650 break;
17651 case IA32_PAUSE_opcode:
17652 doPAUSE(inst);
17653 break;
17654 case IA32_IMUL2_opcode:
17655 doIMUL2(inst);
17656 break;
17657 case IA32_FSUBRP_opcode:
17658 doFSUBRP(inst);
17659 break;
17660 case IA32_FNINIT_opcode:
17661 doFNINIT(inst);
17662 break;
17663 case IA32_FUCOMIP_opcode:
17664 doFUCOMIP(inst);
17665 break;
17666 case IA32_FSTCW_opcode:
17667 doFSTCW(inst);
17668 break;
17669 case IA32_MOVLPS_opcode:
17670 doMOVLPS(inst);
17671 break;
17672 case IA32_FLDZ_opcode:
17673 doFLDZ(inst);
17674 break;
17675 case IA32_MOVQ_opcode:
17676 doMOVQ(inst);
17677 break;
17678 case IA32_FIADD_opcode:
17679 doFIADD(inst);
17680 break;
17681 case IA32_DEC_opcode:
17682 doDEC(inst);
17683 break;
17684 case IA32_OR_opcode:
17685 doOR(inst);
17686 break;
17687 case IA32_MFENCE_opcode:
17688 doMFENCE(inst);
17689 break;
17690 case IA32_PREFETCHNTA_opcode:
17691 doPREFETCHNTA(inst);
17692 break;
17693 case IA32_LEA_opcode:
17694 doLEA(inst);
17695 break;
17696 case IA32_FDIVRP_opcode:
17697 doFDIVRP(inst);
17698 break;
17699 case IA32_ANDPD_opcode:
17700 doANDPD(inst);
17701 break;
17702 case IA32_PSLLQ_opcode:
17703 doPSLLQ(inst);
17704 break;
17705 case IA32_UCOMISD_opcode:
17706 doUCOMISD(inst);
17707 break;
17708 case IA32_FLDLN2_opcode:
17709 doFLDLN2(inst);
17710 break;
17711 case IA32_CMPUNORDSD_opcode:
17712 doCMPUNORDSD(inst);
17713 break;
17714 case IA32_MOV_opcode:
17715 doMOV(inst);
17716 break;
17717 case IA32_MULSD_opcode:
17718 doMULSD(inst);
17719 break;
17720 case IA32_ANDPS_opcode:
17721 doANDPS(inst);
17722 break;
17723 case IA32_UCOMISS_opcode:
17724 doUCOMISS(inst);
17725 break;
17726 case IA32_CMPLTSD_opcode:
17727 doCMPLTSD(inst);
17728 break;
17729 case IA32_JCC_opcode:
17730 doJCC(inst);
17731 break;
17732 case IA32_JMP_opcode:
17733 doJMP(inst);
17734 break;
17735 case IA32_LOCK_opcode:
17736 emitLockNextInstruction();
17737 break;
17738 case IG_PATCH_POINT_opcode:
17739 emitPatchPoint();
17740 break;
17741 case MIR_LOWTABLESWITCH_opcode:
17742 doLOWTABLESWITCH(inst);
17743 // kludge table switches that are unusually long instructions
17744 instructionCount += MIR_LowTableSwitch.getNumberOfTargets(inst);
17745 break;
17746 case IA32_FMOV_ENDING_LIVE_RANGE_opcode:
17747 case IA32_FEXAM_opcode:
17748 case IA32_LOCK_CMPXCHG8B_opcode:
17749 case IA32_FCLEAR_opcode:
17750 case IA32_JCC2_opcode:
17751 case IA32_TRAPIF_opcode:
17752 case IA32_SYSCALL_opcode:
17753 case IA32_LOCK_CMPXCHG_opcode:
17754 case IA32_FMOV_opcode:
17755 throw new OptimizingCompilerException(inst + " has unimplemented IA32 opcode (check excludedOpcodes)");
17756 }
17757 inst.setmcOffset( mi );
17758 }
17759
17760
17761 }