001 /*
002 * This file is part of the Jikes RVM project (http://jikesrvm.org).
003 *
004 * This file is licensed to You under the Eclipse Public License (EPL);
005 * You may not use this file except in compliance with the License. You
006 * may obtain a copy of the License at
007 *
008 * http://www.opensource.org/licenses/eclipse-1.0.php
009 *
010 * See the COPYRIGHT.txt file distributed with this work for information
011 * regarding copyright ownership.
012 */
013 package org.jikesrvm.compilers.opt.lir2mir.ia32;
014
015 import org.jikesrvm.*;
016 import org.jikesrvm.compilers.opt.*;
017 import org.jikesrvm.compilers.opt.depgraph.DepGraphNode;
018 import org.jikesrvm.compilers.opt.ir.*;
019 import org.jikesrvm.compilers.opt.ir.operand.*;
020 import org.jikesrvm.compilers.opt.ir.operand.ia32.*;
021
022 /**
023 * An BURS_TreeNode is a node in a binary tree that is fed
024 * as input to BURS.
025 * Machine-generated, do not edit.
026 *
027 * @see org.jikesrvm.compilers.opt.lir2mir.BURS
028 * @see BURS_STATE
029 */
030 public class BURS_TreeNode implements BURS_Definitions {
031
032 public ArchitectureSpecificOpt.BURS_TreeNode child1;
033 public ArchitectureSpecificOpt.BURS_TreeNode child2;
034
035 /**
036 * Dependence graph node corresponding to
037 * interior node in BURS tree (set to null for
038 * leaf node or for OTHER_OPERAND node).
039 */
040 public final DepGraphNode dg_node;
041
042 /**
043 * Opcode of instruction
044 */
045 private final char opcode;
046
047 /**
048 * nonterminal > 0 ==> this tree node is the
049 * root of a "supernode"; the value of nonterminal
050 * identifies the matching non-terminal
051 * nonterminal = 0 ==> this tree node is NOT the
052 * root of a "supernode".
053 */
054 private byte nonterminal;
055
056 /**
057 * <pre>
058 * trrr rrrr
059 * t = tree root
060 * r = num of registers used
061 * </pre>
062 */
063 private byte treeroot_registersused;
064
065 public final char getOpcode() {
066 return opcode;
067 }
068
069 public final int getNonTerminal() {
070 return (int)nonterminal & 0xFF;
071 }
072
073 public final void setNonTerminal(int nonterminal) {
074 if (VM.VerifyAssertions) VM._assert(nonterminal <= 0xff);
075 this.nonterminal = (byte)nonterminal;
076 }
077
078 public final boolean isTreeRoot() {
079 return (treeroot_registersused & 0x80 ) != 0;
080 }
081
082 public final void setTreeRoot() {
083 treeroot_registersused |= 0x80;
084 }
085
086 public final void setNumRegisters(int r) {
087 treeroot_registersused = (byte)((treeroot_registersused & 0x80) | (r & 0x7f));
088 }
089 public final int numRegisters() {
090 return treeroot_registersused & 0x7f;
091 }
092
093 public final Instruction getInstruction() {
094 return dg_node._instr;
095 }
096
097 /**
098 * Constructor for interior node.
099 */
100 public BURS_TreeNode(DepGraphNode n) {
101 Instruction instr = n._instr;
102 dg_node = n;
103 opcode = instr.getOpcode();
104 }
105
106 /**
107 * Constructor for leaf/auxiliary node.
108 */
109 public BURS_TreeNode(char Opcode) {
110 dg_node = null;
111 opcode = Opcode;
112 }
113
114 @Override
115 public String toString() {
116 String node;
117 node = OperatorNames.operatorName[getOpcode()];
118 return node;
119 }
120
121 public final boolean isSuperNodeRoot() {
122 return (getNonTerminal() > 0 );
123 }
124
125 public final boolean isREGISTERNode() {
126 return getOpcode() == Operators.REGISTER_opcode;
127 }
128
129 /**** remainder will be inserted by the BURS generator *********/
130
131 // program generated file, do not edit
132
133 // cost for each non-terminal
134 public char cost_stm;
135 public char cost_r;
136 public char cost_czr;
137 public char cost_cz;
138 public char cost_szpr;
139 public char cost_szp;
140 public char cost_riv;
141 public char cost_rlv;
142 public char cost_any;
143 public char cost_sload8;
144 public char cost_uload8;
145 public char cost_load8;
146 public char cost_sload16;
147 public char cost_uload16;
148 public char cost_load16;
149 public char cost_load32;
150 public char cost_load16_32;
151 public char cost_load8_16_32;
152 public char cost_load64;
153 public char cost_address1scaledreg;
154 public char cost_address1reg;
155 public char cost_address;
156 public char cost_boolcmp;
157 public char cost_bittest;
158 public char cost_float_load;
159 public char cost_double_load;
160
161 // rule for each non-terminal
162 public int word0;
163 // stm; word:0 offset:0, bits:8, 142 rules);
164 // r; word:0 offset:8, bits:8, 222 rules);
165 // czr; word:0 offset:16, bits:3, 7 rules);
166 // cz; word:0 offset:19, bits:2, 2 rules);
167 // szpr; word:0 offset:21, bits:5, 22 rules);
168 // szp; word:0 offset:26, bits:3, 5 rules);
169 // riv; word:0 offset:29, bits:2, 2 rules);
170 public int word1;
171 // rlv; word:1 offset:0, bits:2, 2 rules);
172 // any; word:1 offset:2, bits:3, 5 rules);
173 // sload8; word:1 offset:5, bits:2, 3 rules);
174 // uload8; word:1 offset:7, bits:3, 4 rules);
175 // load8; word:1 offset:10, bits:2, 3 rules);
176 // sload16; word:1 offset:12, bits:2, 3 rules);
177 // uload16; word:1 offset:14, bits:2, 3 rules);
178 // load16; word:1 offset:16, bits:2, 3 rules);
179 // load32; word:1 offset:18, bits:3, 6 rules);
180 // load16_32; word:1 offset:21, bits:2, 2 rules);
181 // load8_16_32; word:1 offset:23, bits:2, 2 rules);
182 // load64; word:1 offset:25, bits:3, 4 rules);
183 // address1scaledreg; word:1 offset:28, bits:3, 4 rules);
184 public int word2;
185 // address1reg; word:2 offset:0, bits:3, 4 rules);
186 // address; word:2 offset:3, bits:4, 8 rules);
187 // boolcmp; word:2 offset:7, bits:4, 10 rules);
188 // bittest; word:2 offset:11, bits:4, 10 rules);
189 // float_load; word:2 offset:15, bits:3, 4 rules);
190 // double_load; word:2 offset:18, bits:3, 4 rules);
191
192 public char getCost(int goalNT) {
193 switch(goalNT) {
194 case stm_NT: return cost_stm;
195 case r_NT: return cost_r;
196 case czr_NT: return cost_czr;
197 case cz_NT: return cost_cz;
198 case szpr_NT: return cost_szpr;
199 case szp_NT: return cost_szp;
200 case riv_NT: return cost_riv;
201 case rlv_NT: return cost_rlv;
202 case any_NT: return cost_any;
203 case sload8_NT: return cost_sload8;
204 case uload8_NT: return cost_uload8;
205 case load8_NT: return cost_load8;
206 case sload16_NT: return cost_sload16;
207 case uload16_NT: return cost_uload16;
208 case load16_NT: return cost_load16;
209 case load32_NT: return cost_load32;
210 case load16_32_NT: return cost_load16_32;
211 case load8_16_32_NT: return cost_load8_16_32;
212 case load64_NT: return cost_load64;
213 case address1scaledreg_NT: return cost_address1scaledreg;
214 case address1reg_NT: return cost_address1reg;
215 case address_NT: return cost_address;
216 case boolcmp_NT: return cost_boolcmp;
217 case bittest_NT: return cost_bittest;
218 case float_load_NT: return cost_float_load;
219 default: return cost_double_load;
220 }
221 }
222
223 public void initCost() {
224 cost_stm =
225 cost_r =
226 cost_czr =
227 cost_cz =
228 cost_szpr =
229 cost_szp =
230 cost_riv =
231 cost_rlv =
232 cost_any =
233 cost_sload8 =
234 cost_uload8 =
235 cost_load8 =
236 cost_sload16 =
237 cost_uload16 =
238 cost_load16 =
239 cost_load32 =
240 cost_load16_32 =
241 cost_load8_16_32 =
242 cost_load64 =
243 cost_address1scaledreg =
244 cost_address1reg =
245 cost_address =
246 cost_boolcmp =
247 cost_bittest =
248 cost_float_load =
249 cost_double_load =
250 0x7fff;
251 word0 = 0;
252 word1 = 0;
253 word2 = 0;
254
255 }
256
257 public int rule(int goalNT) {
258 int statement = 0;
259 switch(goalNT) {
260 case stm_NT: statement= (word0 & 0xFF); break;// stm
261 case r_NT: statement= ((word0 >>> 8) & 0xFF); break;// r
262 case czr_NT: statement= ((word0 >>> 16) & 0x7); break;// czr
263 case cz_NT: statement= ((word0 >>> 19) & 0x3); break;// cz
264 case szpr_NT: statement= ((word0 >>> 21) & 0x1F); break;// szpr
265 case szp_NT: statement= ((word0 >>> 26) & 0x7); break;// szp
266 case riv_NT: statement= ((word0 >>> 29) & 0x3); break;// riv
267 case rlv_NT: statement= (word1 & 0x3); break;// rlv
268 case any_NT: statement= ((word1 >>> 2) & 0x7); break;// any
269 case sload8_NT: statement= ((word1 >>> 5) & 0x3); break;// sload8
270 case uload8_NT: statement= ((word1 >>> 7) & 0x7); break;// uload8
271 case load8_NT: statement= ((word1 >>> 10) & 0x3); break;// load8
272 case sload16_NT: statement= ((word1 >>> 12) & 0x3); break;// sload16
273 case uload16_NT: statement= ((word1 >>> 14) & 0x3); break;// uload16
274 case load16_NT: statement= ((word1 >>> 16) & 0x3); break;// load16
275 case load32_NT: statement= ((word1 >>> 18) & 0x7); break;// load32
276 case load16_32_NT: statement= ((word1 >>> 21) & 0x3); break;// load16_32
277 case load8_16_32_NT: statement= ((word1 >>> 23) & 0x3); break;// load8_16_32
278 case load64_NT: statement= ((word1 >>> 25) & 0x7); break;// load64
279 case address1scaledreg_NT: statement= ((word1 >>> 28) & 0x7); break;// address1scaledreg
280 case address1reg_NT: statement= (word2 & 0x7); break;// address1reg
281 case address_NT: statement= ((word2 >>> 3) & 0xF); break;// address
282 case boolcmp_NT: statement= ((word2 >>> 7) & 0xF); break;// boolcmp
283 case bittest_NT: statement= ((word2 >>> 11) & 0xF); break;// bittest
284 case float_load_NT: statement= ((word2 >>> 15) & 0x7); break;// float_load
285 default: statement= ((word2 >>> 18) & 0x7); break;// double_load
286 }
287 return BURS_STATE.decode[goalNT][statement];
288 }
289 }
290