001 /*
002 * This file is part of the Jikes RVM project (http://jikesrvm.org).
003 *
004 * This file is licensed to You under the Eclipse Public License (EPL);
005 * You may not use this file except in compliance with the License. You
006 * may obtain a copy of the License at
007 *
008 * http://www.opensource.org/licenses/eclipse-1.0.php
009 *
010 * See the COPYRIGHT.txt file distributed with this work for information
011 * regarding copyright ownership.
012 */
013 package org.jikesrvm.compilers.common.assembler.ia32;
014
015 import org.jikesrvm.*;
016 import org.jikesrvm.runtime.Magic;
017 import org.jikesrvm.compilers.baseline.ia32.BaselineCompilerImpl;
018 import org.jikesrvm.ia32.OutOfLineMachineCode;
019 import org.jikesrvm.ia32.RegisterConstants;
020 import org.jikesrvm.compilers.common.assembler.ForwardReference;
021 import org.jikesrvm.compilers.common.assembler.AbstractAssembler;
022 import static org.jikesrvm.ia32.RegisterConstants.GPR;
023
024 import org.vmmagic.pragma.*;
025 import org.vmmagic.unboxed.*;
026
027 /**
028 * <P> This class is the low-level assembler for Intel; it contains
029 * functionality for encoding specific instructions into an array of
030 * bytes. It consists of three parts: </P>
031 * <UL>
032 * <LI> Some support that handles common operations for generating
033 * any IA32 instruction, such as encoding the operands into the
034 * ModRM and SIB bytes
035 * <LI> Some hand-coded methods that emit instructions with
036 * distinctive formats or with special consistency requirements,
037 * such as FXCH or CMOV
038 * <LI> Machine-generated methods that emit instructions with
039 * relatively standard formats, such as binary accumulation
040 * instructions like ADD and SUB.
041 * </UL>
042 * <P> This assembler provides a direct interface to the IA32 ISA: it
043 * contains emit methods that generate specific IA32 opcodes, and each
044 * emit method specifies the addressing modes and operand sizes that
045 * it expects. Thus, it has an emit method that generates an ADD of a
046 * register-displacement operand and an immediate operand. It is the
047 * job of the client to determine the addressing modes, operand
048 * sizes and exact opcodes that it desires. </P>
049 *
050 * <P> This assembler does provide support for forward branches. It
051 * is permitted to specify a branch operand as an arbitrary label, and
052 * later to inform the assembler to which instruction this label
053 * refers. The assembler, when informed to what the label refers,
054 * will go back and generate the appropriate offsets for all branches
055 * that refer to the given label. The mechanism is implemented by the
056 * following methods and helper classes:
057 * <UL>
058 * <LI> {@link #forwardRefs}
059 * <LI> {@link #resolveForwardReferences}
060 * <LI> {@link #patchUnconditionalBranch}
061 * <LI> {@link #patchConditionalBranch}
062 * <LI> {@link #emitJCC_Cond_Label}
063 * <LI> {@link #emitJMP_Label}
064 * <LI> {@link #emitCALL_Label}
065 * <LI> {@link ForwardReference}
066 * </UL>
067 * </P>
068 *
069 * <P> There is also support for generating tableswitches. This
070 * consists providing support for storing tables of relative addresses
071 * that can be used to compute the target of a tableswitch. This
072 * support assumes a particular code sequence for tableswitches
073 * (followed by baseline and optimizing compilers). See {@link
074 * #emitOFFSET_Imm_ImmOrLabel} for details. </P>
075 *
076 * <P> The automatically-generated emit methods of this assembler
077 * exploit regularities in the IA32 binary encoding; for example,
078 * several instructions (ADD, ADC, SUB, AND, OR, XOR) can be
079 * classified as binary accumulators that share a common set of
080 * permitted addressing modes and binary encoding all the way down a
081 * special case for enconding operands EAX and an immediate. A shell
082 * script (genAssembler.sh in the intel assembler source directory)
083 * explots this by specifying a generic way of emtting a binary
084 * accumulation and then calling it for each specific opcode that fits
085 * that format. These generated methods are combined with the
086 * hand-coded ones (from Assembler.in, also in the assembler
087 * source directory) as part of the Jikes RVM build process. </P>
088 *
089 * <P> This assembler is shared by the baseline and optimizing
090 * compilers: it used directly by the baseline compiler, while the
091 * optimizing compiler has an {@link org.jikesrvm.ArchitectureSpecificOpt.AssemblerOpt}
092 * that is built on top of this one to match
093 * {@link org.jikesrvm.compilers.opt.ir.Instruction}s and
094 * {@link org.jikesrvm.compilers.opt.ir.Operator}s to the emit methods
095 * this assembler provides. The {@link org.jikesrvm.ArchitectureSpecificOpt.AssemblerOpt}
096 * is entirely machine-generated, and this
097 * requires that the methods for encoding instructions use a stylized
098 * naming and signiture convention that is designed to make the method
099 * signiture computable from the opcode and the operand types. The
100 * naming convention is as follows:
101 *
102 * <PRE>
103 * final void emit<EM>opcode</EM>\(_<EM>operand code</EM>\)*[_<EM>size</EM>](\(<EM>operand arguments</EM>\)*)
104 * </PRE>
105 *
106 * where the following substitutions are made:
107 * <DL>
108 * <DT> <EM>opcode</EM>
109 * <DI> is the opcode of the instruction (e.g. ADC, MOV, etc)
110 *
111 * <DT> <EM>operand code</EM>
112 * <DI> represents the type of the nth operand:
113 * <DL>
114 * <DT> "Imm" <DI> immediate operands
115 * <DT> "Reg" <DI> register operands
116 * <DT> "RegInd" <DI> register indirect operands
117 * <DT> "RegDisp" <DI> register displacement
118 * <DT> "RegOff" <DI> shifted index + displacement
119 * <DT> "RegIdx" <DI> register base + shifted index + displacement
120 * <DT> "Cond" <DI> condition codes
121 * </DL>
122 *
123 * <DT> <EM>size</EM>
124 * <DI> indicates non-word-sized operations
125 * <DL>
126 * <DT> "Byte" <DI> bytes
127 * <DT> "Word" <DI> Intel "words" (i.e. 16 bites)
128 * <DT> "Quad" <DI> quad words (i.e. double-precision floating point)
129 * </DL>
130 *
131 * <DT> <EM>operand arguments</EM>
132 * <DI> are the needed components of the operands, in order
133 * <DL>
134 * <DT> "Imm"
135 * <DI>
136 * <UL>
137 * <LI> immediate value (int)
138 * </UL>
139 * <DT> "Reg"
140 * <DI>
141 * <UL>
142 * <LI> register number (byte)
143 * </UL>
144 * <DT> "RegInd"
145 * <DI>
146 * <UL>
147 * <LI> register number (byte)
148 * </UL>
149 * <DT> "RegDisp"
150 * <DI>
151 * <UL>
152 * <LI> register number (byte)
153 * <LI> displacement (int)
154 * </UL>
155 * <DT> "RegOff"
156 * <DI>
157 * <UL>
158 * <LI> index register (byte)
159 * <LI> scale (short)
160 * <LI> displacement (int)
161 * </UL>
162 * <DT> "RegIdx"
163 * <DI>
164 * <UL>
165 * <LI> base register (byte)
166 * <LI> index register (byte)
167 * <LI> scale (short)
168 * <LI> displacement (int)
169 * </UL>
170 * <DT> "Cond"
171 * <DI>
172 * <UL>
173 * <LI> condition code mask (byte)
174 * </UL>
175 * </DL>
176 * </DL>
177 *
178 * @see org.jikesrvm.ArchitectureSpecificOpt.AssemblerOpt
179 * @see Lister
180 * @see ForwardReference
181 *
182 */
183 public abstract class Assembler extends AbstractAssembler implements RegisterConstants, AssemblerConstants {
184
185 /**
186 * The lister object is used to print generated machine code.
187 */
188 protected final Lister lister;
189
190 /**
191 * The array holding the generated binary code.
192 */
193 private byte [] machineCodes;
194
195 /**
196 * The current end of the generated machine code
197 */
198 protected int mi;
199
200 /**
201 * Create an assembler with a given machine code buffer size that
202 * will not print the machine code as it generates it.
203 * The buffer size is merely a heuristic, because the assembler will
204 * expand its buffer if it becomes full.
205 *
206 * @param bytecodeSize initial machine code buffer size.
207 */
208 protected Assembler (int bytecodeSize) {
209 this(bytecodeSize, false);
210 }
211
212 /**
213 * Create an assembler with a given machine code buffer size and
214 * tell it whether or not to print machine code as it generates it.
215 * The buffer size is merely a heuristic, because the assembler will
216 * expand its buffer if it becomes full.
217 *
218 * @param bytecodeSize initial machine code buffer size.
219 * @param shouldPrint whether to dump generated machine code.
220 */
221 protected Assembler (int bytecodeSize, boolean shouldPrint) {
222 machineCodes = new byte[bytecodeSize*CODE_EXPANSION_FACTOR + CODE_OVERHEAD_TERM];
223 lister = shouldPrint ? new Lister((ArchitectureSpecific.Assembler) this) : null;
224 }
225
226 /**
227 * Create an assembler with a given machine code buffer size and
228 * tell it whether or not to print machine code as it generates it.
229 * The buffer size is merely a heuristic, because the assembler will
230 * expand its buffer if it becomes full.
231 *
232 * @param bytecodeSize initial machine code buffer size.
233 * @param shouldPrint whether to dump generated machine code.
234 * @param comp BaselineCompilerImpl instance that this assembler is associated with;
235 * currently ignored on IA32.
236 */
237 protected Assembler (int bytecodeSize, boolean shouldPrint, BaselineCompilerImpl comp) {
238 this(bytecodeSize, shouldPrint);
239 }
240
241 /**
242 * Heuristic constant used to calculate initial size of the machine
243 * code buffer. This is an average of how many bytes of generated
244 * code come from a given bytecode in the baseline compiler.
245 */
246 private static final int CODE_EXPANSION_FACTOR = 12;
247
248 /**
249 * Heuristic constant used to calculate initial size of the machine
250 * code buffer. This is an estimate of the fixed method overhead
251 * code generated by the baseline compiler, such as method
252 * prologue.
253 */
254 private static final int CODE_OVERHEAD_TERM = 100;
255
256 /**
257 * Return the current offset in the generated code buffer of the
258 * end of the genertaed machine code.
259 *
260 * @return the end of the generated machine code.
261 */
262 public final int getMachineCodeIndex () {
263 return mi;
264 }
265
266 /**
267 * Set the given byte offset in the machine code array to the
268 * given byte value. This is the low-level function by which the
269 * assembler produces binary code into its machine code buffer.
270 * This function will resize the underlying machine code array if
271 * the index given exceeds the array's length.
272 *
273 * @param index the byte offset into which to write
274 * @param data the byte data value to write
275 */
276 @NoNullCheck
277 @NoBoundsCheck
278 protected final void setMachineCodes(int index, byte data) {
279 if(index < machineCodes.length) {
280 machineCodes[index] = data;
281 } else {
282 growMachineCodes(index, data);
283 }
284 }
285
286 @NoInline
287 private void growMachineCodes(int index, byte data) {
288 byte [] old = machineCodes;
289 machineCodes = new byte [2 * old.length ];
290 System.arraycopy(old, 0, machineCodes, 0, old.length);
291 machineCodes[index] = data;
292 }
293
294
295 /**
296 * Create a MachineCode object
297 */
298 public final ArchitectureSpecific.MachineCode finalizeMachineCode(int[] bytecodeMap) {
299 return new ArchitectureSpecific.MachineCode(getMachineCodes(), bytecodeMap);
300 }
301
302 /**
303 * Should code created by this assembler instance be allocated in the
304 * hot code code space? By default the answer is false (ie, no).
305 */
306 protected boolean isHotCode() { return false; }
307
308 /**
309 * Return a copy of the generated code as a CodeArray.
310 * @return a copy of the generated code as a CodeArray.
311 */
312 public final ArchitectureSpecific.CodeArray getMachineCodes () {
313 int len = getMachineCodeIndex();
314 ArchitectureSpecific.CodeArray trimmed = ArchitectureSpecific.CodeArray.Factory.create(len, isHotCode());
315 for (int i=0; i<len; i++) {
316 trimmed.set(i, machineCodes[i]);
317 }
318 return trimmed;
319 }
320
321 /**
322 * Give the lister a message associated with a particular
323 * bytecode. This is used by the baseline assembler to print the
324 * bytecode associated with portions of machine code. (The
325 * optimizing compiler does not do this because its association
326 * between bytecodes and generated code is much less direct).
327 *
328 * @param bytecodeNumber the offset of the current bytecode in the
329 * current method's bytecode array.
330 * @param bc a message descriptive of the current bytecode.
331 */
332 public final void noteBytecode (int bytecodeNumber, String bc) {
333 if (lister != null) lister.noteBytecode(bytecodeNumber, bc);
334 }
335
336 @NoInline
337 public final void noteBytecode (int i, String bcode, int x) {
338 noteBytecode(i, bcode+" "+x);
339 }
340
341 @NoInline
342 public final void noteBytecode (int i, String bcode, long x) {
343 noteBytecode(i, bcode+" "+x);
344 }
345
346 @NoInline
347 public final void noteBytecode (int i, String bcode, Object o) {
348 noteBytecode(i, bcode+" "+o);
349 }
350
351 @NoInline
352 public final void noteBytecode (int i, String bcode, int x, int y) {
353 noteBytecode(i, bcode+" "+x+" "+y);
354 }
355
356 @NoInline
357 public final void noteBranchBytecode (int i, String bcode, int off,
358 int bt) {
359 noteBytecode(i, bcode +" "+off+" ["+bt+"] ");
360 }
361
362 @NoInline
363 public final void noteTableswitchBytecode (int i, int l, int h, int d) {
364 noteBytecode(i, "tableswitch [" + l + "--" + h + "] " + d);
365 }
366
367 @NoInline
368 public final void noteLookupswitchBytecode (int i, int n, int d) {
369 noteBytecode(i, "lookupswitch [<" + n + ">]" + d);
370 }
371
372 /**
373 * Inform the lister of a comment related to the currently
374 * generated machine code.
375 *
376 * @param comment a comment string
377 */
378 public final void comment (String comment) {
379 if (lister != null) lister.comment(mi, comment);
380 }
381
382 /**
383 * Print the raw bits of the current instruction. It takes the
384 * start of the instruction as a parameter, and prints from that
385 * start to the current machine code index.
386 *
387 * @see #getMachineCodeIndex
388 *
389 * @param start the starting index of the last instruction.
390 */
391 public final void writeLastInstruction(int start) {
392 for (int j=start; j<mi; j++) {
393 if (j < machineCodes.length) {
394 VM.sysWrite(Lister.hex(machineCodes[j]));
395 } else {
396 VM.sysWrite(Lister.hex((byte)0x0));
397 }
398 }
399 }
400
401 /**
402 * Find out whether a given signed value can be represented in a
403 * given number of bits.
404 *
405 * @param val the value to be represented
406 * @param bits the number of bits to use.
407 * @return true if val can be encoded in bits.
408 */
409 @Inline
410 protected static boolean fits (Offset val, int bits) {
411 return fits(val.toWord(), bits);
412 }
413
414 /**
415 * Find out whether a given signed value can be represented in a
416 * given number of bits.
417 *
418 * @param val the value to be represented
419 * @param bits the number of bits to use.
420 * @return true if val can be encoded in bits.
421 */
422 @Inline
423 protected static boolean fits (Address val, int bits) {
424 return fits(val.toWord(), bits);
425 }
426
427 /**
428 * Find out whether a given signed value can be represented in a
429 * given number of bits.
430 *
431 * @param val the value to be represented
432 * @param bits the number of bits to use.
433 * @return true if val can be encoded in bits.
434 */
435 @Inline
436 protected static boolean fits (Word val, int bits) {
437 Word o = val.rsha(bits-1);
438 return (o.isZero() || o.isMax());
439 }
440
441 /**
442 * Find out whether a given signed value can be represented in a
443 * given number of bits.
444 *
445 * @param val the value to be represented
446 * @param bits the number of bits to use.
447 * @return true if val can be encoded in bits.
448 */
449 @Inline
450 protected static boolean fits (int val, int bits) {
451 val = val >> bits-1;
452 return (val == 0 || val == -1);
453 }
454
455 /**
456 * In the representation of addressing modes in the ModRM and SIB
457 * bytes, the code for register-displacement for on ESP has a
458 * special meaning. Thus, when register-displacement mode using ESP
459 * is desired, this special SIB (scale-index-base) byte must be
460 * emitted.
461 */
462 private static final byte SIBforESP = (byte) ((0<<6) + (4<<3) + ESP.value()); // (scale factor 1) no index, ESP is base
463
464 /**
465 * Generate a REX prefix if necessary
466 *
467 * @param W is a quad word override needed
468 * @param R_reg extension of the modrm field
469 * @param X_reg extension of the SIB index field
470 * @param B_reg extension of the modrm field, SIB base or opcode reg field
471 */
472 @Inline
473 private void generateREXprefix(boolean W, MachineRegister R_reg, MachineRegister X_reg, MachineRegister B_reg) {
474 boolean R = R_reg != null && R_reg.needsREXprefix();
475 boolean X = X_reg != null && X_reg.needsREXprefix();
476 boolean B = B_reg != null && B_reg.needsREXprefix();
477 if (W || R || X || B) {
478 if (VM.VerifyAssertions) VM._assert(!VM.buildFor32Addr());
479 byte prefixByte = (byte)(0x40 | (W ? 8 : 0) | (R ? 4 : 0) | (X ? 2 : 0) | (B ? 1 : 0));
480 setMachineCodes(mi++, prefixByte);
481 }
482 }
483
484 /**
485 * Return a ModRM byte encoding a source and destination register
486 * (i.e. for a register-register instruction).
487 *
488 * @param reg1 the r/m register.
489 * @param reg2 the other register or extended opcode.
490 * @return the encoded ModRM byte.
491 */
492 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
493 private byte regRegModRM(MachineRegister reg1, MachineRegister reg2) {
494 return (byte) ((3 << 6) | ((reg2.value() & 7) << 3) | (reg1.value() & 0x7));
495 }
496
497 /**
498 * Return a ModRM byte encoding a source register-32-bit-displacement
499 * operand and a destination register. Note that the displacement
500 * is handled separately, and not encoded in the ModRM itself.
501 *
502 * @param reg1 the r/m register.
503 * @param reg2 the other register or extended opcode.
504 * @return the encoded ModRM byte.
505 */
506 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
507 private byte regDisp32RegModRM(MachineRegister reg1, MachineRegister reg2) {
508 return (byte) ((2 << 6) | ((reg2.value() & 7)<< 3) | (reg1.value() & 7));
509 }
510
511 /**
512 * Return a ModRM byte encoding a source register-8-bit-displacement
513 * operand and a destination register. Note that the displacement
514 * is handled separately, and not encoded in the ModRM itself.
515 *
516 * @param reg1 the r/m register.
517 * @param reg2 the other register or extended opcode.
518 * @return the encoded ModRM byte.
519 */
520 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
521 private byte regDisp8RegModRM(MachineRegister reg1, MachineRegister reg2) {
522 return (byte) ((1 << 6) | ((reg2.value() & 7) << 3) | (reg1.value() & 7));
523 }
524
525 /**
526 * Return a ModRM byte encoding a source register-indirect
527 * operand and a destination register.
528 *
529 * @param reg1 the r/m register.
530 * @param reg2 the other register or extended opcode.
531 * @return the encoded ModRM byte.
532 */
533 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
534 private byte regIndirectRegModRM(MachineRegister reg1, MachineRegister reg2) {
535 return (byte) (((reg2.value() & 7) << 3) | (reg1.value() & 7));
536 }
537
538 /**
539 * The more complex IA32 addressing modes require a
540 * scale-index-base (SIB) byte. This is used to encode addressing
541 * modes such as [ indexReg \<\< scale + baseReg ]. This method
542 * encodes the SIB byte for a given base, index and scale.
543 *
544 * @param scale the shift amount for the index register value.
545 * @param baseReg the base register.
546 * @param indexReg the index register.
547 * @return the encoded SIB byte.
548 */
549 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2,3})
550 private byte sib(short scale, MachineRegister baseReg, MachineRegister indexReg) {
551 return (byte) ((scale << 6) | ((indexReg.value() & 7) << 3) | (baseReg.value() & 7));
552 }
553
554 /**
555 * Generate the appropriate bytes into the generated machine code
556 * to represent a register-register instruction.
557 *
558 * @param reg1 the r/m operand.
559 * @param reg2 the other register or extended opcode.
560 */
561 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
562 private void emitRegRegOperands(MachineRegister reg1, MachineRegister reg2) {
563 setMachineCodes(mi++, regRegModRM(reg1, reg2));
564 }
565
566 /**
567 * Generate the appropriate bytes into the generated machine code
568 * to represent a register-32-bit-displacement--register
569 * instruction. This method generates the appropriate ModRM, the SIB
570 * if needed for the ESP special case, and the little-endian encoded
571 * 32 bit displacement.
572 *
573 * @see #SIBforESP
574 *
575 * @param reg1 the r/m operand.
576 * @param disp the 32 bit displacement.
577 * @param reg2 the other register or extended opcode.
578 */
579 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
580 private void emitRegDisp32RegOperands(MachineRegister reg1, int disp, MachineRegister reg2) {
581 setMachineCodes(mi++, regDisp32RegModRM(reg1, reg2));
582 if (reg1 == ESP) setMachineCodes(mi++, SIBforESP);
583 emitImm32(disp);
584 }
585
586 /**
587 * Generate the appropriate bytes into the generated machine code
588 * to represent a register-8-bit-displacement--register
589 * instruction. This method generates the appropriate ModRM, the SIB
590 * if needed for the ESP special case, and the little-endian encoded
591 * 32 bit displacement.
592 *
593 * @see #SIBforESP
594 *
595 * @param reg1 the r/m operand.
596 * @param disp the 8 bit displacement.
597 * @param reg2 the other register or extended opcode.
598 */
599 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
600 private void emitRegDisp8RegOperands(MachineRegister reg1, byte disp, MachineRegister reg2) {
601 setMachineCodes(mi++, regDisp8RegModRM(reg1, reg2));
602 if (reg1 == ESP) setMachineCodes(mi++, SIBforESP);
603 emitImm8(disp);
604 }
605
606 /**
607 * Generate the appropriate bytes into the generated machine code
608 * to represent a register-displacement--register instruction. This
609 * method simply chooses the appropriate lower-level method based on
610 * displacement size
611 *
612 * @see #emitRegDisp32RegOperands
613 * @see #emitRegDisp8RegOperands
614 *
615 * @param reg1 the r/m operand.
616 * @param disp the displacement.
617 * @param reg2 the other register or extended opcode.
618 */
619 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
620 private void emitRegDispRegOperands(MachineRegister reg1, Offset disp, MachineRegister reg2) {
621 if (reg1 == GPR.EIP) {
622 setMachineCodes(mi++, regIndirectRegModRM(EBP, reg2)); // EBP == RIP addressing mode
623 emitImm32(disp);
624 } else if (fits(disp,8)) {
625 emitRegDisp8RegOperands(reg1, (byte)disp.toInt(), reg2);
626 } else {
627 if (VM.VerifyAssertions) VM._assert(fits(disp,32));
628 emitRegDisp32RegOperands(reg1, disp.toInt(), reg2);
629 }
630 }
631
632 /**
633 * Generate the appropriate bytes into the generated machine code
634 * to express a register-indirect--register instruction. This
635 * method handles low-level encoding issues, specifically the
636 * special cases for register indirect mode on ESP and EBP. Using
637 * ESP requires an SIB byte, and EBP cannot be used in indirect mode
638 * at all (that encoding is used to express scaled-index-displacement
639 * mode) so this method uses register-displacement with a 0
640 * displacement to fake it.
641 *
642 * @see #emitRegDispRegOperands
643 *
644 * @param reg1 the r/m operand
645 * @param reg2 the other register or extended opcode
646 */
647 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
648 private void emitRegIndirectRegOperands(MachineRegister reg1, MachineRegister reg2) {
649 if (reg1 == EBP) {
650 emitRegDispRegOperands(reg1, Offset.zero(), reg2);
651 } else {
652 setMachineCodes(mi++, regIndirectRegModRM(reg1, reg2));
653 if (reg1 == ESP) setMachineCodes(mi++, SIBforESP);
654 }
655 }
656
657 /**
658 * Generate the appropriate bytes into the generated code to denote
659 * a scaled-register+displacement--register instruction. This
660 * expresses the case where the SIB byte is used, but no base
661 * register is desired. This method handles the somewhat convoluted
662 * special case used to express this mode (the r/m register is 4/ESP and
663 * the base register must be 5/EBP).
664 *
665 * @param index the index register for the r/m operand
666 * @param scale the amount to shift the index register
667 * @param disp the displacement for the r/m operand
668 * @param reg2 the other operand or the extended opcode
669 */
670 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
671 private void emitRegOffRegOperands(MachineRegister index, short scale, Offset disp, MachineRegister reg2) {
672 setMachineCodes(mi++, regIndirectRegModRM(ESP, reg2));
673 setMachineCodes(mi++, sib(scale, EBP, index));
674 emitImm32(disp);
675 }
676
677 /**
678 * Generate the appropriate bytes into the generated code to denote
679 * an absolute-address--register instruction.
680 *
681 * @param disp the displacement for the r/m operand
682 * @param reg2 the other operand or the extended opcode
683 */
684 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
685 private void emitAbsRegOperands(Address disp, MachineRegister reg2) {
686 if (VM.buildFor32Addr()) {
687 setMachineCodes(mi++, regIndirectRegModRM(EBP, reg2)); // EBP == No displacement
688 } else {
689 setMachineCodes(mi++, regIndirectRegModRM(ESP, reg2)); // ESP == SIB byte
690 setMachineCodes(mi++, sib((short)0, EBP, ESP)); // EBP+ESP<<0 == no SIB
691 }
692 emitImm32(disp);
693 }
694
695 /**
696 * Generate the full glory of scaled-index-base-displacement
697 * addressing to the generated machine code. This method handles
698 * various special cases, mostly choosing the smallest displacement
699 * possible.
700 *
701 * @param base the base register for the r/m operand
702 * @param index the index register for the r/m operand
703 * @param scale the amount to shift the index register
704 * @param disp the displacement for the r/m operand
705 * @param reg2 the other operand or the extended opcode
706 */
707 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
708 private void emitSIBRegOperands(MachineRegister base, MachineRegister index, short scale, Offset disp, MachineRegister reg2) {
709 if (VM.VerifyAssertions) VM._assert(index != ESP);
710 if (disp.EQ(Offset.zero()) && base != EBP) {
711 setMachineCodes(mi++, regIndirectRegModRM(ESP, reg2));
712 setMachineCodes(mi++, sib(scale, base, index));
713 } else if (fits(disp,8)) {
714 setMachineCodes(mi++, regDisp8RegModRM(ESP, reg2));
715 setMachineCodes(mi++, sib(scale, base, index));
716 emitImm8((byte)disp.toInt());
717 } else {
718 setMachineCodes(mi++, regDisp32RegModRM(ESP, reg2));
719 setMachineCodes(mi++, sib(scale, base, index));
720 emitImm32(disp);
721 }
722 }
723
724 /**
725 * Generate the smallest-byte-first IA32 encoding of 32 bit
726 * immediates into the generated code.
727 *
728 * @param disp the displacement to generate.
729 */
730 @Inline
731 private void emitImm32(Offset disp) {
732 emitImm32(disp.toWord());
733 }
734
735 /**
736 * Generate the smallest-byte-first IA32 encoding of 32 bit
737 * immediates into the generated code.
738 *
739 * @param disp the displacement to generate.
740 */
741 @Inline
742 private void emitImm32(Address disp) {
743 emitImm32(disp.toWord());
744 }
745
746 /**
747 * Generate the smallest-byte-first IA32 encoding of 32 bit
748 * immediates into the generated code.
749 *
750 * @param disp the displacement to generate.
751 */
752 @Inline
753 private void emitImm32(Word disp) {
754 if (VM.VerifyAssertions) VM._assert(fits(disp,32));
755 mi = emitImm32(disp.toInt(), mi);
756 }
757
758 /**
759 * Generate the smallest-byte-first IA32 encoding of 32 bit
760 * immediates into the generated code.
761 *
762 * @param imm the immediate to generate.
763 */
764 @Inline
765 private void emitImm32(int imm) {
766 mi = emitImm32(imm, mi);
767 }
768
769 /**
770 * Generate the smallest-byte first x86_64 encoding of the 64 bit
771 * immeditate into the generated code.
772 *
773 * @param imm the immediate the generate;
774 */
775 @Inline
776 private void emitImm64(long imm) {
777 mi = emitImm64(imm, mi);
778 }
779
780 /**
781 * Generate the IA32 encoding of an 16 bit immediate into the
782 * generated code.
783 *
784 * @param imm the immediate to generate.
785 */
786 @Inline
787 private void emitImm16(int imm) {
788 mi = emitImm16(imm, mi);
789 }
790
791 /**
792 * Generate the IA32 encoding of an 8 bit immediate into the
793 * generated code.
794 *
795 * @param imm the immediate to generate.
796 */
797 @Inline
798 private void emitImm8(int imm) {
799 mi = emitImm8(imm, mi);
800 }
801
802 /**
803 * Generate the smallest-byte-first IA32 encoding of 16 bit
804 * immediates into the generated code at the location specified.
805 *
806 * @param imm the immediate to generate.
807 * @param idx the location in the generated code to write.
808 */
809 @Inline
810 private int emitImm16(int imm, int idx) {
811 setMachineCodes(idx++, (byte) ((imm >> 0) & 0xFF));
812 setMachineCodes(idx++, (byte) ((imm >> 8) & 0xFF));
813 return idx;
814 }
815
816 /**
817 * Generate the smallest-byte-first IA32 encoding of 32 bit
818 * immediate into the generated code at the location specified.
819 *
820 * @param imm the immediate to generate.
821 * @param idx the location in the generated code to write.
822 */
823 @Inline
824 private int emitImm32(int imm, int idx) {
825 setMachineCodes(idx++, (byte) ((imm >> 0) & 0xFF));
826 setMachineCodes(idx++, (byte) ((imm >> 8) & 0xFF));
827 setMachineCodes(idx++, (byte) ((imm >> 16) & 0xFF));
828 setMachineCodes(idx++, (byte) ((imm >> 24) & 0xFF));
829 return idx;
830 }
831
832 /**
833 * Generate the smallest-byte first x86_64 encoding of the 64 bit
834 * immeditate into the generated code at the location specified.
835 *
836 * @param imm the immediate the generate;
837 * @param idx the location in the generated code to write.
838 */
839 private int emitImm64(long imm, int idx) {
840 setMachineCodes(idx++, (byte) ((imm >> 0) & 0xFF));
841 setMachineCodes(idx++, (byte) ((imm >> 8) & 0xFF));
842 setMachineCodes(idx++, (byte) ((imm >> 16) & 0xFF));
843 setMachineCodes(idx++, (byte) ((imm >> 24) & 0xFF));
844 setMachineCodes(idx++, (byte) ((imm >> 32) & 0xFF));
845 setMachineCodes(idx++, (byte) ((imm >> 40) & 0xFF));
846 setMachineCodes(idx++, (byte) ((imm >> 48) & 0xFF));
847 setMachineCodes(idx++, (byte) ((imm >> 56) & 0xFF));
848 return idx;
849 }
850
851 /**
852 * Generate the IA32 encoding of an 8 bit immediate into the
853 * generated code at the location specified.
854 *
855 * @param imm the immediate to generate.
856 * @param idx the location in the generated code to write.
857 */
858 @Inline
859 private int emitImm8(int imm, int idx) {
860 setMachineCodes(idx++, (byte) imm);
861 return idx;
862 }
863
864 /**
865 * Generate a conditional opcode given the base opcode and the
866 * condition code desired. The CMOVcc, SETcc and Jcc families of
867 * instructions all have opcodes defined as a base opcode plus some
868 * bits representing the condition code. (of course, FCMOV does not
869 * this, since that would be too logical).
870 *
871 * @param opCode the base opcode to emit
872 * @param cond the condition code desired
873 */
874 @Inline
875 private void emitCondOpByte(byte opCode, byte cond) {
876 setMachineCodes(mi++, (byte) (opCode | cond));
877 }
878
879 /**
880 * Generate a locking prefix word into the generated code. Locking
881 * operations on IA32 are expressed by writing a locking byte before
882 * the instruction.
883 */
884 @Inline
885 public final void emitLockNextInstruction() {
886 setMachineCodes(mi++, (byte) 0xF0);
887 if (lister != null) lister.lockPrefix();
888 }
889
890 /**
891 * Generate a branch likely prefix into the generated code.
892 */
893 @Inline
894 public final void emitBranchLikelyNextInstruction() {
895 setMachineCodes(mi++, (byte) 0x3E);
896 if (lister != null) lister.branchLikelyPrefix();
897 }
898
899 /**
900 * Generate a branch unlikely prefix into the generated code.
901 */
902 @Inline
903 public final void emitBranchUnlikelyNextInstruction() {
904 setMachineCodes(mi++, (byte) 0x2E);
905 if (lister != null) lister.branchUnlikelyPrefix();
906 }
907
908 /**
909 * Generate a patch point into the generated code.
910 * (1) force patch point to be 32 bit aligned by optionally
911 * generating a nop.
912 * (2) emit a short branch (2 byte) around 3 bytes of nop.
913 * (3) If the the code is later patched, we first patch the 3
914 * nop bytes to be the upper 24 bits of a long jump
915 * instruction, then update the 2 bytes of the patch
916 * point to be an unconditional jump with a 32 bit immediate.
917 */
918 @Inline
919 public final void emitPatchPoint() {
920 emitNOP((4-mi-1) & 3);
921 ForwardReference r = forwardJMP();
922 emitNOP(3);
923 r.resolve(this);
924 }
925
926 /**
927 * Apply a patch.
928 * We expect the following instruction stream:
929 * i1; JMP rel8; NOP; NOP; NOP; i2;
930 * where patchOffset is the index of the last NOP.
931 * We patch it to be
932 * i1; JMP rel32; i2;
933 *
934 * @param code the code array to patch
935 * @param patchOffset the offset of the last byte of the patch point
936 * @param rel32 the new immediate to use in the branch instruction
937 * the code patcher is going to lay down before patchOffset
938 */
939 public static void patchCode(ArchitectureSpecific.CodeArray code, int patchOffset, int rel32) {
940 byte p0 = (byte)0xE9;
941 byte p1 = (byte) (rel32 & 0x000000ff);
942 byte p2 = (byte)((rel32 & 0x0000ff00) >>> 8);
943 byte p3 = (byte)((rel32 & 0x00ff0000) >>> 16);
944 byte p4 = (byte)((rel32 & 0xff000000) >>> 24);
945 if ((patchOffset & 0x2) == 0x2) {
946 // (a) lay down p4,p3,p2 one byte at a time
947 // (b) pick up the two bytes before p0 and then
948 // lay down b2b1p0p1 as a word.
949 code.set(patchOffset--, p4);
950 code.set(patchOffset--, p3);
951 code.set(patchOffset--, p2);
952 patchOffset -= 2; // skip over p1, p0
953 byte b1 = code.get(patchOffset--);
954 byte b2 = code.get(patchOffset);
955 int patch = (((int)p1&0xff) << 24) | (((int)p0&0xff) << 16) |
956 (((int)b1&0xff) << 8) | ((int)b2&0xff);
957 Magic.setIntAtOffset(code, Offset.fromIntSignExtend(patchOffset), patch);
958 } else {
959 // (a) lay down p4
960 // (b) lay down p0p1p2p3 as a word
961 code.set(patchOffset--, p4);
962 patchOffset -= 3; // skip over p0p1p2p3
963 int patch = (((int)p3&0xff) << 24) | (((int)p2&0xff) << 16) |
964 (((int)p1&0xff) << 8) | ((int)p0&0xff);
965 Magic.setIntAtOffset(code, Offset.fromIntSignExtend(patchOffset), patch);
966 }
967 }
968
969 /**
970 * Return the appropriate condition code if we want to
971 * reverse the sense of the branch
972 */
973 public final byte flipCode(byte cond) {
974 switch (cond) {
975 case EQ: return NE;
976 case NE: return EQ;
977 case LT: return GE;
978 case GT: return LE;
979 case LE: return GT;
980 case GE: return LT;
981 default: throw new InternalError("Unexpected condition code");
982 }
983 }
984
985 /**
986 * Generate a forward JMP instruction into the generated code.
987 * This form is used when the compiler wants to hang onto the
988 * forward reference object and call resolve on it directly. These
989 * forward references are not handled by the mechanism in the
990 * assembler; the client is responsible for calling resolve on the
991 * reference when generating the target instruction. The baseline
992 * compiler uses this form for jumps within the machine code for a
993 * single bytecode.
994 */
995 public final ForwardReference forwardJMP () {
996 int miStart = mi;
997 ForwardReference r = new ForwardReference.ShortBranch(mi);
998 setMachineCodes(mi++, (byte) 0xEB);
999 mi += 1; // leave space for displacement
1000 if (lister != null) lister.I(miStart, "JMP", 0);
1001 return r;
1002 }
1003
1004 /**
1005 * Generate a forward Jcc instruction into the generated code.
1006 * This form is used when the compiler wants to hang onto the
1007 * forward reference object and call resolve on it directly. These
1008 * forward references are not handled by the mechanism in the
1009 * assembler; the client is responsible for calling resolve on the
1010 * reference when generating the target instruction. The baseline
1011 * compiler uses this form for jumps within the machine code for a
1012 * single bytecode.
1013 *
1014 * @param cond the condition code on which to branch
1015 */
1016 public final ForwardReference forwardJcc (byte cond) {
1017 int miStart = mi;
1018 ForwardReference r = new ForwardReference.ShortBranch(mi);
1019 setMachineCodes(mi++, (byte) (0x70 + cond));
1020 mi += 1; // leave space for displacement
1021 if (lister != null) lister.I(miStart, "J" + CONDITION[cond], 0);
1022 return r;
1023 }
1024
1025 /**
1026 * The set of outstanding forward references. This list is used by
1027 * the assembler to keep track of all outstanding forward
1028 * references. References are put on this list by the emit methods
1029 * for JMP and Jcc when they find a branch that is going forward.
1030 * Each reference must understand what instruction it is looking for
1031 * and how to patch its source instruction. Then, when the client
1032 * calls resolveForwardBranches, the assembler searches this list to
1033 * find branches that match the instruction currently being
1034 * generated, and calls the resolve method on each one that does.
1035 *
1036 * All forward branches have a label as the branch target; clients
1037 * can arbirarily associate labels and instructions, but must be
1038 * consistent in giving the chosen label as the target of branches
1039 * to an instruction and calling resolveForwardBranches with the
1040 * given label immediately before emitting the target instruction.
1041 * See the header comments of ForwardReference for more details.
1042 */
1043 protected ForwardReference forwardRefs;
1044
1045 /**
1046 * Resolve all forward branches that have the given target, and
1047 * make them branch to the instruction currently being generated.
1048 * Clients of the assembler call this method immediately before they
1049 * emit the instruction intended to be the target of the given
1050 * label.
1051 *
1052 * All forward branches have a label as the branch target; clients
1053 * can arbirarily associate labels and instructions, but must be
1054 * consistent in giving the chosen label as the target of branches
1055 * to an instruction and calling resolveForwardBranches with the
1056 * given label immediately before emitting the target instruction.
1057 * See the header comments of ForwardReference for more details.
1058 *
1059 * @param label the forward branch label to resolve
1060 */
1061 public final void resolveForwardReferences (int label) {
1062 if (forwardRefs == null) return; // premature optimization
1063 forwardRefs = ForwardReference.resolveMatching(this, forwardRefs, label);
1064 }
1065
1066 /**
1067 * Set up a code sequence to push a return address. This involves pushing the
1068 * current instruction address, and setting up an ADD that gets resolved later.
1069 *
1070 * @param bReturn the return address that is to be loaded.
1071 */
1072 public final void generateLoadReturnAddress(int bReturn) {
1073 /* Push the IP */
1074 emitCALL_Imm(mi + 5);
1075 ForwardReference r = new ForwardReference.LoadReturnAddress(mi, bReturn);
1076 forwardRefs = ForwardReference.enqueue(forwardRefs, r);
1077 /* Fake MAX_INTEGER to ensure 32 bit immediate */
1078 emitADD_RegInd_Imm(ESP, Integer.MAX_VALUE);
1079 }
1080
1081 /**
1082 * Patch the code sequence at sourceIndex to load the complete instruction address
1083 * of the current instruction.
1084 *
1085 * @param sourceIndex the machine code offset of the load return addres to patch.
1086 */
1087 @Override
1088 public final void patchLoadReturnAddress(int sourceIndex) {
1089 /* We have the following pattern:
1090 * | PUSH EIP | [SP] += | IMM32 |
1091 * ^ ^
1092 * sourceIndex +3 */
1093 int ipDelta = mi - sourceIndex;
1094 emitImm32(ipDelta, sourceIndex + 3);
1095 }
1096
1097 /**
1098 * Generate a code sequence that will place the address of the start of the
1099 * method in destReg
1100 *
1101 * @param destReg register to hold address of start of method
1102 */
1103 public final void emitMETHODSTART_Reg(GPR destReg) {
1104 if (VM.buildFor32Addr()) {
1105 Offset pcThunkOffset;
1106 pcThunkOffset = OutOfLineMachineCode.pcThunkInstructionsField[destReg.value()].getOffset();
1107 emitCALL_Abs(Magic.getTocPointer().plus(pcThunkOffset));
1108 emitADD_Reg_Imm(destReg, -mi);
1109 } else {
1110 emitLEA_Reg_RegDisp_Quad(destReg, GPR.EIP, Offset.fromIntZeroExtend(Integer.MAX_VALUE));
1111 emitImm32(-mi, mi-4);
1112 }
1113 }
1114
1115 /**
1116 * Make a forward reference and emit a long JMP
1117 * @param btarget optional
1118 * @return a forward reference for patching later
1119 */
1120 public final ForwardReference generatePendingJMP(int btarget) {
1121 int miStart = mi;
1122 ForwardReference r = new ForwardReference.UnconditionalBranch(mi, btarget);
1123 setMachineCodes(mi++, (byte) 0xE9);
1124 mi += 4; // leave space for displacement
1125 if (lister != null) lister.I(miStart, "JMP", 0);
1126 return r;
1127 }
1128 // END OSR SUPPORT //
1129
1130 /**
1131 * Make the given unconditional branch branch to the current
1132 * generated instruction. It is the client's responsibility to
1133 * ensure the given source index really does contain an
1134 * unconditional branch.
1135 *
1136 * @param sourceIndex the machine code offset of the unconditional
1137 * branch to patch.
1138 */
1139 @Override
1140 public final void patchUnconditionalBranch (int sourceIndex) {
1141 if (VM.AlignmentChecking || isHotCode()) {
1142 // force 4byte alignment here
1143 emitNOP((4 - mi) & 3);
1144 }
1145 if (lister != null) lister.comefrom(mi, sourceIndex);
1146 int relOffset = mi - (sourceIndex+5);
1147 sourceIndex++; // skip the op code
1148 emitImm32(relOffset, sourceIndex);
1149 }
1150
1151 /**
1152 * Make the given conditional branch branch to the current
1153 * generated instruction. It is the client's responsibility to
1154 * ensure the given source index really does contain an
1155 * conditional branch.
1156 *
1157 * @param sourceIndex the machine code offset of the conditional
1158 * branch to patch.
1159 */
1160 @Override
1161 public final void patchConditionalBranch (int sourceIndex) {
1162 if (VM.AlignmentChecking || isHotCode()) {
1163 // force 4byte alignment here
1164 emitNOP((4 - mi) & 3);
1165 }
1166 if (lister != null) lister.comefrom(mi, sourceIndex);
1167 int relOffset = mi - (sourceIndex+6);
1168 sourceIndex += 2; // skip the (two byte) op code
1169 emitImm32(relOffset, sourceIndex);
1170 }
1171
1172 /**
1173 * Make the given unconditional branch branch to the current
1174 * generated instruction. It is the client's responsibility to
1175 * ensure the given source index really does contain an
1176 * unconditional branch. This instruction requires that the branch
1177 * have been generated with an 8 bit offset.
1178 *
1179 * @param sourceIndex the machine code offset of the unconditional
1180 * branch to patch.
1181 */
1182 public final void patchShortBranch (int sourceIndex) {
1183 if (VM.AlignmentChecking || isHotCode()) {
1184 // force 4byte alignment here
1185 emitNOP((4 - mi) & 3);
1186 }
1187 if (lister != null) lister.comefrom(mi, sourceIndex);
1188 int relOffset = mi - (sourceIndex+2);
1189 if (VM.VerifyAssertions) VM._assert(fits(relOffset, 8), "offset too large: "+relOffset);
1190 sourceIndex++; // skip the op code
1191 emitImm8((byte)relOffset, sourceIndex);
1192 }
1193
1194 /////////////////////////////////////
1195 // table switch support /////////////
1196 /////////////////////////////////////
1197
1198 /**
1199 * An OFFSET instruction is not really an instruction; it is rather
1200 * an address (of an instruction) that is written into the binary
1201 * code. These are used to build a table of addresses for table
1202 * switches. The code for tableswitches first calculates the address of the
1203 * start of the method. Using this address a branch relative to the start
1204 * of the method is computed by loading the offset from the start of the
1205 * method for a particular switch case. The OFFSET instruction is encoding
1206 * one value in the table.
1207 *
1208 * This mechanism assumes code for emitting tableswitch looks as
1209 * follows; it is not very nice, but is improved on X86 64 with the addition
1210 * of RIP displacement addressing. The GNU tools generate something.
1211 * Note that default cases must be handled separately. </P>
1212 *
1213 * <PRE>
1214 * T0 = getPCThunk() or RIP less offset from start of method
1215 * T0 += [T0 + m<<2 + tableDisplacement]
1216 * JMP T0
1217 * tableDisplacement:
1218 * OFFSET 0 (case 0 target)
1219 * OFFSET 1 (case 1 target)
1220 * ...
1221 * OFFSET n (case n target)
1222 * </PRE>
1223 *
1224 * @see #patchSwitchCase
1225 *
1226 * @param c the table entry being emitted (i.e. the value of the
1227 * switch expression corresponding to this target)
1228 * @param mTarget the method-relative target offset
1229 * @param bTarget the label associated with the branch target instrucion
1230 */
1231 public final void emitOFFSET_Imm_ImmOrLabel(int c, int mTarget, int bTarget) {
1232 int miStart = mi;
1233 if (0 < mTarget) { // resolved (backward) reference
1234 emitImm32(mTarget);
1235 if (lister != null) lister.I(miStart, "DATA", mTarget);
1236 } else { // unresolved forward reference
1237 ForwardReference r = new ForwardReference.SwitchCase(mi, bTarget);
1238 forwardRefs = ForwardReference.enqueue(forwardRefs, r);
1239 emitImm32(c);
1240 if (lister != null) lister.I(miStart, "DATA", c);
1241 }
1242 }
1243
1244 /**
1245 * Patch a tableswitch offset table entry at the given source
1246 * index. This method resolves the table entry at the given source
1247 * index to point to the current instruction plus an aligning NOP.
1248 *
1249 * @see #emitOFFSET_Imm_ImmOrLabel
1250 *
1251 * @param sourceIndex the location of the offset to patch
1252 */
1253 public final void patchSwitchCase (int sourceIndex) {
1254 if (VM.AlignmentChecking || isHotCode()) {
1255 // force 4byte alignment here
1256 emitNOP((4 - mi) & 3);
1257 }
1258 if (lister != null) lister.comefrom(mi, sourceIndex);
1259 int c = 0;
1260 c |= (machineCodes[sourceIndex+0] & 0xFF) << 0;
1261 c |= (machineCodes[sourceIndex+1] & 0xFF) << 8;
1262 c |= (machineCodes[sourceIndex+2] & 0xFF) << 16;
1263 c |= (machineCodes[sourceIndex+3] & 0xFF) << 24; // c = case index
1264 emitImm32(mi, sourceIndex); // write mi to sourceIndex
1265 }
1266
1267 /**
1268 * Patch the instruction that will load the displacement to the offset table
1269 * from the start of the method assuming that the next code to be created is
1270 * the offset table.
1271 *
1272 * @param toPatchAddress the address of the instruction that performs the
1273 * displacement load
1274 */
1275 public final void patchSwitchTableDisplacement(int toPatchAddress) {
1276 if (VM.buildFor32Addr()) {
1277 // the instruction to patch is an reg = [reg + idx<<scale + disp]
1278 emitImm32(mi, toPatchAddress+3);
1279 } else {
1280 // the instruction to patch is an reg = [reg + idx<<scale + disp]
1281 emitImm32(mi, toPatchAddress+3);
1282 }
1283 }
1284
1285 /////////////////////////////////////
1286 // instructions (hand coded) //
1287 /////////////////////////////////////
1288
1289 public final void emitMFENCE() {
1290 int miStart = mi;
1291 emitLockNextInstruction();
1292 emitADD_RegInd_Imm(ESP, 0);
1293 /**
1294 * The above has the same semantics, but with better performance as a true MFENCE:
1295 * setMachineCodes(mi++,(byte) 0x0F);
1296 * setMachineCodes(mi++,(byte) 0xAE);
1297 * setMachineCodes(mi++,(byte) 0xF0);
1298 * if (lister != null) lister.OP(miStart, "MFENCE");
1299 */
1300 }
1301
1302 /**
1303 * Generate a bswap on a register. That is,
1304 * <PRE>
1305 * bswap reg
1306 * </PRE>
1307 *
1308 * @param reg register to operate upon
1309 */
1310 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
1311 public final void emitBSWAP_Reg(GPR reg) {
1312 int miStart = mi;
1313 generateREXprefix(false, null, null, reg);
1314 setMachineCodes(mi++, (byte) 0x0F);
1315 setMachineCodes(mi++, (byte) (0xC8 | (reg.value() & 7)));
1316 if (lister != null) lister.R(miStart, "bswap", reg);
1317 }
1318
1319 /**
1320 * Generate a bswap on a quad register. That is,
1321 * <PRE>
1322 * bswap reg
1323 * </PRE>
1324 *
1325 * @param reg register to operate upon
1326 */
1327 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
1328 public final void emitBSWAP_Reg_Quad(GPR reg) {
1329 int miStart = mi;
1330 generateREXprefix(true, null, null, reg);
1331 setMachineCodes(mi++, (byte) 0x0F);
1332 setMachineCodes(mi++, (byte) (0xC8 | (reg.value() & 7)));
1333 if (lister != null) lister.R(miStart, "bswap", reg);
1334 }
1335
1336 /**
1337 * Conditionally move the source to the destination, i.e.
1338 * <PRE>
1339 * if (cond) dst = src
1340 * </PRE>
1341 */
1342 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2,3})
1343 public final void emitCMOV_Cond_Reg_Reg(byte cond, GPR dst, GPR src) {
1344 int miStart = mi;
1345 generateREXprefix(false, dst, null, src);
1346 setMachineCodes(mi++, (byte) 0x0F);
1347 emitCondOpByte((byte)0x40, cond);
1348 emitRegRegOperands(src, dst);
1349 if (lister != null) lister.RR(miStart, "CMOV" + CONDITION[cond], dst, src);
1350 }
1351
1352 /**
1353 * Conditionally move the source to the destination, i.e.
1354 * <PRE>
1355 * if (cond) dst = [src + disp]
1356 * </PRE>
1357 */
1358 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2,3})
1359 public final void emitCMOV_Cond_Reg_RegDisp(byte cond, GPR dst, GPR src, Offset disp) {
1360 int miStart = mi;
1361 generateREXprefix(false, dst, null, src);
1362 setMachineCodes(mi++, (byte) 0x0F);
1363 emitCondOpByte((byte)0x40, cond);
1364 emitRegDispRegOperands(src, disp, dst);
1365 if (lister != null) lister.RRD(miStart, "CMOV" + CONDITION[cond], dst, src, disp);
1366 }
1367
1368 /**
1369 * Conditionally move the source to the destination, i.e.
1370 * <PRE>
1371 * if (cond) dst = [src]
1372 * </PRE>
1373 */
1374 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2,3})
1375 public final void emitCMOV_Cond_Reg_RegInd(byte cond, GPR dst, GPR src) {
1376 int miStart = mi;
1377 generateREXprefix(false, dst, null, src);
1378 setMachineCodes(mi++, (byte) 0x0F);
1379 emitCondOpByte((byte)0x40, cond);
1380 emitRegIndirectRegOperands(src, dst);
1381 if (lister != null) lister.RRN(miStart, "CMOV" + CONDITION[cond], dst, src);
1382 }
1383
1384 /**
1385 * Conditionally move the source to the destination, i.e.
1386 * <PRE>
1387 * if (cond) dst = [index2<<scale2 + disp2]
1388 * </PRE>
1389 */
1390 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2,3})
1391 public final void emitCMOV_Cond_Reg_RegOff(byte cond, GPR dst, GPR index2, short scale2, Offset disp2) {
1392 int miStart = mi;
1393 generateREXprefix(false, dst, index2, null);
1394 setMachineCodes(mi++, (byte) 0x0F);
1395 emitCondOpByte((byte)0x40, cond);
1396 emitRegOffRegOperands(index2, scale2, disp2, dst);
1397 if (lister != null) lister.RRFD(miStart, "CMOV" + CONDITION[cond], dst, index2, scale2, disp2);
1398 }
1399
1400 /**
1401 * Conditionally move the source to the destination, i.e.
1402 * <PRE>
1403 * if (cond) dst = [disp2]
1404 * </PRE>
1405 */
1406 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
1407 public final void emitCMOV_Cond_Reg_Abs(byte cond, GPR dst, Address disp2) {
1408 int miStart = mi;
1409 generateREXprefix(false, dst, null, null);
1410 setMachineCodes(mi++, (byte) 0x0F);
1411 emitCondOpByte((byte)0x40, cond);
1412 emitAbsRegOperands(disp2, dst);
1413 if (lister != null) lister.RRA(miStart, "CMOV" + CONDITION[cond], dst, disp2);
1414 }
1415
1416 /**
1417 * Conditionally move the source to the destination, i.e.
1418 * <PRE>
1419 * if (cond) dst = [base2 + index2<<scale2 + disp2]
1420 * </PRE>
1421 */
1422 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2,3,4})
1423 public final void emitCMOV_Cond_Reg_RegIdx(byte cond, GPR dst, GPR base2, GPR index2, short scale2, Offset disp2) {
1424 int miStart = mi;
1425 generateREXprefix(false, dst, index2, base2);
1426 setMachineCodes(mi++, (byte) 0x0F);
1427 emitCondOpByte((byte)0x40, cond);
1428 emitSIBRegOperands(base2, index2, scale2, disp2, dst);
1429 if (lister != null) lister.RRXD(miStart, "CMOV" + CONDITION[cond], dst, base2, index2, scale2, disp2);
1430 }
1431
1432 /**
1433 * Set destination to zero or one, if the given condition is false
1434 * or true, respectively. That is,
1435 * <PRE>
1436 * dst = (cond)? 1: 0
1437 * </PRE>
1438 *
1439 * @param cond the condition to be tested
1440 * @param dst the destination register
1441 */
1442 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
1443 public final void emitSET_Cond_Reg_Byte(byte cond, GPR dst) {
1444 int miStart = mi;
1445 generateREXprefix(false, null, null, dst);
1446 setMachineCodes(mi++, (byte) 0x0F);
1447 emitCondOpByte((byte)0x90, cond);
1448 emitRegRegOperands(dst, EAX /* UNUSED */);
1449 if (lister != null) lister.R(miStart, "SET" + CONDITION[cond], dst);
1450 }
1451
1452 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
1453 public final void emitSET_Cond_RegDisp_Byte(byte cond, GPR dst, Offset disp) {
1454 int miStart = mi;
1455 generateREXprefix(false, null, null, dst);
1456 setMachineCodes(mi++, (byte) 0x0F);
1457 emitCondOpByte((byte)0x90, cond);
1458 emitRegDispRegOperands(dst, disp, EAX /* UNUSED */);
1459 if (lister != null) lister.RD(miStart, "SET" + CONDITION[cond], dst, disp);
1460 }
1461
1462 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
1463 public final void emitSET_Cond_RegInd_Byte(byte cond, GPR dst) {
1464 int miStart = mi;
1465 generateREXprefix(false, null, null, dst);
1466 setMachineCodes(mi++, (byte) 0x0F);
1467 emitCondOpByte((byte)0x90, cond);
1468 emitRegIndirectRegOperands(dst, EAX /* UNUSED */);
1469 if (lister != null) lister.RN(miStart, "SET" + CONDITION[cond], dst);
1470 }
1471
1472 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2,3})
1473 public final void emitSET_Cond_RegIdx_Byte(byte cond, GPR base, GPR index, short scale, Offset disp) {
1474 int miStart = mi;
1475 generateREXprefix(false, null, index, base);
1476 setMachineCodes(mi++, (byte) 0x0F);
1477 emitCondOpByte((byte)0x90, cond);
1478 emitSIBRegOperands(base, index, scale, disp, EAX /* UNUSED */);
1479 if (lister != null) lister.RXD(miStart, "SET" + CONDITION[cond], base, index, scale, disp);
1480 }
1481
1482 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
1483 public final void emitSET_Cond_RegOff_Byte(byte cond, GPR index, short scale, Offset disp) {
1484 int miStart = mi;
1485 generateREXprefix(false, null, index, null);
1486 setMachineCodes(mi++, (byte) 0x0F);
1487 emitCondOpByte((byte)0x90, cond);
1488 emitRegOffRegOperands(index, scale, disp, EAX /* UNUSED */);
1489 if (lister != null) lister.RFD(miStart, "SET" + CONDITION[cond], index, scale, disp);
1490 }
1491
1492 @Inline
1493 public final void emitSET_Cond_Abs_Byte(byte cond, Address disp) {
1494 int miStart = mi;
1495 generateREXprefix(false, null, null, null);
1496 setMachineCodes(mi++, (byte) 0x0F);
1497 emitCondOpByte((byte)0x90, cond);
1498 emitAbsRegOperands(disp, EAX /* UNUSED */);
1499 if (lister != null) lister.RA(miStart, "SET" + CONDITION[cond], disp);
1500 }
1501
1502 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1503 public final void emitIMUL2_Reg_Reg(GPR dstReg, GPR srcReg) {
1504 int miStart = mi;
1505 generateREXprefix(false, dstReg, null, srcReg);
1506 setMachineCodes(mi++, (byte) 0x0F);
1507 setMachineCodes(mi++, (byte) 0xAF);
1508 emitRegRegOperands(srcReg, dstReg);
1509 if (lister != null) lister.RR(miStart, "IMUL", dstReg, srcReg);
1510 }
1511
1512 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1513 public final void emitIMUL2_Reg_RegInd(GPR dstReg, GPR srcBase) {
1514 int miStart = mi;
1515 generateREXprefix(false, dstReg, null, srcBase);
1516 setMachineCodes(mi++, (byte) 0x0F);
1517 setMachineCodes(mi++, (byte) 0xAF);
1518 emitRegIndirectRegOperands(srcBase, dstReg);
1519 if (lister != null) lister.RRN(miStart, "IMUL", dstReg, srcBase);
1520 }
1521
1522 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1523 public final void emitIMUL2_Reg_RegDisp(GPR dstReg, GPR srcBase, Offset srcDisp) {
1524 int miStart = mi;
1525 generateREXprefix(false, dstReg, null, srcBase);
1526 setMachineCodes(mi++, (byte) 0x0F);
1527 setMachineCodes(mi++, (byte) 0xAF);
1528 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
1529 if (lister != null) lister.RRD(miStart, "IMUL", dstReg, srcBase, srcDisp);
1530 }
1531
1532 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1533 public final void emitIMUL2_Reg_RegOff(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
1534 int miStart = mi;
1535 generateREXprefix(false, dstReg, srcIndex, null);
1536 setMachineCodes(mi++, (byte) 0x0F);
1537 setMachineCodes(mi++, (byte) 0xAF);
1538 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
1539 if (lister != null) lister.RRFD(miStart, "IMUL", dstReg, srcIndex, srcScale, srcDisp);
1540 }
1541
1542 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
1543 public final void emitIMUL2_Reg_Abs(GPR dstReg, Address srcDisp) {
1544 int miStart = mi;
1545 generateREXprefix(false, dstReg, null, null);
1546 setMachineCodes(mi++, (byte) 0x0F);
1547 setMachineCodes(mi++, (byte) 0xAF);
1548 emitAbsRegOperands(srcDisp, dstReg);
1549 if (lister != null) lister.RRA(miStart, "IMUL", dstReg, srcDisp);
1550 }
1551
1552 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1553 public final void emitIMUL2_Reg_RegIdx(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
1554 int miStart = mi;
1555 generateREXprefix(false, dstReg, srcIndex, srcBase);
1556 setMachineCodes(mi++, (byte) 0x0F);
1557 setMachineCodes(mi++, (byte) 0xAF);
1558 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
1559 if (lister != null) lister.RRXD(miStart, "IMUL", dstReg, srcBase, srcIndex, srcScale, srcDisp);
1560 }
1561
1562 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
1563 public final void emitIMUL2_Reg_Imm(GPR dstReg, int imm) {
1564 int miStart = mi;
1565 generateREXprefix(false, dstReg, null, null);
1566 if (fits(imm,8)) {
1567 setMachineCodes(mi++, (byte) 0x6B);
1568 emitRegRegOperands(dstReg, dstReg);
1569 emitImm8((byte)imm);
1570 } else {
1571 setMachineCodes(mi++, (byte) 0x69);
1572 emitRegRegOperands(dstReg, dstReg);
1573 emitImm32(imm);
1574 }
1575 if (lister != null) lister.RI(miStart, "IMUL", dstReg, imm);
1576 }
1577
1578 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1579 public final void emitIMUL2_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
1580 int miStart = mi;
1581 generateREXprefix(true, dstReg, null, srcReg);
1582 setMachineCodes(mi++, (byte) 0x0F);
1583 setMachineCodes(mi++, (byte) 0xAF);
1584 emitRegRegOperands(srcReg, dstReg);
1585 if (lister != null) lister.RR(miStart, "IMUL", dstReg, srcReg);
1586 }
1587
1588 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1589 public final void emitIMUL2_Reg_RegInd_Quad(GPR dstReg, GPR srcBase) {
1590 int miStart = mi;
1591 generateREXprefix(true, dstReg, null, srcBase);
1592 setMachineCodes(mi++, (byte) 0x0F);
1593 setMachineCodes(mi++, (byte) 0xAF);
1594 emitRegIndirectRegOperands(srcBase, dstReg);
1595 if (lister != null) lister.RRN(miStart, "IMUL", dstReg, srcBase);
1596 }
1597
1598 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1599 public final void emitIMUL2_Reg_RegDisp_Quad(GPR dstReg, GPR srcBase, Offset srcDisp) {
1600 int miStart = mi;
1601 generateREXprefix(true, dstReg, null, srcBase);
1602 setMachineCodes(mi++, (byte) 0x0F);
1603 setMachineCodes(mi++, (byte) 0xAF);
1604 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
1605 if (lister != null) lister.RRD(miStart, "IMUL", dstReg, srcBase, srcDisp);
1606 }
1607
1608 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1609 public final void emitIMUL2_Reg_RegOff_Quad(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
1610 int miStart = mi;
1611 generateREXprefix(true, dstReg, srcIndex, null);
1612 setMachineCodes(mi++, (byte) 0x0F);
1613 setMachineCodes(mi++, (byte) 0xAF);
1614 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
1615 if (lister != null) lister.RRFD(miStart, "IMUL", dstReg, srcIndex, srcScale, srcDisp);
1616 }
1617
1618 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
1619 public final void emitIMUL2_Reg_Abs_Quad(GPR dstReg, Address srcDisp) {
1620 int miStart = mi;
1621 generateREXprefix(true, dstReg, null, null);
1622 setMachineCodes(mi++, (byte) 0x0F);
1623 setMachineCodes(mi++, (byte) 0xAF);
1624 emitAbsRegOperands(srcDisp, dstReg);
1625 if (lister != null) lister.RRA(miStart, "IMUL", dstReg, srcDisp);
1626 }
1627
1628 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1629 public final void emitIMUL2_Reg_RegIdx_Quad(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
1630 int miStart = mi;
1631 generateREXprefix(true, dstReg, srcIndex, srcBase);
1632 setMachineCodes(mi++, (byte) 0x0F);
1633 setMachineCodes(mi++, (byte) 0xAF);
1634 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
1635 if (lister != null) lister.RRXD(miStart, "IMUL", dstReg, srcBase, srcIndex, srcScale, srcDisp);
1636 }
1637
1638 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
1639 public final void emitIMUL2_Reg_Imm_Quad(GPR dstReg, int imm) {
1640 int miStart = mi;
1641 generateREXprefix(true, dstReg, null, null);
1642 if (fits(imm,8)) {
1643 setMachineCodes(mi++, (byte) 0x6B);
1644 emitRegRegOperands(dstReg, dstReg);
1645 emitImm8((byte)imm);
1646 } else {
1647 setMachineCodes(mi++, (byte) 0x69);
1648 emitRegRegOperands(dstReg, dstReg);
1649 emitImm32(imm);
1650 }
1651 if (lister != null) lister.RI(miStart, "IMUL", dstReg, imm);
1652 }
1653
1654 // trap
1655 public final void emitINT_Imm (int v) {
1656 if (VM.VerifyAssertions) VM._assert(v <= 0xFF);
1657 int miStart = mi;
1658 if (v == 3) { // special case interrupt
1659 setMachineCodes(mi++, (byte) 0xCC);
1660 } else {
1661 setMachineCodes(mi++, (byte) 0xCD);
1662 setMachineCodes(mi++, (byte) v);
1663 }
1664 if (lister != null) lister.I(miStart, "INT", v);
1665 }
1666
1667 /**
1668 * Conditionally branch to the given target, i.e.
1669 * <PRE>
1670 * if (cond) then IP = (instruction @ label)
1671 * </PRE>
1672 *
1673 * This emit method is expecting only a forward branch (that is
1674 * what the Label operand means); it creates a ForwardReference
1675 * to the given label, and puts it into the assembler's list of
1676 * references to resolve. This emiiter knows it emits conditional
1677 * branches, so it uses ForwardReference.ConditionalBranch as the
1678 * forward reference type to create.
1679 *
1680 * All forward branches have a label as the branch target; clients
1681 * can arbirarily associate labels and instructions, but must be
1682 * consistent in giving the chosen label as the target of branches
1683 * to an instruction and calling resolveForwardBranches with the
1684 * given label immediately before emitting the target instruction.
1685 * See the header comments of ForwardReference for more details.
1686 *
1687 * @param cond the IA32 ISA condition code bits to mask into opcode
1688 * @param label the label associated with the branch target instrucion
1689 *
1690 * @see org.jikesrvm.compilers.common.assembler.ForwardReference.ConditionalBranch
1691 */
1692 public final void emitJCC_Cond_Label (byte cond, int label) {
1693 int miStart = mi;
1694 ForwardReference r = new ForwardReference.ConditionalBranch(mi, label);
1695 forwardRefs = ForwardReference.enqueue(forwardRefs, r);
1696 setMachineCodes(mi++, (byte) 0x0F);
1697 setMachineCodes(mi++, (byte) (0x80 + cond));
1698 mi += 4; // leave space for displacement TODO!! handle short branches
1699 if (lister != null) lister.I(miStart, "J" + CONDITION[cond], label);
1700 }
1701
1702 /**
1703 * Conditionally branch to the given target, i.e.
1704 * <PRE>
1705 * if (cond) then IP = mTarget
1706 * </PRE>
1707 *
1708 * This emit method emits only backward branches (that is what
1709 * branching to an Imm operand means), so it simply writes the
1710 * appropriate binary code without bothering with the forward
1711 * reference mechanism.
1712 *
1713 * @param cond the IA32 ISA condition code bits to mask into opcode
1714 * @param mTarget the method-relative target offset
1715 */
1716 public final void emitJCC_Cond_Imm (byte cond, int mTarget) {
1717 int miStart = mi;
1718 int relOffset = mTarget - (mi + 1 + 1); // address relative to next instruction
1719 if (fits(relOffset, 8)) {
1720 emitCondOpByte((byte)0x70, cond);
1721 emitImm8((byte)relOffset);
1722 } else {
1723 setMachineCodes(mi++, (byte) 0x0F);
1724 emitCondOpByte((byte)0x80, cond);
1725 relOffset = mTarget - (mi + 4); // address relative to next instruction
1726 emitImm32(relOffset);
1727 }
1728 if (lister != null) lister.I(miStart, "J" + CONDITION[cond], relOffset);
1729 }
1730
1731 /**
1732 * Conditionally branch to the given target, i.e.
1733 * <PRE>
1734 * if (cond) then IP = mTarget -or- (instruction @ bTarget)
1735 * </PRE>
1736 *
1737 * This emit method represents a branch that could be either
1738 * forward or backward; it simply calls either the Label or Imm
1739 * emit method.
1740 *
1741 * @see #emitJCC_Cond_Label
1742 * @see #emitJCC_Cond_Imm
1743 *
1744 * @param cond the IA32 ISA condition code bits to mask into opcode
1745 * @param mTarget the method-relative target offset
1746 * @param bTarget the label associated with the branch target instrucion
1747 */
1748 public final void emitJCC_Cond_ImmOrLabel (byte cond, int mTarget, int bTarget) {
1749 if (mTarget == 0) { // forward branch
1750 emitJCC_Cond_Label(cond, bTarget);
1751 } else { // backward branch
1752 emitJCC_Cond_Imm(cond, mTarget);
1753 }
1754 }
1755
1756 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1757 public final void emitLEA_Reg_RegDisp(GPR dstReg, GPR srcBase, Offset srcDisp) {
1758 int miStart = mi;
1759 generateREXprefix(false, dstReg, null, srcBase);
1760 setMachineCodes(mi++, (byte) 0x8D);
1761 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
1762 if (lister != null) lister.RRD(miStart, "LEA", dstReg, srcBase, srcDisp);
1763 }
1764
1765 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1766 public final void emitLEA_Reg_RegInd(GPR dstReg, GPR srcBase) {
1767 int miStart = mi;
1768 generateREXprefix(false, dstReg, null, srcBase);
1769 setMachineCodes(mi++, (byte) 0x8D);
1770 emitRegIndirectRegOperands(srcBase, dstReg);
1771 if (lister != null) lister.RRN(miStart, "LEA", dstReg, srcBase);
1772 }
1773
1774 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1775 public final void emitLEA_Reg_RegOff(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
1776 int miStart = mi;
1777 generateREXprefix(false, dstReg, srcIndex, null);
1778 setMachineCodes(mi++, (byte) 0x8D);
1779 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
1780 if (lister != null) lister.RRFD(miStart, "LEA", dstReg, srcIndex, srcScale, srcDisp);
1781 }
1782
1783 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1784 public final void emitLEA_Reg_Abs(GPR dstReg, Address srcDisp) {
1785 int miStart = mi;
1786 generateREXprefix(false, dstReg, null, null);
1787 setMachineCodes(mi++, (byte) 0x8D);
1788 emitAbsRegOperands(srcDisp, dstReg);
1789 if (lister != null) lister.RRA(miStart, "LEA", dstReg, srcDisp);
1790 }
1791
1792 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1793 public final void emitLEA_Reg_RegIdx(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
1794 int miStart = mi;
1795 generateREXprefix(false, dstReg, srcIndex, srcBase);
1796 setMachineCodes(mi++, (byte) 0x8D);
1797 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
1798 if (lister != null) lister.RRXD(miStart, "LEA", dstReg, srcBase, srcIndex, srcScale, srcDisp);
1799 }
1800
1801 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1802 public final void emitLEA_Reg_RegDisp_Quad(GPR dstReg, GPR srcBase, Offset srcDisp) {
1803 int miStart = mi;
1804 generateREXprefix(true, dstReg, null, srcBase);
1805 setMachineCodes(mi++, (byte) 0x8D);
1806 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
1807 if (lister != null) lister.RRD(miStart, "LEA", dstReg, srcBase, srcDisp);
1808 }
1809
1810 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1811 public final void emitLEA_Reg_RegInd_Quad(GPR dstReg, GPR srcBase) {
1812 int miStart = mi;
1813 generateREXprefix(true, dstReg, null, srcBase);
1814 setMachineCodes(mi++, (byte) 0x8D);
1815 emitRegIndirectRegOperands(srcBase, dstReg);
1816 if (lister != null) lister.RRN(miStart, "LEA", dstReg, srcBase);
1817 }
1818
1819 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1820 public final void emitLEA_Reg_RegOff_Quad(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
1821 int miStart = mi;
1822 generateREXprefix(true, dstReg, srcIndex, null);
1823 setMachineCodes(mi++, (byte) 0x8D);
1824 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
1825 if (lister != null) lister.RRFD(miStart, "LEA", dstReg, srcIndex, srcScale, srcDisp);
1826 }
1827
1828 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1829 public final void emitLEA_Reg_Abs_Quad(GPR dstReg, Address srcDisp) {
1830 int miStart = mi;
1831 generateREXprefix(true, dstReg, null, null);
1832 setMachineCodes(mi++, (byte) 0x8D);
1833 emitAbsRegOperands(srcDisp, dstReg);
1834 if (lister != null) lister.RRA(miStart, "LEA", dstReg, srcDisp);
1835 }
1836
1837 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
1838 public final void emitLEA_Reg_RegIdx_Quad(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
1839 int miStart = mi;
1840 generateREXprefix(true, dstReg, srcIndex, srcBase);
1841 setMachineCodes(mi++, (byte) 0x8D);
1842 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
1843 if (lister != null) lister.RRXD(miStart, "LEA", dstReg, srcBase, srcIndex, srcScale, srcDisp);
1844 }
1845
1846 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
1847 public final void emitMOV_Reg_Imm(GPR dstReg, int imm) {
1848 int miStart = mi;
1849 generateREXprefix(false, null, null, dstReg);
1850 setMachineCodes(mi++, (byte) (0xB8 | dstReg.value()));
1851 emitImm32(imm);
1852 if (lister != null) lister.RI(miStart, "MOV", dstReg, imm);
1853 }
1854
1855 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
1856 public final void emitMOV_Reg_Imm_Quad(GPR dstReg, long imm) {
1857 int miStart = mi;
1858 generateREXprefix(true, null, null, dstReg);
1859 setMachineCodes(mi++, (byte) (0xB8 | dstReg.value()));
1860 emitImm64(imm);
1861 if (lister != null) lister.RI(miStart, "MOV", dstReg, imm);
1862 }
1863
1864 /** pop address and goto it */
1865 public final void emitRET () {
1866 int miStart = mi;
1867 setMachineCodes(mi++, (byte) 0xC3);
1868 if (lister != null) lister.OP(miStart, "RET");
1869 }
1870
1871 /** pop address and goto it, pop parameterBytes additional bytes */
1872 public final void emitRET_Imm (int parameterBytes) {
1873 int miStart = mi;
1874 if (parameterBytes == 0) {
1875 setMachineCodes(mi++, (byte) 0xC3);
1876 if (lister != null) lister.OP(miStart, "RET");
1877 } else {
1878 setMachineCodes(mi++, (byte) 0xC2);
1879 emitImm16(parameterBytes);
1880 if (VM.VerifyAssertions) VM._assert ((parameterBytes & 0xffff0000) == 0);
1881 if (lister != null) lister.I(miStart, "RET", parameterBytes);
1882 }
1883 }
1884
1885 /** allocate stack frame for procedure */
1886 public final void emitENTER_Imm (int frameSize) {
1887 int miStart = mi;
1888 setMachineCodes(mi++, (byte) 0xC8);
1889 emitImm16(frameSize);
1890 setMachineCodes(mi++, (byte) 0x0);
1891 if (lister != null) lister.I(miStart, "ENTER", frameSize);
1892 }
1893
1894 /** sign extends EAX into EDX */
1895 public final void emitCDQ () {
1896 int miStart = mi;
1897 setMachineCodes(mi++, (byte)0x99);
1898 if (lister != null) lister.OP(miStart, "CDQ");
1899 }
1900
1901 /** sign extends RAX into RDX */
1902 public final void emitCDO () {
1903 int miStart = mi;
1904 generateREXprefix(true, null, null, null);
1905 setMachineCodes(mi++, (byte)0x99);
1906 if (lister != null) lister.OP(miStart, "CDO");
1907 }
1908
1909 /** sign extends EAX into RDX */
1910 public final void emitCDQE () {
1911 int miStart = mi;
1912 generateREXprefix(true, null, null, null);
1913 setMachineCodes(mi++, (byte)0x98);
1914 if (lister != null) lister.OP(miStart, "CDQE");
1915 }
1916
1917 /**
1918 * Read time stamp into edx:eax, on Linux this appears to be unprivileged.
1919 * <pre>
1920 * edx:eax <- time stamp counter
1921 * </pre>
1922 */
1923 public final void emitRDTSC() {
1924 int miStart = mi;
1925 setMachineCodes(mi++, (byte) 0x0F);
1926 setMachineCodes(mi++, (byte) 0x31);
1927 if (lister != null) lister.OP(miStart, "RDTSC");
1928 }
1929
1930 /** software prefetch */
1931 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
1932 public final void emitPREFETCHNTA_Reg(GPR srcReg) {
1933 int miStart = mi;
1934 setMachineCodes(mi++, (byte) 0x0F);
1935 setMachineCodes(mi++,(byte) 0x18);
1936 emitRegIndirectRegOperands(srcReg, GPR.getForOpcode(0));
1937 if (lister != null) lister.R(miStart, "PREFETCHNTA", srcReg);
1938 }
1939
1940 /** Suggest to process that a a compare for a spin lock has just failed */
1941 public final void emitPAUSE () {
1942 int miStart = mi;
1943 setMachineCodes(mi++, (byte) 0xF3);
1944 setMachineCodes(mi++,(byte) 0x90);
1945 if (lister != null) lister.OP(miStart, "PAUSE");
1946 }
1947
1948 /**
1949 * Compare and exchange 8 bytes
1950 * <PRE>
1951 * cmpxchg8b [dst + disp]
1952 * </PRE>
1953 */
1954 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
1955 public final void emitCMPXCHG8B_RegDisp(GPR base, Offset disp) {
1956 int miStart = mi;
1957 generateREXprefix(false, null, null, base);
1958 setMachineCodes(mi++, (byte) 0x0F);
1959 setMachineCodes(mi++, (byte) 0xC7);
1960 emitRegDispRegOperands(base, disp, GPR.getForOpcode(1));
1961 if (lister != null) lister.RD(miStart, "CMPXCHG8B" , base, disp);
1962 }
1963
1964 /**
1965 * Compare and exchange 8 bytes
1966 * <PRE>
1967 * cmpxchg8b [dst]
1968 * </PRE>
1969 */
1970 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
1971 public final void emitCMPXCHG8B_RegInd(GPR base) {
1972 int miStart = mi;
1973 generateREXprefix(false, null, null, base);
1974 setMachineCodes(mi++, (byte) 0x0F);
1975 setMachineCodes(mi++, (byte) 0xC7);
1976 emitRegIndirectRegOperands(base, GPR.getForOpcode(1));
1977 if (lister != null) lister.R(miStart, "CMPXCHG8B" , base);
1978 }
1979
1980 /**
1981 * Compare and exchange 8 bytes
1982 * <PRE>
1983 * cmpxchg8b [index2<<scale2 + disp2]
1984 * </PRE>
1985 */
1986 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
1987 public final void emitCMPXCHG8B_RegOff(GPR index2, short scale2, Offset disp2) {
1988 int miStart = mi;
1989 generateREXprefix(false, null, index2, null);
1990 setMachineCodes(mi++, (byte) 0x0F);
1991 setMachineCodes(mi++, (byte) 0xC7);
1992 emitRegOffRegOperands(index2, scale2, disp2, GPR.getForOpcode(1));
1993 if (lister != null) lister.RFD(miStart, "CMPXCHG8B", index2, scale2, disp2);
1994 }
1995
1996 /**
1997 * Compare and exchange 8 bytes
1998 * <PRE>
1999 * cmpxchg8b [base + index2<<scale2 + disp2]
2000 * </PRE>
2001 */
2002 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2003 public final void emitCMPXCHG8B_RegIdx(GPR base2, GPR index2, short scale2, Offset disp2) {
2004 int miStart = mi;
2005 generateREXprefix(false, null, index2, base2);
2006 setMachineCodes(mi++, (byte) 0x0F);
2007 setMachineCodes(mi++, (byte) 0xC7);
2008 emitSIBRegOperands(base2, index2, scale2, disp2, GPR.getForOpcode(1));
2009 if (lister != null) lister.RXD(miStart, "CMPXCHG8B", base2, index2, scale2, disp2);
2010 }
2011
2012 /** Store AH into Flags */
2013 public final void emitSAHF () {
2014 int miStart = mi;
2015 setMachineCodes(mi++, (byte) 0x9E);
2016 if (lister != null) lister.OP(miStart, "SAHF");
2017 }
2018
2019 /**
2020 * Emit NOP instruction
2021 *
2022 * @param length size of NOP instruction required
2023 */
2024 public final void emitNOP (int length) {
2025 int miStart = mi;
2026 switch (length) {
2027 case 0:
2028 break;
2029 case 1:
2030 setMachineCodes(mi++, (byte) 0x90);
2031 break;
2032 case 2:
2033 setMachineCodes(mi++, (byte) 0x66);
2034 setMachineCodes(mi++, (byte) 0x90);
2035 break;
2036 case 3:
2037 setMachineCodes(mi++, (byte) 0x0F);
2038 setMachineCodes(mi++, (byte) 0x1F);
2039 setMachineCodes(mi++, (byte) 0x00);
2040 break;
2041 case 4:
2042 setMachineCodes(mi++, (byte) 0x0F);
2043 setMachineCodes(mi++, (byte) 0x1F);
2044 setMachineCodes(mi++, (byte) 0x40);
2045 setMachineCodes(mi++, (byte) 0x00);
2046 break;
2047 case 5:
2048 setMachineCodes(mi++, (byte) 0x0F);
2049 setMachineCodes(mi++, (byte) 0x1F);
2050 setMachineCodes(mi++, (byte) 0x44);
2051 setMachineCodes(mi++, (byte) 0x00);
2052 setMachineCodes(mi++, (byte) 0x00);
2053 break;
2054 case 6:
2055 setMachineCodes(mi++, (byte) 0x66);
2056 setMachineCodes(mi++, (byte) 0x0F);
2057 setMachineCodes(mi++, (byte) 0x1F);
2058 setMachineCodes(mi++, (byte) 0x44);
2059 setMachineCodes(mi++, (byte) 0x00);
2060 setMachineCodes(mi++, (byte) 0x00);
2061 break;
2062 case 7:
2063 setMachineCodes(mi++, (byte) 0x0F);
2064 setMachineCodes(mi++, (byte) 0x1F);
2065 setMachineCodes(mi++, (byte) 0x80);
2066 setMachineCodes(mi++, (byte) 0x00);
2067 setMachineCodes(mi++, (byte) 0x00);
2068 setMachineCodes(mi++, (byte) 0x00);
2069 setMachineCodes(mi++, (byte) 0x00);
2070 break;
2071 case 8:
2072 setMachineCodes(mi++, (byte) 0x0F);
2073 setMachineCodes(mi++, (byte) 0x1F);
2074 setMachineCodes(mi++, (byte) 0x84);
2075 setMachineCodes(mi++, (byte) 0x00);
2076 setMachineCodes(mi++, (byte) 0x00);
2077 setMachineCodes(mi++, (byte) 0x00);
2078 setMachineCodes(mi++, (byte) 0x00);
2079 setMachineCodes(mi++, (byte) 0x00);
2080 break;
2081 case 9:
2082 setMachineCodes(mi++, (byte) 0x66);
2083 setMachineCodes(mi++, (byte) 0x0F);
2084 setMachineCodes(mi++, (byte) 0x1F);
2085 setMachineCodes(mi++, (byte) 0x84);
2086 setMachineCodes(mi++, (byte) 0x00);
2087 setMachineCodes(mi++, (byte) 0x00);
2088 setMachineCodes(mi++, (byte) 0x00);
2089 setMachineCodes(mi++, (byte) 0x00);
2090 setMachineCodes(mi++, (byte) 0x00);
2091 break;
2092 default:
2093 throw new Error("Unexpected NOP length "+length);
2094 }
2095 if (lister != null) lister.OP(miStart, "NOP");
2096 }
2097
2098 ////////////////////////////////////////////
2099 // hand-coded floating point instructions //
2100 ////////////////////////////////////////////
2101
2102 /**
2103 * Empty MMX technology state
2104 * <PRE>
2105 * emms
2106 * </PRE>
2107 */
2108 public final void emitEMMS() {
2109 int miStart = mi;
2110 setMachineCodes(mi++, (byte) 0x0F);
2111 setMachineCodes(mi++, (byte) 0x77);
2112 if (lister != null) lister.OP(miStart, "EMMS");
2113 }
2114
2115 /** x87 floating point conditional moves */
2116 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2,3})
2117 public final void emitFCMOV_Cond_Reg_Reg(byte cond, FPR reg1, FPR reg2) {
2118 int miStart = mi;
2119 if (VM.VerifyAssertions) VM._assert(reg1 == FP0);
2120 switch (cond) {
2121 case LLT:
2122 setMachineCodes(mi++, (byte) 0xDA);
2123 setMachineCodes(mi++, (byte) (0xC0 + reg2.value()));
2124 break;
2125 case EQ:
2126 setMachineCodes(mi++, (byte) 0xDA);
2127 setMachineCodes(mi++, (byte) (0xC8 + reg2.value()));
2128 break;
2129 case LLE:
2130 setMachineCodes(mi++, (byte) 0xDA);
2131 setMachineCodes(mi++, (byte) (0xD0 + reg2.value()));
2132 break;
2133 case PE:
2134 setMachineCodes(mi++, (byte) 0xDA);
2135 setMachineCodes(mi++, (byte) (0xD8 + reg2.value()));
2136 break;
2137 case LGE:
2138 setMachineCodes(mi++, (byte) 0xDB);
2139 setMachineCodes(mi++, (byte) (0xC0 + reg2.value()));
2140 break;
2141 case NE:
2142 setMachineCodes(mi++, (byte) 0xDB);
2143 setMachineCodes(mi++, (byte) (0xC8 + reg2.value()));
2144 break;
2145 case LGT:
2146 setMachineCodes(mi++, (byte) 0xDB);
2147 setMachineCodes(mi++, (byte) (0xD0 + reg2.value()));
2148 break;
2149 case PO:
2150 setMachineCodes(mi++, (byte) 0xDB);
2151 setMachineCodes(mi++, (byte) (0xD8 + reg2.value()));
2152 break;
2153 default:
2154 if (VM.VerifyAssertions) VM._assert(VM.NOT_REACHED);
2155 }
2156 if (lister != null) lister.RR(miStart, "FCMOV" + CONDITION[cond], reg1, reg2);
2157 }
2158
2159 /** x87 floating point push of ST(i) into ST(0) */
2160 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2161 public final void emitFLD_Reg_Reg(FPR destReg, FPR srcReg) {
2162 int miStart = mi;
2163 if (VM.VerifyAssertions) VM._assert(destReg == FP0);
2164 setMachineCodes(mi++, (byte) 0xD9);
2165 setMachineCodes(mi++, (byte) (0xC0 + srcReg.value()));
2166 if (lister != null) lister.R(miStart, "FLD", srcReg);
2167 }
2168
2169 // floating point copy of ST(0) into ST(I)
2170 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2171 public final void emitFST_Reg_Reg(FPR destReg, FPR srcReg) {
2172 int miStart = mi;
2173 if (VM.VerifyAssertions) VM._assert(srcReg == FP0);
2174 setMachineCodes(mi++, (byte) 0xDD);
2175 setMachineCodes(mi++, (byte) (0xD0 + destReg.value()));
2176 if (lister != null) lister.R(miStart, "FST", destReg);
2177 }
2178
2179 // floating point pop of ST(0) into ST(I)
2180 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2181 public final void emitFSTP_Reg_Reg(FPR destReg, FPR srcReg) {
2182 int miStart = mi;
2183 if (VM.VerifyAssertions) VM._assert(srcReg == FP0);
2184 setMachineCodes(mi++, (byte) 0xDD);
2185 setMachineCodes(mi++, (byte) (0xD8 + destReg.value()));
2186 if (lister != null) lister.R(miStart, "FST", destReg);
2187 }
2188
2189 // Change Sign: Top of FPU register stack -= Top og FPU register stack
2190 public final void emitFCHS () {
2191 int miStart = mi;
2192 setMachineCodes(mi++, (byte) 0xD9);
2193 setMachineCodes(mi++, (byte) 0xE0);
2194 if (lister != null) lister.OP(miStart, "FADD32");
2195 }
2196
2197 public final void emitFUCOMPP () {
2198 int miStart = mi;
2199 setMachineCodes(mi++, (byte) 0xDA);
2200 setMachineCodes(mi++, (byte) 0xE9);
2201 if (lister != null) lister.OP(miStart, "FUCOMPP");
2202 }
2203
2204 // Store Status Word into AX register/noexecptions
2205 public final void emitFNSTSW () {
2206 int miStart = mi;
2207 setMachineCodes(mi++, (byte) 0xDF);
2208 setMachineCodes(mi++, (byte) 0xE0);
2209 if (lister != null) lister.OP(miStart, "FNSTSW");
2210 }
2211
2212 // Real Remainder:
2213 // Top of FPU register stack <- ST(0) - (Q*ST(1)
2214 // Q is the interger value obtained from truncating
2215 // ST(0)/ST(1) toward 0
2216 public final void emitFPREM () {
2217 int miStart = mi;
2218 setMachineCodes(mi++, (byte) 0xD9);
2219 setMachineCodes(mi++, (byte) 0xF8);
2220 if (lister != null) lister.OP(miStart, "FPREM");
2221 }
2222
2223 // Blow away floating point state
2224 public final void emitFINIT() {
2225 int miStart = mi;
2226 setMachineCodes(mi++, (byte) 0x9B);
2227 setMachineCodes(mi++, (byte) 0xDB);
2228 setMachineCodes(mi++, (byte) 0xE3);
2229 if (lister != null) lister.OP(miStart, "FINIT");
2230 }
2231
2232 // Blow away floating point state
2233 // Pending exceptions??? Don't tell me about pending exceptions!!
2234 public final void emitFNINIT() {
2235 int miStart = mi;
2236 setMachineCodes(mi++, (byte) 0xDB);
2237 setMachineCodes(mi++, (byte) 0xE3);
2238 if (lister != null) lister.OP(miStart, "FNINIT");
2239 }
2240
2241 /** Declare we are no longer using FP register */
2242 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
2243 public final void emitFFREE_Reg(FPR reg) {
2244 int miStart = mi;
2245 setMachineCodes(mi++, (byte) 0xDD);
2246 setMachineCodes(mi++, (byte) ( (byte)0xC0 + reg.value() ));
2247 if (lister != null) lister.R(miStart, "FFREE", reg);
2248 }
2249
2250 /** The dreaded FXCH (symbol of all that's wrong with x87 floating point) */
2251 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2252 public final void emitFXCH_Reg_Reg(FPR regOne, FPR regTwo) {
2253 int miStart = mi;
2254
2255 // at least one reg must not be FP0
2256 FPR nonZeroReg = FP0; // :)
2257 if (regOne == FP0 && regTwo == FP0)
2258 // do nothing; this is stupid
2259 return;
2260 else if (regOne == FP0 && regTwo != FP0)
2261 nonZeroReg = regTwo;
2262 else if (regTwo == FP0 && regOne != FP0)
2263 nonZeroReg = regOne;
2264
2265 // if not, bad instruction, so die
2266 if (nonZeroReg == FP0)
2267 VM._assert(false, "FXCH of " + regOne + ", " + regTwo);
2268
2269 // generate it, with special case (of course) for FP1
2270 setMachineCodes(mi++, (byte) 0xD9);
2271 if (nonZeroReg == FP1)
2272 setMachineCodes(mi++, (byte) 0xC9);
2273 else
2274 setMachineCodes(mi++, (byte) (0xC8 | nonZeroReg.value()));
2275
2276 // list it
2277 if (lister != null) lister.R(miStart, "FXCH", nonZeroReg);
2278 }
2279
2280 /*
2281 * BELOW HERE ARE AUTOMATICALLY-GENERATED INSTRUCTIONS. DO NOT EDIT.
2282 *
2283 * These instructions are generated by genAssembler.sh in the
2284 * src-generated/ia32-assembler directory. Please make all needed
2285 * edits to that script.
2286 */
2287 /**
2288 * Generate a register(indirect)--register ADC. That is,
2289 * <PRE>
2290 * [dstBase] +CF= srcReg
2291 * </PRE>
2292 *
2293 * @param dstBase the destination base
2294 * @param srcReg the source register
2295 */
2296 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2297 public final void emitADC_RegInd_Reg(GPR dstBase, GPR srcReg) {
2298 int miStart = mi;
2299 // no group 1 to 4 prefix byte
2300 generateREXprefix(false, srcReg, null, dstBase);
2301 // single byte opcode
2302 setMachineCodes(mi++, (byte) 0x11);
2303 emitRegIndirectRegOperands(dstBase, srcReg);
2304 if (lister != null) lister.RNR(miStart, "ADC", dstBase, srcReg);
2305 }
2306
2307 /**
2308 * Generate a register-offset--register ADC. That is,
2309 * <PRE>
2310 * [dstReg<<dstScale + dstDisp] +CF= srcReg
2311 * </PRE>
2312 *
2313 * @param dstIndex the destination index register
2314 * @param dstScale the destination shift amount
2315 * @param dstDisp the destination displacement
2316 * @param srcReg the source register
2317 */
2318 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
2319 public final void emitADC_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
2320 int miStart = mi;
2321 // no group 1 to 4 prefix byte
2322 generateREXprefix(false, srcReg, dstIndex, null);
2323 // single byte opcode
2324 setMachineCodes(mi++, (byte) 0x11);
2325 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
2326 if (lister != null) lister.RFDR(miStart, "ADC", dstIndex, dstScale, dstDisp, srcReg);
2327 }
2328
2329 /**
2330 * Generate a absolute--register ADC. That is,
2331 * <PRE>
2332 * [dstDisp] +CF= srcReg
2333 * </PRE>
2334 *
2335 * @param dstDisp the destination address
2336 * @param srcReg the source register
2337 */
2338 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
2339 public final void emitADC_Abs_Reg(Address dstDisp, GPR srcReg) {
2340 int miStart = mi;
2341 // no group 1 to 4 prefix byte
2342 generateREXprefix(false, srcReg, null, null);
2343 // single byte opcode
2344 setMachineCodes(mi++, (byte) 0x11);
2345 emitAbsRegOperands(dstDisp, srcReg);
2346 if (lister != null) lister.RAR(miStart, "ADC", dstDisp, srcReg);
2347 }
2348
2349 /**
2350 * Generate a register-index--register ADC. That is,
2351 * <PRE>
2352 * [dstBase + dstIndex<<dstScale + dstDisp] +CF= srcReg
2353 * </PRE>
2354 *
2355 * @param dstBase the base register
2356 * @param dstIndex the destination index register
2357 * @param dstScale the destination shift amount
2358 * @param dstDisp the destination displacement
2359 * @param srcReg the source register
2360 */
2361 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
2362 public final void emitADC_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
2363 int miStart = mi;
2364 // no group 1 to 4 prefix byte
2365 generateREXprefix(false, srcReg, dstIndex, dstBase);
2366 // single byte opcode
2367 setMachineCodes(mi++, (byte) 0x11);
2368 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
2369 if (lister != null) lister.RXDR(miStart, "ADC", dstBase, dstIndex, dstScale, dstDisp, srcReg);
2370 }
2371
2372 /**
2373 * Generate a register-displacement--register ADC. That is,
2374 * <PRE>
2375 * [dstBase + dstDisp] +CF= srcReg
2376 * </PRE>
2377 *
2378 * @param dstBase the base register
2379 * @param dstDisp the destination displacement
2380 * @param srcReg the source register
2381 */
2382 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
2383 public final void emitADC_RegDisp_Reg(GPR dstBase, Offset dstDisp, GPR srcReg) {
2384 int miStart = mi;
2385 // no group 1 to 4 prefix byte
2386 generateREXprefix(false, srcReg, null, dstBase);
2387 // single byte opcode
2388 setMachineCodes(mi++, (byte) 0x11);
2389 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
2390 if (lister != null) lister.RDR(miStart, "ADC", dstBase, dstDisp, srcReg);
2391 }
2392
2393 /**
2394 * Generate a register--register ADC. That is,
2395 * <PRE>
2396 * dstReg +CF= srcReg
2397 * </PRE>
2398 *
2399 * @param dstReg the destination register
2400 * @param srcReg the source register
2401 */
2402 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2403 public final void emitADC_Reg_Reg(GPR dstReg, GPR srcReg) {
2404 int miStart = mi;
2405 // no group 1 to 4 prefix byte
2406 generateREXprefix(false, srcReg, null, dstReg);
2407 // single byte opcode
2408 setMachineCodes(mi++, (byte) 0x11);
2409 emitRegRegOperands(dstReg, srcReg);
2410 if (lister != null) lister.RR(miStart, "ADC", dstReg, srcReg);
2411 }
2412
2413 /**
2414 * Generate a register--register-displacement ADC. That is,
2415 * <PRE>
2416 * dstReg +CF= [srcReg + srcDisp]
2417 * </PRE>
2418 *
2419 * @param dstReg the destination register
2420 * @param srcBase the source register
2421 * @param srcDisp the source displacement
2422 */
2423 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2424 public final void emitADC_Reg_RegDisp(GPR dstReg, GPR srcBase, Offset srcDisp) {
2425 int miStart = mi;
2426 // no group 1 to 4 prefix byte
2427 generateREXprefix(false, dstReg, null, srcBase);
2428 // single byte opcode
2429 setMachineCodes(mi++, (byte) 0x13);
2430 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
2431 if (lister != null) lister.RRD(miStart, "ADC", dstReg, srcBase, srcDisp);
2432 }
2433
2434 /**
2435 * Generate a register--register-offset ADC. That is,
2436 * <PRE>
2437 * dstReg +CF= [srcIndex<<srcScale + srcDisp]
2438 * </PRE>
2439 *
2440 * @param dstReg the destination register
2441 * @param srcIndex the source index register
2442 * @param srcScale the source shift amount
2443 * @param srcDisp the source displacement
2444 */
2445 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2446 public final void emitADC_Reg_RegOff(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
2447 int miStart = mi;
2448 // no group 1 to 4 prefix byte
2449 generateREXprefix(false, dstReg, srcIndex, null);
2450 // single byte opcode
2451 setMachineCodes(mi++, (byte) 0x13);
2452 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
2453 if (lister != null) lister.RRFD(miStart, "ADC", dstReg, srcIndex, srcScale, srcDisp);
2454 }
2455
2456 /**
2457 * Generate a register--register-offset ADC. That is,
2458 * <PRE>
2459 * dstReg +CF= [srcDisp]
2460 * </PRE>
2461 *
2462 * @param dstReg the destination register
2463 * @param srcDisp the source displacement
2464 */
2465 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
2466 public final void emitADC_Reg_Abs(GPR dstReg, Address srcDisp) {
2467 int miStart = mi;
2468 // no group 1 to 4 prefix byte
2469 generateREXprefix(false, dstReg, null, null);
2470 // single byte opcode
2471 setMachineCodes(mi++, (byte) 0x13);
2472 emitAbsRegOperands(srcDisp, dstReg);
2473 if (lister != null) lister.RRA(miStart, "ADC", dstReg, srcDisp);
2474 }
2475
2476 /**
2477 * Generate a register--register-offset ADC. That is,
2478 * <PRE>
2479 * dstReg +CF= [srcBase + srcIndex<<srcScale + srcDisp]
2480 * </PRE>
2481 *
2482 * @param dstReg the destination register
2483 * @param srcBase the source base register
2484 * @param srcIndex the source index register
2485 * @param srcScale the source shift amount
2486 * @param srcDisp the source displacement
2487 */
2488 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
2489 public final void emitADC_Reg_RegIdx(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
2490 int miStart = mi;
2491 // no group 1 to 4 prefix byte
2492 generateREXprefix(false, dstReg, srcIndex, srcBase);
2493 // single byte opcode
2494 setMachineCodes(mi++, (byte) 0x13);
2495 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
2496 if (lister != null) lister.RRXD(miStart, "ADC", dstReg, srcBase, srcIndex, srcScale, srcDisp);
2497 }
2498
2499 /**
2500 * Generate a register--register(indirect) ADC. That is,
2501 * <PRE>
2502 * dstReg +CF= [srcBase]
2503 * </PRE>
2504 *
2505 * @param dstReg the destination register
2506 * @param srcBase the source base register
2507 */
2508 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2509 public final void emitADC_Reg_RegInd(GPR dstReg, GPR srcBase) {
2510 int miStart = mi;
2511 // no group 1 to 4 prefix byte
2512 generateREXprefix(false, dstReg, null, srcBase);
2513 // single byte opcode
2514 setMachineCodes(mi++, (byte) 0x13);
2515 emitRegIndirectRegOperands(srcBase, dstReg);
2516 if (lister != null) lister.RRN(miStart, "ADC", dstReg, srcBase);
2517 }
2518
2519 /**
2520 * Generate a register(indirect)--register ADC. That is,
2521 * <PRE>
2522 * [dstBase] +CF= (word) srcReg
2523 * </PRE>
2524 *
2525 * @param dstBase the destination base
2526 * @param srcReg the source register
2527 */
2528 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2529 public final void emitADC_RegInd_Reg_Word(GPR dstBase, GPR srcReg) {
2530 int miStart = mi;
2531 setMachineCodes(mi++, (byte) 0x66);
2532 generateREXprefix(false, srcReg, null, dstBase);
2533 // single byte opcode
2534 setMachineCodes(mi++, (byte) 0x11);
2535 emitRegIndirectRegOperands(dstBase, srcReg);
2536 if (lister != null) lister.RNR(miStart, "ADC", dstBase, srcReg);
2537 }
2538
2539 /**
2540 * Generate a register-offset--register ADC. That is,
2541 * <PRE>
2542 * [dstReg<<dstScale + dstDisp] +CF= (word) srcReg
2543 * </PRE>
2544 *
2545 * @param dstIndex the destination index register
2546 * @param dstScale the destination shift amount
2547 * @param dstDisp the destination displacement
2548 * @param srcReg the source register
2549 */
2550 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
2551 public final void emitADC_RegOff_Reg_Word(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
2552 int miStart = mi;
2553 setMachineCodes(mi++, (byte) 0x66);
2554 generateREXprefix(false, srcReg, dstIndex, null);
2555 // single byte opcode
2556 setMachineCodes(mi++, (byte) 0x11);
2557 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
2558 if (lister != null) lister.RFDR(miStart, "ADC", dstIndex, dstScale, dstDisp, srcReg);
2559 }
2560
2561 /**
2562 * Generate a absolute--register ADC. That is,
2563 * <PRE>
2564 * [dstDisp] +CF= (word) srcReg
2565 * </PRE>
2566 *
2567 * @param dstDisp the destination address
2568 * @param srcReg the source register
2569 */
2570 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
2571 public final void emitADC_Abs_Reg_Word(Address dstDisp, GPR srcReg) {
2572 int miStart = mi;
2573 setMachineCodes(mi++, (byte) 0x66);
2574 generateREXprefix(false, srcReg, null, null);
2575 // single byte opcode
2576 setMachineCodes(mi++, (byte) 0x11);
2577 emitAbsRegOperands(dstDisp, srcReg);
2578 if (lister != null) lister.RAR(miStart, "ADC", dstDisp, srcReg);
2579 }
2580
2581 /**
2582 * Generate a register-index--register ADC. That is,
2583 * <PRE>
2584 * [dstBase + dstIndex<<dstScale + dstDisp] +CF= (word) srcReg
2585 * </PRE>
2586 *
2587 * @param dstBase the base register
2588 * @param dstIndex the destination index register
2589 * @param dstScale the destination shift amount
2590 * @param dstDisp the destination displacement
2591 * @param srcReg the source register
2592 */
2593 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
2594 public final void emitADC_RegIdx_Reg_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
2595 int miStart = mi;
2596 setMachineCodes(mi++, (byte) 0x66);
2597 generateREXprefix(false, srcReg, dstIndex, dstBase);
2598 // single byte opcode
2599 setMachineCodes(mi++, (byte) 0x11);
2600 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
2601 if (lister != null) lister.RXDR(miStart, "ADC", dstBase, dstIndex, dstScale, dstDisp, srcReg);
2602 }
2603
2604 /**
2605 * Generate a register-displacement--register ADC. That is,
2606 * <PRE>
2607 * [dstBase + dstDisp] +CF= (word) srcReg
2608 * </PRE>
2609 *
2610 * @param dstBase the base register
2611 * @param dstDisp the destination displacement
2612 * @param srcReg the source register
2613 */
2614 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
2615 public final void emitADC_RegDisp_Reg_Word(GPR dstBase, Offset dstDisp, GPR srcReg) {
2616 int miStart = mi;
2617 setMachineCodes(mi++, (byte) 0x66);
2618 generateREXprefix(false, srcReg, null, dstBase);
2619 // single byte opcode
2620 setMachineCodes(mi++, (byte) 0x11);
2621 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
2622 if (lister != null) lister.RDR(miStart, "ADC", dstBase, dstDisp, srcReg);
2623 }
2624
2625 /**
2626 * Generate a register--register ADC. That is,
2627 * <PRE>
2628 * dstReg +CF= (word) srcReg
2629 * </PRE>
2630 *
2631 * @param dstReg the destination register
2632 * @param srcReg the source register
2633 */
2634 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2635 public final void emitADC_Reg_Reg_Word(GPR dstReg, GPR srcReg) {
2636 int miStart = mi;
2637 setMachineCodes(mi++, (byte) 0x66);
2638 generateREXprefix(false, srcReg, null, dstReg);
2639 // single byte opcode
2640 setMachineCodes(mi++, (byte) 0x11);
2641 emitRegRegOperands(dstReg, srcReg);
2642 if (lister != null) lister.RR(miStart, "ADC", dstReg, srcReg);
2643 }
2644
2645 /**
2646 * Generate a register--register-displacement ADC. That is,
2647 * <PRE>
2648 * dstReg +CF= (word) [srcReg + srcDisp]
2649 * </PRE>
2650 *
2651 * @param dstReg the destination register
2652 * @param srcBase the source register
2653 * @param srcDisp the source displacement
2654 */
2655 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2656 public final void emitADC_Reg_RegDisp_Word(GPR dstReg, GPR srcBase, Offset srcDisp) {
2657 int miStart = mi;
2658 setMachineCodes(mi++, (byte) 0x66);
2659 generateREXprefix(false, dstReg, null, srcBase);
2660 // single byte opcode
2661 setMachineCodes(mi++, (byte) 0x13);
2662 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
2663 if (lister != null) lister.RRD(miStart, "ADC", dstReg, srcBase, srcDisp);
2664 }
2665
2666 /**
2667 * Generate a register--register-offset ADC. That is,
2668 * <PRE>
2669 * dstReg +CF= (word) [srcIndex<<srcScale + srcDisp]
2670 * </PRE>
2671 *
2672 * @param dstReg the destination register
2673 * @param srcIndex the source index register
2674 * @param srcScale the source shift amount
2675 * @param srcDisp the source displacement
2676 */
2677 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2678 public final void emitADC_Reg_RegOff_Word(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
2679 int miStart = mi;
2680 setMachineCodes(mi++, (byte) 0x66);
2681 generateREXprefix(false, dstReg, srcIndex, null);
2682 // single byte opcode
2683 setMachineCodes(mi++, (byte) 0x13);
2684 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
2685 if (lister != null) lister.RRFD(miStart, "ADC", dstReg, srcIndex, srcScale, srcDisp);
2686 }
2687
2688 /**
2689 * Generate a register--register-offset ADC. That is,
2690 * <PRE>
2691 * dstReg +CF= (word) [srcDisp]
2692 * </PRE>
2693 *
2694 * @param dstReg the destination register
2695 * @param srcDisp the source displacement
2696 */
2697 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
2698 public final void emitADC_Reg_Abs_Word(GPR dstReg, Address srcDisp) {
2699 int miStart = mi;
2700 setMachineCodes(mi++, (byte) 0x66);
2701 generateREXprefix(false, dstReg, null, null);
2702 // single byte opcode
2703 setMachineCodes(mi++, (byte) 0x13);
2704 emitAbsRegOperands(srcDisp, dstReg);
2705 if (lister != null) lister.RRA(miStart, "ADC", dstReg, srcDisp);
2706 }
2707
2708 /**
2709 * Generate a register--register-offset ADC. That is,
2710 * <PRE>
2711 * dstReg +CF= (word) [srcBase + srcIndex<<srcScale + srcDisp]
2712 * </PRE>
2713 *
2714 * @param dstReg the destination register
2715 * @param srcBase the source base register
2716 * @param srcIndex the source index register
2717 * @param srcScale the source shift amount
2718 * @param srcDisp the source displacement
2719 */
2720 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
2721 public final void emitADC_Reg_RegIdx_Word(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
2722 int miStart = mi;
2723 setMachineCodes(mi++, (byte) 0x66);
2724 generateREXprefix(false, dstReg, srcIndex, srcBase);
2725 // single byte opcode
2726 setMachineCodes(mi++, (byte) 0x13);
2727 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
2728 if (lister != null) lister.RRXD(miStart, "ADC", dstReg, srcBase, srcIndex, srcScale, srcDisp);
2729 }
2730
2731 /**
2732 * Generate a register--register(indirect) ADC. That is,
2733 * <PRE>
2734 * dstReg +CF= (word) [srcBase]
2735 * </PRE>
2736 *
2737 * @param dstReg the destination register
2738 * @param srcBase the source base register
2739 */
2740 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2741 public final void emitADC_Reg_RegInd_Word(GPR dstReg, GPR srcBase) {
2742 int miStart = mi;
2743 setMachineCodes(mi++, (byte) 0x66);
2744 generateREXprefix(false, dstReg, null, srcBase);
2745 // single byte opcode
2746 setMachineCodes(mi++, (byte) 0x13);
2747 emitRegIndirectRegOperands(srcBase, dstReg);
2748 if (lister != null) lister.RRN(miStart, "ADC", dstReg, srcBase);
2749 }
2750
2751 /**
2752 * Generate a register(indirect)--register ADC. That is,
2753 * <PRE>
2754 * [dstBase] +CF= (quad) srcReg
2755 * </PRE>
2756 *
2757 * @param dstBase the destination base
2758 * @param srcReg the source register
2759 */
2760 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2761 public final void emitADC_RegInd_Reg_Quad(GPR dstBase, GPR srcReg) {
2762 int miStart = mi;
2763 // no group 1 to 4 prefix byte
2764 generateREXprefix(true, srcReg, null, dstBase);
2765 // single byte opcode
2766 setMachineCodes(mi++, (byte) 0x11);
2767 emitRegIndirectRegOperands(dstBase, srcReg);
2768 if (lister != null) lister.RNR(miStart, "ADC", dstBase, srcReg);
2769 }
2770
2771 /**
2772 * Generate a register-offset--register ADC. That is,
2773 * <PRE>
2774 * [dstReg<<dstScale + dstDisp] +CF= (quad) srcReg
2775 * </PRE>
2776 *
2777 * @param dstIndex the destination index register
2778 * @param dstScale the destination shift amount
2779 * @param dstDisp the destination displacement
2780 * @param srcReg the source register
2781 */
2782 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
2783 public final void emitADC_RegOff_Reg_Quad(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
2784 int miStart = mi;
2785 // no group 1 to 4 prefix byte
2786 generateREXprefix(true, srcReg, dstIndex, null);
2787 // single byte opcode
2788 setMachineCodes(mi++, (byte) 0x11);
2789 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
2790 if (lister != null) lister.RFDR(miStart, "ADC", dstIndex, dstScale, dstDisp, srcReg);
2791 }
2792
2793 /**
2794 * Generate a absolute--register ADC. That is,
2795 * <PRE>
2796 * [dstDisp] +CF= (quad) srcReg
2797 * </PRE>
2798 *
2799 * @param dstDisp the destination address
2800 * @param srcReg the source register
2801 */
2802 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
2803 public final void emitADC_Abs_Reg_Quad(Address dstDisp, GPR srcReg) {
2804 int miStart = mi;
2805 // no group 1 to 4 prefix byte
2806 generateREXprefix(true, srcReg, null, null);
2807 // single byte opcode
2808 setMachineCodes(mi++, (byte) 0x11);
2809 emitAbsRegOperands(dstDisp, srcReg);
2810 if (lister != null) lister.RAR(miStart, "ADC", dstDisp, srcReg);
2811 }
2812
2813 /**
2814 * Generate a register-index--register ADC. That is,
2815 * <PRE>
2816 * [dstBase + dstIndex<<dstScale + dstDisp] +CF= (quad) srcReg
2817 * </PRE>
2818 *
2819 * @param dstBase the base register
2820 * @param dstIndex the destination index register
2821 * @param dstScale the destination shift amount
2822 * @param dstDisp the destination displacement
2823 * @param srcReg the source register
2824 */
2825 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
2826 public final void emitADC_RegIdx_Reg_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
2827 int miStart = mi;
2828 // no group 1 to 4 prefix byte
2829 generateREXprefix(true, srcReg, dstIndex, dstBase);
2830 // single byte opcode
2831 setMachineCodes(mi++, (byte) 0x11);
2832 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
2833 if (lister != null) lister.RXDR(miStart, "ADC", dstBase, dstIndex, dstScale, dstDisp, srcReg);
2834 }
2835
2836 /**
2837 * Generate a register-displacement--register ADC. That is,
2838 * <PRE>
2839 * [dstBase + dstDisp] +CF= (quad) srcReg
2840 * </PRE>
2841 *
2842 * @param dstBase the base register
2843 * @param dstDisp the destination displacement
2844 * @param srcReg the source register
2845 */
2846 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
2847 public final void emitADC_RegDisp_Reg_Quad(GPR dstBase, Offset dstDisp, GPR srcReg) {
2848 int miStart = mi;
2849 // no group 1 to 4 prefix byte
2850 generateREXprefix(true, srcReg, null, dstBase);
2851 // single byte opcode
2852 setMachineCodes(mi++, (byte) 0x11);
2853 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
2854 if (lister != null) lister.RDR(miStart, "ADC", dstBase, dstDisp, srcReg);
2855 }
2856
2857 /**
2858 * Generate a register--register ADC. That is,
2859 * <PRE>
2860 * dstReg +CF= (quad) srcReg
2861 * </PRE>
2862 *
2863 * @param dstReg the destination register
2864 * @param srcReg the source register
2865 */
2866 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2867 public final void emitADC_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
2868 int miStart = mi;
2869 // no group 1 to 4 prefix byte
2870 generateREXprefix(true, srcReg, null, dstReg);
2871 // single byte opcode
2872 setMachineCodes(mi++, (byte) 0x11);
2873 emitRegRegOperands(dstReg, srcReg);
2874 if (lister != null) lister.RR(miStart, "ADC", dstReg, srcReg);
2875 }
2876
2877 /**
2878 * Generate a register--register-displacement ADC. That is,
2879 * <PRE>
2880 * dstReg +CF= (quad) [srcReg + srcDisp]
2881 * </PRE>
2882 *
2883 * @param dstReg the destination register
2884 * @param srcBase the source register
2885 * @param srcDisp the source displacement
2886 */
2887 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2888 public final void emitADC_Reg_RegDisp_Quad(GPR dstReg, GPR srcBase, Offset srcDisp) {
2889 int miStart = mi;
2890 // no group 1 to 4 prefix byte
2891 generateREXprefix(true, dstReg, null, srcBase);
2892 // single byte opcode
2893 setMachineCodes(mi++, (byte) 0x13);
2894 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
2895 if (lister != null) lister.RRD(miStart, "ADC", dstReg, srcBase, srcDisp);
2896 }
2897
2898 /**
2899 * Generate a register--register-offset ADC. That is,
2900 * <PRE>
2901 * dstReg +CF= (quad) [srcIndex<<srcScale + srcDisp]
2902 * </PRE>
2903 *
2904 * @param dstReg the destination register
2905 * @param srcIndex the source index register
2906 * @param srcScale the source shift amount
2907 * @param srcDisp the source displacement
2908 */
2909 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2910 public final void emitADC_Reg_RegOff_Quad(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
2911 int miStart = mi;
2912 // no group 1 to 4 prefix byte
2913 generateREXprefix(true, dstReg, srcIndex, null);
2914 // single byte opcode
2915 setMachineCodes(mi++, (byte) 0x13);
2916 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
2917 if (lister != null) lister.RRFD(miStart, "ADC", dstReg, srcIndex, srcScale, srcDisp);
2918 }
2919
2920 /**
2921 * Generate a register--register-offset ADC. That is,
2922 * <PRE>
2923 * dstReg +CF= (quad) [srcDisp]
2924 * </PRE>
2925 *
2926 * @param dstReg the destination register
2927 * @param srcDisp the source displacement
2928 */
2929 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
2930 public final void emitADC_Reg_Abs_Quad(GPR dstReg, Address srcDisp) {
2931 int miStart = mi;
2932 // no group 1 to 4 prefix byte
2933 generateREXprefix(true, dstReg, null, null);
2934 // single byte opcode
2935 setMachineCodes(mi++, (byte) 0x13);
2936 emitAbsRegOperands(srcDisp, dstReg);
2937 if (lister != null) lister.RRA(miStart, "ADC", dstReg, srcDisp);
2938 }
2939
2940 /**
2941 * Generate a register--register-offset ADC. That is,
2942 * <PRE>
2943 * dstReg +CF= (quad) [srcBase + srcIndex<<srcScale + srcDisp]
2944 * </PRE>
2945 *
2946 * @param dstReg the destination register
2947 * @param srcBase the source base register
2948 * @param srcIndex the source index register
2949 * @param srcScale the source shift amount
2950 * @param srcDisp the source displacement
2951 */
2952 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
2953 public final void emitADC_Reg_RegIdx_Quad(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
2954 int miStart = mi;
2955 // no group 1 to 4 prefix byte
2956 generateREXprefix(true, dstReg, srcIndex, srcBase);
2957 // single byte opcode
2958 setMachineCodes(mi++, (byte) 0x13);
2959 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
2960 if (lister != null) lister.RRXD(miStart, "ADC", dstReg, srcBase, srcIndex, srcScale, srcDisp);
2961 }
2962
2963 /**
2964 * Generate a register--register(indirect) ADC. That is,
2965 * <PRE>
2966 * dstReg +CF= (quad) [srcBase]
2967 * </PRE>
2968 *
2969 * @param dstReg the destination register
2970 * @param srcBase the source base register
2971 */
2972 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2973 public final void emitADC_Reg_RegInd_Quad(GPR dstReg, GPR srcBase) {
2974 int miStart = mi;
2975 // no group 1 to 4 prefix byte
2976 generateREXprefix(true, dstReg, null, srcBase);
2977 // single byte opcode
2978 setMachineCodes(mi++, (byte) 0x13);
2979 emitRegIndirectRegOperands(srcBase, dstReg);
2980 if (lister != null) lister.RRN(miStart, "ADC", dstReg, srcBase);
2981 }
2982
2983 /**
2984 * Generate a register(indirect)--register ADC. That is,
2985 * <PRE>
2986 * [dstBase] +CF= (byte) srcReg
2987 * </PRE>
2988 *
2989 * @param dstBase the destination base
2990 * @param srcReg the source register
2991 */
2992 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
2993 public final void emitADC_RegInd_Reg_Byte(GPR dstBase, GPR srcReg) {
2994 int miStart = mi;
2995 // no group 1 to 4 prefix byte
2996 generateREXprefix(false, srcReg, null, dstBase);
2997 // single byte opcode
2998 setMachineCodes(mi++, (byte) 0x10);
2999 emitRegIndirectRegOperands(dstBase, srcReg);
3000 if (lister != null) lister.RNR(miStart, "ADC", dstBase, srcReg);
3001 }
3002
3003 /**
3004 * Generate a register-offset--register ADC. That is,
3005 * <PRE>
3006 * [dstReg<<dstScale + dstDisp] +CF= (byte) srcReg
3007 * </PRE>
3008 *
3009 * @param dstIndex the destination index register
3010 * @param dstScale the destination shift amount
3011 * @param dstDisp the destination displacement
3012 * @param srcReg the source register
3013 */
3014 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
3015 public final void emitADC_RegOff_Reg_Byte(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
3016 int miStart = mi;
3017 // no group 1 to 4 prefix byte
3018 generateREXprefix(false, srcReg, dstIndex, null);
3019 // single byte opcode
3020 setMachineCodes(mi++, (byte) 0x10);
3021 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
3022 if (lister != null) lister.RFDR(miStart, "ADC", dstIndex, dstScale, dstDisp, srcReg);
3023 }
3024
3025 /**
3026 * Generate a absolute--register ADC. That is,
3027 * <PRE>
3028 * [dstDisp] +CF= (byte) srcReg
3029 * </PRE>
3030 *
3031 * @param dstDisp the destination address
3032 * @param srcReg the source register
3033 */
3034 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
3035 public final void emitADC_Abs_Reg_Byte(Address dstDisp, GPR srcReg) {
3036 int miStart = mi;
3037 // no group 1 to 4 prefix byte
3038 generateREXprefix(false, srcReg, null, null);
3039 // single byte opcode
3040 setMachineCodes(mi++, (byte) 0x10);
3041 emitAbsRegOperands(dstDisp, srcReg);
3042 if (lister != null) lister.RAR(miStart, "ADC", dstDisp, srcReg);
3043 }
3044
3045 /**
3046 * Generate a register-index--register ADC. That is,
3047 * <PRE>
3048 * [dstBase + dstIndex<<dstScale + dstDisp] +CF= (byte) srcReg
3049 * </PRE>
3050 *
3051 * @param dstBase the base register
3052 * @param dstIndex the destination index register
3053 * @param dstScale the destination shift amount
3054 * @param dstDisp the destination displacement
3055 * @param srcReg the source register
3056 */
3057 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
3058 public final void emitADC_RegIdx_Reg_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
3059 int miStart = mi;
3060 // no group 1 to 4 prefix byte
3061 generateREXprefix(false, srcReg, dstIndex, dstBase);
3062 // single byte opcode
3063 setMachineCodes(mi++, (byte) 0x10);
3064 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
3065 if (lister != null) lister.RXDR(miStart, "ADC", dstBase, dstIndex, dstScale, dstDisp, srcReg);
3066 }
3067
3068 /**
3069 * Generate a register-displacement--register ADC. That is,
3070 * <PRE>
3071 * [dstBase + dstDisp] +CF= (byte) srcReg
3072 * </PRE>
3073 *
3074 * @param dstBase the base register
3075 * @param dstDisp the destination displacement
3076 * @param srcReg the source register
3077 */
3078 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
3079 public final void emitADC_RegDisp_Reg_Byte(GPR dstBase, Offset dstDisp, GPR srcReg) {
3080 int miStart = mi;
3081 // no group 1 to 4 prefix byte
3082 generateREXprefix(false, srcReg, null, dstBase);
3083 // single byte opcode
3084 setMachineCodes(mi++, (byte) 0x10);
3085 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
3086 if (lister != null) lister.RDR(miStart, "ADC", dstBase, dstDisp, srcReg);
3087 }
3088
3089 /**
3090 * Generate a register--register ADC. That is,
3091 * <PRE>
3092 * dstReg +CF= (byte) srcReg
3093 * </PRE>
3094 *
3095 * @param dstReg the destination register
3096 * @param srcReg the source register
3097 */
3098 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
3099 public final void emitADC_Reg_Reg_Byte(GPR dstReg, GPR srcReg) {
3100 int miStart = mi;
3101 // no group 1 to 4 prefix byte
3102 generateREXprefix(false, srcReg, null, dstReg);
3103 // single byte opcode
3104 setMachineCodes(mi++, (byte) 0x10);
3105 emitRegRegOperands(dstReg, srcReg);
3106 if (lister != null) lister.RR(miStart, "ADC", dstReg, srcReg);
3107 }
3108
3109 /**
3110 * Generate a register--register-displacement ADC. That is,
3111 * <PRE>
3112 * dstReg +CF= (byte) [srcReg + srcDisp]
3113 * </PRE>
3114 *
3115 * @param dstReg the destination register
3116 * @param srcBase the source register
3117 * @param srcDisp the source displacement
3118 */
3119 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
3120 public final void emitADC_Reg_RegDisp_Byte(GPR dstReg, GPR srcBase, Offset srcDisp) {
3121 int miStart = mi;
3122 // no group 1 to 4 prefix byte
3123 generateREXprefix(false, dstReg, null, srcBase);
3124 // single byte opcode
3125 setMachineCodes(mi++, (byte) 0x12);
3126 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
3127 if (lister != null) lister.RRD(miStart, "ADC", dstReg, srcBase, srcDisp);
3128 }
3129
3130 /**
3131 * Generate a register--register-offset ADC. That is,
3132 * <PRE>
3133 * dstReg +CF= (byte) [srcIndex<<srcScale + srcDisp]
3134 * </PRE>
3135 *
3136 * @param dstReg the destination register
3137 * @param srcIndex the source index register
3138 * @param srcScale the source shift amount
3139 * @param srcDisp the source displacement
3140 */
3141 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
3142 public final void emitADC_Reg_RegOff_Byte(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
3143 int miStart = mi;
3144 // no group 1 to 4 prefix byte
3145 generateREXprefix(false, dstReg, srcIndex, null);
3146 // single byte opcode
3147 setMachineCodes(mi++, (byte) 0x12);
3148 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
3149 if (lister != null) lister.RRFD(miStart, "ADC", dstReg, srcIndex, srcScale, srcDisp);
3150 }
3151
3152 /**
3153 * Generate a register--register-offset ADC. That is,
3154 * <PRE>
3155 * dstReg +CF= (byte) [srcDisp]
3156 * </PRE>
3157 *
3158 * @param dstReg the destination register
3159 * @param srcDisp the source displacement
3160 */
3161 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
3162 public final void emitADC_Reg_Abs_Byte(GPR dstReg, Address srcDisp) {
3163 int miStart = mi;
3164 // no group 1 to 4 prefix byte
3165 generateREXprefix(false, dstReg, null, null);
3166 // single byte opcode
3167 setMachineCodes(mi++, (byte) 0x12);
3168 emitAbsRegOperands(srcDisp, dstReg);
3169 if (lister != null) lister.RRA(miStart, "ADC", dstReg, srcDisp);
3170 }
3171
3172 /**
3173 * Generate a register--register-offset ADC. That is,
3174 * <PRE>
3175 * dstReg +CF= (byte) [srcBase + srcIndex<<srcScale + srcDisp]
3176 * </PRE>
3177 *
3178 * @param dstReg the destination register
3179 * @param srcBase the source base register
3180 * @param srcIndex the source index register
3181 * @param srcScale the source shift amount
3182 * @param srcDisp the source displacement
3183 */
3184 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
3185 public final void emitADC_Reg_RegIdx_Byte(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
3186 int miStart = mi;
3187 // no group 1 to 4 prefix byte
3188 generateREXprefix(false, dstReg, srcIndex, srcBase);
3189 // single byte opcode
3190 setMachineCodes(mi++, (byte) 0x12);
3191 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
3192 if (lister != null) lister.RRXD(miStart, "ADC", dstReg, srcBase, srcIndex, srcScale, srcDisp);
3193 }
3194
3195 /**
3196 * Generate a register--register(indirect) ADC. That is,
3197 * <PRE>
3198 * dstReg +CF= (byte) [srcBase]
3199 * </PRE>
3200 *
3201 * @param dstReg the destination register
3202 * @param srcBase the source base register
3203 */
3204 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
3205 public final void emitADC_Reg_RegInd_Byte(GPR dstReg, GPR srcBase) {
3206 int miStart = mi;
3207 // no group 1 to 4 prefix byte
3208 generateREXprefix(false, dstReg, null, srcBase);
3209 // single byte opcode
3210 setMachineCodes(mi++, (byte) 0x12);
3211 emitRegIndirectRegOperands(srcBase, dstReg);
3212 if (lister != null) lister.RRN(miStart, "ADC", dstReg, srcBase);
3213 }
3214
3215 /**
3216 * Generate a register--immediate ADC. That is,
3217 * <PRE>
3218 * dstReg +CF= imm
3219 * </PRE>
3220 *
3221 * @param dstReg the destination register
3222 * @param imm immediate
3223 */
3224 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
3225 public final void emitADC_Reg_Imm(GPR dstReg, int imm) {
3226 int miStart = mi;
3227 // no group 1 to 4 prefix byte
3228 generateREXprefix(false, null, null, dstReg);
3229 // single byte opcode
3230 if (fits(imm,8)) {
3231 setMachineCodes(mi++, (byte) 0x83);
3232 // "register 0x2" is really part of the opcode
3233 emitRegRegOperands(dstReg, GPR.getForOpcode(0x2));
3234 emitImm8((byte)imm);
3235 } else if (dstReg == EAX) {
3236 setMachineCodes(mi++, (byte) 0x15);
3237 emitImm32(imm);
3238 } else {
3239 setMachineCodes(mi++, (byte) 0x81);
3240 // "register 0x2" is really part of the opcode
3241 emitRegRegOperands(dstReg, GPR.getForOpcode(0x2));
3242 emitImm32(imm);
3243 }
3244 if (lister != null) lister.RI(miStart, "ADC", dstReg, imm);
3245 }
3246
3247 /**
3248 * Generate a register-displacement--immediate ADC. That is,
3249 * <PRE>
3250 * [dstBase + dstDisp] +CF= imm
3251 * </PRE>
3252 *
3253 * @param dstBase the destination register
3254 * @param dstDisp the destination displacement
3255 * @param imm immediate
3256 */
3257 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
3258 public final void emitADC_RegDisp_Imm(GPR dstBase, Offset dstDisp, int imm) {
3259 int miStart = mi;
3260 // no group 1 to 4 prefix byte
3261 generateREXprefix(false, null, null, dstBase);
3262 // single byte opcode
3263 if (fits(imm,8)) {
3264 setMachineCodes(mi++, (byte) 0x83);
3265 // "register 0x2" is really part of the opcode
3266 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x2));
3267 emitImm8((byte)imm);
3268 } else {
3269 setMachineCodes(mi++, (byte) 0x81);
3270 // "register 0x2" is really part of the opcode
3271 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x2));
3272 emitImm32(imm);
3273 }
3274 if (lister != null) lister.RDI(miStart, "ADC", dstBase, dstDisp, imm);
3275 }
3276
3277 /**
3278 * Generate a register-offset--immediate ADC. That is,
3279 * <PRE>
3280 * [dstIndex<<dstScale + dstDisp] +CF= imm
3281 * </PRE>
3282 *
3283 * @param dstIndex the destination index register
3284 * @param dstScale the destination shift amount
3285 * @param dstDisp the destination displacement
3286 * @param imm immediate
3287 */
3288 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
3289 public final void emitADC_RegOff_Imm(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
3290 int miStart = mi;
3291 // no group 1 to 4 prefix byte
3292 generateREXprefix(false, null, dstIndex, null);
3293 // single byte opcode
3294 if (fits(imm,8)) {
3295 setMachineCodes(mi++, (byte) 0x83);
3296 // "register 0x2" is really part of the opcode
3297 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
3298 emitImm8((byte)imm);
3299 } else {
3300 setMachineCodes(mi++, (byte) 0x81);
3301 // "register 0x2" is really part of the opcode
3302 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
3303 emitImm32(imm);
3304 }
3305 if (lister != null) lister.RFDI(miStart, "ADC", dstIndex, dstScale, dstDisp, imm);
3306 }
3307
3308 /**
3309 * Generate a absolute--immediate ADC. That is,
3310 * <PRE>
3311 * [dstDisp] +CF= imm
3312 * </PRE>
3313 *
3314 * @param dstDisp the destination displacement
3315 * @param imm immediate
3316 */
3317 public final void emitADC_Abs_Imm(Address dstDisp, int imm) {
3318 int miStart = mi;
3319 // no group 1 to 4 prefix byte
3320 generateREXprefix(false, null, null, null);
3321 // single byte opcode
3322 if (fits(imm,8)) {
3323 setMachineCodes(mi++, (byte) 0x83);
3324 // "register 0x2" is really part of the opcode
3325 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x2));
3326 emitImm8((byte)imm);
3327 } else {
3328 setMachineCodes(mi++, (byte) 0x81);
3329 // "register 0x2" is really part of the opcode
3330 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x2));
3331 emitImm32(imm);
3332 }
3333 if (lister != null) lister.RAI(miStart, "ADC", dstDisp, imm);
3334 }
3335
3336 /**
3337 * Generate a register-index--immediate ADC. That is,
3338 * <PRE>
3339 * [dstBase + dstIndex<<dstScale + dstDisp] +CF= imm
3340 * </PRE>
3341 *
3342 * @param dstBase the destination base register
3343 * @param dstIndex the destination index register
3344 * @param dstScale the destination shift amount
3345 * @param dstDisp the destination displacement
3346 * @param imm immediate
3347 */
3348 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
3349 public final void emitADC_RegIdx_Imm(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
3350 int miStart = mi;
3351 // no group 1 to 4 prefix byte
3352 generateREXprefix(false, null, dstIndex, dstBase);
3353 // single byte opcode
3354 if (fits(imm,8)) {
3355 setMachineCodes(mi++, (byte) 0x83);
3356 // "register 0x2" is really part of the opcode
3357 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
3358 emitImm8((byte)imm);
3359 } else {
3360 setMachineCodes(mi++, (byte) 0x81);
3361 // "register 0x2" is really part of the opcode
3362 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
3363 emitImm32(imm);
3364 }
3365 if (lister != null) lister.RXDI(miStart, "ADC", dstBase, dstIndex, dstScale, dstDisp, imm);
3366 }
3367
3368 /**
3369 * Generate a register(indirect)--immediate ADC. That is,
3370 * <PRE>
3371 * [dstBase] +CF= imm
3372 * </PRE>
3373 *
3374 * @param dstBase the destination base register
3375 * @param imm immediate
3376 */
3377 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
3378 public final void emitADC_RegInd_Imm(GPR dstBase, int imm) {
3379 int miStart = mi;
3380 // no group 1 to 4 prefix byte
3381 generateREXprefix(false, null, null, dstBase);
3382 // single byte opcode
3383 if (fits(imm,8)) {
3384 setMachineCodes(mi++, (byte) 0x83);
3385 // "register 0x2" is really part of the opcode
3386 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x2));
3387 emitImm8((byte)imm);
3388 } else {
3389 setMachineCodes(mi++, (byte) 0x81);
3390 // "register 0x2" is really part of the opcode
3391 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x2));
3392 emitImm32(imm);
3393 }
3394 if (lister != null) lister.RNI(miStart, "ADC", dstBase, imm);
3395 }
3396
3397 /**
3398 * Generate a register--immediate ADC. That is,
3399 * <PRE>
3400 * dstReg +CF= (word) imm
3401 * </PRE>
3402 *
3403 * @param dstReg the destination register
3404 * @param imm immediate
3405 */
3406 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
3407 public final void emitADC_Reg_Imm_Word(GPR dstReg, int imm) {
3408 int miStart = mi;
3409 setMachineCodes(mi++, (byte) 0x66);
3410 generateREXprefix(false, null, null, dstReg);
3411 // single byte opcode
3412 if (fits(imm,8)) {
3413 setMachineCodes(mi++, (byte) 0x83);
3414 // "register 0x2" is really part of the opcode
3415 emitRegRegOperands(dstReg, GPR.getForOpcode(0x2));
3416 emitImm8((byte)imm);
3417 } else if (dstReg == EAX) {
3418 setMachineCodes(mi++, (byte) 0x15);
3419 emitImm16(imm);
3420 } else {
3421 setMachineCodes(mi++, (byte) 0x81);
3422 // "register 0x2" is really part of the opcode
3423 emitRegRegOperands(dstReg, GPR.getForOpcode(0x2));
3424 emitImm16(imm);
3425 }
3426 if (lister != null) lister.RI(miStart, "ADC", dstReg, imm);
3427 }
3428
3429 /**
3430 * Generate a register-displacement--immediate ADC. That is,
3431 * <PRE>
3432 * [dstBase + dstDisp] +CF= (word) imm
3433 * </PRE>
3434 *
3435 * @param dstBase the destination register
3436 * @param dstDisp the destination displacement
3437 * @param imm immediate
3438 */
3439 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
3440 public final void emitADC_RegDisp_Imm_Word(GPR dstBase, Offset dstDisp, int imm) {
3441 int miStart = mi;
3442 setMachineCodes(mi++, (byte) 0x66);
3443 generateREXprefix(false, null, null, dstBase);
3444 // single byte opcode
3445 if (fits(imm,8)) {
3446 setMachineCodes(mi++, (byte) 0x83);
3447 // "register 0x2" is really part of the opcode
3448 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x2));
3449 emitImm8((byte)imm);
3450 } else {
3451 setMachineCodes(mi++, (byte) 0x81);
3452 // "register 0x2" is really part of the opcode
3453 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x2));
3454 emitImm16(imm);
3455 }
3456 if (lister != null) lister.RDI(miStart, "ADC", dstBase, dstDisp, imm);
3457 }
3458
3459 /**
3460 * Generate a register-offset--immediate ADC. That is,
3461 * <PRE>
3462 * [dstIndex<<dstScale + dstDisp] +CF= (word) imm
3463 * </PRE>
3464 *
3465 * @param dstIndex the destination index register
3466 * @param dstScale the destination shift amount
3467 * @param dstDisp the destination displacement
3468 * @param imm immediate
3469 */
3470 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
3471 public final void emitADC_RegOff_Imm_Word(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
3472 int miStart = mi;
3473 setMachineCodes(mi++, (byte) 0x66);
3474 generateREXprefix(false, null, dstIndex, null);
3475 // single byte opcode
3476 if (fits(imm,8)) {
3477 setMachineCodes(mi++, (byte) 0x83);
3478 // "register 0x2" is really part of the opcode
3479 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
3480 emitImm8((byte)imm);
3481 } else {
3482 setMachineCodes(mi++, (byte) 0x81);
3483 // "register 0x2" is really part of the opcode
3484 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
3485 emitImm16(imm);
3486 }
3487 if (lister != null) lister.RFDI(miStart, "ADC", dstIndex, dstScale, dstDisp, imm);
3488 }
3489
3490 /**
3491 * Generate a absolute--immediate ADC. That is,
3492 * <PRE>
3493 * [dstDisp] +CF= (word) imm
3494 * </PRE>
3495 *
3496 * @param dstDisp the destination displacement
3497 * @param imm immediate
3498 */
3499 public final void emitADC_Abs_Imm_Word(Address dstDisp, int imm) {
3500 int miStart = mi;
3501 setMachineCodes(mi++, (byte) 0x66);
3502 generateREXprefix(false, null, null, null);
3503 // single byte opcode
3504 if (fits(imm,8)) {
3505 setMachineCodes(mi++, (byte) 0x83);
3506 // "register 0x2" is really part of the opcode
3507 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x2));
3508 emitImm8((byte)imm);
3509 } else {
3510 setMachineCodes(mi++, (byte) 0x81);
3511 // "register 0x2" is really part of the opcode
3512 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x2));
3513 emitImm16(imm);
3514 }
3515 if (lister != null) lister.RAI(miStart, "ADC", dstDisp, imm);
3516 }
3517
3518 /**
3519 * Generate a register-index--immediate ADC. That is,
3520 * <PRE>
3521 * [dstBase + dstIndex<<dstScale + dstDisp] +CF= (word) imm
3522 * </PRE>
3523 *
3524 * @param dstBase the destination base register
3525 * @param dstIndex the destination index register
3526 * @param dstScale the destination shift amount
3527 * @param dstDisp the destination displacement
3528 * @param imm immediate
3529 */
3530 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
3531 public final void emitADC_RegIdx_Imm_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
3532 int miStart = mi;
3533 setMachineCodes(mi++, (byte) 0x66);
3534 generateREXprefix(false, null, dstIndex, dstBase);
3535 // single byte opcode
3536 if (fits(imm,8)) {
3537 setMachineCodes(mi++, (byte) 0x83);
3538 // "register 0x2" is really part of the opcode
3539 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
3540 emitImm8((byte)imm);
3541 } else {
3542 setMachineCodes(mi++, (byte) 0x81);
3543 // "register 0x2" is really part of the opcode
3544 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
3545 emitImm16(imm);
3546 }
3547 if (lister != null) lister.RXDI(miStart, "ADC", dstBase, dstIndex, dstScale, dstDisp, imm);
3548 }
3549
3550 /**
3551 * Generate a register(indirect)--immediate ADC. That is,
3552 * <PRE>
3553 * [dstBase] +CF= (word) imm
3554 * </PRE>
3555 *
3556 * @param dstBase the destination base register
3557 * @param imm immediate
3558 */
3559 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
3560 public final void emitADC_RegInd_Imm_Word(GPR dstBase, int imm) {
3561 int miStart = mi;
3562 setMachineCodes(mi++, (byte) 0x66);
3563 generateREXprefix(false, null, null, dstBase);
3564 // single byte opcode
3565 if (fits(imm,8)) {
3566 setMachineCodes(mi++, (byte) 0x83);
3567 // "register 0x2" is really part of the opcode
3568 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x2));
3569 emitImm8((byte)imm);
3570 } else {
3571 setMachineCodes(mi++, (byte) 0x81);
3572 // "register 0x2" is really part of the opcode
3573 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x2));
3574 emitImm16(imm);
3575 }
3576 if (lister != null) lister.RNI(miStart, "ADC", dstBase, imm);
3577 }
3578
3579 /**
3580 * Generate a register--immediate ADC. That is,
3581 * <PRE>
3582 * dstReg +CF= (quad) imm
3583 * </PRE>
3584 *
3585 * @param dstReg the destination register
3586 * @param imm immediate
3587 */
3588 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
3589 public final void emitADC_Reg_Imm_Quad(GPR dstReg, int imm) {
3590 int miStart = mi;
3591 // no group 1 to 4 prefix byte
3592 generateREXprefix(true, null, null, dstReg);
3593 // single byte opcode
3594 if (fits(imm,8)) {
3595 setMachineCodes(mi++, (byte) 0x83);
3596 // "register 0x2" is really part of the opcode
3597 emitRegRegOperands(dstReg, GPR.getForOpcode(0x2));
3598 emitImm8((byte)imm);
3599 } else if (dstReg == EAX) {
3600 setMachineCodes(mi++, (byte) 0x15);
3601 emitImm32(imm);
3602 } else {
3603 setMachineCodes(mi++, (byte) 0x81);
3604 // "register 0x2" is really part of the opcode
3605 emitRegRegOperands(dstReg, GPR.getForOpcode(0x2));
3606 emitImm32(imm);
3607 }
3608 if (lister != null) lister.RI(miStart, "ADC", dstReg, imm);
3609 }
3610
3611 /**
3612 * Generate a register-displacement--immediate ADC. That is,
3613 * <PRE>
3614 * [dstBase + dstDisp] +CF= (quad) imm
3615 * </PRE>
3616 *
3617 * @param dstBase the destination register
3618 * @param dstDisp the destination displacement
3619 * @param imm immediate
3620 */
3621 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
3622 public final void emitADC_RegDisp_Imm_Quad(GPR dstBase, Offset dstDisp, int imm) {
3623 int miStart = mi;
3624 // no group 1 to 4 prefix byte
3625 generateREXprefix(true, null, null, dstBase);
3626 // single byte opcode
3627 if (fits(imm,8)) {
3628 setMachineCodes(mi++, (byte) 0x83);
3629 // "register 0x2" is really part of the opcode
3630 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x2));
3631 emitImm8((byte)imm);
3632 } else {
3633 setMachineCodes(mi++, (byte) 0x81);
3634 // "register 0x2" is really part of the opcode
3635 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x2));
3636 emitImm32(imm);
3637 }
3638 if (lister != null) lister.RDI(miStart, "ADC", dstBase, dstDisp, imm);
3639 }
3640
3641 /**
3642 * Generate a register-offset--immediate ADC. That is,
3643 * <PRE>
3644 * [dstIndex<<dstScale + dstDisp] +CF= (quad) imm
3645 * </PRE>
3646 *
3647 * @param dstIndex the destination index register
3648 * @param dstScale the destination shift amount
3649 * @param dstDisp the destination displacement
3650 * @param imm immediate
3651 */
3652 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
3653 public final void emitADC_RegOff_Imm_Quad(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
3654 int miStart = mi;
3655 // no group 1 to 4 prefix byte
3656 generateREXprefix(true, null, dstIndex, null);
3657 // single byte opcode
3658 if (fits(imm,8)) {
3659 setMachineCodes(mi++, (byte) 0x83);
3660 // "register 0x2" is really part of the opcode
3661 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
3662 emitImm8((byte)imm);
3663 } else {
3664 setMachineCodes(mi++, (byte) 0x81);
3665 // "register 0x2" is really part of the opcode
3666 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
3667 emitImm32(imm);
3668 }
3669 if (lister != null) lister.RFDI(miStart, "ADC", dstIndex, dstScale, dstDisp, imm);
3670 }
3671
3672 /**
3673 * Generate a absolute--immediate ADC. That is,
3674 * <PRE>
3675 * [dstDisp] +CF= (quad) imm
3676 * </PRE>
3677 *
3678 * @param dstDisp the destination displacement
3679 * @param imm immediate
3680 */
3681 public final void emitADC_Abs_Imm_Quad(Address dstDisp, int imm) {
3682 int miStart = mi;
3683 // no group 1 to 4 prefix byte
3684 generateREXprefix(true, null, null, null);
3685 // single byte opcode
3686 if (fits(imm,8)) {
3687 setMachineCodes(mi++, (byte) 0x83);
3688 // "register 0x2" is really part of the opcode
3689 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x2));
3690 emitImm8((byte)imm);
3691 } else {
3692 setMachineCodes(mi++, (byte) 0x81);
3693 // "register 0x2" is really part of the opcode
3694 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x2));
3695 emitImm32(imm);
3696 }
3697 if (lister != null) lister.RAI(miStart, "ADC", dstDisp, imm);
3698 }
3699
3700 /**
3701 * Generate a register-index--immediate ADC. That is,
3702 * <PRE>
3703 * [dstBase + dstIndex<<dstScale + dstDisp] +CF= (quad) imm
3704 * </PRE>
3705 *
3706 * @param dstBase the destination base register
3707 * @param dstIndex the destination index register
3708 * @param dstScale the destination shift amount
3709 * @param dstDisp the destination displacement
3710 * @param imm immediate
3711 */
3712 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
3713 public final void emitADC_RegIdx_Imm_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
3714 int miStart = mi;
3715 // no group 1 to 4 prefix byte
3716 generateREXprefix(true, null, dstIndex, dstBase);
3717 // single byte opcode
3718 if (fits(imm,8)) {
3719 setMachineCodes(mi++, (byte) 0x83);
3720 // "register 0x2" is really part of the opcode
3721 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
3722 emitImm8((byte)imm);
3723 } else {
3724 setMachineCodes(mi++, (byte) 0x81);
3725 // "register 0x2" is really part of the opcode
3726 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
3727 emitImm32(imm);
3728 }
3729 if (lister != null) lister.RXDI(miStart, "ADC", dstBase, dstIndex, dstScale, dstDisp, imm);
3730 }
3731
3732 /**
3733 * Generate a register(indirect)--immediate ADC. That is,
3734 * <PRE>
3735 * [dstBase] +CF= (quad) imm
3736 * </PRE>
3737 *
3738 * @param dstBase the destination base register
3739 * @param imm immediate
3740 */
3741 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
3742 public final void emitADC_RegInd_Imm_Quad(GPR dstBase, int imm) {
3743 int miStart = mi;
3744 // no group 1 to 4 prefix byte
3745 generateREXprefix(true, null, null, dstBase);
3746 // single byte opcode
3747 if (fits(imm,8)) {
3748 setMachineCodes(mi++, (byte) 0x83);
3749 // "register 0x2" is really part of the opcode
3750 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x2));
3751 emitImm8((byte)imm);
3752 } else {
3753 setMachineCodes(mi++, (byte) 0x81);
3754 // "register 0x2" is really part of the opcode
3755 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x2));
3756 emitImm32(imm);
3757 }
3758 if (lister != null) lister.RNI(miStart, "ADC", dstBase, imm);
3759 }
3760
3761 /**
3762 * Generate a register--immediate ADC. That is,
3763 * <PRE>
3764 * dstReg +CF= (byte) imm
3765 * </PRE>
3766 *
3767 * @param dstReg the destination register
3768 * @param imm immediate
3769 */
3770 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
3771 public final void emitADC_Reg_Imm_Byte(GPR dstReg, int imm) {
3772 int miStart = mi;
3773 if (dstReg == EAX) {
3774 setMachineCodes(mi++, (byte) 0x14);
3775 emitImm8(imm);
3776 } else {
3777 generateREXprefix(false, null, null, dstReg);
3778 setMachineCodes(mi++, (byte) 0x80);
3779 // "register 0x2" is really part of the opcode
3780 emitRegRegOperands(dstReg, GPR.getForOpcode(0x2));
3781 emitImm8(imm);
3782 }
3783 if (lister != null) lister.RI(miStart, "ADC", dstReg, imm);
3784 }
3785
3786 /**
3787 * Generate a register-displacement--immediate ADC. That is,
3788 * <PRE>
3789 * [dstBase + dstDisp] +CF= (byte) imm
3790 * </PRE>
3791 *
3792 * @param dstBase the destination register
3793 * @param dstDisp the destination displacement
3794 * @param imm immediate
3795 */
3796 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
3797 public final void emitADC_RegDisp_Imm_Byte(GPR dstBase, Offset dstDisp, int imm) {
3798 int miStart = mi;
3799 generateREXprefix(false, null, null, dstBase);
3800 setMachineCodes(mi++, (byte) 0x80);
3801 // "register 0x2" is really part of the opcode
3802 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x2));
3803 emitImm8(imm);
3804 if (lister != null) lister.RDI(miStart, "ADC", dstBase, dstDisp, imm);
3805 }
3806
3807 /**
3808 * Generate a register-index--immediate ADC. That is,
3809 * <PRE>
3810 * [dstBase + dstIndex<<scale + dstDisp] +CF= (byte) imm
3811 * </PRE>
3812 *
3813 * @param dstBase the destination base register
3814 * @param dstIndex the destination index register
3815 * @param dstScale the destination shift amount
3816 * @param dstDisp the destination displacement
3817 * @param imm immediate
3818 */
3819 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
3820 public final void emitADC_RegIdx_Imm_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
3821 int miStart = mi;
3822 generateREXprefix(false, null, dstIndex, dstBase);
3823 setMachineCodes(mi++, (byte) 0x80);
3824 // "register 0x2" is really part of the opcode
3825 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
3826 emitImm8(imm);
3827 if (lister != null) lister.RXDI(miStart, "ADC", dstBase, dstIndex, dstScale, dstDisp, imm);
3828 }
3829
3830 /**
3831 * Generate a register-offset--immediate ADC. That is,
3832 * <PRE>
3833 * [dstIndex<<dstScale + dstDisp] +CF= (byte) imm
3834 * </PRE>
3835 *
3836 * @param dstIndex the destination index register
3837 * @param dstScale the destination shift amount
3838 * @param dstDisp the destination displacement
3839 * @param imm immediate
3840 */
3841 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
3842 public final void emitADC_RegOff_Imm_Byte(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
3843 int miStart = mi;
3844 generateREXprefix(false, null, dstIndex, null);
3845 setMachineCodes(mi++, (byte) 0x80);
3846 // "register 0x2" is really part of the opcode
3847 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
3848 emitImm8(imm);
3849 if (lister != null) lister.RFDI(miStart, "ADC", dstIndex, dstScale, dstDisp, imm);
3850 }
3851
3852 /**
3853 * Generate a absolute--immediate ADC. That is,
3854 * <PRE>
3855 * [dstDisp] +CF= (byte) imm
3856 * </PRE>
3857 *
3858 * @param dstDisp the destination displacement
3859 * @param imm immediate
3860 */
3861 public final void emitADC_Abs_Imm_Byte(Address dstDisp, int imm) {
3862 int miStart = mi;
3863 generateREXprefix(false, null, null, null);
3864 setMachineCodes(mi++, (byte) 0x80);
3865 // "register 0x2" is really part of the opcode
3866 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x2));
3867 emitImm8(imm);
3868 if (lister != null) lister.RAI(miStart, "ADC", dstDisp, imm);
3869 }
3870
3871 /**
3872 * Generate a register(indirect)--immediate ADC. That is,
3873 * <PRE>
3874 * [dstBase] +CF= (byte) imm
3875 * </PRE>
3876 *
3877 * @param dstBase the destination base register
3878 * @param imm immediate
3879 */
3880 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
3881 public final void emitADC_RegInd_Imm_Byte(GPR dstBase, int imm) {
3882 int miStart = mi;
3883 generateREXprefix(false, null, null, dstBase);
3884 setMachineCodes(mi++, (byte) 0x80);
3885 // "register 0x2" is really part of the opcode
3886 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x2));
3887 emitImm8(imm);
3888 if (lister != null) lister.RNI(miStart, "ADC", dstBase, imm);
3889 }
3890
3891 /**
3892 * Generate a register(indirect)--register ADD. That is,
3893 * <PRE>
3894 * [dstBase] += srcReg
3895 * </PRE>
3896 *
3897 * @param dstBase the destination base
3898 * @param srcReg the source register
3899 */
3900 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
3901 public final void emitADD_RegInd_Reg(GPR dstBase, GPR srcReg) {
3902 int miStart = mi;
3903 // no group 1 to 4 prefix byte
3904 generateREXprefix(false, srcReg, null, dstBase);
3905 // single byte opcode
3906 setMachineCodes(mi++, (byte) 0x01);
3907 emitRegIndirectRegOperands(dstBase, srcReg);
3908 if (lister != null) lister.RNR(miStart, "ADD", dstBase, srcReg);
3909 }
3910
3911 /**
3912 * Generate a register-offset--register ADD. That is,
3913 * <PRE>
3914 * [dstReg<<dstScale + dstDisp] += srcReg
3915 * </PRE>
3916 *
3917 * @param dstIndex the destination index register
3918 * @param dstScale the destination shift amount
3919 * @param dstDisp the destination displacement
3920 * @param srcReg the source register
3921 */
3922 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
3923 public final void emitADD_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
3924 int miStart = mi;
3925 // no group 1 to 4 prefix byte
3926 generateREXprefix(false, srcReg, dstIndex, null);
3927 // single byte opcode
3928 setMachineCodes(mi++, (byte) 0x01);
3929 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
3930 if (lister != null) lister.RFDR(miStart, "ADD", dstIndex, dstScale, dstDisp, srcReg);
3931 }
3932
3933 /**
3934 * Generate a absolute--register ADD. That is,
3935 * <PRE>
3936 * [dstDisp] += srcReg
3937 * </PRE>
3938 *
3939 * @param dstDisp the destination address
3940 * @param srcReg the source register
3941 */
3942 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
3943 public final void emitADD_Abs_Reg(Address dstDisp, GPR srcReg) {
3944 int miStart = mi;
3945 // no group 1 to 4 prefix byte
3946 generateREXprefix(false, srcReg, null, null);
3947 // single byte opcode
3948 setMachineCodes(mi++, (byte) 0x01);
3949 emitAbsRegOperands(dstDisp, srcReg);
3950 if (lister != null) lister.RAR(miStart, "ADD", dstDisp, srcReg);
3951 }
3952
3953 /**
3954 * Generate a register-index--register ADD. That is,
3955 * <PRE>
3956 * [dstBase + dstIndex<<dstScale + dstDisp] += srcReg
3957 * </PRE>
3958 *
3959 * @param dstBase the base register
3960 * @param dstIndex the destination index register
3961 * @param dstScale the destination shift amount
3962 * @param dstDisp the destination displacement
3963 * @param srcReg the source register
3964 */
3965 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
3966 public final void emitADD_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
3967 int miStart = mi;
3968 // no group 1 to 4 prefix byte
3969 generateREXprefix(false, srcReg, dstIndex, dstBase);
3970 // single byte opcode
3971 setMachineCodes(mi++, (byte) 0x01);
3972 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
3973 if (lister != null) lister.RXDR(miStart, "ADD", dstBase, dstIndex, dstScale, dstDisp, srcReg);
3974 }
3975
3976 /**
3977 * Generate a register-displacement--register ADD. That is,
3978 * <PRE>
3979 * [dstBase + dstDisp] += srcReg
3980 * </PRE>
3981 *
3982 * @param dstBase the base register
3983 * @param dstDisp the destination displacement
3984 * @param srcReg the source register
3985 */
3986 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
3987 public final void emitADD_RegDisp_Reg(GPR dstBase, Offset dstDisp, GPR srcReg) {
3988 int miStart = mi;
3989 // no group 1 to 4 prefix byte
3990 generateREXprefix(false, srcReg, null, dstBase);
3991 // single byte opcode
3992 setMachineCodes(mi++, (byte) 0x01);
3993 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
3994 if (lister != null) lister.RDR(miStart, "ADD", dstBase, dstDisp, srcReg);
3995 }
3996
3997 /**
3998 * Generate a register--register ADD. That is,
3999 * <PRE>
4000 * dstReg += srcReg
4001 * </PRE>
4002 *
4003 * @param dstReg the destination register
4004 * @param srcReg the source register
4005 */
4006 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4007 public final void emitADD_Reg_Reg(GPR dstReg, GPR srcReg) {
4008 int miStart = mi;
4009 // no group 1 to 4 prefix byte
4010 generateREXprefix(false, srcReg, null, dstReg);
4011 // single byte opcode
4012 setMachineCodes(mi++, (byte) 0x01);
4013 emitRegRegOperands(dstReg, srcReg);
4014 if (lister != null) lister.RR(miStart, "ADD", dstReg, srcReg);
4015 }
4016
4017 /**
4018 * Generate a register--register-displacement ADD. That is,
4019 * <PRE>
4020 * dstReg += [srcReg + srcDisp]
4021 * </PRE>
4022 *
4023 * @param dstReg the destination register
4024 * @param srcBase the source register
4025 * @param srcDisp the source displacement
4026 */
4027 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4028 public final void emitADD_Reg_RegDisp(GPR dstReg, GPR srcBase, Offset srcDisp) {
4029 int miStart = mi;
4030 // no group 1 to 4 prefix byte
4031 generateREXprefix(false, dstReg, null, srcBase);
4032 // single byte opcode
4033 setMachineCodes(mi++, (byte) 0x03);
4034 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
4035 if (lister != null) lister.RRD(miStart, "ADD", dstReg, srcBase, srcDisp);
4036 }
4037
4038 /**
4039 * Generate a register--register-offset ADD. That is,
4040 * <PRE>
4041 * dstReg += [srcIndex<<srcScale + srcDisp]
4042 * </PRE>
4043 *
4044 * @param dstReg the destination register
4045 * @param srcIndex the source index register
4046 * @param srcScale the source shift amount
4047 * @param srcDisp the source displacement
4048 */
4049 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4050 public final void emitADD_Reg_RegOff(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
4051 int miStart = mi;
4052 // no group 1 to 4 prefix byte
4053 generateREXprefix(false, dstReg, srcIndex, null);
4054 // single byte opcode
4055 setMachineCodes(mi++, (byte) 0x03);
4056 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
4057 if (lister != null) lister.RRFD(miStart, "ADD", dstReg, srcIndex, srcScale, srcDisp);
4058 }
4059
4060 /**
4061 * Generate a register--register-offset ADD. That is,
4062 * <PRE>
4063 * dstReg += [srcDisp]
4064 * </PRE>
4065 *
4066 * @param dstReg the destination register
4067 * @param srcDisp the source displacement
4068 */
4069 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
4070 public final void emitADD_Reg_Abs(GPR dstReg, Address srcDisp) {
4071 int miStart = mi;
4072 // no group 1 to 4 prefix byte
4073 generateREXprefix(false, dstReg, null, null);
4074 // single byte opcode
4075 setMachineCodes(mi++, (byte) 0x03);
4076 emitAbsRegOperands(srcDisp, dstReg);
4077 if (lister != null) lister.RRA(miStart, "ADD", dstReg, srcDisp);
4078 }
4079
4080 /**
4081 * Generate a register--register-offset ADD. That is,
4082 * <PRE>
4083 * dstReg += [srcBase + srcIndex<<srcScale + srcDisp]
4084 * </PRE>
4085 *
4086 * @param dstReg the destination register
4087 * @param srcBase the source base register
4088 * @param srcIndex the source index register
4089 * @param srcScale the source shift amount
4090 * @param srcDisp the source displacement
4091 */
4092 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
4093 public final void emitADD_Reg_RegIdx(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
4094 int miStart = mi;
4095 // no group 1 to 4 prefix byte
4096 generateREXprefix(false, dstReg, srcIndex, srcBase);
4097 // single byte opcode
4098 setMachineCodes(mi++, (byte) 0x03);
4099 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
4100 if (lister != null) lister.RRXD(miStart, "ADD", dstReg, srcBase, srcIndex, srcScale, srcDisp);
4101 }
4102
4103 /**
4104 * Generate a register--register(indirect) ADD. That is,
4105 * <PRE>
4106 * dstReg += [srcBase]
4107 * </PRE>
4108 *
4109 * @param dstReg the destination register
4110 * @param srcBase the source base register
4111 */
4112 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4113 public final void emitADD_Reg_RegInd(GPR dstReg, GPR srcBase) {
4114 int miStart = mi;
4115 // no group 1 to 4 prefix byte
4116 generateREXprefix(false, dstReg, null, srcBase);
4117 // single byte opcode
4118 setMachineCodes(mi++, (byte) 0x03);
4119 emitRegIndirectRegOperands(srcBase, dstReg);
4120 if (lister != null) lister.RRN(miStart, "ADD", dstReg, srcBase);
4121 }
4122
4123 /**
4124 * Generate a register(indirect)--register ADD. That is,
4125 * <PRE>
4126 * [dstBase] += (word) srcReg
4127 * </PRE>
4128 *
4129 * @param dstBase the destination base
4130 * @param srcReg the source register
4131 */
4132 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4133 public final void emitADD_RegInd_Reg_Word(GPR dstBase, GPR srcReg) {
4134 int miStart = mi;
4135 setMachineCodes(mi++, (byte) 0x66);
4136 generateREXprefix(false, srcReg, null, dstBase);
4137 // single byte opcode
4138 setMachineCodes(mi++, (byte) 0x01);
4139 emitRegIndirectRegOperands(dstBase, srcReg);
4140 if (lister != null) lister.RNR(miStart, "ADD", dstBase, srcReg);
4141 }
4142
4143 /**
4144 * Generate a register-offset--register ADD. That is,
4145 * <PRE>
4146 * [dstReg<<dstScale + dstDisp] += (word) srcReg
4147 * </PRE>
4148 *
4149 * @param dstIndex the destination index register
4150 * @param dstScale the destination shift amount
4151 * @param dstDisp the destination displacement
4152 * @param srcReg the source register
4153 */
4154 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
4155 public final void emitADD_RegOff_Reg_Word(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
4156 int miStart = mi;
4157 setMachineCodes(mi++, (byte) 0x66);
4158 generateREXprefix(false, srcReg, dstIndex, null);
4159 // single byte opcode
4160 setMachineCodes(mi++, (byte) 0x01);
4161 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
4162 if (lister != null) lister.RFDR(miStart, "ADD", dstIndex, dstScale, dstDisp, srcReg);
4163 }
4164
4165 /**
4166 * Generate a absolute--register ADD. That is,
4167 * <PRE>
4168 * [dstDisp] += (word) srcReg
4169 * </PRE>
4170 *
4171 * @param dstDisp the destination address
4172 * @param srcReg the source register
4173 */
4174 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
4175 public final void emitADD_Abs_Reg_Word(Address dstDisp, GPR srcReg) {
4176 int miStart = mi;
4177 setMachineCodes(mi++, (byte) 0x66);
4178 generateREXprefix(false, srcReg, null, null);
4179 // single byte opcode
4180 setMachineCodes(mi++, (byte) 0x01);
4181 emitAbsRegOperands(dstDisp, srcReg);
4182 if (lister != null) lister.RAR(miStart, "ADD", dstDisp, srcReg);
4183 }
4184
4185 /**
4186 * Generate a register-index--register ADD. That is,
4187 * <PRE>
4188 * [dstBase + dstIndex<<dstScale + dstDisp] += (word) srcReg
4189 * </PRE>
4190 *
4191 * @param dstBase the base register
4192 * @param dstIndex the destination index register
4193 * @param dstScale the destination shift amount
4194 * @param dstDisp the destination displacement
4195 * @param srcReg the source register
4196 */
4197 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
4198 public final void emitADD_RegIdx_Reg_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
4199 int miStart = mi;
4200 setMachineCodes(mi++, (byte) 0x66);
4201 generateREXprefix(false, srcReg, dstIndex, dstBase);
4202 // single byte opcode
4203 setMachineCodes(mi++, (byte) 0x01);
4204 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
4205 if (lister != null) lister.RXDR(miStart, "ADD", dstBase, dstIndex, dstScale, dstDisp, srcReg);
4206 }
4207
4208 /**
4209 * Generate a register-displacement--register ADD. That is,
4210 * <PRE>
4211 * [dstBase + dstDisp] += (word) srcReg
4212 * </PRE>
4213 *
4214 * @param dstBase the base register
4215 * @param dstDisp the destination displacement
4216 * @param srcReg the source register
4217 */
4218 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
4219 public final void emitADD_RegDisp_Reg_Word(GPR dstBase, Offset dstDisp, GPR srcReg) {
4220 int miStart = mi;
4221 setMachineCodes(mi++, (byte) 0x66);
4222 generateREXprefix(false, srcReg, null, dstBase);
4223 // single byte opcode
4224 setMachineCodes(mi++, (byte) 0x01);
4225 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
4226 if (lister != null) lister.RDR(miStart, "ADD", dstBase, dstDisp, srcReg);
4227 }
4228
4229 /**
4230 * Generate a register--register ADD. That is,
4231 * <PRE>
4232 * dstReg += (word) srcReg
4233 * </PRE>
4234 *
4235 * @param dstReg the destination register
4236 * @param srcReg the source register
4237 */
4238 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4239 public final void emitADD_Reg_Reg_Word(GPR dstReg, GPR srcReg) {
4240 int miStart = mi;
4241 setMachineCodes(mi++, (byte) 0x66);
4242 generateREXprefix(false, srcReg, null, dstReg);
4243 // single byte opcode
4244 setMachineCodes(mi++, (byte) 0x01);
4245 emitRegRegOperands(dstReg, srcReg);
4246 if (lister != null) lister.RR(miStart, "ADD", dstReg, srcReg);
4247 }
4248
4249 /**
4250 * Generate a register--register-displacement ADD. That is,
4251 * <PRE>
4252 * dstReg += (word) [srcReg + srcDisp]
4253 * </PRE>
4254 *
4255 * @param dstReg the destination register
4256 * @param srcBase the source register
4257 * @param srcDisp the source displacement
4258 */
4259 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4260 public final void emitADD_Reg_RegDisp_Word(GPR dstReg, GPR srcBase, Offset srcDisp) {
4261 int miStart = mi;
4262 setMachineCodes(mi++, (byte) 0x66);
4263 generateREXprefix(false, dstReg, null, srcBase);
4264 // single byte opcode
4265 setMachineCodes(mi++, (byte) 0x03);
4266 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
4267 if (lister != null) lister.RRD(miStart, "ADD", dstReg, srcBase, srcDisp);
4268 }
4269
4270 /**
4271 * Generate a register--register-offset ADD. That is,
4272 * <PRE>
4273 * dstReg += (word) [srcIndex<<srcScale + srcDisp]
4274 * </PRE>
4275 *
4276 * @param dstReg the destination register
4277 * @param srcIndex the source index register
4278 * @param srcScale the source shift amount
4279 * @param srcDisp the source displacement
4280 */
4281 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4282 public final void emitADD_Reg_RegOff_Word(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
4283 int miStart = mi;
4284 setMachineCodes(mi++, (byte) 0x66);
4285 generateREXprefix(false, dstReg, srcIndex, null);
4286 // single byte opcode
4287 setMachineCodes(mi++, (byte) 0x03);
4288 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
4289 if (lister != null) lister.RRFD(miStart, "ADD", dstReg, srcIndex, srcScale, srcDisp);
4290 }
4291
4292 /**
4293 * Generate a register--register-offset ADD. That is,
4294 * <PRE>
4295 * dstReg += (word) [srcDisp]
4296 * </PRE>
4297 *
4298 * @param dstReg the destination register
4299 * @param srcDisp the source displacement
4300 */
4301 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
4302 public final void emitADD_Reg_Abs_Word(GPR dstReg, Address srcDisp) {
4303 int miStart = mi;
4304 setMachineCodes(mi++, (byte) 0x66);
4305 generateREXprefix(false, dstReg, null, null);
4306 // single byte opcode
4307 setMachineCodes(mi++, (byte) 0x03);
4308 emitAbsRegOperands(srcDisp, dstReg);
4309 if (lister != null) lister.RRA(miStart, "ADD", dstReg, srcDisp);
4310 }
4311
4312 /**
4313 * Generate a register--register-offset ADD. That is,
4314 * <PRE>
4315 * dstReg += (word) [srcBase + srcIndex<<srcScale + srcDisp]
4316 * </PRE>
4317 *
4318 * @param dstReg the destination register
4319 * @param srcBase the source base register
4320 * @param srcIndex the source index register
4321 * @param srcScale the source shift amount
4322 * @param srcDisp the source displacement
4323 */
4324 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
4325 public final void emitADD_Reg_RegIdx_Word(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
4326 int miStart = mi;
4327 setMachineCodes(mi++, (byte) 0x66);
4328 generateREXprefix(false, dstReg, srcIndex, srcBase);
4329 // single byte opcode
4330 setMachineCodes(mi++, (byte) 0x03);
4331 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
4332 if (lister != null) lister.RRXD(miStart, "ADD", dstReg, srcBase, srcIndex, srcScale, srcDisp);
4333 }
4334
4335 /**
4336 * Generate a register--register(indirect) ADD. That is,
4337 * <PRE>
4338 * dstReg += (word) [srcBase]
4339 * </PRE>
4340 *
4341 * @param dstReg the destination register
4342 * @param srcBase the source base register
4343 */
4344 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4345 public final void emitADD_Reg_RegInd_Word(GPR dstReg, GPR srcBase) {
4346 int miStart = mi;
4347 setMachineCodes(mi++, (byte) 0x66);
4348 generateREXprefix(false, dstReg, null, srcBase);
4349 // single byte opcode
4350 setMachineCodes(mi++, (byte) 0x03);
4351 emitRegIndirectRegOperands(srcBase, dstReg);
4352 if (lister != null) lister.RRN(miStart, "ADD", dstReg, srcBase);
4353 }
4354
4355 /**
4356 * Generate a register(indirect)--register ADD. That is,
4357 * <PRE>
4358 * [dstBase] += (quad) srcReg
4359 * </PRE>
4360 *
4361 * @param dstBase the destination base
4362 * @param srcReg the source register
4363 */
4364 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4365 public final void emitADD_RegInd_Reg_Quad(GPR dstBase, GPR srcReg) {
4366 int miStart = mi;
4367 // no group 1 to 4 prefix byte
4368 generateREXprefix(true, srcReg, null, dstBase);
4369 // single byte opcode
4370 setMachineCodes(mi++, (byte) 0x01);
4371 emitRegIndirectRegOperands(dstBase, srcReg);
4372 if (lister != null) lister.RNR(miStart, "ADD", dstBase, srcReg);
4373 }
4374
4375 /**
4376 * Generate a register-offset--register ADD. That is,
4377 * <PRE>
4378 * [dstReg<<dstScale + dstDisp] += (quad) srcReg
4379 * </PRE>
4380 *
4381 * @param dstIndex the destination index register
4382 * @param dstScale the destination shift amount
4383 * @param dstDisp the destination displacement
4384 * @param srcReg the source register
4385 */
4386 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
4387 public final void emitADD_RegOff_Reg_Quad(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
4388 int miStart = mi;
4389 // no group 1 to 4 prefix byte
4390 generateREXprefix(true, srcReg, dstIndex, null);
4391 // single byte opcode
4392 setMachineCodes(mi++, (byte) 0x01);
4393 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
4394 if (lister != null) lister.RFDR(miStart, "ADD", dstIndex, dstScale, dstDisp, srcReg);
4395 }
4396
4397 /**
4398 * Generate a absolute--register ADD. That is,
4399 * <PRE>
4400 * [dstDisp] += (quad) srcReg
4401 * </PRE>
4402 *
4403 * @param dstDisp the destination address
4404 * @param srcReg the source register
4405 */
4406 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
4407 public final void emitADD_Abs_Reg_Quad(Address dstDisp, GPR srcReg) {
4408 int miStart = mi;
4409 // no group 1 to 4 prefix byte
4410 generateREXprefix(true, srcReg, null, null);
4411 // single byte opcode
4412 setMachineCodes(mi++, (byte) 0x01);
4413 emitAbsRegOperands(dstDisp, srcReg);
4414 if (lister != null) lister.RAR(miStart, "ADD", dstDisp, srcReg);
4415 }
4416
4417 /**
4418 * Generate a register-index--register ADD. That is,
4419 * <PRE>
4420 * [dstBase + dstIndex<<dstScale + dstDisp] += (quad) srcReg
4421 * </PRE>
4422 *
4423 * @param dstBase the base register
4424 * @param dstIndex the destination index register
4425 * @param dstScale the destination shift amount
4426 * @param dstDisp the destination displacement
4427 * @param srcReg the source register
4428 */
4429 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
4430 public final void emitADD_RegIdx_Reg_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
4431 int miStart = mi;
4432 // no group 1 to 4 prefix byte
4433 generateREXprefix(true, srcReg, dstIndex, dstBase);
4434 // single byte opcode
4435 setMachineCodes(mi++, (byte) 0x01);
4436 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
4437 if (lister != null) lister.RXDR(miStart, "ADD", dstBase, dstIndex, dstScale, dstDisp, srcReg);
4438 }
4439
4440 /**
4441 * Generate a register-displacement--register ADD. That is,
4442 * <PRE>
4443 * [dstBase + dstDisp] += (quad) srcReg
4444 * </PRE>
4445 *
4446 * @param dstBase the base register
4447 * @param dstDisp the destination displacement
4448 * @param srcReg the source register
4449 */
4450 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
4451 public final void emitADD_RegDisp_Reg_Quad(GPR dstBase, Offset dstDisp, GPR srcReg) {
4452 int miStart = mi;
4453 // no group 1 to 4 prefix byte
4454 generateREXprefix(true, srcReg, null, dstBase);
4455 // single byte opcode
4456 setMachineCodes(mi++, (byte) 0x01);
4457 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
4458 if (lister != null) lister.RDR(miStart, "ADD", dstBase, dstDisp, srcReg);
4459 }
4460
4461 /**
4462 * Generate a register--register ADD. That is,
4463 * <PRE>
4464 * dstReg += (quad) srcReg
4465 * </PRE>
4466 *
4467 * @param dstReg the destination register
4468 * @param srcReg the source register
4469 */
4470 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4471 public final void emitADD_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
4472 int miStart = mi;
4473 // no group 1 to 4 prefix byte
4474 generateREXprefix(true, srcReg, null, dstReg);
4475 // single byte opcode
4476 setMachineCodes(mi++, (byte) 0x01);
4477 emitRegRegOperands(dstReg, srcReg);
4478 if (lister != null) lister.RR(miStart, "ADD", dstReg, srcReg);
4479 }
4480
4481 /**
4482 * Generate a register--register-displacement ADD. That is,
4483 * <PRE>
4484 * dstReg += (quad) [srcReg + srcDisp]
4485 * </PRE>
4486 *
4487 * @param dstReg the destination register
4488 * @param srcBase the source register
4489 * @param srcDisp the source displacement
4490 */
4491 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4492 public final void emitADD_Reg_RegDisp_Quad(GPR dstReg, GPR srcBase, Offset srcDisp) {
4493 int miStart = mi;
4494 // no group 1 to 4 prefix byte
4495 generateREXprefix(true, dstReg, null, srcBase);
4496 // single byte opcode
4497 setMachineCodes(mi++, (byte) 0x03);
4498 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
4499 if (lister != null) lister.RRD(miStart, "ADD", dstReg, srcBase, srcDisp);
4500 }
4501
4502 /**
4503 * Generate a register--register-offset ADD. That is,
4504 * <PRE>
4505 * dstReg += (quad) [srcIndex<<srcScale + srcDisp]
4506 * </PRE>
4507 *
4508 * @param dstReg the destination register
4509 * @param srcIndex the source index register
4510 * @param srcScale the source shift amount
4511 * @param srcDisp the source displacement
4512 */
4513 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4514 public final void emitADD_Reg_RegOff_Quad(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
4515 int miStart = mi;
4516 // no group 1 to 4 prefix byte
4517 generateREXprefix(true, dstReg, srcIndex, null);
4518 // single byte opcode
4519 setMachineCodes(mi++, (byte) 0x03);
4520 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
4521 if (lister != null) lister.RRFD(miStart, "ADD", dstReg, srcIndex, srcScale, srcDisp);
4522 }
4523
4524 /**
4525 * Generate a register--register-offset ADD. That is,
4526 * <PRE>
4527 * dstReg += (quad) [srcDisp]
4528 * </PRE>
4529 *
4530 * @param dstReg the destination register
4531 * @param srcDisp the source displacement
4532 */
4533 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
4534 public final void emitADD_Reg_Abs_Quad(GPR dstReg, Address srcDisp) {
4535 int miStart = mi;
4536 // no group 1 to 4 prefix byte
4537 generateREXprefix(true, dstReg, null, null);
4538 // single byte opcode
4539 setMachineCodes(mi++, (byte) 0x03);
4540 emitAbsRegOperands(srcDisp, dstReg);
4541 if (lister != null) lister.RRA(miStart, "ADD", dstReg, srcDisp);
4542 }
4543
4544 /**
4545 * Generate a register--register-offset ADD. That is,
4546 * <PRE>
4547 * dstReg += (quad) [srcBase + srcIndex<<srcScale + srcDisp]
4548 * </PRE>
4549 *
4550 * @param dstReg the destination register
4551 * @param srcBase the source base register
4552 * @param srcIndex the source index register
4553 * @param srcScale the source shift amount
4554 * @param srcDisp the source displacement
4555 */
4556 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
4557 public final void emitADD_Reg_RegIdx_Quad(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
4558 int miStart = mi;
4559 // no group 1 to 4 prefix byte
4560 generateREXprefix(true, dstReg, srcIndex, srcBase);
4561 // single byte opcode
4562 setMachineCodes(mi++, (byte) 0x03);
4563 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
4564 if (lister != null) lister.RRXD(miStart, "ADD", dstReg, srcBase, srcIndex, srcScale, srcDisp);
4565 }
4566
4567 /**
4568 * Generate a register--register(indirect) ADD. That is,
4569 * <PRE>
4570 * dstReg += (quad) [srcBase]
4571 * </PRE>
4572 *
4573 * @param dstReg the destination register
4574 * @param srcBase the source base register
4575 */
4576 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4577 public final void emitADD_Reg_RegInd_Quad(GPR dstReg, GPR srcBase) {
4578 int miStart = mi;
4579 // no group 1 to 4 prefix byte
4580 generateREXprefix(true, dstReg, null, srcBase);
4581 // single byte opcode
4582 setMachineCodes(mi++, (byte) 0x03);
4583 emitRegIndirectRegOperands(srcBase, dstReg);
4584 if (lister != null) lister.RRN(miStart, "ADD", dstReg, srcBase);
4585 }
4586
4587 /**
4588 * Generate a register(indirect)--register ADD. That is,
4589 * <PRE>
4590 * [dstBase] += (byte) srcReg
4591 * </PRE>
4592 *
4593 * @param dstBase the destination base
4594 * @param srcReg the source register
4595 */
4596 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4597 public final void emitADD_RegInd_Reg_Byte(GPR dstBase, GPR srcReg) {
4598 int miStart = mi;
4599 // no group 1 to 4 prefix byte
4600 generateREXprefix(false, srcReg, null, dstBase);
4601 // single byte opcode
4602 setMachineCodes(mi++, (byte) 0x00);
4603 emitRegIndirectRegOperands(dstBase, srcReg);
4604 if (lister != null) lister.RNR(miStart, "ADD", dstBase, srcReg);
4605 }
4606
4607 /**
4608 * Generate a register-offset--register ADD. That is,
4609 * <PRE>
4610 * [dstReg<<dstScale + dstDisp] += (byte) srcReg
4611 * </PRE>
4612 *
4613 * @param dstIndex the destination index register
4614 * @param dstScale the destination shift amount
4615 * @param dstDisp the destination displacement
4616 * @param srcReg the source register
4617 */
4618 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
4619 public final void emitADD_RegOff_Reg_Byte(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
4620 int miStart = mi;
4621 // no group 1 to 4 prefix byte
4622 generateREXprefix(false, srcReg, dstIndex, null);
4623 // single byte opcode
4624 setMachineCodes(mi++, (byte) 0x00);
4625 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
4626 if (lister != null) lister.RFDR(miStart, "ADD", dstIndex, dstScale, dstDisp, srcReg);
4627 }
4628
4629 /**
4630 * Generate a absolute--register ADD. That is,
4631 * <PRE>
4632 * [dstDisp] += (byte) srcReg
4633 * </PRE>
4634 *
4635 * @param dstDisp the destination address
4636 * @param srcReg the source register
4637 */
4638 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
4639 public final void emitADD_Abs_Reg_Byte(Address dstDisp, GPR srcReg) {
4640 int miStart = mi;
4641 // no group 1 to 4 prefix byte
4642 generateREXprefix(false, srcReg, null, null);
4643 // single byte opcode
4644 setMachineCodes(mi++, (byte) 0x00);
4645 emitAbsRegOperands(dstDisp, srcReg);
4646 if (lister != null) lister.RAR(miStart, "ADD", dstDisp, srcReg);
4647 }
4648
4649 /**
4650 * Generate a register-index--register ADD. That is,
4651 * <PRE>
4652 * [dstBase + dstIndex<<dstScale + dstDisp] += (byte) srcReg
4653 * </PRE>
4654 *
4655 * @param dstBase the base register
4656 * @param dstIndex the destination index register
4657 * @param dstScale the destination shift amount
4658 * @param dstDisp the destination displacement
4659 * @param srcReg the source register
4660 */
4661 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
4662 public final void emitADD_RegIdx_Reg_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
4663 int miStart = mi;
4664 // no group 1 to 4 prefix byte
4665 generateREXprefix(false, srcReg, dstIndex, dstBase);
4666 // single byte opcode
4667 setMachineCodes(mi++, (byte) 0x00);
4668 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
4669 if (lister != null) lister.RXDR(miStart, "ADD", dstBase, dstIndex, dstScale, dstDisp, srcReg);
4670 }
4671
4672 /**
4673 * Generate a register-displacement--register ADD. That is,
4674 * <PRE>
4675 * [dstBase + dstDisp] += (byte) srcReg
4676 * </PRE>
4677 *
4678 * @param dstBase the base register
4679 * @param dstDisp the destination displacement
4680 * @param srcReg the source register
4681 */
4682 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
4683 public final void emitADD_RegDisp_Reg_Byte(GPR dstBase, Offset dstDisp, GPR srcReg) {
4684 int miStart = mi;
4685 // no group 1 to 4 prefix byte
4686 generateREXprefix(false, srcReg, null, dstBase);
4687 // single byte opcode
4688 setMachineCodes(mi++, (byte) 0x00);
4689 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
4690 if (lister != null) lister.RDR(miStart, "ADD", dstBase, dstDisp, srcReg);
4691 }
4692
4693 /**
4694 * Generate a register--register ADD. That is,
4695 * <PRE>
4696 * dstReg += (byte) srcReg
4697 * </PRE>
4698 *
4699 * @param dstReg the destination register
4700 * @param srcReg the source register
4701 */
4702 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4703 public final void emitADD_Reg_Reg_Byte(GPR dstReg, GPR srcReg) {
4704 int miStart = mi;
4705 // no group 1 to 4 prefix byte
4706 generateREXprefix(false, srcReg, null, dstReg);
4707 // single byte opcode
4708 setMachineCodes(mi++, (byte) 0x00);
4709 emitRegRegOperands(dstReg, srcReg);
4710 if (lister != null) lister.RR(miStart, "ADD", dstReg, srcReg);
4711 }
4712
4713 /**
4714 * Generate a register--register-displacement ADD. That is,
4715 * <PRE>
4716 * dstReg += (byte) [srcReg + srcDisp]
4717 * </PRE>
4718 *
4719 * @param dstReg the destination register
4720 * @param srcBase the source register
4721 * @param srcDisp the source displacement
4722 */
4723 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4724 public final void emitADD_Reg_RegDisp_Byte(GPR dstReg, GPR srcBase, Offset srcDisp) {
4725 int miStart = mi;
4726 // no group 1 to 4 prefix byte
4727 generateREXprefix(false, dstReg, null, srcBase);
4728 // single byte opcode
4729 setMachineCodes(mi++, (byte) 0x02);
4730 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
4731 if (lister != null) lister.RRD(miStart, "ADD", dstReg, srcBase, srcDisp);
4732 }
4733
4734 /**
4735 * Generate a register--register-offset ADD. That is,
4736 * <PRE>
4737 * dstReg += (byte) [srcIndex<<srcScale + srcDisp]
4738 * </PRE>
4739 *
4740 * @param dstReg the destination register
4741 * @param srcIndex the source index register
4742 * @param srcScale the source shift amount
4743 * @param srcDisp the source displacement
4744 */
4745 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4746 public final void emitADD_Reg_RegOff_Byte(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
4747 int miStart = mi;
4748 // no group 1 to 4 prefix byte
4749 generateREXprefix(false, dstReg, srcIndex, null);
4750 // single byte opcode
4751 setMachineCodes(mi++, (byte) 0x02);
4752 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
4753 if (lister != null) lister.RRFD(miStart, "ADD", dstReg, srcIndex, srcScale, srcDisp);
4754 }
4755
4756 /**
4757 * Generate a register--register-offset ADD. That is,
4758 * <PRE>
4759 * dstReg += (byte) [srcDisp]
4760 * </PRE>
4761 *
4762 * @param dstReg the destination register
4763 * @param srcDisp the source displacement
4764 */
4765 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
4766 public final void emitADD_Reg_Abs_Byte(GPR dstReg, Address srcDisp) {
4767 int miStart = mi;
4768 // no group 1 to 4 prefix byte
4769 generateREXprefix(false, dstReg, null, null);
4770 // single byte opcode
4771 setMachineCodes(mi++, (byte) 0x02);
4772 emitAbsRegOperands(srcDisp, dstReg);
4773 if (lister != null) lister.RRA(miStart, "ADD", dstReg, srcDisp);
4774 }
4775
4776 /**
4777 * Generate a register--register-offset ADD. That is,
4778 * <PRE>
4779 * dstReg += (byte) [srcBase + srcIndex<<srcScale + srcDisp]
4780 * </PRE>
4781 *
4782 * @param dstReg the destination register
4783 * @param srcBase the source base register
4784 * @param srcIndex the source index register
4785 * @param srcScale the source shift amount
4786 * @param srcDisp the source displacement
4787 */
4788 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
4789 public final void emitADD_Reg_RegIdx_Byte(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
4790 int miStart = mi;
4791 // no group 1 to 4 prefix byte
4792 generateREXprefix(false, dstReg, srcIndex, srcBase);
4793 // single byte opcode
4794 setMachineCodes(mi++, (byte) 0x02);
4795 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
4796 if (lister != null) lister.RRXD(miStart, "ADD", dstReg, srcBase, srcIndex, srcScale, srcDisp);
4797 }
4798
4799 /**
4800 * Generate a register--register(indirect) ADD. That is,
4801 * <PRE>
4802 * dstReg += (byte) [srcBase]
4803 * </PRE>
4804 *
4805 * @param dstReg the destination register
4806 * @param srcBase the source base register
4807 */
4808 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4809 public final void emitADD_Reg_RegInd_Byte(GPR dstReg, GPR srcBase) {
4810 int miStart = mi;
4811 // no group 1 to 4 prefix byte
4812 generateREXprefix(false, dstReg, null, srcBase);
4813 // single byte opcode
4814 setMachineCodes(mi++, (byte) 0x02);
4815 emitRegIndirectRegOperands(srcBase, dstReg);
4816 if (lister != null) lister.RRN(miStart, "ADD", dstReg, srcBase);
4817 }
4818
4819 /**
4820 * Generate a register--immediate ADD. That is,
4821 * <PRE>
4822 * dstReg += imm
4823 * </PRE>
4824 *
4825 * @param dstReg the destination register
4826 * @param imm immediate
4827 */
4828 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
4829 public final void emitADD_Reg_Imm(GPR dstReg, int imm) {
4830 int miStart = mi;
4831 // no group 1 to 4 prefix byte
4832 generateREXprefix(false, null, null, dstReg);
4833 // single byte opcode
4834 if (fits(imm,8)) {
4835 setMachineCodes(mi++, (byte) 0x83);
4836 // "register 0x0" is really part of the opcode
4837 emitRegRegOperands(dstReg, GPR.getForOpcode(0x0));
4838 emitImm8((byte)imm);
4839 } else if (dstReg == EAX) {
4840 setMachineCodes(mi++, (byte) 0x05);
4841 emitImm32(imm);
4842 } else {
4843 setMachineCodes(mi++, (byte) 0x81);
4844 // "register 0x0" is really part of the opcode
4845 emitRegRegOperands(dstReg, GPR.getForOpcode(0x0));
4846 emitImm32(imm);
4847 }
4848 if (lister != null) lister.RI(miStart, "ADD", dstReg, imm);
4849 }
4850
4851 /**
4852 * Generate a register-displacement--immediate ADD. That is,
4853 * <PRE>
4854 * [dstBase + dstDisp] += imm
4855 * </PRE>
4856 *
4857 * @param dstBase the destination register
4858 * @param dstDisp the destination displacement
4859 * @param imm immediate
4860 */
4861 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
4862 public final void emitADD_RegDisp_Imm(GPR dstBase, Offset dstDisp, int imm) {
4863 int miStart = mi;
4864 // no group 1 to 4 prefix byte
4865 generateREXprefix(false, null, null, dstBase);
4866 // single byte opcode
4867 if (fits(imm,8)) {
4868 setMachineCodes(mi++, (byte) 0x83);
4869 // "register 0x0" is really part of the opcode
4870 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
4871 emitImm8((byte)imm);
4872 } else {
4873 setMachineCodes(mi++, (byte) 0x81);
4874 // "register 0x0" is really part of the opcode
4875 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
4876 emitImm32(imm);
4877 }
4878 if (lister != null) lister.RDI(miStart, "ADD", dstBase, dstDisp, imm);
4879 }
4880
4881 /**
4882 * Generate a register-offset--immediate ADD. That is,
4883 * <PRE>
4884 * [dstIndex<<dstScale + dstDisp] += imm
4885 * </PRE>
4886 *
4887 * @param dstIndex the destination index register
4888 * @param dstScale the destination shift amount
4889 * @param dstDisp the destination displacement
4890 * @param imm immediate
4891 */
4892 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
4893 public final void emitADD_RegOff_Imm(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
4894 int miStart = mi;
4895 // no group 1 to 4 prefix byte
4896 generateREXprefix(false, null, dstIndex, null);
4897 // single byte opcode
4898 if (fits(imm,8)) {
4899 setMachineCodes(mi++, (byte) 0x83);
4900 // "register 0x0" is really part of the opcode
4901 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
4902 emitImm8((byte)imm);
4903 } else {
4904 setMachineCodes(mi++, (byte) 0x81);
4905 // "register 0x0" is really part of the opcode
4906 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
4907 emitImm32(imm);
4908 }
4909 if (lister != null) lister.RFDI(miStart, "ADD", dstIndex, dstScale, dstDisp, imm);
4910 }
4911
4912 /**
4913 * Generate a absolute--immediate ADD. That is,
4914 * <PRE>
4915 * [dstDisp] += imm
4916 * </PRE>
4917 *
4918 * @param dstDisp the destination displacement
4919 * @param imm immediate
4920 */
4921 public final void emitADD_Abs_Imm(Address dstDisp, int imm) {
4922 int miStart = mi;
4923 // no group 1 to 4 prefix byte
4924 generateREXprefix(false, null, null, null);
4925 // single byte opcode
4926 if (fits(imm,8)) {
4927 setMachineCodes(mi++, (byte) 0x83);
4928 // "register 0x0" is really part of the opcode
4929 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
4930 emitImm8((byte)imm);
4931 } else {
4932 setMachineCodes(mi++, (byte) 0x81);
4933 // "register 0x0" is really part of the opcode
4934 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
4935 emitImm32(imm);
4936 }
4937 if (lister != null) lister.RAI(miStart, "ADD", dstDisp, imm);
4938 }
4939
4940 /**
4941 * Generate a register-index--immediate ADD. That is,
4942 * <PRE>
4943 * [dstBase + dstIndex<<dstScale + dstDisp] += imm
4944 * </PRE>
4945 *
4946 * @param dstBase the destination base register
4947 * @param dstIndex the destination index register
4948 * @param dstScale the destination shift amount
4949 * @param dstDisp the destination displacement
4950 * @param imm immediate
4951 */
4952 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
4953 public final void emitADD_RegIdx_Imm(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
4954 int miStart = mi;
4955 // no group 1 to 4 prefix byte
4956 generateREXprefix(false, null, dstIndex, dstBase);
4957 // single byte opcode
4958 if (fits(imm,8)) {
4959 setMachineCodes(mi++, (byte) 0x83);
4960 // "register 0x0" is really part of the opcode
4961 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
4962 emitImm8((byte)imm);
4963 } else {
4964 setMachineCodes(mi++, (byte) 0x81);
4965 // "register 0x0" is really part of the opcode
4966 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
4967 emitImm32(imm);
4968 }
4969 if (lister != null) lister.RXDI(miStart, "ADD", dstBase, dstIndex, dstScale, dstDisp, imm);
4970 }
4971
4972 /**
4973 * Generate a register(indirect)--immediate ADD. That is,
4974 * <PRE>
4975 * [dstBase] += imm
4976 * </PRE>
4977 *
4978 * @param dstBase the destination base register
4979 * @param imm immediate
4980 */
4981 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
4982 public final void emitADD_RegInd_Imm(GPR dstBase, int imm) {
4983 int miStart = mi;
4984 // no group 1 to 4 prefix byte
4985 generateREXprefix(false, null, null, dstBase);
4986 // single byte opcode
4987 if (fits(imm,8)) {
4988 setMachineCodes(mi++, (byte) 0x83);
4989 // "register 0x0" is really part of the opcode
4990 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
4991 emitImm8((byte)imm);
4992 } else {
4993 setMachineCodes(mi++, (byte) 0x81);
4994 // "register 0x0" is really part of the opcode
4995 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
4996 emitImm32(imm);
4997 }
4998 if (lister != null) lister.RNI(miStart, "ADD", dstBase, imm);
4999 }
5000
5001 /**
5002 * Generate a register--immediate ADD. That is,
5003 * <PRE>
5004 * dstReg += (word) imm
5005 * </PRE>
5006 *
5007 * @param dstReg the destination register
5008 * @param imm immediate
5009 */
5010 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
5011 public final void emitADD_Reg_Imm_Word(GPR dstReg, int imm) {
5012 int miStart = mi;
5013 setMachineCodes(mi++, (byte) 0x66);
5014 generateREXprefix(false, null, null, dstReg);
5015 // single byte opcode
5016 if (fits(imm,8)) {
5017 setMachineCodes(mi++, (byte) 0x83);
5018 // "register 0x0" is really part of the opcode
5019 emitRegRegOperands(dstReg, GPR.getForOpcode(0x0));
5020 emitImm8((byte)imm);
5021 } else if (dstReg == EAX) {
5022 setMachineCodes(mi++, (byte) 0x05);
5023 emitImm16(imm);
5024 } else {
5025 setMachineCodes(mi++, (byte) 0x81);
5026 // "register 0x0" is really part of the opcode
5027 emitRegRegOperands(dstReg, GPR.getForOpcode(0x0));
5028 emitImm16(imm);
5029 }
5030 if (lister != null) lister.RI(miStart, "ADD", dstReg, imm);
5031 }
5032
5033 /**
5034 * Generate a register-displacement--immediate ADD. That is,
5035 * <PRE>
5036 * [dstBase + dstDisp] += (word) imm
5037 * </PRE>
5038 *
5039 * @param dstBase the destination register
5040 * @param dstDisp the destination displacement
5041 * @param imm immediate
5042 */
5043 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
5044 public final void emitADD_RegDisp_Imm_Word(GPR dstBase, Offset dstDisp, int imm) {
5045 int miStart = mi;
5046 setMachineCodes(mi++, (byte) 0x66);
5047 generateREXprefix(false, null, null, dstBase);
5048 // single byte opcode
5049 if (fits(imm,8)) {
5050 setMachineCodes(mi++, (byte) 0x83);
5051 // "register 0x0" is really part of the opcode
5052 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
5053 emitImm8((byte)imm);
5054 } else {
5055 setMachineCodes(mi++, (byte) 0x81);
5056 // "register 0x0" is really part of the opcode
5057 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
5058 emitImm16(imm);
5059 }
5060 if (lister != null) lister.RDI(miStart, "ADD", dstBase, dstDisp, imm);
5061 }
5062
5063 /**
5064 * Generate a register-offset--immediate ADD. That is,
5065 * <PRE>
5066 * [dstIndex<<dstScale + dstDisp] += (word) imm
5067 * </PRE>
5068 *
5069 * @param dstIndex the destination index register
5070 * @param dstScale the destination shift amount
5071 * @param dstDisp the destination displacement
5072 * @param imm immediate
5073 */
5074 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
5075 public final void emitADD_RegOff_Imm_Word(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
5076 int miStart = mi;
5077 setMachineCodes(mi++, (byte) 0x66);
5078 generateREXprefix(false, null, dstIndex, null);
5079 // single byte opcode
5080 if (fits(imm,8)) {
5081 setMachineCodes(mi++, (byte) 0x83);
5082 // "register 0x0" is really part of the opcode
5083 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
5084 emitImm8((byte)imm);
5085 } else {
5086 setMachineCodes(mi++, (byte) 0x81);
5087 // "register 0x0" is really part of the opcode
5088 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
5089 emitImm16(imm);
5090 }
5091 if (lister != null) lister.RFDI(miStart, "ADD", dstIndex, dstScale, dstDisp, imm);
5092 }
5093
5094 /**
5095 * Generate a absolute--immediate ADD. That is,
5096 * <PRE>
5097 * [dstDisp] += (word) imm
5098 * </PRE>
5099 *
5100 * @param dstDisp the destination displacement
5101 * @param imm immediate
5102 */
5103 public final void emitADD_Abs_Imm_Word(Address dstDisp, int imm) {
5104 int miStart = mi;
5105 setMachineCodes(mi++, (byte) 0x66);
5106 generateREXprefix(false, null, null, null);
5107 // single byte opcode
5108 if (fits(imm,8)) {
5109 setMachineCodes(mi++, (byte) 0x83);
5110 // "register 0x0" is really part of the opcode
5111 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
5112 emitImm8((byte)imm);
5113 } else {
5114 setMachineCodes(mi++, (byte) 0x81);
5115 // "register 0x0" is really part of the opcode
5116 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
5117 emitImm16(imm);
5118 }
5119 if (lister != null) lister.RAI(miStart, "ADD", dstDisp, imm);
5120 }
5121
5122 /**
5123 * Generate a register-index--immediate ADD. That is,
5124 * <PRE>
5125 * [dstBase + dstIndex<<dstScale + dstDisp] += (word) imm
5126 * </PRE>
5127 *
5128 * @param dstBase the destination base register
5129 * @param dstIndex the destination index register
5130 * @param dstScale the destination shift amount
5131 * @param dstDisp the destination displacement
5132 * @param imm immediate
5133 */
5134 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
5135 public final void emitADD_RegIdx_Imm_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
5136 int miStart = mi;
5137 setMachineCodes(mi++, (byte) 0x66);
5138 generateREXprefix(false, null, dstIndex, dstBase);
5139 // single byte opcode
5140 if (fits(imm,8)) {
5141 setMachineCodes(mi++, (byte) 0x83);
5142 // "register 0x0" is really part of the opcode
5143 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
5144 emitImm8((byte)imm);
5145 } else {
5146 setMachineCodes(mi++, (byte) 0x81);
5147 // "register 0x0" is really part of the opcode
5148 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
5149 emitImm16(imm);
5150 }
5151 if (lister != null) lister.RXDI(miStart, "ADD", dstBase, dstIndex, dstScale, dstDisp, imm);
5152 }
5153
5154 /**
5155 * Generate a register(indirect)--immediate ADD. That is,
5156 * <PRE>
5157 * [dstBase] += (word) imm
5158 * </PRE>
5159 *
5160 * @param dstBase the destination base register
5161 * @param imm immediate
5162 */
5163 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
5164 public final void emitADD_RegInd_Imm_Word(GPR dstBase, int imm) {
5165 int miStart = mi;
5166 setMachineCodes(mi++, (byte) 0x66);
5167 generateREXprefix(false, null, null, dstBase);
5168 // single byte opcode
5169 if (fits(imm,8)) {
5170 setMachineCodes(mi++, (byte) 0x83);
5171 // "register 0x0" is really part of the opcode
5172 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
5173 emitImm8((byte)imm);
5174 } else {
5175 setMachineCodes(mi++, (byte) 0x81);
5176 // "register 0x0" is really part of the opcode
5177 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
5178 emitImm16(imm);
5179 }
5180 if (lister != null) lister.RNI(miStart, "ADD", dstBase, imm);
5181 }
5182
5183 /**
5184 * Generate a register--immediate ADD. That is,
5185 * <PRE>
5186 * dstReg += (quad) imm
5187 * </PRE>
5188 *
5189 * @param dstReg the destination register
5190 * @param imm immediate
5191 */
5192 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
5193 public final void emitADD_Reg_Imm_Quad(GPR dstReg, int imm) {
5194 int miStart = mi;
5195 // no group 1 to 4 prefix byte
5196 generateREXprefix(true, null, null, dstReg);
5197 // single byte opcode
5198 if (fits(imm,8)) {
5199 setMachineCodes(mi++, (byte) 0x83);
5200 // "register 0x0" is really part of the opcode
5201 emitRegRegOperands(dstReg, GPR.getForOpcode(0x0));
5202 emitImm8((byte)imm);
5203 } else if (dstReg == EAX) {
5204 setMachineCodes(mi++, (byte) 0x05);
5205 emitImm32(imm);
5206 } else {
5207 setMachineCodes(mi++, (byte) 0x81);
5208 // "register 0x0" is really part of the opcode
5209 emitRegRegOperands(dstReg, GPR.getForOpcode(0x0));
5210 emitImm32(imm);
5211 }
5212 if (lister != null) lister.RI(miStart, "ADD", dstReg, imm);
5213 }
5214
5215 /**
5216 * Generate a register-displacement--immediate ADD. That is,
5217 * <PRE>
5218 * [dstBase + dstDisp] += (quad) imm
5219 * </PRE>
5220 *
5221 * @param dstBase the destination register
5222 * @param dstDisp the destination displacement
5223 * @param imm immediate
5224 */
5225 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
5226 public final void emitADD_RegDisp_Imm_Quad(GPR dstBase, Offset dstDisp, int imm) {
5227 int miStart = mi;
5228 // no group 1 to 4 prefix byte
5229 generateREXprefix(true, null, null, dstBase);
5230 // single byte opcode
5231 if (fits(imm,8)) {
5232 setMachineCodes(mi++, (byte) 0x83);
5233 // "register 0x0" is really part of the opcode
5234 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
5235 emitImm8((byte)imm);
5236 } else {
5237 setMachineCodes(mi++, (byte) 0x81);
5238 // "register 0x0" is really part of the opcode
5239 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
5240 emitImm32(imm);
5241 }
5242 if (lister != null) lister.RDI(miStart, "ADD", dstBase, dstDisp, imm);
5243 }
5244
5245 /**
5246 * Generate a register-offset--immediate ADD. That is,
5247 * <PRE>
5248 * [dstIndex<<dstScale + dstDisp] += (quad) imm
5249 * </PRE>
5250 *
5251 * @param dstIndex the destination index register
5252 * @param dstScale the destination shift amount
5253 * @param dstDisp the destination displacement
5254 * @param imm immediate
5255 */
5256 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
5257 public final void emitADD_RegOff_Imm_Quad(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
5258 int miStart = mi;
5259 // no group 1 to 4 prefix byte
5260 generateREXprefix(true, null, dstIndex, null);
5261 // single byte opcode
5262 if (fits(imm,8)) {
5263 setMachineCodes(mi++, (byte) 0x83);
5264 // "register 0x0" is really part of the opcode
5265 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
5266 emitImm8((byte)imm);
5267 } else {
5268 setMachineCodes(mi++, (byte) 0x81);
5269 // "register 0x0" is really part of the opcode
5270 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
5271 emitImm32(imm);
5272 }
5273 if (lister != null) lister.RFDI(miStart, "ADD", dstIndex, dstScale, dstDisp, imm);
5274 }
5275
5276 /**
5277 * Generate a absolute--immediate ADD. That is,
5278 * <PRE>
5279 * [dstDisp] += (quad) imm
5280 * </PRE>
5281 *
5282 * @param dstDisp the destination displacement
5283 * @param imm immediate
5284 */
5285 public final void emitADD_Abs_Imm_Quad(Address dstDisp, int imm) {
5286 int miStart = mi;
5287 // no group 1 to 4 prefix byte
5288 generateREXprefix(true, null, null, null);
5289 // single byte opcode
5290 if (fits(imm,8)) {
5291 setMachineCodes(mi++, (byte) 0x83);
5292 // "register 0x0" is really part of the opcode
5293 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
5294 emitImm8((byte)imm);
5295 } else {
5296 setMachineCodes(mi++, (byte) 0x81);
5297 // "register 0x0" is really part of the opcode
5298 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
5299 emitImm32(imm);
5300 }
5301 if (lister != null) lister.RAI(miStart, "ADD", dstDisp, imm);
5302 }
5303
5304 /**
5305 * Generate a register-index--immediate ADD. That is,
5306 * <PRE>
5307 * [dstBase + dstIndex<<dstScale + dstDisp] += (quad) imm
5308 * </PRE>
5309 *
5310 * @param dstBase the destination base register
5311 * @param dstIndex the destination index register
5312 * @param dstScale the destination shift amount
5313 * @param dstDisp the destination displacement
5314 * @param imm immediate
5315 */
5316 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
5317 public final void emitADD_RegIdx_Imm_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
5318 int miStart = mi;
5319 // no group 1 to 4 prefix byte
5320 generateREXprefix(true, null, dstIndex, dstBase);
5321 // single byte opcode
5322 if (fits(imm,8)) {
5323 setMachineCodes(mi++, (byte) 0x83);
5324 // "register 0x0" is really part of the opcode
5325 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
5326 emitImm8((byte)imm);
5327 } else {
5328 setMachineCodes(mi++, (byte) 0x81);
5329 // "register 0x0" is really part of the opcode
5330 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
5331 emitImm32(imm);
5332 }
5333 if (lister != null) lister.RXDI(miStart, "ADD", dstBase, dstIndex, dstScale, dstDisp, imm);
5334 }
5335
5336 /**
5337 * Generate a register(indirect)--immediate ADD. That is,
5338 * <PRE>
5339 * [dstBase] += (quad) imm
5340 * </PRE>
5341 *
5342 * @param dstBase the destination base register
5343 * @param imm immediate
5344 */
5345 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
5346 public final void emitADD_RegInd_Imm_Quad(GPR dstBase, int imm) {
5347 int miStart = mi;
5348 // no group 1 to 4 prefix byte
5349 generateREXprefix(true, null, null, dstBase);
5350 // single byte opcode
5351 if (fits(imm,8)) {
5352 setMachineCodes(mi++, (byte) 0x83);
5353 // "register 0x0" is really part of the opcode
5354 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
5355 emitImm8((byte)imm);
5356 } else {
5357 setMachineCodes(mi++, (byte) 0x81);
5358 // "register 0x0" is really part of the opcode
5359 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
5360 emitImm32(imm);
5361 }
5362 if (lister != null) lister.RNI(miStart, "ADD", dstBase, imm);
5363 }
5364
5365 /**
5366 * Generate a register--immediate ADD. That is,
5367 * <PRE>
5368 * dstReg += (byte) imm
5369 * </PRE>
5370 *
5371 * @param dstReg the destination register
5372 * @param imm immediate
5373 */
5374 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
5375 public final void emitADD_Reg_Imm_Byte(GPR dstReg, int imm) {
5376 int miStart = mi;
5377 if (dstReg == EAX) {
5378 setMachineCodes(mi++, (byte) 0x04);
5379 emitImm8(imm);
5380 } else {
5381 generateREXprefix(false, null, null, dstReg);
5382 setMachineCodes(mi++, (byte) 0x80);
5383 // "register 0x0" is really part of the opcode
5384 emitRegRegOperands(dstReg, GPR.getForOpcode(0x0));
5385 emitImm8(imm);
5386 }
5387 if (lister != null) lister.RI(miStart, "ADD", dstReg, imm);
5388 }
5389
5390 /**
5391 * Generate a register-displacement--immediate ADD. That is,
5392 * <PRE>
5393 * [dstBase + dstDisp] += (byte) imm
5394 * </PRE>
5395 *
5396 * @param dstBase the destination register
5397 * @param dstDisp the destination displacement
5398 * @param imm immediate
5399 */
5400 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
5401 public final void emitADD_RegDisp_Imm_Byte(GPR dstBase, Offset dstDisp, int imm) {
5402 int miStart = mi;
5403 generateREXprefix(false, null, null, dstBase);
5404 setMachineCodes(mi++, (byte) 0x80);
5405 // "register 0x0" is really part of the opcode
5406 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
5407 emitImm8(imm);
5408 if (lister != null) lister.RDI(miStart, "ADD", dstBase, dstDisp, imm);
5409 }
5410
5411 /**
5412 * Generate a register-index--immediate ADD. That is,
5413 * <PRE>
5414 * [dstBase + dstIndex<<scale + dstDisp] += (byte) imm
5415 * </PRE>
5416 *
5417 * @param dstBase the destination base register
5418 * @param dstIndex the destination index register
5419 * @param dstScale the destination shift amount
5420 * @param dstDisp the destination displacement
5421 * @param imm immediate
5422 */
5423 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
5424 public final void emitADD_RegIdx_Imm_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
5425 int miStart = mi;
5426 generateREXprefix(false, null, dstIndex, dstBase);
5427 setMachineCodes(mi++, (byte) 0x80);
5428 // "register 0x0" is really part of the opcode
5429 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
5430 emitImm8(imm);
5431 if (lister != null) lister.RXDI(miStart, "ADD", dstBase, dstIndex, dstScale, dstDisp, imm);
5432 }
5433
5434 /**
5435 * Generate a register-offset--immediate ADD. That is,
5436 * <PRE>
5437 * [dstIndex<<dstScale + dstDisp] += (byte) imm
5438 * </PRE>
5439 *
5440 * @param dstIndex the destination index register
5441 * @param dstScale the destination shift amount
5442 * @param dstDisp the destination displacement
5443 * @param imm immediate
5444 */
5445 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
5446 public final void emitADD_RegOff_Imm_Byte(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
5447 int miStart = mi;
5448 generateREXprefix(false, null, dstIndex, null);
5449 setMachineCodes(mi++, (byte) 0x80);
5450 // "register 0x0" is really part of the opcode
5451 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
5452 emitImm8(imm);
5453 if (lister != null) lister.RFDI(miStart, "ADD", dstIndex, dstScale, dstDisp, imm);
5454 }
5455
5456 /**
5457 * Generate a absolute--immediate ADD. That is,
5458 * <PRE>
5459 * [dstDisp] += (byte) imm
5460 * </PRE>
5461 *
5462 * @param dstDisp the destination displacement
5463 * @param imm immediate
5464 */
5465 public final void emitADD_Abs_Imm_Byte(Address dstDisp, int imm) {
5466 int miStart = mi;
5467 generateREXprefix(false, null, null, null);
5468 setMachineCodes(mi++, (byte) 0x80);
5469 // "register 0x0" is really part of the opcode
5470 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
5471 emitImm8(imm);
5472 if (lister != null) lister.RAI(miStart, "ADD", dstDisp, imm);
5473 }
5474
5475 /**
5476 * Generate a register(indirect)--immediate ADD. That is,
5477 * <PRE>
5478 * [dstBase] += (byte) imm
5479 * </PRE>
5480 *
5481 * @param dstBase the destination base register
5482 * @param imm immediate
5483 */
5484 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
5485 public final void emitADD_RegInd_Imm_Byte(GPR dstBase, int imm) {
5486 int miStart = mi;
5487 generateREXprefix(false, null, null, dstBase);
5488 setMachineCodes(mi++, (byte) 0x80);
5489 // "register 0x0" is really part of the opcode
5490 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
5491 emitImm8(imm);
5492 if (lister != null) lister.RNI(miStart, "ADD", dstBase, imm);
5493 }
5494
5495 /**
5496 * Generate a register(indirect)--register AND. That is,
5497 * <PRE>
5498 * [dstBase] &= srcReg
5499 * </PRE>
5500 *
5501 * @param dstBase the destination base
5502 * @param srcReg the source register
5503 */
5504 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
5505 public final void emitAND_RegInd_Reg(GPR dstBase, GPR srcReg) {
5506 int miStart = mi;
5507 // no group 1 to 4 prefix byte
5508 generateREXprefix(false, srcReg, null, dstBase);
5509 // single byte opcode
5510 setMachineCodes(mi++, (byte) 0x21);
5511 emitRegIndirectRegOperands(dstBase, srcReg);
5512 if (lister != null) lister.RNR(miStart, "AND", dstBase, srcReg);
5513 }
5514
5515 /**
5516 * Generate a register-offset--register AND. That is,
5517 * <PRE>
5518 * [dstReg<<dstScale + dstDisp] &= srcReg
5519 * </PRE>
5520 *
5521 * @param dstIndex the destination index register
5522 * @param dstScale the destination shift amount
5523 * @param dstDisp the destination displacement
5524 * @param srcReg the source register
5525 */
5526 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
5527 public final void emitAND_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
5528 int miStart = mi;
5529 // no group 1 to 4 prefix byte
5530 generateREXprefix(false, srcReg, dstIndex, null);
5531 // single byte opcode
5532 setMachineCodes(mi++, (byte) 0x21);
5533 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
5534 if (lister != null) lister.RFDR(miStart, "AND", dstIndex, dstScale, dstDisp, srcReg);
5535 }
5536
5537 /**
5538 * Generate a absolute--register AND. That is,
5539 * <PRE>
5540 * [dstDisp] &= srcReg
5541 * </PRE>
5542 *
5543 * @param dstDisp the destination address
5544 * @param srcReg the source register
5545 */
5546 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
5547 public final void emitAND_Abs_Reg(Address dstDisp, GPR srcReg) {
5548 int miStart = mi;
5549 // no group 1 to 4 prefix byte
5550 generateREXprefix(false, srcReg, null, null);
5551 // single byte opcode
5552 setMachineCodes(mi++, (byte) 0x21);
5553 emitAbsRegOperands(dstDisp, srcReg);
5554 if (lister != null) lister.RAR(miStart, "AND", dstDisp, srcReg);
5555 }
5556
5557 /**
5558 * Generate a register-index--register AND. That is,
5559 * <PRE>
5560 * [dstBase + dstIndex<<dstScale + dstDisp] &= srcReg
5561 * </PRE>
5562 *
5563 * @param dstBase the base register
5564 * @param dstIndex the destination index register
5565 * @param dstScale the destination shift amount
5566 * @param dstDisp the destination displacement
5567 * @param srcReg the source register
5568 */
5569 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
5570 public final void emitAND_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
5571 int miStart = mi;
5572 // no group 1 to 4 prefix byte
5573 generateREXprefix(false, srcReg, dstIndex, dstBase);
5574 // single byte opcode
5575 setMachineCodes(mi++, (byte) 0x21);
5576 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
5577 if (lister != null) lister.RXDR(miStart, "AND", dstBase, dstIndex, dstScale, dstDisp, srcReg);
5578 }
5579
5580 /**
5581 * Generate a register-displacement--register AND. That is,
5582 * <PRE>
5583 * [dstBase + dstDisp] &= srcReg
5584 * </PRE>
5585 *
5586 * @param dstBase the base register
5587 * @param dstDisp the destination displacement
5588 * @param srcReg the source register
5589 */
5590 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
5591 public final void emitAND_RegDisp_Reg(GPR dstBase, Offset dstDisp, GPR srcReg) {
5592 int miStart = mi;
5593 // no group 1 to 4 prefix byte
5594 generateREXprefix(false, srcReg, null, dstBase);
5595 // single byte opcode
5596 setMachineCodes(mi++, (byte) 0x21);
5597 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
5598 if (lister != null) lister.RDR(miStart, "AND", dstBase, dstDisp, srcReg);
5599 }
5600
5601 /**
5602 * Generate a register--register AND. That is,
5603 * <PRE>
5604 * dstReg &= srcReg
5605 * </PRE>
5606 *
5607 * @param dstReg the destination register
5608 * @param srcReg the source register
5609 */
5610 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
5611 public final void emitAND_Reg_Reg(GPR dstReg, GPR srcReg) {
5612 int miStart = mi;
5613 // no group 1 to 4 prefix byte
5614 generateREXprefix(false, srcReg, null, dstReg);
5615 // single byte opcode
5616 setMachineCodes(mi++, (byte) 0x21);
5617 emitRegRegOperands(dstReg, srcReg);
5618 if (lister != null) lister.RR(miStart, "AND", dstReg, srcReg);
5619 }
5620
5621 /**
5622 * Generate a register--register-displacement AND. That is,
5623 * <PRE>
5624 * dstReg &= [srcReg + srcDisp]
5625 * </PRE>
5626 *
5627 * @param dstReg the destination register
5628 * @param srcBase the source register
5629 * @param srcDisp the source displacement
5630 */
5631 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
5632 public final void emitAND_Reg_RegDisp(GPR dstReg, GPR srcBase, Offset srcDisp) {
5633 int miStart = mi;
5634 // no group 1 to 4 prefix byte
5635 generateREXprefix(false, dstReg, null, srcBase);
5636 // single byte opcode
5637 setMachineCodes(mi++, (byte) 0x23);
5638 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
5639 if (lister != null) lister.RRD(miStart, "AND", dstReg, srcBase, srcDisp);
5640 }
5641
5642 /**
5643 * Generate a register--register-offset AND. That is,
5644 * <PRE>
5645 * dstReg &= [srcIndex<<srcScale + srcDisp]
5646 * </PRE>
5647 *
5648 * @param dstReg the destination register
5649 * @param srcIndex the source index register
5650 * @param srcScale the source shift amount
5651 * @param srcDisp the source displacement
5652 */
5653 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
5654 public final void emitAND_Reg_RegOff(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
5655 int miStart = mi;
5656 // no group 1 to 4 prefix byte
5657 generateREXprefix(false, dstReg, srcIndex, null);
5658 // single byte opcode
5659 setMachineCodes(mi++, (byte) 0x23);
5660 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
5661 if (lister != null) lister.RRFD(miStart, "AND", dstReg, srcIndex, srcScale, srcDisp);
5662 }
5663
5664 /**
5665 * Generate a register--register-offset AND. That is,
5666 * <PRE>
5667 * dstReg &= [srcDisp]
5668 * </PRE>
5669 *
5670 * @param dstReg the destination register
5671 * @param srcDisp the source displacement
5672 */
5673 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
5674 public final void emitAND_Reg_Abs(GPR dstReg, Address srcDisp) {
5675 int miStart = mi;
5676 // no group 1 to 4 prefix byte
5677 generateREXprefix(false, dstReg, null, null);
5678 // single byte opcode
5679 setMachineCodes(mi++, (byte) 0x23);
5680 emitAbsRegOperands(srcDisp, dstReg);
5681 if (lister != null) lister.RRA(miStart, "AND", dstReg, srcDisp);
5682 }
5683
5684 /**
5685 * Generate a register--register-offset AND. That is,
5686 * <PRE>
5687 * dstReg &= [srcBase + srcIndex<<srcScale + srcDisp]
5688 * </PRE>
5689 *
5690 * @param dstReg the destination register
5691 * @param srcBase the source base register
5692 * @param srcIndex the source index register
5693 * @param srcScale the source shift amount
5694 * @param srcDisp the source displacement
5695 */
5696 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
5697 public final void emitAND_Reg_RegIdx(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
5698 int miStart = mi;
5699 // no group 1 to 4 prefix byte
5700 generateREXprefix(false, dstReg, srcIndex, srcBase);
5701 // single byte opcode
5702 setMachineCodes(mi++, (byte) 0x23);
5703 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
5704 if (lister != null) lister.RRXD(miStart, "AND", dstReg, srcBase, srcIndex, srcScale, srcDisp);
5705 }
5706
5707 /**
5708 * Generate a register--register(indirect) AND. That is,
5709 * <PRE>
5710 * dstReg &= [srcBase]
5711 * </PRE>
5712 *
5713 * @param dstReg the destination register
5714 * @param srcBase the source base register
5715 */
5716 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
5717 public final void emitAND_Reg_RegInd(GPR dstReg, GPR srcBase) {
5718 int miStart = mi;
5719 // no group 1 to 4 prefix byte
5720 generateREXprefix(false, dstReg, null, srcBase);
5721 // single byte opcode
5722 setMachineCodes(mi++, (byte) 0x23);
5723 emitRegIndirectRegOperands(srcBase, dstReg);
5724 if (lister != null) lister.RRN(miStart, "AND", dstReg, srcBase);
5725 }
5726
5727 /**
5728 * Generate a register(indirect)--register AND. That is,
5729 * <PRE>
5730 * [dstBase] &= (word) srcReg
5731 * </PRE>
5732 *
5733 * @param dstBase the destination base
5734 * @param srcReg the source register
5735 */
5736 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
5737 public final void emitAND_RegInd_Reg_Word(GPR dstBase, GPR srcReg) {
5738 int miStart = mi;
5739 setMachineCodes(mi++, (byte) 0x66);
5740 generateREXprefix(false, srcReg, null, dstBase);
5741 // single byte opcode
5742 setMachineCodes(mi++, (byte) 0x21);
5743 emitRegIndirectRegOperands(dstBase, srcReg);
5744 if (lister != null) lister.RNR(miStart, "AND", dstBase, srcReg);
5745 }
5746
5747 /**
5748 * Generate a register-offset--register AND. That is,
5749 * <PRE>
5750 * [dstReg<<dstScale + dstDisp] &= (word) srcReg
5751 * </PRE>
5752 *
5753 * @param dstIndex the destination index register
5754 * @param dstScale the destination shift amount
5755 * @param dstDisp the destination displacement
5756 * @param srcReg the source register
5757 */
5758 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
5759 public final void emitAND_RegOff_Reg_Word(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
5760 int miStart = mi;
5761 setMachineCodes(mi++, (byte) 0x66);
5762 generateREXprefix(false, srcReg, dstIndex, null);
5763 // single byte opcode
5764 setMachineCodes(mi++, (byte) 0x21);
5765 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
5766 if (lister != null) lister.RFDR(miStart, "AND", dstIndex, dstScale, dstDisp, srcReg);
5767 }
5768
5769 /**
5770 * Generate a absolute--register AND. That is,
5771 * <PRE>
5772 * [dstDisp] &= (word) srcReg
5773 * </PRE>
5774 *
5775 * @param dstDisp the destination address
5776 * @param srcReg the source register
5777 */
5778 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
5779 public final void emitAND_Abs_Reg_Word(Address dstDisp, GPR srcReg) {
5780 int miStart = mi;
5781 setMachineCodes(mi++, (byte) 0x66);
5782 generateREXprefix(false, srcReg, null, null);
5783 // single byte opcode
5784 setMachineCodes(mi++, (byte) 0x21);
5785 emitAbsRegOperands(dstDisp, srcReg);
5786 if (lister != null) lister.RAR(miStart, "AND", dstDisp, srcReg);
5787 }
5788
5789 /**
5790 * Generate a register-index--register AND. That is,
5791 * <PRE>
5792 * [dstBase + dstIndex<<dstScale + dstDisp] &= (word) srcReg
5793 * </PRE>
5794 *
5795 * @param dstBase the base register
5796 * @param dstIndex the destination index register
5797 * @param dstScale the destination shift amount
5798 * @param dstDisp the destination displacement
5799 * @param srcReg the source register
5800 */
5801 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
5802 public final void emitAND_RegIdx_Reg_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
5803 int miStart = mi;
5804 setMachineCodes(mi++, (byte) 0x66);
5805 generateREXprefix(false, srcReg, dstIndex, dstBase);
5806 // single byte opcode
5807 setMachineCodes(mi++, (byte) 0x21);
5808 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
5809 if (lister != null) lister.RXDR(miStart, "AND", dstBase, dstIndex, dstScale, dstDisp, srcReg);
5810 }
5811
5812 /**
5813 * Generate a register-displacement--register AND. That is,
5814 * <PRE>
5815 * [dstBase + dstDisp] &= (word) srcReg
5816 * </PRE>
5817 *
5818 * @param dstBase the base register
5819 * @param dstDisp the destination displacement
5820 * @param srcReg the source register
5821 */
5822 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
5823 public final void emitAND_RegDisp_Reg_Word(GPR dstBase, Offset dstDisp, GPR srcReg) {
5824 int miStart = mi;
5825 setMachineCodes(mi++, (byte) 0x66);
5826 generateREXprefix(false, srcReg, null, dstBase);
5827 // single byte opcode
5828 setMachineCodes(mi++, (byte) 0x21);
5829 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
5830 if (lister != null) lister.RDR(miStart, "AND", dstBase, dstDisp, srcReg);
5831 }
5832
5833 /**
5834 * Generate a register--register AND. That is,
5835 * <PRE>
5836 * dstReg &= (word) srcReg
5837 * </PRE>
5838 *
5839 * @param dstReg the destination register
5840 * @param srcReg the source register
5841 */
5842 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
5843 public final void emitAND_Reg_Reg_Word(GPR dstReg, GPR srcReg) {
5844 int miStart = mi;
5845 setMachineCodes(mi++, (byte) 0x66);
5846 generateREXprefix(false, srcReg, null, dstReg);
5847 // single byte opcode
5848 setMachineCodes(mi++, (byte) 0x21);
5849 emitRegRegOperands(dstReg, srcReg);
5850 if (lister != null) lister.RR(miStart, "AND", dstReg, srcReg);
5851 }
5852
5853 /**
5854 * Generate a register--register-displacement AND. That is,
5855 * <PRE>
5856 * dstReg &= (word) [srcReg + srcDisp]
5857 * </PRE>
5858 *
5859 * @param dstReg the destination register
5860 * @param srcBase the source register
5861 * @param srcDisp the source displacement
5862 */
5863 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
5864 public final void emitAND_Reg_RegDisp_Word(GPR dstReg, GPR srcBase, Offset srcDisp) {
5865 int miStart = mi;
5866 setMachineCodes(mi++, (byte) 0x66);
5867 generateREXprefix(false, dstReg, null, srcBase);
5868 // single byte opcode
5869 setMachineCodes(mi++, (byte) 0x23);
5870 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
5871 if (lister != null) lister.RRD(miStart, "AND", dstReg, srcBase, srcDisp);
5872 }
5873
5874 /**
5875 * Generate a register--register-offset AND. That is,
5876 * <PRE>
5877 * dstReg &= (word) [srcIndex<<srcScale + srcDisp]
5878 * </PRE>
5879 *
5880 * @param dstReg the destination register
5881 * @param srcIndex the source index register
5882 * @param srcScale the source shift amount
5883 * @param srcDisp the source displacement
5884 */
5885 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
5886 public final void emitAND_Reg_RegOff_Word(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
5887 int miStart = mi;
5888 setMachineCodes(mi++, (byte) 0x66);
5889 generateREXprefix(false, dstReg, srcIndex, null);
5890 // single byte opcode
5891 setMachineCodes(mi++, (byte) 0x23);
5892 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
5893 if (lister != null) lister.RRFD(miStart, "AND", dstReg, srcIndex, srcScale, srcDisp);
5894 }
5895
5896 /**
5897 * Generate a register--register-offset AND. That is,
5898 * <PRE>
5899 * dstReg &= (word) [srcDisp]
5900 * </PRE>
5901 *
5902 * @param dstReg the destination register
5903 * @param srcDisp the source displacement
5904 */
5905 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
5906 public final void emitAND_Reg_Abs_Word(GPR dstReg, Address srcDisp) {
5907 int miStart = mi;
5908 setMachineCodes(mi++, (byte) 0x66);
5909 generateREXprefix(false, dstReg, null, null);
5910 // single byte opcode
5911 setMachineCodes(mi++, (byte) 0x23);
5912 emitAbsRegOperands(srcDisp, dstReg);
5913 if (lister != null) lister.RRA(miStart, "AND", dstReg, srcDisp);
5914 }
5915
5916 /**
5917 * Generate a register--register-offset AND. That is,
5918 * <PRE>
5919 * dstReg &= (word) [srcBase + srcIndex<<srcScale + srcDisp]
5920 * </PRE>
5921 *
5922 * @param dstReg the destination register
5923 * @param srcBase the source base register
5924 * @param srcIndex the source index register
5925 * @param srcScale the source shift amount
5926 * @param srcDisp the source displacement
5927 */
5928 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
5929 public final void emitAND_Reg_RegIdx_Word(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
5930 int miStart = mi;
5931 setMachineCodes(mi++, (byte) 0x66);
5932 generateREXprefix(false, dstReg, srcIndex, srcBase);
5933 // single byte opcode
5934 setMachineCodes(mi++, (byte) 0x23);
5935 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
5936 if (lister != null) lister.RRXD(miStart, "AND", dstReg, srcBase, srcIndex, srcScale, srcDisp);
5937 }
5938
5939 /**
5940 * Generate a register--register(indirect) AND. That is,
5941 * <PRE>
5942 * dstReg &= (word) [srcBase]
5943 * </PRE>
5944 *
5945 * @param dstReg the destination register
5946 * @param srcBase the source base register
5947 */
5948 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
5949 public final void emitAND_Reg_RegInd_Word(GPR dstReg, GPR srcBase) {
5950 int miStart = mi;
5951 setMachineCodes(mi++, (byte) 0x66);
5952 generateREXprefix(false, dstReg, null, srcBase);
5953 // single byte opcode
5954 setMachineCodes(mi++, (byte) 0x23);
5955 emitRegIndirectRegOperands(srcBase, dstReg);
5956 if (lister != null) lister.RRN(miStart, "AND", dstReg, srcBase);
5957 }
5958
5959 /**
5960 * Generate a register(indirect)--register AND. That is,
5961 * <PRE>
5962 * [dstBase] &= (quad) srcReg
5963 * </PRE>
5964 *
5965 * @param dstBase the destination base
5966 * @param srcReg the source register
5967 */
5968 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
5969 public final void emitAND_RegInd_Reg_Quad(GPR dstBase, GPR srcReg) {
5970 int miStart = mi;
5971 // no group 1 to 4 prefix byte
5972 generateREXprefix(true, srcReg, null, dstBase);
5973 // single byte opcode
5974 setMachineCodes(mi++, (byte) 0x21);
5975 emitRegIndirectRegOperands(dstBase, srcReg);
5976 if (lister != null) lister.RNR(miStart, "AND", dstBase, srcReg);
5977 }
5978
5979 /**
5980 * Generate a register-offset--register AND. That is,
5981 * <PRE>
5982 * [dstReg<<dstScale + dstDisp] &= (quad) srcReg
5983 * </PRE>
5984 *
5985 * @param dstIndex the destination index register
5986 * @param dstScale the destination shift amount
5987 * @param dstDisp the destination displacement
5988 * @param srcReg the source register
5989 */
5990 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
5991 public final void emitAND_RegOff_Reg_Quad(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
5992 int miStart = mi;
5993 // no group 1 to 4 prefix byte
5994 generateREXprefix(true, srcReg, dstIndex, null);
5995 // single byte opcode
5996 setMachineCodes(mi++, (byte) 0x21);
5997 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
5998 if (lister != null) lister.RFDR(miStart, "AND", dstIndex, dstScale, dstDisp, srcReg);
5999 }
6000
6001 /**
6002 * Generate a absolute--register AND. That is,
6003 * <PRE>
6004 * [dstDisp] &= (quad) srcReg
6005 * </PRE>
6006 *
6007 * @param dstDisp the destination address
6008 * @param srcReg the source register
6009 */
6010 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
6011 public final void emitAND_Abs_Reg_Quad(Address dstDisp, GPR srcReg) {
6012 int miStart = mi;
6013 // no group 1 to 4 prefix byte
6014 generateREXprefix(true, srcReg, null, null);
6015 // single byte opcode
6016 setMachineCodes(mi++, (byte) 0x21);
6017 emitAbsRegOperands(dstDisp, srcReg);
6018 if (lister != null) lister.RAR(miStart, "AND", dstDisp, srcReg);
6019 }
6020
6021 /**
6022 * Generate a register-index--register AND. That is,
6023 * <PRE>
6024 * [dstBase + dstIndex<<dstScale + dstDisp] &= (quad) srcReg
6025 * </PRE>
6026 *
6027 * @param dstBase the base register
6028 * @param dstIndex the destination index register
6029 * @param dstScale the destination shift amount
6030 * @param dstDisp the destination displacement
6031 * @param srcReg the source register
6032 */
6033 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
6034 public final void emitAND_RegIdx_Reg_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
6035 int miStart = mi;
6036 // no group 1 to 4 prefix byte
6037 generateREXprefix(true, srcReg, dstIndex, dstBase);
6038 // single byte opcode
6039 setMachineCodes(mi++, (byte) 0x21);
6040 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
6041 if (lister != null) lister.RXDR(miStart, "AND", dstBase, dstIndex, dstScale, dstDisp, srcReg);
6042 }
6043
6044 /**
6045 * Generate a register-displacement--register AND. That is,
6046 * <PRE>
6047 * [dstBase + dstDisp] &= (quad) srcReg
6048 * </PRE>
6049 *
6050 * @param dstBase the base register
6051 * @param dstDisp the destination displacement
6052 * @param srcReg the source register
6053 */
6054 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
6055 public final void emitAND_RegDisp_Reg_Quad(GPR dstBase, Offset dstDisp, GPR srcReg) {
6056 int miStart = mi;
6057 // no group 1 to 4 prefix byte
6058 generateREXprefix(true, srcReg, null, dstBase);
6059 // single byte opcode
6060 setMachineCodes(mi++, (byte) 0x21);
6061 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
6062 if (lister != null) lister.RDR(miStart, "AND", dstBase, dstDisp, srcReg);
6063 }
6064
6065 /**
6066 * Generate a register--register AND. That is,
6067 * <PRE>
6068 * dstReg &= (quad) srcReg
6069 * </PRE>
6070 *
6071 * @param dstReg the destination register
6072 * @param srcReg the source register
6073 */
6074 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
6075 public final void emitAND_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
6076 int miStart = mi;
6077 // no group 1 to 4 prefix byte
6078 generateREXprefix(true, srcReg, null, dstReg);
6079 // single byte opcode
6080 setMachineCodes(mi++, (byte) 0x21);
6081 emitRegRegOperands(dstReg, srcReg);
6082 if (lister != null) lister.RR(miStart, "AND", dstReg, srcReg);
6083 }
6084
6085 /**
6086 * Generate a register--register-displacement AND. That is,
6087 * <PRE>
6088 * dstReg &= (quad) [srcReg + srcDisp]
6089 * </PRE>
6090 *
6091 * @param dstReg the destination register
6092 * @param srcBase the source register
6093 * @param srcDisp the source displacement
6094 */
6095 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
6096 public final void emitAND_Reg_RegDisp_Quad(GPR dstReg, GPR srcBase, Offset srcDisp) {
6097 int miStart = mi;
6098 // no group 1 to 4 prefix byte
6099 generateREXprefix(true, dstReg, null, srcBase);
6100 // single byte opcode
6101 setMachineCodes(mi++, (byte) 0x23);
6102 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
6103 if (lister != null) lister.RRD(miStart, "AND", dstReg, srcBase, srcDisp);
6104 }
6105
6106 /**
6107 * Generate a register--register-offset AND. That is,
6108 * <PRE>
6109 * dstReg &= (quad) [srcIndex<<srcScale + srcDisp]
6110 * </PRE>
6111 *
6112 * @param dstReg the destination register
6113 * @param srcIndex the source index register
6114 * @param srcScale the source shift amount
6115 * @param srcDisp the source displacement
6116 */
6117 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
6118 public final void emitAND_Reg_RegOff_Quad(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
6119 int miStart = mi;
6120 // no group 1 to 4 prefix byte
6121 generateREXprefix(true, dstReg, srcIndex, null);
6122 // single byte opcode
6123 setMachineCodes(mi++, (byte) 0x23);
6124 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
6125 if (lister != null) lister.RRFD(miStart, "AND", dstReg, srcIndex, srcScale, srcDisp);
6126 }
6127
6128 /**
6129 * Generate a register--register-offset AND. That is,
6130 * <PRE>
6131 * dstReg &= (quad) [srcDisp]
6132 * </PRE>
6133 *
6134 * @param dstReg the destination register
6135 * @param srcDisp the source displacement
6136 */
6137 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
6138 public final void emitAND_Reg_Abs_Quad(GPR dstReg, Address srcDisp) {
6139 int miStart = mi;
6140 // no group 1 to 4 prefix byte
6141 generateREXprefix(true, dstReg, null, null);
6142 // single byte opcode
6143 setMachineCodes(mi++, (byte) 0x23);
6144 emitAbsRegOperands(srcDisp, dstReg);
6145 if (lister != null) lister.RRA(miStart, "AND", dstReg, srcDisp);
6146 }
6147
6148 /**
6149 * Generate a register--register-offset AND. That is,
6150 * <PRE>
6151 * dstReg &= (quad) [srcBase + srcIndex<<srcScale + srcDisp]
6152 * </PRE>
6153 *
6154 * @param dstReg the destination register
6155 * @param srcBase the source base register
6156 * @param srcIndex the source index register
6157 * @param srcScale the source shift amount
6158 * @param srcDisp the source displacement
6159 */
6160 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
6161 public final void emitAND_Reg_RegIdx_Quad(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
6162 int miStart = mi;
6163 // no group 1 to 4 prefix byte
6164 generateREXprefix(true, dstReg, srcIndex, srcBase);
6165 // single byte opcode
6166 setMachineCodes(mi++, (byte) 0x23);
6167 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
6168 if (lister != null) lister.RRXD(miStart, "AND", dstReg, srcBase, srcIndex, srcScale, srcDisp);
6169 }
6170
6171 /**
6172 * Generate a register--register(indirect) AND. That is,
6173 * <PRE>
6174 * dstReg &= (quad) [srcBase]
6175 * </PRE>
6176 *
6177 * @param dstReg the destination register
6178 * @param srcBase the source base register
6179 */
6180 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
6181 public final void emitAND_Reg_RegInd_Quad(GPR dstReg, GPR srcBase) {
6182 int miStart = mi;
6183 // no group 1 to 4 prefix byte
6184 generateREXprefix(true, dstReg, null, srcBase);
6185 // single byte opcode
6186 setMachineCodes(mi++, (byte) 0x23);
6187 emitRegIndirectRegOperands(srcBase, dstReg);
6188 if (lister != null) lister.RRN(miStart, "AND", dstReg, srcBase);
6189 }
6190
6191 /**
6192 * Generate a register(indirect)--register AND. That is,
6193 * <PRE>
6194 * [dstBase] &= (byte) srcReg
6195 * </PRE>
6196 *
6197 * @param dstBase the destination base
6198 * @param srcReg the source register
6199 */
6200 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
6201 public final void emitAND_RegInd_Reg_Byte(GPR dstBase, GPR srcReg) {
6202 int miStart = mi;
6203 // no group 1 to 4 prefix byte
6204 generateREXprefix(false, srcReg, null, dstBase);
6205 // single byte opcode
6206 setMachineCodes(mi++, (byte) 0x20);
6207 emitRegIndirectRegOperands(dstBase, srcReg);
6208 if (lister != null) lister.RNR(miStart, "AND", dstBase, srcReg);
6209 }
6210
6211 /**
6212 * Generate a register-offset--register AND. That is,
6213 * <PRE>
6214 * [dstReg<<dstScale + dstDisp] &= (byte) srcReg
6215 * </PRE>
6216 *
6217 * @param dstIndex the destination index register
6218 * @param dstScale the destination shift amount
6219 * @param dstDisp the destination displacement
6220 * @param srcReg the source register
6221 */
6222 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
6223 public final void emitAND_RegOff_Reg_Byte(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
6224 int miStart = mi;
6225 // no group 1 to 4 prefix byte
6226 generateREXprefix(false, srcReg, dstIndex, null);
6227 // single byte opcode
6228 setMachineCodes(mi++, (byte) 0x20);
6229 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
6230 if (lister != null) lister.RFDR(miStart, "AND", dstIndex, dstScale, dstDisp, srcReg);
6231 }
6232
6233 /**
6234 * Generate a absolute--register AND. That is,
6235 * <PRE>
6236 * [dstDisp] &= (byte) srcReg
6237 * </PRE>
6238 *
6239 * @param dstDisp the destination address
6240 * @param srcReg the source register
6241 */
6242 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
6243 public final void emitAND_Abs_Reg_Byte(Address dstDisp, GPR srcReg) {
6244 int miStart = mi;
6245 // no group 1 to 4 prefix byte
6246 generateREXprefix(false, srcReg, null, null);
6247 // single byte opcode
6248 setMachineCodes(mi++, (byte) 0x20);
6249 emitAbsRegOperands(dstDisp, srcReg);
6250 if (lister != null) lister.RAR(miStart, "AND", dstDisp, srcReg);
6251 }
6252
6253 /**
6254 * Generate a register-index--register AND. That is,
6255 * <PRE>
6256 * [dstBase + dstIndex<<dstScale + dstDisp] &= (byte) srcReg
6257 * </PRE>
6258 *
6259 * @param dstBase the base register
6260 * @param dstIndex the destination index register
6261 * @param dstScale the destination shift amount
6262 * @param dstDisp the destination displacement
6263 * @param srcReg the source register
6264 */
6265 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
6266 public final void emitAND_RegIdx_Reg_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
6267 int miStart = mi;
6268 // no group 1 to 4 prefix byte
6269 generateREXprefix(false, srcReg, dstIndex, dstBase);
6270 // single byte opcode
6271 setMachineCodes(mi++, (byte) 0x20);
6272 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
6273 if (lister != null) lister.RXDR(miStart, "AND", dstBase, dstIndex, dstScale, dstDisp, srcReg);
6274 }
6275
6276 /**
6277 * Generate a register-displacement--register AND. That is,
6278 * <PRE>
6279 * [dstBase + dstDisp] &= (byte) srcReg
6280 * </PRE>
6281 *
6282 * @param dstBase the base register
6283 * @param dstDisp the destination displacement
6284 * @param srcReg the source register
6285 */
6286 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
6287 public final void emitAND_RegDisp_Reg_Byte(GPR dstBase, Offset dstDisp, GPR srcReg) {
6288 int miStart = mi;
6289 // no group 1 to 4 prefix byte
6290 generateREXprefix(false, srcReg, null, dstBase);
6291 // single byte opcode
6292 setMachineCodes(mi++, (byte) 0x20);
6293 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
6294 if (lister != null) lister.RDR(miStart, "AND", dstBase, dstDisp, srcReg);
6295 }
6296
6297 /**
6298 * Generate a register--register AND. That is,
6299 * <PRE>
6300 * dstReg &= (byte) srcReg
6301 * </PRE>
6302 *
6303 * @param dstReg the destination register
6304 * @param srcReg the source register
6305 */
6306 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
6307 public final void emitAND_Reg_Reg_Byte(GPR dstReg, GPR srcReg) {
6308 int miStart = mi;
6309 // no group 1 to 4 prefix byte
6310 generateREXprefix(false, srcReg, null, dstReg);
6311 // single byte opcode
6312 setMachineCodes(mi++, (byte) 0x20);
6313 emitRegRegOperands(dstReg, srcReg);
6314 if (lister != null) lister.RR(miStart, "AND", dstReg, srcReg);
6315 }
6316
6317 /**
6318 * Generate a register--register-displacement AND. That is,
6319 * <PRE>
6320 * dstReg &= (byte) [srcReg + srcDisp]
6321 * </PRE>
6322 *
6323 * @param dstReg the destination register
6324 * @param srcBase the source register
6325 * @param srcDisp the source displacement
6326 */
6327 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
6328 public final void emitAND_Reg_RegDisp_Byte(GPR dstReg, GPR srcBase, Offset srcDisp) {
6329 int miStart = mi;
6330 // no group 1 to 4 prefix byte
6331 generateREXprefix(false, dstReg, null, srcBase);
6332 // single byte opcode
6333 setMachineCodes(mi++, (byte) 0x22);
6334 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
6335 if (lister != null) lister.RRD(miStart, "AND", dstReg, srcBase, srcDisp);
6336 }
6337
6338 /**
6339 * Generate a register--register-offset AND. That is,
6340 * <PRE>
6341 * dstReg &= (byte) [srcIndex<<srcScale + srcDisp]
6342 * </PRE>
6343 *
6344 * @param dstReg the destination register
6345 * @param srcIndex the source index register
6346 * @param srcScale the source shift amount
6347 * @param srcDisp the source displacement
6348 */
6349 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
6350 public final void emitAND_Reg_RegOff_Byte(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
6351 int miStart = mi;
6352 // no group 1 to 4 prefix byte
6353 generateREXprefix(false, dstReg, srcIndex, null);
6354 // single byte opcode
6355 setMachineCodes(mi++, (byte) 0x22);
6356 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
6357 if (lister != null) lister.RRFD(miStart, "AND", dstReg, srcIndex, srcScale, srcDisp);
6358 }
6359
6360 /**
6361 * Generate a register--register-offset AND. That is,
6362 * <PRE>
6363 * dstReg &= (byte) [srcDisp]
6364 * </PRE>
6365 *
6366 * @param dstReg the destination register
6367 * @param srcDisp the source displacement
6368 */
6369 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
6370 public final void emitAND_Reg_Abs_Byte(GPR dstReg, Address srcDisp) {
6371 int miStart = mi;
6372 // no group 1 to 4 prefix byte
6373 generateREXprefix(false, dstReg, null, null);
6374 // single byte opcode
6375 setMachineCodes(mi++, (byte) 0x22);
6376 emitAbsRegOperands(srcDisp, dstReg);
6377 if (lister != null) lister.RRA(miStart, "AND", dstReg, srcDisp);
6378 }
6379
6380 /**
6381 * Generate a register--register-offset AND. That is,
6382 * <PRE>
6383 * dstReg &= (byte) [srcBase + srcIndex<<srcScale + srcDisp]
6384 * </PRE>
6385 *
6386 * @param dstReg the destination register
6387 * @param srcBase the source base register
6388 * @param srcIndex the source index register
6389 * @param srcScale the source shift amount
6390 * @param srcDisp the source displacement
6391 */
6392 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
6393 public final void emitAND_Reg_RegIdx_Byte(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
6394 int miStart = mi;
6395 // no group 1 to 4 prefix byte
6396 generateREXprefix(false, dstReg, srcIndex, srcBase);
6397 // single byte opcode
6398 setMachineCodes(mi++, (byte) 0x22);
6399 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
6400 if (lister != null) lister.RRXD(miStart, "AND", dstReg, srcBase, srcIndex, srcScale, srcDisp);
6401 }
6402
6403 /**
6404 * Generate a register--register(indirect) AND. That is,
6405 * <PRE>
6406 * dstReg &= (byte) [srcBase]
6407 * </PRE>
6408 *
6409 * @param dstReg the destination register
6410 * @param srcBase the source base register
6411 */
6412 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
6413 public final void emitAND_Reg_RegInd_Byte(GPR dstReg, GPR srcBase) {
6414 int miStart = mi;
6415 // no group 1 to 4 prefix byte
6416 generateREXprefix(false, dstReg, null, srcBase);
6417 // single byte opcode
6418 setMachineCodes(mi++, (byte) 0x22);
6419 emitRegIndirectRegOperands(srcBase, dstReg);
6420 if (lister != null) lister.RRN(miStart, "AND", dstReg, srcBase);
6421 }
6422
6423 /**
6424 * Generate a register--immediate AND. That is,
6425 * <PRE>
6426 * dstReg &= imm
6427 * </PRE>
6428 *
6429 * @param dstReg the destination register
6430 * @param imm immediate
6431 */
6432 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
6433 public final void emitAND_Reg_Imm(GPR dstReg, int imm) {
6434 int miStart = mi;
6435 // no group 1 to 4 prefix byte
6436 generateREXprefix(false, null, null, dstReg);
6437 // single byte opcode
6438 if (fits(imm,8)) {
6439 setMachineCodes(mi++, (byte) 0x83);
6440 // "register 0x4" is really part of the opcode
6441 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
6442 emitImm8((byte)imm);
6443 } else if (dstReg == EAX) {
6444 setMachineCodes(mi++, (byte) 0x25);
6445 emitImm32(imm);
6446 } else {
6447 setMachineCodes(mi++, (byte) 0x81);
6448 // "register 0x4" is really part of the opcode
6449 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
6450 emitImm32(imm);
6451 }
6452 if (lister != null) lister.RI(miStart, "AND", dstReg, imm);
6453 }
6454
6455 /**
6456 * Generate a register-displacement--immediate AND. That is,
6457 * <PRE>
6458 * [dstBase + dstDisp] &= imm
6459 * </PRE>
6460 *
6461 * @param dstBase the destination register
6462 * @param dstDisp the destination displacement
6463 * @param imm immediate
6464 */
6465 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
6466 public final void emitAND_RegDisp_Imm(GPR dstBase, Offset dstDisp, int imm) {
6467 int miStart = mi;
6468 // no group 1 to 4 prefix byte
6469 generateREXprefix(false, null, null, dstBase);
6470 // single byte opcode
6471 if (fits(imm,8)) {
6472 setMachineCodes(mi++, (byte) 0x83);
6473 // "register 0x4" is really part of the opcode
6474 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
6475 emitImm8((byte)imm);
6476 } else {
6477 setMachineCodes(mi++, (byte) 0x81);
6478 // "register 0x4" is really part of the opcode
6479 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
6480 emitImm32(imm);
6481 }
6482 if (lister != null) lister.RDI(miStart, "AND", dstBase, dstDisp, imm);
6483 }
6484
6485 /**
6486 * Generate a register-offset--immediate AND. That is,
6487 * <PRE>
6488 * [dstIndex<<dstScale + dstDisp] &= imm
6489 * </PRE>
6490 *
6491 * @param dstIndex the destination index register
6492 * @param dstScale the destination shift amount
6493 * @param dstDisp the destination displacement
6494 * @param imm immediate
6495 */
6496 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
6497 public final void emitAND_RegOff_Imm(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
6498 int miStart = mi;
6499 // no group 1 to 4 prefix byte
6500 generateREXprefix(false, null, dstIndex, null);
6501 // single byte opcode
6502 if (fits(imm,8)) {
6503 setMachineCodes(mi++, (byte) 0x83);
6504 // "register 0x4" is really part of the opcode
6505 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
6506 emitImm8((byte)imm);
6507 } else {
6508 setMachineCodes(mi++, (byte) 0x81);
6509 // "register 0x4" is really part of the opcode
6510 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
6511 emitImm32(imm);
6512 }
6513 if (lister != null) lister.RFDI(miStart, "AND", dstIndex, dstScale, dstDisp, imm);
6514 }
6515
6516 /**
6517 * Generate a absolute--immediate AND. That is,
6518 * <PRE>
6519 * [dstDisp] &= imm
6520 * </PRE>
6521 *
6522 * @param dstDisp the destination displacement
6523 * @param imm immediate
6524 */
6525 public final void emitAND_Abs_Imm(Address dstDisp, int imm) {
6526 int miStart = mi;
6527 // no group 1 to 4 prefix byte
6528 generateREXprefix(false, null, null, null);
6529 // single byte opcode
6530 if (fits(imm,8)) {
6531 setMachineCodes(mi++, (byte) 0x83);
6532 // "register 0x4" is really part of the opcode
6533 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
6534 emitImm8((byte)imm);
6535 } else {
6536 setMachineCodes(mi++, (byte) 0x81);
6537 // "register 0x4" is really part of the opcode
6538 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
6539 emitImm32(imm);
6540 }
6541 if (lister != null) lister.RAI(miStart, "AND", dstDisp, imm);
6542 }
6543
6544 /**
6545 * Generate a register-index--immediate AND. That is,
6546 * <PRE>
6547 * [dstBase + dstIndex<<dstScale + dstDisp] &= imm
6548 * </PRE>
6549 *
6550 * @param dstBase the destination base register
6551 * @param dstIndex the destination index register
6552 * @param dstScale the destination shift amount
6553 * @param dstDisp the destination displacement
6554 * @param imm immediate
6555 */
6556 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
6557 public final void emitAND_RegIdx_Imm(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
6558 int miStart = mi;
6559 // no group 1 to 4 prefix byte
6560 generateREXprefix(false, null, dstIndex, dstBase);
6561 // single byte opcode
6562 if (fits(imm,8)) {
6563 setMachineCodes(mi++, (byte) 0x83);
6564 // "register 0x4" is really part of the opcode
6565 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
6566 emitImm8((byte)imm);
6567 } else {
6568 setMachineCodes(mi++, (byte) 0x81);
6569 // "register 0x4" is really part of the opcode
6570 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
6571 emitImm32(imm);
6572 }
6573 if (lister != null) lister.RXDI(miStart, "AND", dstBase, dstIndex, dstScale, dstDisp, imm);
6574 }
6575
6576 /**
6577 * Generate a register(indirect)--immediate AND. That is,
6578 * <PRE>
6579 * [dstBase] &= imm
6580 * </PRE>
6581 *
6582 * @param dstBase the destination base register
6583 * @param imm immediate
6584 */
6585 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
6586 public final void emitAND_RegInd_Imm(GPR dstBase, int imm) {
6587 int miStart = mi;
6588 // no group 1 to 4 prefix byte
6589 generateREXprefix(false, null, null, dstBase);
6590 // single byte opcode
6591 if (fits(imm,8)) {
6592 setMachineCodes(mi++, (byte) 0x83);
6593 // "register 0x4" is really part of the opcode
6594 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
6595 emitImm8((byte)imm);
6596 } else {
6597 setMachineCodes(mi++, (byte) 0x81);
6598 // "register 0x4" is really part of the opcode
6599 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
6600 emitImm32(imm);
6601 }
6602 if (lister != null) lister.RNI(miStart, "AND", dstBase, imm);
6603 }
6604
6605 /**
6606 * Generate a register--immediate AND. That is,
6607 * <PRE>
6608 * dstReg &= (word) imm
6609 * </PRE>
6610 *
6611 * @param dstReg the destination register
6612 * @param imm immediate
6613 */
6614 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
6615 public final void emitAND_Reg_Imm_Word(GPR dstReg, int imm) {
6616 int miStart = mi;
6617 setMachineCodes(mi++, (byte) 0x66);
6618 generateREXprefix(false, null, null, dstReg);
6619 // single byte opcode
6620 if (fits(imm,8)) {
6621 setMachineCodes(mi++, (byte) 0x83);
6622 // "register 0x4" is really part of the opcode
6623 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
6624 emitImm8((byte)imm);
6625 } else if (dstReg == EAX) {
6626 setMachineCodes(mi++, (byte) 0x25);
6627 emitImm16(imm);
6628 } else {
6629 setMachineCodes(mi++, (byte) 0x81);
6630 // "register 0x4" is really part of the opcode
6631 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
6632 emitImm16(imm);
6633 }
6634 if (lister != null) lister.RI(miStart, "AND", dstReg, imm);
6635 }
6636
6637 /**
6638 * Generate a register-displacement--immediate AND. That is,
6639 * <PRE>
6640 * [dstBase + dstDisp] &= (word) imm
6641 * </PRE>
6642 *
6643 * @param dstBase the destination register
6644 * @param dstDisp the destination displacement
6645 * @param imm immediate
6646 */
6647 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
6648 public final void emitAND_RegDisp_Imm_Word(GPR dstBase, Offset dstDisp, int imm) {
6649 int miStart = mi;
6650 setMachineCodes(mi++, (byte) 0x66);
6651 generateREXprefix(false, null, null, dstBase);
6652 // single byte opcode
6653 if (fits(imm,8)) {
6654 setMachineCodes(mi++, (byte) 0x83);
6655 // "register 0x4" is really part of the opcode
6656 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
6657 emitImm8((byte)imm);
6658 } else {
6659 setMachineCodes(mi++, (byte) 0x81);
6660 // "register 0x4" is really part of the opcode
6661 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
6662 emitImm16(imm);
6663 }
6664 if (lister != null) lister.RDI(miStart, "AND", dstBase, dstDisp, imm);
6665 }
6666
6667 /**
6668 * Generate a register-offset--immediate AND. That is,
6669 * <PRE>
6670 * [dstIndex<<dstScale + dstDisp] &= (word) imm
6671 * </PRE>
6672 *
6673 * @param dstIndex the destination index register
6674 * @param dstScale the destination shift amount
6675 * @param dstDisp the destination displacement
6676 * @param imm immediate
6677 */
6678 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
6679 public final void emitAND_RegOff_Imm_Word(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
6680 int miStart = mi;
6681 setMachineCodes(mi++, (byte) 0x66);
6682 generateREXprefix(false, null, dstIndex, null);
6683 // single byte opcode
6684 if (fits(imm,8)) {
6685 setMachineCodes(mi++, (byte) 0x83);
6686 // "register 0x4" is really part of the opcode
6687 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
6688 emitImm8((byte)imm);
6689 } else {
6690 setMachineCodes(mi++, (byte) 0x81);
6691 // "register 0x4" is really part of the opcode
6692 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
6693 emitImm16(imm);
6694 }
6695 if (lister != null) lister.RFDI(miStart, "AND", dstIndex, dstScale, dstDisp, imm);
6696 }
6697
6698 /**
6699 * Generate a absolute--immediate AND. That is,
6700 * <PRE>
6701 * [dstDisp] &= (word) imm
6702 * </PRE>
6703 *
6704 * @param dstDisp the destination displacement
6705 * @param imm immediate
6706 */
6707 public final void emitAND_Abs_Imm_Word(Address dstDisp, int imm) {
6708 int miStart = mi;
6709 setMachineCodes(mi++, (byte) 0x66);
6710 generateREXprefix(false, null, null, null);
6711 // single byte opcode
6712 if (fits(imm,8)) {
6713 setMachineCodes(mi++, (byte) 0x83);
6714 // "register 0x4" is really part of the opcode
6715 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
6716 emitImm8((byte)imm);
6717 } else {
6718 setMachineCodes(mi++, (byte) 0x81);
6719 // "register 0x4" is really part of the opcode
6720 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
6721 emitImm16(imm);
6722 }
6723 if (lister != null) lister.RAI(miStart, "AND", dstDisp, imm);
6724 }
6725
6726 /**
6727 * Generate a register-index--immediate AND. That is,
6728 * <PRE>
6729 * [dstBase + dstIndex<<dstScale + dstDisp] &= (word) imm
6730 * </PRE>
6731 *
6732 * @param dstBase the destination base register
6733 * @param dstIndex the destination index register
6734 * @param dstScale the destination shift amount
6735 * @param dstDisp the destination displacement
6736 * @param imm immediate
6737 */
6738 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
6739 public final void emitAND_RegIdx_Imm_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
6740 int miStart = mi;
6741 setMachineCodes(mi++, (byte) 0x66);
6742 generateREXprefix(false, null, dstIndex, dstBase);
6743 // single byte opcode
6744 if (fits(imm,8)) {
6745 setMachineCodes(mi++, (byte) 0x83);
6746 // "register 0x4" is really part of the opcode
6747 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
6748 emitImm8((byte)imm);
6749 } else {
6750 setMachineCodes(mi++, (byte) 0x81);
6751 // "register 0x4" is really part of the opcode
6752 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
6753 emitImm16(imm);
6754 }
6755 if (lister != null) lister.RXDI(miStart, "AND", dstBase, dstIndex, dstScale, dstDisp, imm);
6756 }
6757
6758 /**
6759 * Generate a register(indirect)--immediate AND. That is,
6760 * <PRE>
6761 * [dstBase] &= (word) imm
6762 * </PRE>
6763 *
6764 * @param dstBase the destination base register
6765 * @param imm immediate
6766 */
6767 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
6768 public final void emitAND_RegInd_Imm_Word(GPR dstBase, int imm) {
6769 int miStart = mi;
6770 setMachineCodes(mi++, (byte) 0x66);
6771 generateREXprefix(false, null, null, dstBase);
6772 // single byte opcode
6773 if (fits(imm,8)) {
6774 setMachineCodes(mi++, (byte) 0x83);
6775 // "register 0x4" is really part of the opcode
6776 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
6777 emitImm8((byte)imm);
6778 } else {
6779 setMachineCodes(mi++, (byte) 0x81);
6780 // "register 0x4" is really part of the opcode
6781 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
6782 emitImm16(imm);
6783 }
6784 if (lister != null) lister.RNI(miStart, "AND", dstBase, imm);
6785 }
6786
6787 /**
6788 * Generate a register--immediate AND. That is,
6789 * <PRE>
6790 * dstReg &= (quad) imm
6791 * </PRE>
6792 *
6793 * @param dstReg the destination register
6794 * @param imm immediate
6795 */
6796 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
6797 public final void emitAND_Reg_Imm_Quad(GPR dstReg, int imm) {
6798 int miStart = mi;
6799 // no group 1 to 4 prefix byte
6800 generateREXprefix(true, null, null, dstReg);
6801 // single byte opcode
6802 if (fits(imm,8)) {
6803 setMachineCodes(mi++, (byte) 0x83);
6804 // "register 0x4" is really part of the opcode
6805 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
6806 emitImm8((byte)imm);
6807 } else if (dstReg == EAX) {
6808 setMachineCodes(mi++, (byte) 0x25);
6809 emitImm32(imm);
6810 } else {
6811 setMachineCodes(mi++, (byte) 0x81);
6812 // "register 0x4" is really part of the opcode
6813 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
6814 emitImm32(imm);
6815 }
6816 if (lister != null) lister.RI(miStart, "AND", dstReg, imm);
6817 }
6818
6819 /**
6820 * Generate a register-displacement--immediate AND. That is,
6821 * <PRE>
6822 * [dstBase + dstDisp] &= (quad) imm
6823 * </PRE>
6824 *
6825 * @param dstBase the destination register
6826 * @param dstDisp the destination displacement
6827 * @param imm immediate
6828 */
6829 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
6830 public final void emitAND_RegDisp_Imm_Quad(GPR dstBase, Offset dstDisp, int imm) {
6831 int miStart = mi;
6832 // no group 1 to 4 prefix byte
6833 generateREXprefix(true, null, null, dstBase);
6834 // single byte opcode
6835 if (fits(imm,8)) {
6836 setMachineCodes(mi++, (byte) 0x83);
6837 // "register 0x4" is really part of the opcode
6838 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
6839 emitImm8((byte)imm);
6840 } else {
6841 setMachineCodes(mi++, (byte) 0x81);
6842 // "register 0x4" is really part of the opcode
6843 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
6844 emitImm32(imm);
6845 }
6846 if (lister != null) lister.RDI(miStart, "AND", dstBase, dstDisp, imm);
6847 }
6848
6849 /**
6850 * Generate a register-offset--immediate AND. That is,
6851 * <PRE>
6852 * [dstIndex<<dstScale + dstDisp] &= (quad) imm
6853 * </PRE>
6854 *
6855 * @param dstIndex the destination index register
6856 * @param dstScale the destination shift amount
6857 * @param dstDisp the destination displacement
6858 * @param imm immediate
6859 */
6860 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
6861 public final void emitAND_RegOff_Imm_Quad(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
6862 int miStart = mi;
6863 // no group 1 to 4 prefix byte
6864 generateREXprefix(true, null, dstIndex, null);
6865 // single byte opcode
6866 if (fits(imm,8)) {
6867 setMachineCodes(mi++, (byte) 0x83);
6868 // "register 0x4" is really part of the opcode
6869 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
6870 emitImm8((byte)imm);
6871 } else {
6872 setMachineCodes(mi++, (byte) 0x81);
6873 // "register 0x4" is really part of the opcode
6874 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
6875 emitImm32(imm);
6876 }
6877 if (lister != null) lister.RFDI(miStart, "AND", dstIndex, dstScale, dstDisp, imm);
6878 }
6879
6880 /**
6881 * Generate a absolute--immediate AND. That is,
6882 * <PRE>
6883 * [dstDisp] &= (quad) imm
6884 * </PRE>
6885 *
6886 * @param dstDisp the destination displacement
6887 * @param imm immediate
6888 */
6889 public final void emitAND_Abs_Imm_Quad(Address dstDisp, int imm) {
6890 int miStart = mi;
6891 // no group 1 to 4 prefix byte
6892 generateREXprefix(true, null, null, null);
6893 // single byte opcode
6894 if (fits(imm,8)) {
6895 setMachineCodes(mi++, (byte) 0x83);
6896 // "register 0x4" is really part of the opcode
6897 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
6898 emitImm8((byte)imm);
6899 } else {
6900 setMachineCodes(mi++, (byte) 0x81);
6901 // "register 0x4" is really part of the opcode
6902 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
6903 emitImm32(imm);
6904 }
6905 if (lister != null) lister.RAI(miStart, "AND", dstDisp, imm);
6906 }
6907
6908 /**
6909 * Generate a register-index--immediate AND. That is,
6910 * <PRE>
6911 * [dstBase + dstIndex<<dstScale + dstDisp] &= (quad) imm
6912 * </PRE>
6913 *
6914 * @param dstBase the destination base register
6915 * @param dstIndex the destination index register
6916 * @param dstScale the destination shift amount
6917 * @param dstDisp the destination displacement
6918 * @param imm immediate
6919 */
6920 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
6921 public final void emitAND_RegIdx_Imm_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
6922 int miStart = mi;
6923 // no group 1 to 4 prefix byte
6924 generateREXprefix(true, null, dstIndex, dstBase);
6925 // single byte opcode
6926 if (fits(imm,8)) {
6927 setMachineCodes(mi++, (byte) 0x83);
6928 // "register 0x4" is really part of the opcode
6929 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
6930 emitImm8((byte)imm);
6931 } else {
6932 setMachineCodes(mi++, (byte) 0x81);
6933 // "register 0x4" is really part of the opcode
6934 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
6935 emitImm32(imm);
6936 }
6937 if (lister != null) lister.RXDI(miStart, "AND", dstBase, dstIndex, dstScale, dstDisp, imm);
6938 }
6939
6940 /**
6941 * Generate a register(indirect)--immediate AND. That is,
6942 * <PRE>
6943 * [dstBase] &= (quad) imm
6944 * </PRE>
6945 *
6946 * @param dstBase the destination base register
6947 * @param imm immediate
6948 */
6949 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
6950 public final void emitAND_RegInd_Imm_Quad(GPR dstBase, int imm) {
6951 int miStart = mi;
6952 // no group 1 to 4 prefix byte
6953 generateREXprefix(true, null, null, dstBase);
6954 // single byte opcode
6955 if (fits(imm,8)) {
6956 setMachineCodes(mi++, (byte) 0x83);
6957 // "register 0x4" is really part of the opcode
6958 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
6959 emitImm8((byte)imm);
6960 } else {
6961 setMachineCodes(mi++, (byte) 0x81);
6962 // "register 0x4" is really part of the opcode
6963 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
6964 emitImm32(imm);
6965 }
6966 if (lister != null) lister.RNI(miStart, "AND", dstBase, imm);
6967 }
6968
6969 /**
6970 * Generate a register--immediate AND. That is,
6971 * <PRE>
6972 * dstReg &= (byte) imm
6973 * </PRE>
6974 *
6975 * @param dstReg the destination register
6976 * @param imm immediate
6977 */
6978 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
6979 public final void emitAND_Reg_Imm_Byte(GPR dstReg, int imm) {
6980 int miStart = mi;
6981 if (dstReg == EAX) {
6982 setMachineCodes(mi++, (byte) 0x24);
6983 emitImm8(imm);
6984 } else {
6985 generateREXprefix(false, null, null, dstReg);
6986 setMachineCodes(mi++, (byte) 0x80);
6987 // "register 0x4" is really part of the opcode
6988 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
6989 emitImm8(imm);
6990 }
6991 if (lister != null) lister.RI(miStart, "AND", dstReg, imm);
6992 }
6993
6994 /**
6995 * Generate a register-displacement--immediate AND. That is,
6996 * <PRE>
6997 * [dstBase + dstDisp] &= (byte) imm
6998 * </PRE>
6999 *
7000 * @param dstBase the destination register
7001 * @param dstDisp the destination displacement
7002 * @param imm immediate
7003 */
7004 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
7005 public final void emitAND_RegDisp_Imm_Byte(GPR dstBase, Offset dstDisp, int imm) {
7006 int miStart = mi;
7007 generateREXprefix(false, null, null, dstBase);
7008 setMachineCodes(mi++, (byte) 0x80);
7009 // "register 0x4" is really part of the opcode
7010 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
7011 emitImm8(imm);
7012 if (lister != null) lister.RDI(miStart, "AND", dstBase, dstDisp, imm);
7013 }
7014
7015 /**
7016 * Generate a register-index--immediate AND. That is,
7017 * <PRE>
7018 * [dstBase + dstIndex<<scale + dstDisp] &= (byte) imm
7019 * </PRE>
7020 *
7021 * @param dstBase the destination base register
7022 * @param dstIndex the destination index register
7023 * @param dstScale the destination shift amount
7024 * @param dstDisp the destination displacement
7025 * @param imm immediate
7026 */
7027 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7028 public final void emitAND_RegIdx_Imm_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
7029 int miStart = mi;
7030 generateREXprefix(false, null, dstIndex, dstBase);
7031 setMachineCodes(mi++, (byte) 0x80);
7032 // "register 0x4" is really part of the opcode
7033 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
7034 emitImm8(imm);
7035 if (lister != null) lister.RXDI(miStart, "AND", dstBase, dstIndex, dstScale, dstDisp, imm);
7036 }
7037
7038 /**
7039 * Generate a register-offset--immediate AND. That is,
7040 * <PRE>
7041 * [dstIndex<<dstScale + dstDisp] &= (byte) imm
7042 * </PRE>
7043 *
7044 * @param dstIndex the destination index register
7045 * @param dstScale the destination shift amount
7046 * @param dstDisp the destination displacement
7047 * @param imm immediate
7048 */
7049 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
7050 public final void emitAND_RegOff_Imm_Byte(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
7051 int miStart = mi;
7052 generateREXprefix(false, null, dstIndex, null);
7053 setMachineCodes(mi++, (byte) 0x80);
7054 // "register 0x4" is really part of the opcode
7055 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
7056 emitImm8(imm);
7057 if (lister != null) lister.RFDI(miStart, "AND", dstIndex, dstScale, dstDisp, imm);
7058 }
7059
7060 /**
7061 * Generate a absolute--immediate AND. That is,
7062 * <PRE>
7063 * [dstDisp] &= (byte) imm
7064 * </PRE>
7065 *
7066 * @param dstDisp the destination displacement
7067 * @param imm immediate
7068 */
7069 public final void emitAND_Abs_Imm_Byte(Address dstDisp, int imm) {
7070 int miStart = mi;
7071 generateREXprefix(false, null, null, null);
7072 setMachineCodes(mi++, (byte) 0x80);
7073 // "register 0x4" is really part of the opcode
7074 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
7075 emitImm8(imm);
7076 if (lister != null) lister.RAI(miStart, "AND", dstDisp, imm);
7077 }
7078
7079 /**
7080 * Generate a register(indirect)--immediate AND. That is,
7081 * <PRE>
7082 * [dstBase] &= (byte) imm
7083 * </PRE>
7084 *
7085 * @param dstBase the destination base register
7086 * @param imm immediate
7087 */
7088 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
7089 public final void emitAND_RegInd_Imm_Byte(GPR dstBase, int imm) {
7090 int miStart = mi;
7091 generateREXprefix(false, null, null, dstBase);
7092 setMachineCodes(mi++, (byte) 0x80);
7093 // "register 0x4" is really part of the opcode
7094 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
7095 emitImm8(imm);
7096 if (lister != null) lister.RNI(miStart, "AND", dstBase, imm);
7097 }
7098
7099 /**
7100 * Generate a register(indirect)--register CMP. That is,
7101 * <PRE>
7102 * [dstBase] == srcReg
7103 * </PRE>
7104 *
7105 * @param dstBase the destination base
7106 * @param srcReg the source register
7107 */
7108 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7109 public final void emitCMP_RegInd_Reg(GPR dstBase, GPR srcReg) {
7110 int miStart = mi;
7111 // no group 1 to 4 prefix byte
7112 generateREXprefix(false, srcReg, null, dstBase);
7113 // single byte opcode
7114 setMachineCodes(mi++, (byte) 0x39);
7115 emitRegIndirectRegOperands(dstBase, srcReg);
7116 if (lister != null) lister.RNR(miStart, "CMP", dstBase, srcReg);
7117 }
7118
7119 /**
7120 * Generate a register-offset--register CMP. That is,
7121 * <PRE>
7122 * [dstReg<<dstScale + dstDisp] == srcReg
7123 * </PRE>
7124 *
7125 * @param dstIndex the destination index register
7126 * @param dstScale the destination shift amount
7127 * @param dstDisp the destination displacement
7128 * @param srcReg the source register
7129 */
7130 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
7131 public final void emitCMP_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
7132 int miStart = mi;
7133 // no group 1 to 4 prefix byte
7134 generateREXprefix(false, srcReg, dstIndex, null);
7135 // single byte opcode
7136 setMachineCodes(mi++, (byte) 0x39);
7137 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
7138 if (lister != null) lister.RFDR(miStart, "CMP", dstIndex, dstScale, dstDisp, srcReg);
7139 }
7140
7141 /**
7142 * Generate a absolute--register CMP. That is,
7143 * <PRE>
7144 * [dstDisp] == srcReg
7145 * </PRE>
7146 *
7147 * @param dstDisp the destination address
7148 * @param srcReg the source register
7149 */
7150 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
7151 public final void emitCMP_Abs_Reg(Address dstDisp, GPR srcReg) {
7152 int miStart = mi;
7153 // no group 1 to 4 prefix byte
7154 generateREXprefix(false, srcReg, null, null);
7155 // single byte opcode
7156 setMachineCodes(mi++, (byte) 0x39);
7157 emitAbsRegOperands(dstDisp, srcReg);
7158 if (lister != null) lister.RAR(miStart, "CMP", dstDisp, srcReg);
7159 }
7160
7161 /**
7162 * Generate a register-index--register CMP. That is,
7163 * <PRE>
7164 * [dstBase + dstIndex<<dstScale + dstDisp] == srcReg
7165 * </PRE>
7166 *
7167 * @param dstBase the base register
7168 * @param dstIndex the destination index register
7169 * @param dstScale the destination shift amount
7170 * @param dstDisp the destination displacement
7171 * @param srcReg the source register
7172 */
7173 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
7174 public final void emitCMP_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
7175 int miStart = mi;
7176 // no group 1 to 4 prefix byte
7177 generateREXprefix(false, srcReg, dstIndex, dstBase);
7178 // single byte opcode
7179 setMachineCodes(mi++, (byte) 0x39);
7180 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
7181 if (lister != null) lister.RXDR(miStart, "CMP", dstBase, dstIndex, dstScale, dstDisp, srcReg);
7182 }
7183
7184 /**
7185 * Generate a register-displacement--register CMP. That is,
7186 * <PRE>
7187 * [dstBase + dstDisp] == srcReg
7188 * </PRE>
7189 *
7190 * @param dstBase the base register
7191 * @param dstDisp the destination displacement
7192 * @param srcReg the source register
7193 */
7194 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
7195 public final void emitCMP_RegDisp_Reg(GPR dstBase, Offset dstDisp, GPR srcReg) {
7196 int miStart = mi;
7197 // no group 1 to 4 prefix byte
7198 generateREXprefix(false, srcReg, null, dstBase);
7199 // single byte opcode
7200 setMachineCodes(mi++, (byte) 0x39);
7201 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
7202 if (lister != null) lister.RDR(miStart, "CMP", dstBase, dstDisp, srcReg);
7203 }
7204
7205 /**
7206 * Generate a register--register CMP. That is,
7207 * <PRE>
7208 * dstReg == srcReg
7209 * </PRE>
7210 *
7211 * @param dstReg the destination register
7212 * @param srcReg the source register
7213 */
7214 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7215 public final void emitCMP_Reg_Reg(GPR dstReg, GPR srcReg) {
7216 int miStart = mi;
7217 // no group 1 to 4 prefix byte
7218 generateREXprefix(false, srcReg, null, dstReg);
7219 // single byte opcode
7220 setMachineCodes(mi++, (byte) 0x39);
7221 emitRegRegOperands(dstReg, srcReg);
7222 if (lister != null) lister.RR(miStart, "CMP", dstReg, srcReg);
7223 }
7224
7225 /**
7226 * Generate a register--register-displacement CMP. That is,
7227 * <PRE>
7228 * dstReg == [srcReg + srcDisp]
7229 * </PRE>
7230 *
7231 * @param dstReg the destination register
7232 * @param srcBase the source register
7233 * @param srcDisp the source displacement
7234 */
7235 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7236 public final void emitCMP_Reg_RegDisp(GPR dstReg, GPR srcBase, Offset srcDisp) {
7237 int miStart = mi;
7238 // no group 1 to 4 prefix byte
7239 generateREXprefix(false, dstReg, null, srcBase);
7240 // single byte opcode
7241 setMachineCodes(mi++, (byte) 0x3B);
7242 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
7243 if (lister != null) lister.RRD(miStart, "CMP", dstReg, srcBase, srcDisp);
7244 }
7245
7246 /**
7247 * Generate a register--register-offset CMP. That is,
7248 * <PRE>
7249 * dstReg == [srcIndex<<srcScale + srcDisp]
7250 * </PRE>
7251 *
7252 * @param dstReg the destination register
7253 * @param srcIndex the source index register
7254 * @param srcScale the source shift amount
7255 * @param srcDisp the source displacement
7256 */
7257 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7258 public final void emitCMP_Reg_RegOff(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
7259 int miStart = mi;
7260 // no group 1 to 4 prefix byte
7261 generateREXprefix(false, dstReg, srcIndex, null);
7262 // single byte opcode
7263 setMachineCodes(mi++, (byte) 0x3B);
7264 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
7265 if (lister != null) lister.RRFD(miStart, "CMP", dstReg, srcIndex, srcScale, srcDisp);
7266 }
7267
7268 /**
7269 * Generate a register--register-offset CMP. That is,
7270 * <PRE>
7271 * dstReg == [srcDisp]
7272 * </PRE>
7273 *
7274 * @param dstReg the destination register
7275 * @param srcDisp the source displacement
7276 */
7277 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
7278 public final void emitCMP_Reg_Abs(GPR dstReg, Address srcDisp) {
7279 int miStart = mi;
7280 // no group 1 to 4 prefix byte
7281 generateREXprefix(false, dstReg, null, null);
7282 // single byte opcode
7283 setMachineCodes(mi++, (byte) 0x3B);
7284 emitAbsRegOperands(srcDisp, dstReg);
7285 if (lister != null) lister.RRA(miStart, "CMP", dstReg, srcDisp);
7286 }
7287
7288 /**
7289 * Generate a register--register-offset CMP. That is,
7290 * <PRE>
7291 * dstReg == [srcBase + srcIndex<<srcScale + srcDisp]
7292 * </PRE>
7293 *
7294 * @param dstReg the destination register
7295 * @param srcBase the source base register
7296 * @param srcIndex the source index register
7297 * @param srcScale the source shift amount
7298 * @param srcDisp the source displacement
7299 */
7300 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
7301 public final void emitCMP_Reg_RegIdx(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
7302 int miStart = mi;
7303 // no group 1 to 4 prefix byte
7304 generateREXprefix(false, dstReg, srcIndex, srcBase);
7305 // single byte opcode
7306 setMachineCodes(mi++, (byte) 0x3B);
7307 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
7308 if (lister != null) lister.RRXD(miStart, "CMP", dstReg, srcBase, srcIndex, srcScale, srcDisp);
7309 }
7310
7311 /**
7312 * Generate a register--register(indirect) CMP. That is,
7313 * <PRE>
7314 * dstReg == [srcBase]
7315 * </PRE>
7316 *
7317 * @param dstReg the destination register
7318 * @param srcBase the source base register
7319 */
7320 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7321 public final void emitCMP_Reg_RegInd(GPR dstReg, GPR srcBase) {
7322 int miStart = mi;
7323 // no group 1 to 4 prefix byte
7324 generateREXprefix(false, dstReg, null, srcBase);
7325 // single byte opcode
7326 setMachineCodes(mi++, (byte) 0x3B);
7327 emitRegIndirectRegOperands(srcBase, dstReg);
7328 if (lister != null) lister.RRN(miStart, "CMP", dstReg, srcBase);
7329 }
7330
7331 /**
7332 * Generate a register(indirect)--register CMP. That is,
7333 * <PRE>
7334 * [dstBase] == (word) srcReg
7335 * </PRE>
7336 *
7337 * @param dstBase the destination base
7338 * @param srcReg the source register
7339 */
7340 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7341 public final void emitCMP_RegInd_Reg_Word(GPR dstBase, GPR srcReg) {
7342 int miStart = mi;
7343 setMachineCodes(mi++, (byte) 0x66);
7344 generateREXprefix(false, srcReg, null, dstBase);
7345 // single byte opcode
7346 setMachineCodes(mi++, (byte) 0x39);
7347 emitRegIndirectRegOperands(dstBase, srcReg);
7348 if (lister != null) lister.RNR(miStart, "CMP", dstBase, srcReg);
7349 }
7350
7351 /**
7352 * Generate a register-offset--register CMP. That is,
7353 * <PRE>
7354 * [dstReg<<dstScale + dstDisp] == (word) srcReg
7355 * </PRE>
7356 *
7357 * @param dstIndex the destination index register
7358 * @param dstScale the destination shift amount
7359 * @param dstDisp the destination displacement
7360 * @param srcReg the source register
7361 */
7362 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
7363 public final void emitCMP_RegOff_Reg_Word(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
7364 int miStart = mi;
7365 setMachineCodes(mi++, (byte) 0x66);
7366 generateREXprefix(false, srcReg, dstIndex, null);
7367 // single byte opcode
7368 setMachineCodes(mi++, (byte) 0x39);
7369 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
7370 if (lister != null) lister.RFDR(miStart, "CMP", dstIndex, dstScale, dstDisp, srcReg);
7371 }
7372
7373 /**
7374 * Generate a absolute--register CMP. That is,
7375 * <PRE>
7376 * [dstDisp] == (word) srcReg
7377 * </PRE>
7378 *
7379 * @param dstDisp the destination address
7380 * @param srcReg the source register
7381 */
7382 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
7383 public final void emitCMP_Abs_Reg_Word(Address dstDisp, GPR srcReg) {
7384 int miStart = mi;
7385 setMachineCodes(mi++, (byte) 0x66);
7386 generateREXprefix(false, srcReg, null, null);
7387 // single byte opcode
7388 setMachineCodes(mi++, (byte) 0x39);
7389 emitAbsRegOperands(dstDisp, srcReg);
7390 if (lister != null) lister.RAR(miStart, "CMP", dstDisp, srcReg);
7391 }
7392
7393 /**
7394 * Generate a register-index--register CMP. That is,
7395 * <PRE>
7396 * [dstBase + dstIndex<<dstScale + dstDisp] == (word) srcReg
7397 * </PRE>
7398 *
7399 * @param dstBase the base register
7400 * @param dstIndex the destination index register
7401 * @param dstScale the destination shift amount
7402 * @param dstDisp the destination displacement
7403 * @param srcReg the source register
7404 */
7405 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
7406 public final void emitCMP_RegIdx_Reg_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
7407 int miStart = mi;
7408 setMachineCodes(mi++, (byte) 0x66);
7409 generateREXprefix(false, srcReg, dstIndex, dstBase);
7410 // single byte opcode
7411 setMachineCodes(mi++, (byte) 0x39);
7412 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
7413 if (lister != null) lister.RXDR(miStart, "CMP", dstBase, dstIndex, dstScale, dstDisp, srcReg);
7414 }
7415
7416 /**
7417 * Generate a register-displacement--register CMP. That is,
7418 * <PRE>
7419 * [dstBase + dstDisp] == (word) srcReg
7420 * </PRE>
7421 *
7422 * @param dstBase the base register
7423 * @param dstDisp the destination displacement
7424 * @param srcReg the source register
7425 */
7426 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
7427 public final void emitCMP_RegDisp_Reg_Word(GPR dstBase, Offset dstDisp, GPR srcReg) {
7428 int miStart = mi;
7429 setMachineCodes(mi++, (byte) 0x66);
7430 generateREXprefix(false, srcReg, null, dstBase);
7431 // single byte opcode
7432 setMachineCodes(mi++, (byte) 0x39);
7433 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
7434 if (lister != null) lister.RDR(miStart, "CMP", dstBase, dstDisp, srcReg);
7435 }
7436
7437 /**
7438 * Generate a register--register CMP. That is,
7439 * <PRE>
7440 * dstReg == (word) srcReg
7441 * </PRE>
7442 *
7443 * @param dstReg the destination register
7444 * @param srcReg the source register
7445 */
7446 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7447 public final void emitCMP_Reg_Reg_Word(GPR dstReg, GPR srcReg) {
7448 int miStart = mi;
7449 setMachineCodes(mi++, (byte) 0x66);
7450 generateREXprefix(false, srcReg, null, dstReg);
7451 // single byte opcode
7452 setMachineCodes(mi++, (byte) 0x39);
7453 emitRegRegOperands(dstReg, srcReg);
7454 if (lister != null) lister.RR(miStart, "CMP", dstReg, srcReg);
7455 }
7456
7457 /**
7458 * Generate a register--register-displacement CMP. That is,
7459 * <PRE>
7460 * dstReg == (word) [srcReg + srcDisp]
7461 * </PRE>
7462 *
7463 * @param dstReg the destination register
7464 * @param srcBase the source register
7465 * @param srcDisp the source displacement
7466 */
7467 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7468 public final void emitCMP_Reg_RegDisp_Word(GPR dstReg, GPR srcBase, Offset srcDisp) {
7469 int miStart = mi;
7470 setMachineCodes(mi++, (byte) 0x66);
7471 generateREXprefix(false, dstReg, null, srcBase);
7472 // single byte opcode
7473 setMachineCodes(mi++, (byte) 0x3B);
7474 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
7475 if (lister != null) lister.RRD(miStart, "CMP", dstReg, srcBase, srcDisp);
7476 }
7477
7478 /**
7479 * Generate a register--register-offset CMP. That is,
7480 * <PRE>
7481 * dstReg == (word) [srcIndex<<srcScale + srcDisp]
7482 * </PRE>
7483 *
7484 * @param dstReg the destination register
7485 * @param srcIndex the source index register
7486 * @param srcScale the source shift amount
7487 * @param srcDisp the source displacement
7488 */
7489 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7490 public final void emitCMP_Reg_RegOff_Word(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
7491 int miStart = mi;
7492 setMachineCodes(mi++, (byte) 0x66);
7493 generateREXprefix(false, dstReg, srcIndex, null);
7494 // single byte opcode
7495 setMachineCodes(mi++, (byte) 0x3B);
7496 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
7497 if (lister != null) lister.RRFD(miStart, "CMP", dstReg, srcIndex, srcScale, srcDisp);
7498 }
7499
7500 /**
7501 * Generate a register--register-offset CMP. That is,
7502 * <PRE>
7503 * dstReg == (word) [srcDisp]
7504 * </PRE>
7505 *
7506 * @param dstReg the destination register
7507 * @param srcDisp the source displacement
7508 */
7509 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
7510 public final void emitCMP_Reg_Abs_Word(GPR dstReg, Address srcDisp) {
7511 int miStart = mi;
7512 setMachineCodes(mi++, (byte) 0x66);
7513 generateREXprefix(false, dstReg, null, null);
7514 // single byte opcode
7515 setMachineCodes(mi++, (byte) 0x3B);
7516 emitAbsRegOperands(srcDisp, dstReg);
7517 if (lister != null) lister.RRA(miStart, "CMP", dstReg, srcDisp);
7518 }
7519
7520 /**
7521 * Generate a register--register-offset CMP. That is,
7522 * <PRE>
7523 * dstReg == (word) [srcBase + srcIndex<<srcScale + srcDisp]
7524 * </PRE>
7525 *
7526 * @param dstReg the destination register
7527 * @param srcBase the source base register
7528 * @param srcIndex the source index register
7529 * @param srcScale the source shift amount
7530 * @param srcDisp the source displacement
7531 */
7532 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
7533 public final void emitCMP_Reg_RegIdx_Word(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
7534 int miStart = mi;
7535 setMachineCodes(mi++, (byte) 0x66);
7536 generateREXprefix(false, dstReg, srcIndex, srcBase);
7537 // single byte opcode
7538 setMachineCodes(mi++, (byte) 0x3B);
7539 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
7540 if (lister != null) lister.RRXD(miStart, "CMP", dstReg, srcBase, srcIndex, srcScale, srcDisp);
7541 }
7542
7543 /**
7544 * Generate a register--register(indirect) CMP. That is,
7545 * <PRE>
7546 * dstReg == (word) [srcBase]
7547 * </PRE>
7548 *
7549 * @param dstReg the destination register
7550 * @param srcBase the source base register
7551 */
7552 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7553 public final void emitCMP_Reg_RegInd_Word(GPR dstReg, GPR srcBase) {
7554 int miStart = mi;
7555 setMachineCodes(mi++, (byte) 0x66);
7556 generateREXprefix(false, dstReg, null, srcBase);
7557 // single byte opcode
7558 setMachineCodes(mi++, (byte) 0x3B);
7559 emitRegIndirectRegOperands(srcBase, dstReg);
7560 if (lister != null) lister.RRN(miStart, "CMP", dstReg, srcBase);
7561 }
7562
7563 /**
7564 * Generate a register(indirect)--register CMP. That is,
7565 * <PRE>
7566 * [dstBase] == (quad) srcReg
7567 * </PRE>
7568 *
7569 * @param dstBase the destination base
7570 * @param srcReg the source register
7571 */
7572 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7573 public final void emitCMP_RegInd_Reg_Quad(GPR dstBase, GPR srcReg) {
7574 int miStart = mi;
7575 // no group 1 to 4 prefix byte
7576 generateREXprefix(true, srcReg, null, dstBase);
7577 // single byte opcode
7578 setMachineCodes(mi++, (byte) 0x39);
7579 emitRegIndirectRegOperands(dstBase, srcReg);
7580 if (lister != null) lister.RNR(miStart, "CMP", dstBase, srcReg);
7581 }
7582
7583 /**
7584 * Generate a register-offset--register CMP. That is,
7585 * <PRE>
7586 * [dstReg<<dstScale + dstDisp] == (quad) srcReg
7587 * </PRE>
7588 *
7589 * @param dstIndex the destination index register
7590 * @param dstScale the destination shift amount
7591 * @param dstDisp the destination displacement
7592 * @param srcReg the source register
7593 */
7594 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
7595 public final void emitCMP_RegOff_Reg_Quad(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
7596 int miStart = mi;
7597 // no group 1 to 4 prefix byte
7598 generateREXprefix(true, srcReg, dstIndex, null);
7599 // single byte opcode
7600 setMachineCodes(mi++, (byte) 0x39);
7601 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
7602 if (lister != null) lister.RFDR(miStart, "CMP", dstIndex, dstScale, dstDisp, srcReg);
7603 }
7604
7605 /**
7606 * Generate a absolute--register CMP. That is,
7607 * <PRE>
7608 * [dstDisp] == (quad) srcReg
7609 * </PRE>
7610 *
7611 * @param dstDisp the destination address
7612 * @param srcReg the source register
7613 */
7614 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
7615 public final void emitCMP_Abs_Reg_Quad(Address dstDisp, GPR srcReg) {
7616 int miStart = mi;
7617 // no group 1 to 4 prefix byte
7618 generateREXprefix(true, srcReg, null, null);
7619 // single byte opcode
7620 setMachineCodes(mi++, (byte) 0x39);
7621 emitAbsRegOperands(dstDisp, srcReg);
7622 if (lister != null) lister.RAR(miStart, "CMP", dstDisp, srcReg);
7623 }
7624
7625 /**
7626 * Generate a register-index--register CMP. That is,
7627 * <PRE>
7628 * [dstBase + dstIndex<<dstScale + dstDisp] == (quad) srcReg
7629 * </PRE>
7630 *
7631 * @param dstBase the base register
7632 * @param dstIndex the destination index register
7633 * @param dstScale the destination shift amount
7634 * @param dstDisp the destination displacement
7635 * @param srcReg the source register
7636 */
7637 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
7638 public final void emitCMP_RegIdx_Reg_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
7639 int miStart = mi;
7640 // no group 1 to 4 prefix byte
7641 generateREXprefix(true, srcReg, dstIndex, dstBase);
7642 // single byte opcode
7643 setMachineCodes(mi++, (byte) 0x39);
7644 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
7645 if (lister != null) lister.RXDR(miStart, "CMP", dstBase, dstIndex, dstScale, dstDisp, srcReg);
7646 }
7647
7648 /**
7649 * Generate a register-displacement--register CMP. That is,
7650 * <PRE>
7651 * [dstBase + dstDisp] == (quad) srcReg
7652 * </PRE>
7653 *
7654 * @param dstBase the base register
7655 * @param dstDisp the destination displacement
7656 * @param srcReg the source register
7657 */
7658 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
7659 public final void emitCMP_RegDisp_Reg_Quad(GPR dstBase, Offset dstDisp, GPR srcReg) {
7660 int miStart = mi;
7661 // no group 1 to 4 prefix byte
7662 generateREXprefix(true, srcReg, null, dstBase);
7663 // single byte opcode
7664 setMachineCodes(mi++, (byte) 0x39);
7665 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
7666 if (lister != null) lister.RDR(miStart, "CMP", dstBase, dstDisp, srcReg);
7667 }
7668
7669 /**
7670 * Generate a register--register CMP. That is,
7671 * <PRE>
7672 * dstReg == (quad) srcReg
7673 * </PRE>
7674 *
7675 * @param dstReg the destination register
7676 * @param srcReg the source register
7677 */
7678 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7679 public final void emitCMP_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
7680 int miStart = mi;
7681 // no group 1 to 4 prefix byte
7682 generateREXprefix(true, srcReg, null, dstReg);
7683 // single byte opcode
7684 setMachineCodes(mi++, (byte) 0x39);
7685 emitRegRegOperands(dstReg, srcReg);
7686 if (lister != null) lister.RR(miStart, "CMP", dstReg, srcReg);
7687 }
7688
7689 /**
7690 * Generate a register--register-displacement CMP. That is,
7691 * <PRE>
7692 * dstReg == (quad) [srcReg + srcDisp]
7693 * </PRE>
7694 *
7695 * @param dstReg the destination register
7696 * @param srcBase the source register
7697 * @param srcDisp the source displacement
7698 */
7699 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7700 public final void emitCMP_Reg_RegDisp_Quad(GPR dstReg, GPR srcBase, Offset srcDisp) {
7701 int miStart = mi;
7702 // no group 1 to 4 prefix byte
7703 generateREXprefix(true, dstReg, null, srcBase);
7704 // single byte opcode
7705 setMachineCodes(mi++, (byte) 0x3B);
7706 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
7707 if (lister != null) lister.RRD(miStart, "CMP", dstReg, srcBase, srcDisp);
7708 }
7709
7710 /**
7711 * Generate a register--register-offset CMP. That is,
7712 * <PRE>
7713 * dstReg == (quad) [srcIndex<<srcScale + srcDisp]
7714 * </PRE>
7715 *
7716 * @param dstReg the destination register
7717 * @param srcIndex the source index register
7718 * @param srcScale the source shift amount
7719 * @param srcDisp the source displacement
7720 */
7721 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7722 public final void emitCMP_Reg_RegOff_Quad(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
7723 int miStart = mi;
7724 // no group 1 to 4 prefix byte
7725 generateREXprefix(true, dstReg, srcIndex, null);
7726 // single byte opcode
7727 setMachineCodes(mi++, (byte) 0x3B);
7728 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
7729 if (lister != null) lister.RRFD(miStart, "CMP", dstReg, srcIndex, srcScale, srcDisp);
7730 }
7731
7732 /**
7733 * Generate a register--register-offset CMP. That is,
7734 * <PRE>
7735 * dstReg == (quad) [srcDisp]
7736 * </PRE>
7737 *
7738 * @param dstReg the destination register
7739 * @param srcDisp the source displacement
7740 */
7741 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
7742 public final void emitCMP_Reg_Abs_Quad(GPR dstReg, Address srcDisp) {
7743 int miStart = mi;
7744 // no group 1 to 4 prefix byte
7745 generateREXprefix(true, dstReg, null, null);
7746 // single byte opcode
7747 setMachineCodes(mi++, (byte) 0x3B);
7748 emitAbsRegOperands(srcDisp, dstReg);
7749 if (lister != null) lister.RRA(miStart, "CMP", dstReg, srcDisp);
7750 }
7751
7752 /**
7753 * Generate a register--register-offset CMP. That is,
7754 * <PRE>
7755 * dstReg == (quad) [srcBase + srcIndex<<srcScale + srcDisp]
7756 * </PRE>
7757 *
7758 * @param dstReg the destination register
7759 * @param srcBase the source base register
7760 * @param srcIndex the source index register
7761 * @param srcScale the source shift amount
7762 * @param srcDisp the source displacement
7763 */
7764 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
7765 public final void emitCMP_Reg_RegIdx_Quad(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
7766 int miStart = mi;
7767 // no group 1 to 4 prefix byte
7768 generateREXprefix(true, dstReg, srcIndex, srcBase);
7769 // single byte opcode
7770 setMachineCodes(mi++, (byte) 0x3B);
7771 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
7772 if (lister != null) lister.RRXD(miStart, "CMP", dstReg, srcBase, srcIndex, srcScale, srcDisp);
7773 }
7774
7775 /**
7776 * Generate a register--register(indirect) CMP. That is,
7777 * <PRE>
7778 * dstReg == (quad) [srcBase]
7779 * </PRE>
7780 *
7781 * @param dstReg the destination register
7782 * @param srcBase the source base register
7783 */
7784 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7785 public final void emitCMP_Reg_RegInd_Quad(GPR dstReg, GPR srcBase) {
7786 int miStart = mi;
7787 // no group 1 to 4 prefix byte
7788 generateREXprefix(true, dstReg, null, srcBase);
7789 // single byte opcode
7790 setMachineCodes(mi++, (byte) 0x3B);
7791 emitRegIndirectRegOperands(srcBase, dstReg);
7792 if (lister != null) lister.RRN(miStart, "CMP", dstReg, srcBase);
7793 }
7794
7795 /**
7796 * Generate a register(indirect)--register CMP. That is,
7797 * <PRE>
7798 * [dstBase] == (byte) srcReg
7799 * </PRE>
7800 *
7801 * @param dstBase the destination base
7802 * @param srcReg the source register
7803 */
7804 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7805 public final void emitCMP_RegInd_Reg_Byte(GPR dstBase, GPR srcReg) {
7806 int miStart = mi;
7807 // no group 1 to 4 prefix byte
7808 generateREXprefix(false, srcReg, null, dstBase);
7809 // single byte opcode
7810 setMachineCodes(mi++, (byte) 0x38);
7811 emitRegIndirectRegOperands(dstBase, srcReg);
7812 if (lister != null) lister.RNR(miStart, "CMP", dstBase, srcReg);
7813 }
7814
7815 /**
7816 * Generate a register-offset--register CMP. That is,
7817 * <PRE>
7818 * [dstReg<<dstScale + dstDisp] == (byte) srcReg
7819 * </PRE>
7820 *
7821 * @param dstIndex the destination index register
7822 * @param dstScale the destination shift amount
7823 * @param dstDisp the destination displacement
7824 * @param srcReg the source register
7825 */
7826 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
7827 public final void emitCMP_RegOff_Reg_Byte(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
7828 int miStart = mi;
7829 // no group 1 to 4 prefix byte
7830 generateREXprefix(false, srcReg, dstIndex, null);
7831 // single byte opcode
7832 setMachineCodes(mi++, (byte) 0x38);
7833 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
7834 if (lister != null) lister.RFDR(miStart, "CMP", dstIndex, dstScale, dstDisp, srcReg);
7835 }
7836
7837 /**
7838 * Generate a absolute--register CMP. That is,
7839 * <PRE>
7840 * [dstDisp] == (byte) srcReg
7841 * </PRE>
7842 *
7843 * @param dstDisp the destination address
7844 * @param srcReg the source register
7845 */
7846 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
7847 public final void emitCMP_Abs_Reg_Byte(Address dstDisp, GPR srcReg) {
7848 int miStart = mi;
7849 // no group 1 to 4 prefix byte
7850 generateREXprefix(false, srcReg, null, null);
7851 // single byte opcode
7852 setMachineCodes(mi++, (byte) 0x38);
7853 emitAbsRegOperands(dstDisp, srcReg);
7854 if (lister != null) lister.RAR(miStart, "CMP", dstDisp, srcReg);
7855 }
7856
7857 /**
7858 * Generate a register-index--register CMP. That is,
7859 * <PRE>
7860 * [dstBase + dstIndex<<dstScale + dstDisp] == (byte) srcReg
7861 * </PRE>
7862 *
7863 * @param dstBase the base register
7864 * @param dstIndex the destination index register
7865 * @param dstScale the destination shift amount
7866 * @param dstDisp the destination displacement
7867 * @param srcReg the source register
7868 */
7869 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
7870 public final void emitCMP_RegIdx_Reg_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
7871 int miStart = mi;
7872 // no group 1 to 4 prefix byte
7873 generateREXprefix(false, srcReg, dstIndex, dstBase);
7874 // single byte opcode
7875 setMachineCodes(mi++, (byte) 0x38);
7876 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
7877 if (lister != null) lister.RXDR(miStart, "CMP", dstBase, dstIndex, dstScale, dstDisp, srcReg);
7878 }
7879
7880 /**
7881 * Generate a register-displacement--register CMP. That is,
7882 * <PRE>
7883 * [dstBase + dstDisp] == (byte) srcReg
7884 * </PRE>
7885 *
7886 * @param dstBase the base register
7887 * @param dstDisp the destination displacement
7888 * @param srcReg the source register
7889 */
7890 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
7891 public final void emitCMP_RegDisp_Reg_Byte(GPR dstBase, Offset dstDisp, GPR srcReg) {
7892 int miStart = mi;
7893 // no group 1 to 4 prefix byte
7894 generateREXprefix(false, srcReg, null, dstBase);
7895 // single byte opcode
7896 setMachineCodes(mi++, (byte) 0x38);
7897 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
7898 if (lister != null) lister.RDR(miStart, "CMP", dstBase, dstDisp, srcReg);
7899 }
7900
7901 /**
7902 * Generate a register--register CMP. That is,
7903 * <PRE>
7904 * dstReg == (byte) srcReg
7905 * </PRE>
7906 *
7907 * @param dstReg the destination register
7908 * @param srcReg the source register
7909 */
7910 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7911 public final void emitCMP_Reg_Reg_Byte(GPR dstReg, GPR srcReg) {
7912 int miStart = mi;
7913 // no group 1 to 4 prefix byte
7914 generateREXprefix(false, srcReg, null, dstReg);
7915 // single byte opcode
7916 setMachineCodes(mi++, (byte) 0x38);
7917 emitRegRegOperands(dstReg, srcReg);
7918 if (lister != null) lister.RR(miStart, "CMP", dstReg, srcReg);
7919 }
7920
7921 /**
7922 * Generate a register--register-displacement CMP. That is,
7923 * <PRE>
7924 * dstReg == (byte) [srcReg + srcDisp]
7925 * </PRE>
7926 *
7927 * @param dstReg the destination register
7928 * @param srcBase the source register
7929 * @param srcDisp the source displacement
7930 */
7931 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7932 public final void emitCMP_Reg_RegDisp_Byte(GPR dstReg, GPR srcBase, Offset srcDisp) {
7933 int miStart = mi;
7934 // no group 1 to 4 prefix byte
7935 generateREXprefix(false, dstReg, null, srcBase);
7936 // single byte opcode
7937 setMachineCodes(mi++, (byte) 0x3A);
7938 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
7939 if (lister != null) lister.RRD(miStart, "CMP", dstReg, srcBase, srcDisp);
7940 }
7941
7942 /**
7943 * Generate a register--register-offset CMP. That is,
7944 * <PRE>
7945 * dstReg == (byte) [srcIndex<<srcScale + srcDisp]
7946 * </PRE>
7947 *
7948 * @param dstReg the destination register
7949 * @param srcIndex the source index register
7950 * @param srcScale the source shift amount
7951 * @param srcDisp the source displacement
7952 */
7953 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
7954 public final void emitCMP_Reg_RegOff_Byte(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
7955 int miStart = mi;
7956 // no group 1 to 4 prefix byte
7957 generateREXprefix(false, dstReg, srcIndex, null);
7958 // single byte opcode
7959 setMachineCodes(mi++, (byte) 0x3A);
7960 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
7961 if (lister != null) lister.RRFD(miStart, "CMP", dstReg, srcIndex, srcScale, srcDisp);
7962 }
7963
7964 /**
7965 * Generate a register--register-offset CMP. That is,
7966 * <PRE>
7967 * dstReg == (byte) [srcDisp]
7968 * </PRE>
7969 *
7970 * @param dstReg the destination register
7971 * @param srcDisp the source displacement
7972 */
7973 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
7974 public final void emitCMP_Reg_Abs_Byte(GPR dstReg, Address srcDisp) {
7975 int miStart = mi;
7976 // no group 1 to 4 prefix byte
7977 generateREXprefix(false, dstReg, null, null);
7978 // single byte opcode
7979 setMachineCodes(mi++, (byte) 0x3A);
7980 emitAbsRegOperands(srcDisp, dstReg);
7981 if (lister != null) lister.RRA(miStart, "CMP", dstReg, srcDisp);
7982 }
7983
7984 /**
7985 * Generate a register--register-offset CMP. That is,
7986 * <PRE>
7987 * dstReg == (byte) [srcBase + srcIndex<<srcScale + srcDisp]
7988 * </PRE>
7989 *
7990 * @param dstReg the destination register
7991 * @param srcBase the source base register
7992 * @param srcIndex the source index register
7993 * @param srcScale the source shift amount
7994 * @param srcDisp the source displacement
7995 */
7996 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
7997 public final void emitCMP_Reg_RegIdx_Byte(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
7998 int miStart = mi;
7999 // no group 1 to 4 prefix byte
8000 generateREXprefix(false, dstReg, srcIndex, srcBase);
8001 // single byte opcode
8002 setMachineCodes(mi++, (byte) 0x3A);
8003 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
8004 if (lister != null) lister.RRXD(miStart, "CMP", dstReg, srcBase, srcIndex, srcScale, srcDisp);
8005 }
8006
8007 /**
8008 * Generate a register--register(indirect) CMP. That is,
8009 * <PRE>
8010 * dstReg == (byte) [srcBase]
8011 * </PRE>
8012 *
8013 * @param dstReg the destination register
8014 * @param srcBase the source base register
8015 */
8016 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
8017 public final void emitCMP_Reg_RegInd_Byte(GPR dstReg, GPR srcBase) {
8018 int miStart = mi;
8019 // no group 1 to 4 prefix byte
8020 generateREXprefix(false, dstReg, null, srcBase);
8021 // single byte opcode
8022 setMachineCodes(mi++, (byte) 0x3A);
8023 emitRegIndirectRegOperands(srcBase, dstReg);
8024 if (lister != null) lister.RRN(miStart, "CMP", dstReg, srcBase);
8025 }
8026
8027 /**
8028 * Generate a register--immediate CMP. That is,
8029 * <PRE>
8030 * dstReg == imm
8031 * </PRE>
8032 *
8033 * @param dstReg the destination register
8034 * @param imm immediate
8035 */
8036 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
8037 public final void emitCMP_Reg_Imm(GPR dstReg, int imm) {
8038 int miStart = mi;
8039 // no group 1 to 4 prefix byte
8040 generateREXprefix(false, null, null, dstReg);
8041 // single byte opcode
8042 if (fits(imm,8)) {
8043 setMachineCodes(mi++, (byte) 0x83);
8044 // "register 0x7" is really part of the opcode
8045 emitRegRegOperands(dstReg, GPR.getForOpcode(0x7));
8046 emitImm8((byte)imm);
8047 } else if (dstReg == EAX) {
8048 setMachineCodes(mi++, (byte) 0x3D);
8049 emitImm32(imm);
8050 } else {
8051 setMachineCodes(mi++, (byte) 0x81);
8052 // "register 0x7" is really part of the opcode
8053 emitRegRegOperands(dstReg, GPR.getForOpcode(0x7));
8054 emitImm32(imm);
8055 }
8056 if (lister != null) lister.RI(miStart, "CMP", dstReg, imm);
8057 }
8058
8059 /**
8060 * Generate a register-displacement--immediate CMP. That is,
8061 * <PRE>
8062 * [dstBase + dstDisp] == imm
8063 * </PRE>
8064 *
8065 * @param dstBase the destination register
8066 * @param dstDisp the destination displacement
8067 * @param imm immediate
8068 */
8069 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
8070 public final void emitCMP_RegDisp_Imm(GPR dstBase, Offset dstDisp, int imm) {
8071 int miStart = mi;
8072 // no group 1 to 4 prefix byte
8073 generateREXprefix(false, null, null, dstBase);
8074 // single byte opcode
8075 if (fits(imm,8)) {
8076 setMachineCodes(mi++, (byte) 0x83);
8077 // "register 0x7" is really part of the opcode
8078 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x7));
8079 emitImm8((byte)imm);
8080 } else {
8081 setMachineCodes(mi++, (byte) 0x81);
8082 // "register 0x7" is really part of the opcode
8083 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x7));
8084 emitImm32(imm);
8085 }
8086 if (lister != null) lister.RDI(miStart, "CMP", dstBase, dstDisp, imm);
8087 }
8088
8089 /**
8090 * Generate a register-offset--immediate CMP. That is,
8091 * <PRE>
8092 * [dstIndex<<dstScale + dstDisp] == imm
8093 * </PRE>
8094 *
8095 * @param dstIndex the destination index register
8096 * @param dstScale the destination shift amount
8097 * @param dstDisp the destination displacement
8098 * @param imm immediate
8099 */
8100 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
8101 public final void emitCMP_RegOff_Imm(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
8102 int miStart = mi;
8103 // no group 1 to 4 prefix byte
8104 generateREXprefix(false, null, dstIndex, null);
8105 // single byte opcode
8106 if (fits(imm,8)) {
8107 setMachineCodes(mi++, (byte) 0x83);
8108 // "register 0x7" is really part of the opcode
8109 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
8110 emitImm8((byte)imm);
8111 } else {
8112 setMachineCodes(mi++, (byte) 0x81);
8113 // "register 0x7" is really part of the opcode
8114 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
8115 emitImm32(imm);
8116 }
8117 if (lister != null) lister.RFDI(miStart, "CMP", dstIndex, dstScale, dstDisp, imm);
8118 }
8119
8120 /**
8121 * Generate a absolute--immediate CMP. That is,
8122 * <PRE>
8123 * [dstDisp] == imm
8124 * </PRE>
8125 *
8126 * @param dstDisp the destination displacement
8127 * @param imm immediate
8128 */
8129 public final void emitCMP_Abs_Imm(Address dstDisp, int imm) {
8130 int miStart = mi;
8131 // no group 1 to 4 prefix byte
8132 generateREXprefix(false, null, null, null);
8133 // single byte opcode
8134 if (fits(imm,8)) {
8135 setMachineCodes(mi++, (byte) 0x83);
8136 // "register 0x7" is really part of the opcode
8137 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x7));
8138 emitImm8((byte)imm);
8139 } else {
8140 setMachineCodes(mi++, (byte) 0x81);
8141 // "register 0x7" is really part of the opcode
8142 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x7));
8143 emitImm32(imm);
8144 }
8145 if (lister != null) lister.RAI(miStart, "CMP", dstDisp, imm);
8146 }
8147
8148 /**
8149 * Generate a register-index--immediate CMP. That is,
8150 * <PRE>
8151 * [dstBase + dstIndex<<dstScale + dstDisp] == imm
8152 * </PRE>
8153 *
8154 * @param dstBase the destination base register
8155 * @param dstIndex the destination index register
8156 * @param dstScale the destination shift amount
8157 * @param dstDisp the destination displacement
8158 * @param imm immediate
8159 */
8160 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
8161 public final void emitCMP_RegIdx_Imm(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
8162 int miStart = mi;
8163 // no group 1 to 4 prefix byte
8164 generateREXprefix(false, null, dstIndex, dstBase);
8165 // single byte opcode
8166 if (fits(imm,8)) {
8167 setMachineCodes(mi++, (byte) 0x83);
8168 // "register 0x7" is really part of the opcode
8169 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
8170 emitImm8((byte)imm);
8171 } else {
8172 setMachineCodes(mi++, (byte) 0x81);
8173 // "register 0x7" is really part of the opcode
8174 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
8175 emitImm32(imm);
8176 }
8177 if (lister != null) lister.RXDI(miStart, "CMP", dstBase, dstIndex, dstScale, dstDisp, imm);
8178 }
8179
8180 /**
8181 * Generate a register(indirect)--immediate CMP. That is,
8182 * <PRE>
8183 * [dstBase] == imm
8184 * </PRE>
8185 *
8186 * @param dstBase the destination base register
8187 * @param imm immediate
8188 */
8189 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
8190 public final void emitCMP_RegInd_Imm(GPR dstBase, int imm) {
8191 int miStart = mi;
8192 // no group 1 to 4 prefix byte
8193 generateREXprefix(false, null, null, dstBase);
8194 // single byte opcode
8195 if (fits(imm,8)) {
8196 setMachineCodes(mi++, (byte) 0x83);
8197 // "register 0x7" is really part of the opcode
8198 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x7));
8199 emitImm8((byte)imm);
8200 } else {
8201 setMachineCodes(mi++, (byte) 0x81);
8202 // "register 0x7" is really part of the opcode
8203 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x7));
8204 emitImm32(imm);
8205 }
8206 if (lister != null) lister.RNI(miStart, "CMP", dstBase, imm);
8207 }
8208
8209 /**
8210 * Generate a register--immediate CMP. That is,
8211 * <PRE>
8212 * dstReg == (word) imm
8213 * </PRE>
8214 *
8215 * @param dstReg the destination register
8216 * @param imm immediate
8217 */
8218 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
8219 public final void emitCMP_Reg_Imm_Word(GPR dstReg, int imm) {
8220 int miStart = mi;
8221 setMachineCodes(mi++, (byte) 0x66);
8222 generateREXprefix(false, null, null, dstReg);
8223 // single byte opcode
8224 if (fits(imm,8)) {
8225 setMachineCodes(mi++, (byte) 0x83);
8226 // "register 0x7" is really part of the opcode
8227 emitRegRegOperands(dstReg, GPR.getForOpcode(0x7));
8228 emitImm8((byte)imm);
8229 } else if (dstReg == EAX) {
8230 setMachineCodes(mi++, (byte) 0x3D);
8231 emitImm16(imm);
8232 } else {
8233 setMachineCodes(mi++, (byte) 0x81);
8234 // "register 0x7" is really part of the opcode
8235 emitRegRegOperands(dstReg, GPR.getForOpcode(0x7));
8236 emitImm16(imm);
8237 }
8238 if (lister != null) lister.RI(miStart, "CMP", dstReg, imm);
8239 }
8240
8241 /**
8242 * Generate a register-displacement--immediate CMP. That is,
8243 * <PRE>
8244 * [dstBase + dstDisp] == (word) imm
8245 * </PRE>
8246 *
8247 * @param dstBase the destination register
8248 * @param dstDisp the destination displacement
8249 * @param imm immediate
8250 */
8251 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
8252 public final void emitCMP_RegDisp_Imm_Word(GPR dstBase, Offset dstDisp, int imm) {
8253 int miStart = mi;
8254 setMachineCodes(mi++, (byte) 0x66);
8255 generateREXprefix(false, null, null, dstBase);
8256 // single byte opcode
8257 if (fits(imm,8)) {
8258 setMachineCodes(mi++, (byte) 0x83);
8259 // "register 0x7" is really part of the opcode
8260 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x7));
8261 emitImm8((byte)imm);
8262 } else {
8263 setMachineCodes(mi++, (byte) 0x81);
8264 // "register 0x7" is really part of the opcode
8265 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x7));
8266 emitImm16(imm);
8267 }
8268 if (lister != null) lister.RDI(miStart, "CMP", dstBase, dstDisp, imm);
8269 }
8270
8271 /**
8272 * Generate a register-offset--immediate CMP. That is,
8273 * <PRE>
8274 * [dstIndex<<dstScale + dstDisp] == (word) imm
8275 * </PRE>
8276 *
8277 * @param dstIndex the destination index register
8278 * @param dstScale the destination shift amount
8279 * @param dstDisp the destination displacement
8280 * @param imm immediate
8281 */
8282 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
8283 public final void emitCMP_RegOff_Imm_Word(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
8284 int miStart = mi;
8285 setMachineCodes(mi++, (byte) 0x66);
8286 generateREXprefix(false, null, dstIndex, null);
8287 // single byte opcode
8288 if (fits(imm,8)) {
8289 setMachineCodes(mi++, (byte) 0x83);
8290 // "register 0x7" is really part of the opcode
8291 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
8292 emitImm8((byte)imm);
8293 } else {
8294 setMachineCodes(mi++, (byte) 0x81);
8295 // "register 0x7" is really part of the opcode
8296 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
8297 emitImm16(imm);
8298 }
8299 if (lister != null) lister.RFDI(miStart, "CMP", dstIndex, dstScale, dstDisp, imm);
8300 }
8301
8302 /**
8303 * Generate a absolute--immediate CMP. That is,
8304 * <PRE>
8305 * [dstDisp] == (word) imm
8306 * </PRE>
8307 *
8308 * @param dstDisp the destination displacement
8309 * @param imm immediate
8310 */
8311 public final void emitCMP_Abs_Imm_Word(Address dstDisp, int imm) {
8312 int miStart = mi;
8313 setMachineCodes(mi++, (byte) 0x66);
8314 generateREXprefix(false, null, null, null);
8315 // single byte opcode
8316 if (fits(imm,8)) {
8317 setMachineCodes(mi++, (byte) 0x83);
8318 // "register 0x7" is really part of the opcode
8319 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x7));
8320 emitImm8((byte)imm);
8321 } else {
8322 setMachineCodes(mi++, (byte) 0x81);
8323 // "register 0x7" is really part of the opcode
8324 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x7));
8325 emitImm16(imm);
8326 }
8327 if (lister != null) lister.RAI(miStart, "CMP", dstDisp, imm);
8328 }
8329
8330 /**
8331 * Generate a register-index--immediate CMP. That is,
8332 * <PRE>
8333 * [dstBase + dstIndex<<dstScale + dstDisp] == (word) imm
8334 * </PRE>
8335 *
8336 * @param dstBase the destination base register
8337 * @param dstIndex the destination index register
8338 * @param dstScale the destination shift amount
8339 * @param dstDisp the destination displacement
8340 * @param imm immediate
8341 */
8342 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
8343 public final void emitCMP_RegIdx_Imm_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
8344 int miStart = mi;
8345 setMachineCodes(mi++, (byte) 0x66);
8346 generateREXprefix(false, null, dstIndex, dstBase);
8347 // single byte opcode
8348 if (fits(imm,8)) {
8349 setMachineCodes(mi++, (byte) 0x83);
8350 // "register 0x7" is really part of the opcode
8351 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
8352 emitImm8((byte)imm);
8353 } else {
8354 setMachineCodes(mi++, (byte) 0x81);
8355 // "register 0x7" is really part of the opcode
8356 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
8357 emitImm16(imm);
8358 }
8359 if (lister != null) lister.RXDI(miStart, "CMP", dstBase, dstIndex, dstScale, dstDisp, imm);
8360 }
8361
8362 /**
8363 * Generate a register(indirect)--immediate CMP. That is,
8364 * <PRE>
8365 * [dstBase] == (word) imm
8366 * </PRE>
8367 *
8368 * @param dstBase the destination base register
8369 * @param imm immediate
8370 */
8371 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
8372 public final void emitCMP_RegInd_Imm_Word(GPR dstBase, int imm) {
8373 int miStart = mi;
8374 setMachineCodes(mi++, (byte) 0x66);
8375 generateREXprefix(false, null, null, dstBase);
8376 // single byte opcode
8377 if (fits(imm,8)) {
8378 setMachineCodes(mi++, (byte) 0x83);
8379 // "register 0x7" is really part of the opcode
8380 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x7));
8381 emitImm8((byte)imm);
8382 } else {
8383 setMachineCodes(mi++, (byte) 0x81);
8384 // "register 0x7" is really part of the opcode
8385 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x7));
8386 emitImm16(imm);
8387 }
8388 if (lister != null) lister.RNI(miStart, "CMP", dstBase, imm);
8389 }
8390
8391 /**
8392 * Generate a register--immediate CMP. That is,
8393 * <PRE>
8394 * dstReg == (quad) imm
8395 * </PRE>
8396 *
8397 * @param dstReg the destination register
8398 * @param imm immediate
8399 */
8400 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
8401 public final void emitCMP_Reg_Imm_Quad(GPR dstReg, int imm) {
8402 int miStart = mi;
8403 // no group 1 to 4 prefix byte
8404 generateREXprefix(true, null, null, dstReg);
8405 // single byte opcode
8406 if (fits(imm,8)) {
8407 setMachineCodes(mi++, (byte) 0x83);
8408 // "register 0x7" is really part of the opcode
8409 emitRegRegOperands(dstReg, GPR.getForOpcode(0x7));
8410 emitImm8((byte)imm);
8411 } else if (dstReg == EAX) {
8412 setMachineCodes(mi++, (byte) 0x3D);
8413 emitImm32(imm);
8414 } else {
8415 setMachineCodes(mi++, (byte) 0x81);
8416 // "register 0x7" is really part of the opcode
8417 emitRegRegOperands(dstReg, GPR.getForOpcode(0x7));
8418 emitImm32(imm);
8419 }
8420 if (lister != null) lister.RI(miStart, "CMP", dstReg, imm);
8421 }
8422
8423 /**
8424 * Generate a register-displacement--immediate CMP. That is,
8425 * <PRE>
8426 * [dstBase + dstDisp] == (quad) imm
8427 * </PRE>
8428 *
8429 * @param dstBase the destination register
8430 * @param dstDisp the destination displacement
8431 * @param imm immediate
8432 */
8433 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
8434 public final void emitCMP_RegDisp_Imm_Quad(GPR dstBase, Offset dstDisp, int imm) {
8435 int miStart = mi;
8436 // no group 1 to 4 prefix byte
8437 generateREXprefix(true, null, null, dstBase);
8438 // single byte opcode
8439 if (fits(imm,8)) {
8440 setMachineCodes(mi++, (byte) 0x83);
8441 // "register 0x7" is really part of the opcode
8442 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x7));
8443 emitImm8((byte)imm);
8444 } else {
8445 setMachineCodes(mi++, (byte) 0x81);
8446 // "register 0x7" is really part of the opcode
8447 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x7));
8448 emitImm32(imm);
8449 }
8450 if (lister != null) lister.RDI(miStart, "CMP", dstBase, dstDisp, imm);
8451 }
8452
8453 /**
8454 * Generate a register-offset--immediate CMP. That is,
8455 * <PRE>
8456 * [dstIndex<<dstScale + dstDisp] == (quad) imm
8457 * </PRE>
8458 *
8459 * @param dstIndex the destination index register
8460 * @param dstScale the destination shift amount
8461 * @param dstDisp the destination displacement
8462 * @param imm immediate
8463 */
8464 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
8465 public final void emitCMP_RegOff_Imm_Quad(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
8466 int miStart = mi;
8467 // no group 1 to 4 prefix byte
8468 generateREXprefix(true, null, dstIndex, null);
8469 // single byte opcode
8470 if (fits(imm,8)) {
8471 setMachineCodes(mi++, (byte) 0x83);
8472 // "register 0x7" is really part of the opcode
8473 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
8474 emitImm8((byte)imm);
8475 } else {
8476 setMachineCodes(mi++, (byte) 0x81);
8477 // "register 0x7" is really part of the opcode
8478 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
8479 emitImm32(imm);
8480 }
8481 if (lister != null) lister.RFDI(miStart, "CMP", dstIndex, dstScale, dstDisp, imm);
8482 }
8483
8484 /**
8485 * Generate a absolute--immediate CMP. That is,
8486 * <PRE>
8487 * [dstDisp] == (quad) imm
8488 * </PRE>
8489 *
8490 * @param dstDisp the destination displacement
8491 * @param imm immediate
8492 */
8493 public final void emitCMP_Abs_Imm_Quad(Address dstDisp, int imm) {
8494 int miStart = mi;
8495 // no group 1 to 4 prefix byte
8496 generateREXprefix(true, null, null, null);
8497 // single byte opcode
8498 if (fits(imm,8)) {
8499 setMachineCodes(mi++, (byte) 0x83);
8500 // "register 0x7" is really part of the opcode
8501 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x7));
8502 emitImm8((byte)imm);
8503 } else {
8504 setMachineCodes(mi++, (byte) 0x81);
8505 // "register 0x7" is really part of the opcode
8506 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x7));
8507 emitImm32(imm);
8508 }
8509 if (lister != null) lister.RAI(miStart, "CMP", dstDisp, imm);
8510 }
8511
8512 /**
8513 * Generate a register-index--immediate CMP. That is,
8514 * <PRE>
8515 * [dstBase + dstIndex<<dstScale + dstDisp] == (quad) imm
8516 * </PRE>
8517 *
8518 * @param dstBase the destination base register
8519 * @param dstIndex the destination index register
8520 * @param dstScale the destination shift amount
8521 * @param dstDisp the destination displacement
8522 * @param imm immediate
8523 */
8524 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
8525 public final void emitCMP_RegIdx_Imm_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
8526 int miStart = mi;
8527 // no group 1 to 4 prefix byte
8528 generateREXprefix(true, null, dstIndex, dstBase);
8529 // single byte opcode
8530 if (fits(imm,8)) {
8531 setMachineCodes(mi++, (byte) 0x83);
8532 // "register 0x7" is really part of the opcode
8533 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
8534 emitImm8((byte)imm);
8535 } else {
8536 setMachineCodes(mi++, (byte) 0x81);
8537 // "register 0x7" is really part of the opcode
8538 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
8539 emitImm32(imm);
8540 }
8541 if (lister != null) lister.RXDI(miStart, "CMP", dstBase, dstIndex, dstScale, dstDisp, imm);
8542 }
8543
8544 /**
8545 * Generate a register(indirect)--immediate CMP. That is,
8546 * <PRE>
8547 * [dstBase] == (quad) imm
8548 * </PRE>
8549 *
8550 * @param dstBase the destination base register
8551 * @param imm immediate
8552 */
8553 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
8554 public final void emitCMP_RegInd_Imm_Quad(GPR dstBase, int imm) {
8555 int miStart = mi;
8556 // no group 1 to 4 prefix byte
8557 generateREXprefix(true, null, null, dstBase);
8558 // single byte opcode
8559 if (fits(imm,8)) {
8560 setMachineCodes(mi++, (byte) 0x83);
8561 // "register 0x7" is really part of the opcode
8562 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x7));
8563 emitImm8((byte)imm);
8564 } else {
8565 setMachineCodes(mi++, (byte) 0x81);
8566 // "register 0x7" is really part of the opcode
8567 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x7));
8568 emitImm32(imm);
8569 }
8570 if (lister != null) lister.RNI(miStart, "CMP", dstBase, imm);
8571 }
8572
8573 /**
8574 * Generate a register--immediate CMP. That is,
8575 * <PRE>
8576 * dstReg == (byte) imm
8577 * </PRE>
8578 *
8579 * @param dstReg the destination register
8580 * @param imm immediate
8581 */
8582 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
8583 public final void emitCMP_Reg_Imm_Byte(GPR dstReg, int imm) {
8584 int miStart = mi;
8585 if (dstReg == EAX) {
8586 setMachineCodes(mi++, (byte) 0x3C);
8587 emitImm8(imm);
8588 } else {
8589 generateREXprefix(false, null, null, dstReg);
8590 setMachineCodes(mi++, (byte) 0x80);
8591 // "register 0x7" is really part of the opcode
8592 emitRegRegOperands(dstReg, GPR.getForOpcode(0x7));
8593 emitImm8(imm);
8594 }
8595 if (lister != null) lister.RI(miStart, "CMP", dstReg, imm);
8596 }
8597
8598 /**
8599 * Generate a register-displacement--immediate CMP. That is,
8600 * <PRE>
8601 * [dstBase + dstDisp] == (byte) imm
8602 * </PRE>
8603 *
8604 * @param dstBase the destination register
8605 * @param dstDisp the destination displacement
8606 * @param imm immediate
8607 */
8608 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
8609 public final void emitCMP_RegDisp_Imm_Byte(GPR dstBase, Offset dstDisp, int imm) {
8610 int miStart = mi;
8611 generateREXprefix(false, null, null, dstBase);
8612 setMachineCodes(mi++, (byte) 0x80);
8613 // "register 0x7" is really part of the opcode
8614 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x7));
8615 emitImm8(imm);
8616 if (lister != null) lister.RDI(miStart, "CMP", dstBase, dstDisp, imm);
8617 }
8618
8619 /**
8620 * Generate a register-index--immediate CMP. That is,
8621 * <PRE>
8622 * [dstBase + dstIndex<<scale + dstDisp] == (byte) imm
8623 * </PRE>
8624 *
8625 * @param dstBase the destination base register
8626 * @param dstIndex the destination index register
8627 * @param dstScale the destination shift amount
8628 * @param dstDisp the destination displacement
8629 * @param imm immediate
8630 */
8631 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
8632 public final void emitCMP_RegIdx_Imm_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
8633 int miStart = mi;
8634 generateREXprefix(false, null, dstIndex, dstBase);
8635 setMachineCodes(mi++, (byte) 0x80);
8636 // "register 0x7" is really part of the opcode
8637 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
8638 emitImm8(imm);
8639 if (lister != null) lister.RXDI(miStart, "CMP", dstBase, dstIndex, dstScale, dstDisp, imm);
8640 }
8641
8642 /**
8643 * Generate a register-offset--immediate CMP. That is,
8644 * <PRE>
8645 * [dstIndex<<dstScale + dstDisp] == (byte) imm
8646 * </PRE>
8647 *
8648 * @param dstIndex the destination index register
8649 * @param dstScale the destination shift amount
8650 * @param dstDisp the destination displacement
8651 * @param imm immediate
8652 */
8653 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
8654 public final void emitCMP_RegOff_Imm_Byte(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
8655 int miStart = mi;
8656 generateREXprefix(false, null, dstIndex, null);
8657 setMachineCodes(mi++, (byte) 0x80);
8658 // "register 0x7" is really part of the opcode
8659 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
8660 emitImm8(imm);
8661 if (lister != null) lister.RFDI(miStart, "CMP", dstIndex, dstScale, dstDisp, imm);
8662 }
8663
8664 /**
8665 * Generate a absolute--immediate CMP. That is,
8666 * <PRE>
8667 * [dstDisp] == (byte) imm
8668 * </PRE>
8669 *
8670 * @param dstDisp the destination displacement
8671 * @param imm immediate
8672 */
8673 public final void emitCMP_Abs_Imm_Byte(Address dstDisp, int imm) {
8674 int miStart = mi;
8675 generateREXprefix(false, null, null, null);
8676 setMachineCodes(mi++, (byte) 0x80);
8677 // "register 0x7" is really part of the opcode
8678 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x7));
8679 emitImm8(imm);
8680 if (lister != null) lister.RAI(miStart, "CMP", dstDisp, imm);
8681 }
8682
8683 /**
8684 * Generate a register(indirect)--immediate CMP. That is,
8685 * <PRE>
8686 * [dstBase] == (byte) imm
8687 * </PRE>
8688 *
8689 * @param dstBase the destination base register
8690 * @param imm immediate
8691 */
8692 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
8693 public final void emitCMP_RegInd_Imm_Byte(GPR dstBase, int imm) {
8694 int miStart = mi;
8695 generateREXprefix(false, null, null, dstBase);
8696 setMachineCodes(mi++, (byte) 0x80);
8697 // "register 0x7" is really part of the opcode
8698 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x7));
8699 emitImm8(imm);
8700 if (lister != null) lister.RNI(miStart, "CMP", dstBase, imm);
8701 }
8702
8703 /**
8704 * Generate a register(indirect)--register OR. That is,
8705 * <PRE>
8706 * [dstBase] |= srcReg
8707 * </PRE>
8708 *
8709 * @param dstBase the destination base
8710 * @param srcReg the source register
8711 */
8712 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
8713 public final void emitOR_RegInd_Reg(GPR dstBase, GPR srcReg) {
8714 int miStart = mi;
8715 // no group 1 to 4 prefix byte
8716 generateREXprefix(false, srcReg, null, dstBase);
8717 // single byte opcode
8718 setMachineCodes(mi++, (byte) 0x09);
8719 emitRegIndirectRegOperands(dstBase, srcReg);
8720 if (lister != null) lister.RNR(miStart, "OR", dstBase, srcReg);
8721 }
8722
8723 /**
8724 * Generate a register-offset--register OR. That is,
8725 * <PRE>
8726 * [dstReg<<dstScale + dstDisp] |= srcReg
8727 * </PRE>
8728 *
8729 * @param dstIndex the destination index register
8730 * @param dstScale the destination shift amount
8731 * @param dstDisp the destination displacement
8732 * @param srcReg the source register
8733 */
8734 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
8735 public final void emitOR_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
8736 int miStart = mi;
8737 // no group 1 to 4 prefix byte
8738 generateREXprefix(false, srcReg, dstIndex, null);
8739 // single byte opcode
8740 setMachineCodes(mi++, (byte) 0x09);
8741 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
8742 if (lister != null) lister.RFDR(miStart, "OR", dstIndex, dstScale, dstDisp, srcReg);
8743 }
8744
8745 /**
8746 * Generate a absolute--register OR. That is,
8747 * <PRE>
8748 * [dstDisp] |= srcReg
8749 * </PRE>
8750 *
8751 * @param dstDisp the destination address
8752 * @param srcReg the source register
8753 */
8754 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
8755 public final void emitOR_Abs_Reg(Address dstDisp, GPR srcReg) {
8756 int miStart = mi;
8757 // no group 1 to 4 prefix byte
8758 generateREXprefix(false, srcReg, null, null);
8759 // single byte opcode
8760 setMachineCodes(mi++, (byte) 0x09);
8761 emitAbsRegOperands(dstDisp, srcReg);
8762 if (lister != null) lister.RAR(miStart, "OR", dstDisp, srcReg);
8763 }
8764
8765 /**
8766 * Generate a register-index--register OR. That is,
8767 * <PRE>
8768 * [dstBase + dstIndex<<dstScale + dstDisp] |= srcReg
8769 * </PRE>
8770 *
8771 * @param dstBase the base register
8772 * @param dstIndex the destination index register
8773 * @param dstScale the destination shift amount
8774 * @param dstDisp the destination displacement
8775 * @param srcReg the source register
8776 */
8777 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
8778 public final void emitOR_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
8779 int miStart = mi;
8780 // no group 1 to 4 prefix byte
8781 generateREXprefix(false, srcReg, dstIndex, dstBase);
8782 // single byte opcode
8783 setMachineCodes(mi++, (byte) 0x09);
8784 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
8785 if (lister != null) lister.RXDR(miStart, "OR", dstBase, dstIndex, dstScale, dstDisp, srcReg);
8786 }
8787
8788 /**
8789 * Generate a register-displacement--register OR. That is,
8790 * <PRE>
8791 * [dstBase + dstDisp] |= srcReg
8792 * </PRE>
8793 *
8794 * @param dstBase the base register
8795 * @param dstDisp the destination displacement
8796 * @param srcReg the source register
8797 */
8798 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
8799 public final void emitOR_RegDisp_Reg(GPR dstBase, Offset dstDisp, GPR srcReg) {
8800 int miStart = mi;
8801 // no group 1 to 4 prefix byte
8802 generateREXprefix(false, srcReg, null, dstBase);
8803 // single byte opcode
8804 setMachineCodes(mi++, (byte) 0x09);
8805 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
8806 if (lister != null) lister.RDR(miStart, "OR", dstBase, dstDisp, srcReg);
8807 }
8808
8809 /**
8810 * Generate a register--register OR. That is,
8811 * <PRE>
8812 * dstReg |= srcReg
8813 * </PRE>
8814 *
8815 * @param dstReg the destination register
8816 * @param srcReg the source register
8817 */
8818 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
8819 public final void emitOR_Reg_Reg(GPR dstReg, GPR srcReg) {
8820 int miStart = mi;
8821 // no group 1 to 4 prefix byte
8822 generateREXprefix(false, srcReg, null, dstReg);
8823 // single byte opcode
8824 setMachineCodes(mi++, (byte) 0x09);
8825 emitRegRegOperands(dstReg, srcReg);
8826 if (lister != null) lister.RR(miStart, "OR", dstReg, srcReg);
8827 }
8828
8829 /**
8830 * Generate a register--register-displacement OR. That is,
8831 * <PRE>
8832 * dstReg |= [srcReg + srcDisp]
8833 * </PRE>
8834 *
8835 * @param dstReg the destination register
8836 * @param srcBase the source register
8837 * @param srcDisp the source displacement
8838 */
8839 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
8840 public final void emitOR_Reg_RegDisp(GPR dstReg, GPR srcBase, Offset srcDisp) {
8841 int miStart = mi;
8842 // no group 1 to 4 prefix byte
8843 generateREXprefix(false, dstReg, null, srcBase);
8844 // single byte opcode
8845 setMachineCodes(mi++, (byte) 0x0B);
8846 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
8847 if (lister != null) lister.RRD(miStart, "OR", dstReg, srcBase, srcDisp);
8848 }
8849
8850 /**
8851 * Generate a register--register-offset OR. That is,
8852 * <PRE>
8853 * dstReg |= [srcIndex<<srcScale + srcDisp]
8854 * </PRE>
8855 *
8856 * @param dstReg the destination register
8857 * @param srcIndex the source index register
8858 * @param srcScale the source shift amount
8859 * @param srcDisp the source displacement
8860 */
8861 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
8862 public final void emitOR_Reg_RegOff(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
8863 int miStart = mi;
8864 // no group 1 to 4 prefix byte
8865 generateREXprefix(false, dstReg, srcIndex, null);
8866 // single byte opcode
8867 setMachineCodes(mi++, (byte) 0x0B);
8868 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
8869 if (lister != null) lister.RRFD(miStart, "OR", dstReg, srcIndex, srcScale, srcDisp);
8870 }
8871
8872 /**
8873 * Generate a register--register-offset OR. That is,
8874 * <PRE>
8875 * dstReg |= [srcDisp]
8876 * </PRE>
8877 *
8878 * @param dstReg the destination register
8879 * @param srcDisp the source displacement
8880 */
8881 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
8882 public final void emitOR_Reg_Abs(GPR dstReg, Address srcDisp) {
8883 int miStart = mi;
8884 // no group 1 to 4 prefix byte
8885 generateREXprefix(false, dstReg, null, null);
8886 // single byte opcode
8887 setMachineCodes(mi++, (byte) 0x0B);
8888 emitAbsRegOperands(srcDisp, dstReg);
8889 if (lister != null) lister.RRA(miStart, "OR", dstReg, srcDisp);
8890 }
8891
8892 /**
8893 * Generate a register--register-offset OR. That is,
8894 * <PRE>
8895 * dstReg |= [srcBase + srcIndex<<srcScale + srcDisp]
8896 * </PRE>
8897 *
8898 * @param dstReg the destination register
8899 * @param srcBase the source base register
8900 * @param srcIndex the source index register
8901 * @param srcScale the source shift amount
8902 * @param srcDisp the source displacement
8903 */
8904 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
8905 public final void emitOR_Reg_RegIdx(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
8906 int miStart = mi;
8907 // no group 1 to 4 prefix byte
8908 generateREXprefix(false, dstReg, srcIndex, srcBase);
8909 // single byte opcode
8910 setMachineCodes(mi++, (byte) 0x0B);
8911 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
8912 if (lister != null) lister.RRXD(miStart, "OR", dstReg, srcBase, srcIndex, srcScale, srcDisp);
8913 }
8914
8915 /**
8916 * Generate a register--register(indirect) OR. That is,
8917 * <PRE>
8918 * dstReg |= [srcBase]
8919 * </PRE>
8920 *
8921 * @param dstReg the destination register
8922 * @param srcBase the source base register
8923 */
8924 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
8925 public final void emitOR_Reg_RegInd(GPR dstReg, GPR srcBase) {
8926 int miStart = mi;
8927 // no group 1 to 4 prefix byte
8928 generateREXprefix(false, dstReg, null, srcBase);
8929 // single byte opcode
8930 setMachineCodes(mi++, (byte) 0x0B);
8931 emitRegIndirectRegOperands(srcBase, dstReg);
8932 if (lister != null) lister.RRN(miStart, "OR", dstReg, srcBase);
8933 }
8934
8935 /**
8936 * Generate a register(indirect)--register OR. That is,
8937 * <PRE>
8938 * [dstBase] |= (word) srcReg
8939 * </PRE>
8940 *
8941 * @param dstBase the destination base
8942 * @param srcReg the source register
8943 */
8944 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
8945 public final void emitOR_RegInd_Reg_Word(GPR dstBase, GPR srcReg) {
8946 int miStart = mi;
8947 setMachineCodes(mi++, (byte) 0x66);
8948 generateREXprefix(false, srcReg, null, dstBase);
8949 // single byte opcode
8950 setMachineCodes(mi++, (byte) 0x09);
8951 emitRegIndirectRegOperands(dstBase, srcReg);
8952 if (lister != null) lister.RNR(miStart, "OR", dstBase, srcReg);
8953 }
8954
8955 /**
8956 * Generate a register-offset--register OR. That is,
8957 * <PRE>
8958 * [dstReg<<dstScale + dstDisp] |= (word) srcReg
8959 * </PRE>
8960 *
8961 * @param dstIndex the destination index register
8962 * @param dstScale the destination shift amount
8963 * @param dstDisp the destination displacement
8964 * @param srcReg the source register
8965 */
8966 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
8967 public final void emitOR_RegOff_Reg_Word(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
8968 int miStart = mi;
8969 setMachineCodes(mi++, (byte) 0x66);
8970 generateREXprefix(false, srcReg, dstIndex, null);
8971 // single byte opcode
8972 setMachineCodes(mi++, (byte) 0x09);
8973 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
8974 if (lister != null) lister.RFDR(miStart, "OR", dstIndex, dstScale, dstDisp, srcReg);
8975 }
8976
8977 /**
8978 * Generate a absolute--register OR. That is,
8979 * <PRE>
8980 * [dstDisp] |= (word) srcReg
8981 * </PRE>
8982 *
8983 * @param dstDisp the destination address
8984 * @param srcReg the source register
8985 */
8986 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
8987 public final void emitOR_Abs_Reg_Word(Address dstDisp, GPR srcReg) {
8988 int miStart = mi;
8989 setMachineCodes(mi++, (byte) 0x66);
8990 generateREXprefix(false, srcReg, null, null);
8991 // single byte opcode
8992 setMachineCodes(mi++, (byte) 0x09);
8993 emitAbsRegOperands(dstDisp, srcReg);
8994 if (lister != null) lister.RAR(miStart, "OR", dstDisp, srcReg);
8995 }
8996
8997 /**
8998 * Generate a register-index--register OR. That is,
8999 * <PRE>
9000 * [dstBase + dstIndex<<dstScale + dstDisp] |= (word) srcReg
9001 * </PRE>
9002 *
9003 * @param dstBase the base register
9004 * @param dstIndex the destination index register
9005 * @param dstScale the destination shift amount
9006 * @param dstDisp the destination displacement
9007 * @param srcReg the source register
9008 */
9009 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
9010 public final void emitOR_RegIdx_Reg_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
9011 int miStart = mi;
9012 setMachineCodes(mi++, (byte) 0x66);
9013 generateREXprefix(false, srcReg, dstIndex, dstBase);
9014 // single byte opcode
9015 setMachineCodes(mi++, (byte) 0x09);
9016 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
9017 if (lister != null) lister.RXDR(miStart, "OR", dstBase, dstIndex, dstScale, dstDisp, srcReg);
9018 }
9019
9020 /**
9021 * Generate a register-displacement--register OR. That is,
9022 * <PRE>
9023 * [dstBase + dstDisp] |= (word) srcReg
9024 * </PRE>
9025 *
9026 * @param dstBase the base register
9027 * @param dstDisp the destination displacement
9028 * @param srcReg the source register
9029 */
9030 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
9031 public final void emitOR_RegDisp_Reg_Word(GPR dstBase, Offset dstDisp, GPR srcReg) {
9032 int miStart = mi;
9033 setMachineCodes(mi++, (byte) 0x66);
9034 generateREXprefix(false, srcReg, null, dstBase);
9035 // single byte opcode
9036 setMachineCodes(mi++, (byte) 0x09);
9037 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
9038 if (lister != null) lister.RDR(miStart, "OR", dstBase, dstDisp, srcReg);
9039 }
9040
9041 /**
9042 * Generate a register--register OR. That is,
9043 * <PRE>
9044 * dstReg |= (word) srcReg
9045 * </PRE>
9046 *
9047 * @param dstReg the destination register
9048 * @param srcReg the source register
9049 */
9050 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
9051 public final void emitOR_Reg_Reg_Word(GPR dstReg, GPR srcReg) {
9052 int miStart = mi;
9053 setMachineCodes(mi++, (byte) 0x66);
9054 generateREXprefix(false, srcReg, null, dstReg);
9055 // single byte opcode
9056 setMachineCodes(mi++, (byte) 0x09);
9057 emitRegRegOperands(dstReg, srcReg);
9058 if (lister != null) lister.RR(miStart, "OR", dstReg, srcReg);
9059 }
9060
9061 /**
9062 * Generate a register--register-displacement OR. That is,
9063 * <PRE>
9064 * dstReg |= (word) [srcReg + srcDisp]
9065 * </PRE>
9066 *
9067 * @param dstReg the destination register
9068 * @param srcBase the source register
9069 * @param srcDisp the source displacement
9070 */
9071 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
9072 public final void emitOR_Reg_RegDisp_Word(GPR dstReg, GPR srcBase, Offset srcDisp) {
9073 int miStart = mi;
9074 setMachineCodes(mi++, (byte) 0x66);
9075 generateREXprefix(false, dstReg, null, srcBase);
9076 // single byte opcode
9077 setMachineCodes(mi++, (byte) 0x0B);
9078 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
9079 if (lister != null) lister.RRD(miStart, "OR", dstReg, srcBase, srcDisp);
9080 }
9081
9082 /**
9083 * Generate a register--register-offset OR. That is,
9084 * <PRE>
9085 * dstReg |= (word) [srcIndex<<srcScale + srcDisp]
9086 * </PRE>
9087 *
9088 * @param dstReg the destination register
9089 * @param srcIndex the source index register
9090 * @param srcScale the source shift amount
9091 * @param srcDisp the source displacement
9092 */
9093 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
9094 public final void emitOR_Reg_RegOff_Word(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
9095 int miStart = mi;
9096 setMachineCodes(mi++, (byte) 0x66);
9097 generateREXprefix(false, dstReg, srcIndex, null);
9098 // single byte opcode
9099 setMachineCodes(mi++, (byte) 0x0B);
9100 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
9101 if (lister != null) lister.RRFD(miStart, "OR", dstReg, srcIndex, srcScale, srcDisp);
9102 }
9103
9104 /**
9105 * Generate a register--register-offset OR. That is,
9106 * <PRE>
9107 * dstReg |= (word) [srcDisp]
9108 * </PRE>
9109 *
9110 * @param dstReg the destination register
9111 * @param srcDisp the source displacement
9112 */
9113 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
9114 public final void emitOR_Reg_Abs_Word(GPR dstReg, Address srcDisp) {
9115 int miStart = mi;
9116 setMachineCodes(mi++, (byte) 0x66);
9117 generateREXprefix(false, dstReg, null, null);
9118 // single byte opcode
9119 setMachineCodes(mi++, (byte) 0x0B);
9120 emitAbsRegOperands(srcDisp, dstReg);
9121 if (lister != null) lister.RRA(miStart, "OR", dstReg, srcDisp);
9122 }
9123
9124 /**
9125 * Generate a register--register-offset OR. That is,
9126 * <PRE>
9127 * dstReg |= (word) [srcBase + srcIndex<<srcScale + srcDisp]
9128 * </PRE>
9129 *
9130 * @param dstReg the destination register
9131 * @param srcBase the source base register
9132 * @param srcIndex the source index register
9133 * @param srcScale the source shift amount
9134 * @param srcDisp the source displacement
9135 */
9136 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
9137 public final void emitOR_Reg_RegIdx_Word(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
9138 int miStart = mi;
9139 setMachineCodes(mi++, (byte) 0x66);
9140 generateREXprefix(false, dstReg, srcIndex, srcBase);
9141 // single byte opcode
9142 setMachineCodes(mi++, (byte) 0x0B);
9143 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
9144 if (lister != null) lister.RRXD(miStart, "OR", dstReg, srcBase, srcIndex, srcScale, srcDisp);
9145 }
9146
9147 /**
9148 * Generate a register--register(indirect) OR. That is,
9149 * <PRE>
9150 * dstReg |= (word) [srcBase]
9151 * </PRE>
9152 *
9153 * @param dstReg the destination register
9154 * @param srcBase the source base register
9155 */
9156 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
9157 public final void emitOR_Reg_RegInd_Word(GPR dstReg, GPR srcBase) {
9158 int miStart = mi;
9159 setMachineCodes(mi++, (byte) 0x66);
9160 generateREXprefix(false, dstReg, null, srcBase);
9161 // single byte opcode
9162 setMachineCodes(mi++, (byte) 0x0B);
9163 emitRegIndirectRegOperands(srcBase, dstReg);
9164 if (lister != null) lister.RRN(miStart, "OR", dstReg, srcBase);
9165 }
9166
9167 /**
9168 * Generate a register(indirect)--register OR. That is,
9169 * <PRE>
9170 * [dstBase] |= (quad) srcReg
9171 * </PRE>
9172 *
9173 * @param dstBase the destination base
9174 * @param srcReg the source register
9175 */
9176 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
9177 public final void emitOR_RegInd_Reg_Quad(GPR dstBase, GPR srcReg) {
9178 int miStart = mi;
9179 // no group 1 to 4 prefix byte
9180 generateREXprefix(true, srcReg, null, dstBase);
9181 // single byte opcode
9182 setMachineCodes(mi++, (byte) 0x09);
9183 emitRegIndirectRegOperands(dstBase, srcReg);
9184 if (lister != null) lister.RNR(miStart, "OR", dstBase, srcReg);
9185 }
9186
9187 /**
9188 * Generate a register-offset--register OR. That is,
9189 * <PRE>
9190 * [dstReg<<dstScale + dstDisp] |= (quad) srcReg
9191 * </PRE>
9192 *
9193 * @param dstIndex the destination index register
9194 * @param dstScale the destination shift amount
9195 * @param dstDisp the destination displacement
9196 * @param srcReg the source register
9197 */
9198 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
9199 public final void emitOR_RegOff_Reg_Quad(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
9200 int miStart = mi;
9201 // no group 1 to 4 prefix byte
9202 generateREXprefix(true, srcReg, dstIndex, null);
9203 // single byte opcode
9204 setMachineCodes(mi++, (byte) 0x09);
9205 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
9206 if (lister != null) lister.RFDR(miStart, "OR", dstIndex, dstScale, dstDisp, srcReg);
9207 }
9208
9209 /**
9210 * Generate a absolute--register OR. That is,
9211 * <PRE>
9212 * [dstDisp] |= (quad) srcReg
9213 * </PRE>
9214 *
9215 * @param dstDisp the destination address
9216 * @param srcReg the source register
9217 */
9218 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
9219 public final void emitOR_Abs_Reg_Quad(Address dstDisp, GPR srcReg) {
9220 int miStart = mi;
9221 // no group 1 to 4 prefix byte
9222 generateREXprefix(true, srcReg, null, null);
9223 // single byte opcode
9224 setMachineCodes(mi++, (byte) 0x09);
9225 emitAbsRegOperands(dstDisp, srcReg);
9226 if (lister != null) lister.RAR(miStart, "OR", dstDisp, srcReg);
9227 }
9228
9229 /**
9230 * Generate a register-index--register OR. That is,
9231 * <PRE>
9232 * [dstBase + dstIndex<<dstScale + dstDisp] |= (quad) srcReg
9233 * </PRE>
9234 *
9235 * @param dstBase the base register
9236 * @param dstIndex the destination index register
9237 * @param dstScale the destination shift amount
9238 * @param dstDisp the destination displacement
9239 * @param srcReg the source register
9240 */
9241 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
9242 public final void emitOR_RegIdx_Reg_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
9243 int miStart = mi;
9244 // no group 1 to 4 prefix byte
9245 generateREXprefix(true, srcReg, dstIndex, dstBase);
9246 // single byte opcode
9247 setMachineCodes(mi++, (byte) 0x09);
9248 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
9249 if (lister != null) lister.RXDR(miStart, "OR", dstBase, dstIndex, dstScale, dstDisp, srcReg);
9250 }
9251
9252 /**
9253 * Generate a register-displacement--register OR. That is,
9254 * <PRE>
9255 * [dstBase + dstDisp] |= (quad) srcReg
9256 * </PRE>
9257 *
9258 * @param dstBase the base register
9259 * @param dstDisp the destination displacement
9260 * @param srcReg the source register
9261 */
9262 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
9263 public final void emitOR_RegDisp_Reg_Quad(GPR dstBase, Offset dstDisp, GPR srcReg) {
9264 int miStart = mi;
9265 // no group 1 to 4 prefix byte
9266 generateREXprefix(true, srcReg, null, dstBase);
9267 // single byte opcode
9268 setMachineCodes(mi++, (byte) 0x09);
9269 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
9270 if (lister != null) lister.RDR(miStart, "OR", dstBase, dstDisp, srcReg);
9271 }
9272
9273 /**
9274 * Generate a register--register OR. That is,
9275 * <PRE>
9276 * dstReg |= (quad) srcReg
9277 * </PRE>
9278 *
9279 * @param dstReg the destination register
9280 * @param srcReg the source register
9281 */
9282 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
9283 public final void emitOR_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
9284 int miStart = mi;
9285 // no group 1 to 4 prefix byte
9286 generateREXprefix(true, srcReg, null, dstReg);
9287 // single byte opcode
9288 setMachineCodes(mi++, (byte) 0x09);
9289 emitRegRegOperands(dstReg, srcReg);
9290 if (lister != null) lister.RR(miStart, "OR", dstReg, srcReg);
9291 }
9292
9293 /**
9294 * Generate a register--register-displacement OR. That is,
9295 * <PRE>
9296 * dstReg |= (quad) [srcReg + srcDisp]
9297 * </PRE>
9298 *
9299 * @param dstReg the destination register
9300 * @param srcBase the source register
9301 * @param srcDisp the source displacement
9302 */
9303 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
9304 public final void emitOR_Reg_RegDisp_Quad(GPR dstReg, GPR srcBase, Offset srcDisp) {
9305 int miStart = mi;
9306 // no group 1 to 4 prefix byte
9307 generateREXprefix(true, dstReg, null, srcBase);
9308 // single byte opcode
9309 setMachineCodes(mi++, (byte) 0x0B);
9310 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
9311 if (lister != null) lister.RRD(miStart, "OR", dstReg, srcBase, srcDisp);
9312 }
9313
9314 /**
9315 * Generate a register--register-offset OR. That is,
9316 * <PRE>
9317 * dstReg |= (quad) [srcIndex<<srcScale + srcDisp]
9318 * </PRE>
9319 *
9320 * @param dstReg the destination register
9321 * @param srcIndex the source index register
9322 * @param srcScale the source shift amount
9323 * @param srcDisp the source displacement
9324 */
9325 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
9326 public final void emitOR_Reg_RegOff_Quad(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
9327 int miStart = mi;
9328 // no group 1 to 4 prefix byte
9329 generateREXprefix(true, dstReg, srcIndex, null);
9330 // single byte opcode
9331 setMachineCodes(mi++, (byte) 0x0B);
9332 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
9333 if (lister != null) lister.RRFD(miStart, "OR", dstReg, srcIndex, srcScale, srcDisp);
9334 }
9335
9336 /**
9337 * Generate a register--register-offset OR. That is,
9338 * <PRE>
9339 * dstReg |= (quad) [srcDisp]
9340 * </PRE>
9341 *
9342 * @param dstReg the destination register
9343 * @param srcDisp the source displacement
9344 */
9345 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
9346 public final void emitOR_Reg_Abs_Quad(GPR dstReg, Address srcDisp) {
9347 int miStart = mi;
9348 // no group 1 to 4 prefix byte
9349 generateREXprefix(true, dstReg, null, null);
9350 // single byte opcode
9351 setMachineCodes(mi++, (byte) 0x0B);
9352 emitAbsRegOperands(srcDisp, dstReg);
9353 if (lister != null) lister.RRA(miStart, "OR", dstReg, srcDisp);
9354 }
9355
9356 /**
9357 * Generate a register--register-offset OR. That is,
9358 * <PRE>
9359 * dstReg |= (quad) [srcBase + srcIndex<<srcScale + srcDisp]
9360 * </PRE>
9361 *
9362 * @param dstReg the destination register
9363 * @param srcBase the source base register
9364 * @param srcIndex the source index register
9365 * @param srcScale the source shift amount
9366 * @param srcDisp the source displacement
9367 */
9368 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
9369 public final void emitOR_Reg_RegIdx_Quad(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
9370 int miStart = mi;
9371 // no group 1 to 4 prefix byte
9372 generateREXprefix(true, dstReg, srcIndex, srcBase);
9373 // single byte opcode
9374 setMachineCodes(mi++, (byte) 0x0B);
9375 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
9376 if (lister != null) lister.RRXD(miStart, "OR", dstReg, srcBase, srcIndex, srcScale, srcDisp);
9377 }
9378
9379 /**
9380 * Generate a register--register(indirect) OR. That is,
9381 * <PRE>
9382 * dstReg |= (quad) [srcBase]
9383 * </PRE>
9384 *
9385 * @param dstReg the destination register
9386 * @param srcBase the source base register
9387 */
9388 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
9389 public final void emitOR_Reg_RegInd_Quad(GPR dstReg, GPR srcBase) {
9390 int miStart = mi;
9391 // no group 1 to 4 prefix byte
9392 generateREXprefix(true, dstReg, null, srcBase);
9393 // single byte opcode
9394 setMachineCodes(mi++, (byte) 0x0B);
9395 emitRegIndirectRegOperands(srcBase, dstReg);
9396 if (lister != null) lister.RRN(miStart, "OR", dstReg, srcBase);
9397 }
9398
9399 /**
9400 * Generate a register(indirect)--register OR. That is,
9401 * <PRE>
9402 * [dstBase] |= (byte) srcReg
9403 * </PRE>
9404 *
9405 * @param dstBase the destination base
9406 * @param srcReg the source register
9407 */
9408 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
9409 public final void emitOR_RegInd_Reg_Byte(GPR dstBase, GPR srcReg) {
9410 int miStart = mi;
9411 // no group 1 to 4 prefix byte
9412 generateREXprefix(false, srcReg, null, dstBase);
9413 // single byte opcode
9414 setMachineCodes(mi++, (byte) 0x08);
9415 emitRegIndirectRegOperands(dstBase, srcReg);
9416 if (lister != null) lister.RNR(miStart, "OR", dstBase, srcReg);
9417 }
9418
9419 /**
9420 * Generate a register-offset--register OR. That is,
9421 * <PRE>
9422 * [dstReg<<dstScale + dstDisp] |= (byte) srcReg
9423 * </PRE>
9424 *
9425 * @param dstIndex the destination index register
9426 * @param dstScale the destination shift amount
9427 * @param dstDisp the destination displacement
9428 * @param srcReg the source register
9429 */
9430 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
9431 public final void emitOR_RegOff_Reg_Byte(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
9432 int miStart = mi;
9433 // no group 1 to 4 prefix byte
9434 generateREXprefix(false, srcReg, dstIndex, null);
9435 // single byte opcode
9436 setMachineCodes(mi++, (byte) 0x08);
9437 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
9438 if (lister != null) lister.RFDR(miStart, "OR", dstIndex, dstScale, dstDisp, srcReg);
9439 }
9440
9441 /**
9442 * Generate a absolute--register OR. That is,
9443 * <PRE>
9444 * [dstDisp] |= (byte) srcReg
9445 * </PRE>
9446 *
9447 * @param dstDisp the destination address
9448 * @param srcReg the source register
9449 */
9450 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
9451 public final void emitOR_Abs_Reg_Byte(Address dstDisp, GPR srcReg) {
9452 int miStart = mi;
9453 // no group 1 to 4 prefix byte
9454 generateREXprefix(false, srcReg, null, null);
9455 // single byte opcode
9456 setMachineCodes(mi++, (byte) 0x08);
9457 emitAbsRegOperands(dstDisp, srcReg);
9458 if (lister != null) lister.RAR(miStart, "OR", dstDisp, srcReg);
9459 }
9460
9461 /**
9462 * Generate a register-index--register OR. That is,
9463 * <PRE>
9464 * [dstBase + dstIndex<<dstScale + dstDisp] |= (byte) srcReg
9465 * </PRE>
9466 *
9467 * @param dstBase the base register
9468 * @param dstIndex the destination index register
9469 * @param dstScale the destination shift amount
9470 * @param dstDisp the destination displacement
9471 * @param srcReg the source register
9472 */
9473 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
9474 public final void emitOR_RegIdx_Reg_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
9475 int miStart = mi;
9476 // no group 1 to 4 prefix byte
9477 generateREXprefix(false, srcReg, dstIndex, dstBase);
9478 // single byte opcode
9479 setMachineCodes(mi++, (byte) 0x08);
9480 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
9481 if (lister != null) lister.RXDR(miStart, "OR", dstBase, dstIndex, dstScale, dstDisp, srcReg);
9482 }
9483
9484 /**
9485 * Generate a register-displacement--register OR. That is,
9486 * <PRE>
9487 * [dstBase + dstDisp] |= (byte) srcReg
9488 * </PRE>
9489 *
9490 * @param dstBase the base register
9491 * @param dstDisp the destination displacement
9492 * @param srcReg the source register
9493 */
9494 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
9495 public final void emitOR_RegDisp_Reg_Byte(GPR dstBase, Offset dstDisp, GPR srcReg) {
9496 int miStart = mi;
9497 // no group 1 to 4 prefix byte
9498 generateREXprefix(false, srcReg, null, dstBase);
9499 // single byte opcode
9500 setMachineCodes(mi++, (byte) 0x08);
9501 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
9502 if (lister != null) lister.RDR(miStart, "OR", dstBase, dstDisp, srcReg);
9503 }
9504
9505 /**
9506 * Generate a register--register OR. That is,
9507 * <PRE>
9508 * dstReg |= (byte) srcReg
9509 * </PRE>
9510 *
9511 * @param dstReg the destination register
9512 * @param srcReg the source register
9513 */
9514 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
9515 public final void emitOR_Reg_Reg_Byte(GPR dstReg, GPR srcReg) {
9516 int miStart = mi;
9517 // no group 1 to 4 prefix byte
9518 generateREXprefix(false, srcReg, null, dstReg);
9519 // single byte opcode
9520 setMachineCodes(mi++, (byte) 0x08);
9521 emitRegRegOperands(dstReg, srcReg);
9522 if (lister != null) lister.RR(miStart, "OR", dstReg, srcReg);
9523 }
9524
9525 /**
9526 * Generate a register--register-displacement OR. That is,
9527 * <PRE>
9528 * dstReg |= (byte) [srcReg + srcDisp]
9529 * </PRE>
9530 *
9531 * @param dstReg the destination register
9532 * @param srcBase the source register
9533 * @param srcDisp the source displacement
9534 */
9535 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
9536 public final void emitOR_Reg_RegDisp_Byte(GPR dstReg, GPR srcBase, Offset srcDisp) {
9537 int miStart = mi;
9538 // no group 1 to 4 prefix byte
9539 generateREXprefix(false, dstReg, null, srcBase);
9540 // single byte opcode
9541 setMachineCodes(mi++, (byte) 0x0A);
9542 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
9543 if (lister != null) lister.RRD(miStart, "OR", dstReg, srcBase, srcDisp);
9544 }
9545
9546 /**
9547 * Generate a register--register-offset OR. That is,
9548 * <PRE>
9549 * dstReg |= (byte) [srcIndex<<srcScale + srcDisp]
9550 * </PRE>
9551 *
9552 * @param dstReg the destination register
9553 * @param srcIndex the source index register
9554 * @param srcScale the source shift amount
9555 * @param srcDisp the source displacement
9556 */
9557 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
9558 public final void emitOR_Reg_RegOff_Byte(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
9559 int miStart = mi;
9560 // no group 1 to 4 prefix byte
9561 generateREXprefix(false, dstReg, srcIndex, null);
9562 // single byte opcode
9563 setMachineCodes(mi++, (byte) 0x0A);
9564 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
9565 if (lister != null) lister.RRFD(miStart, "OR", dstReg, srcIndex, srcScale, srcDisp);
9566 }
9567
9568 /**
9569 * Generate a register--register-offset OR. That is,
9570 * <PRE>
9571 * dstReg |= (byte) [srcDisp]
9572 * </PRE>
9573 *
9574 * @param dstReg the destination register
9575 * @param srcDisp the source displacement
9576 */
9577 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
9578 public final void emitOR_Reg_Abs_Byte(GPR dstReg, Address srcDisp) {
9579 int miStart = mi;
9580 // no group 1 to 4 prefix byte
9581 generateREXprefix(false, dstReg, null, null);
9582 // single byte opcode
9583 setMachineCodes(mi++, (byte) 0x0A);
9584 emitAbsRegOperands(srcDisp, dstReg);
9585 if (lister != null) lister.RRA(miStart, "OR", dstReg, srcDisp);
9586 }
9587
9588 /**
9589 * Generate a register--register-offset OR. That is,
9590 * <PRE>
9591 * dstReg |= (byte) [srcBase + srcIndex<<srcScale + srcDisp]
9592 * </PRE>
9593 *
9594 * @param dstReg the destination register
9595 * @param srcBase the source base register
9596 * @param srcIndex the source index register
9597 * @param srcScale the source shift amount
9598 * @param srcDisp the source displacement
9599 */
9600 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
9601 public final void emitOR_Reg_RegIdx_Byte(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
9602 int miStart = mi;
9603 // no group 1 to 4 prefix byte
9604 generateREXprefix(false, dstReg, srcIndex, srcBase);
9605 // single byte opcode
9606 setMachineCodes(mi++, (byte) 0x0A);
9607 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
9608 if (lister != null) lister.RRXD(miStart, "OR", dstReg, srcBase, srcIndex, srcScale, srcDisp);
9609 }
9610
9611 /**
9612 * Generate a register--register(indirect) OR. That is,
9613 * <PRE>
9614 * dstReg |= (byte) [srcBase]
9615 * </PRE>
9616 *
9617 * @param dstReg the destination register
9618 * @param srcBase the source base register
9619 */
9620 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
9621 public final void emitOR_Reg_RegInd_Byte(GPR dstReg, GPR srcBase) {
9622 int miStart = mi;
9623 // no group 1 to 4 prefix byte
9624 generateREXprefix(false, dstReg, null, srcBase);
9625 // single byte opcode
9626 setMachineCodes(mi++, (byte) 0x0A);
9627 emitRegIndirectRegOperands(srcBase, dstReg);
9628 if (lister != null) lister.RRN(miStart, "OR", dstReg, srcBase);
9629 }
9630
9631 /**
9632 * Generate a register--immediate OR. That is,
9633 * <PRE>
9634 * dstReg |= imm
9635 * </PRE>
9636 *
9637 * @param dstReg the destination register
9638 * @param imm immediate
9639 */
9640 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
9641 public final void emitOR_Reg_Imm(GPR dstReg, int imm) {
9642 int miStart = mi;
9643 // no group 1 to 4 prefix byte
9644 generateREXprefix(false, null, null, dstReg);
9645 // single byte opcode
9646 if (fits(imm,8)) {
9647 setMachineCodes(mi++, (byte) 0x83);
9648 // "register 0x1" is really part of the opcode
9649 emitRegRegOperands(dstReg, GPR.getForOpcode(0x1));
9650 emitImm8((byte)imm);
9651 } else if (dstReg == EAX) {
9652 setMachineCodes(mi++, (byte) 0x0D);
9653 emitImm32(imm);
9654 } else {
9655 setMachineCodes(mi++, (byte) 0x81);
9656 // "register 0x1" is really part of the opcode
9657 emitRegRegOperands(dstReg, GPR.getForOpcode(0x1));
9658 emitImm32(imm);
9659 }
9660 if (lister != null) lister.RI(miStart, "OR", dstReg, imm);
9661 }
9662
9663 /**
9664 * Generate a register-displacement--immediate OR. That is,
9665 * <PRE>
9666 * [dstBase + dstDisp] |= imm
9667 * </PRE>
9668 *
9669 * @param dstBase the destination register
9670 * @param dstDisp the destination displacement
9671 * @param imm immediate
9672 */
9673 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
9674 public final void emitOR_RegDisp_Imm(GPR dstBase, Offset dstDisp, int imm) {
9675 int miStart = mi;
9676 // no group 1 to 4 prefix byte
9677 generateREXprefix(false, null, null, dstBase);
9678 // single byte opcode
9679 if (fits(imm,8)) {
9680 setMachineCodes(mi++, (byte) 0x83);
9681 // "register 0x1" is really part of the opcode
9682 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x1));
9683 emitImm8((byte)imm);
9684 } else {
9685 setMachineCodes(mi++, (byte) 0x81);
9686 // "register 0x1" is really part of the opcode
9687 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x1));
9688 emitImm32(imm);
9689 }
9690 if (lister != null) lister.RDI(miStart, "OR", dstBase, dstDisp, imm);
9691 }
9692
9693 /**
9694 * Generate a register-offset--immediate OR. That is,
9695 * <PRE>
9696 * [dstIndex<<dstScale + dstDisp] |= imm
9697 * </PRE>
9698 *
9699 * @param dstIndex the destination index register
9700 * @param dstScale the destination shift amount
9701 * @param dstDisp the destination displacement
9702 * @param imm immediate
9703 */
9704 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
9705 public final void emitOR_RegOff_Imm(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
9706 int miStart = mi;
9707 // no group 1 to 4 prefix byte
9708 generateREXprefix(false, null, dstIndex, null);
9709 // single byte opcode
9710 if (fits(imm,8)) {
9711 setMachineCodes(mi++, (byte) 0x83);
9712 // "register 0x1" is really part of the opcode
9713 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
9714 emitImm8((byte)imm);
9715 } else {
9716 setMachineCodes(mi++, (byte) 0x81);
9717 // "register 0x1" is really part of the opcode
9718 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
9719 emitImm32(imm);
9720 }
9721 if (lister != null) lister.RFDI(miStart, "OR", dstIndex, dstScale, dstDisp, imm);
9722 }
9723
9724 /**
9725 * Generate a absolute--immediate OR. That is,
9726 * <PRE>
9727 * [dstDisp] |= imm
9728 * </PRE>
9729 *
9730 * @param dstDisp the destination displacement
9731 * @param imm immediate
9732 */
9733 public final void emitOR_Abs_Imm(Address dstDisp, int imm) {
9734 int miStart = mi;
9735 // no group 1 to 4 prefix byte
9736 generateREXprefix(false, null, null, null);
9737 // single byte opcode
9738 if (fits(imm,8)) {
9739 setMachineCodes(mi++, (byte) 0x83);
9740 // "register 0x1" is really part of the opcode
9741 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x1));
9742 emitImm8((byte)imm);
9743 } else {
9744 setMachineCodes(mi++, (byte) 0x81);
9745 // "register 0x1" is really part of the opcode
9746 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x1));
9747 emitImm32(imm);
9748 }
9749 if (lister != null) lister.RAI(miStart, "OR", dstDisp, imm);
9750 }
9751
9752 /**
9753 * Generate a register-index--immediate OR. That is,
9754 * <PRE>
9755 * [dstBase + dstIndex<<dstScale + dstDisp] |= imm
9756 * </PRE>
9757 *
9758 * @param dstBase the destination base register
9759 * @param dstIndex the destination index register
9760 * @param dstScale the destination shift amount
9761 * @param dstDisp the destination displacement
9762 * @param imm immediate
9763 */
9764 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
9765 public final void emitOR_RegIdx_Imm(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
9766 int miStart = mi;
9767 // no group 1 to 4 prefix byte
9768 generateREXprefix(false, null, dstIndex, dstBase);
9769 // single byte opcode
9770 if (fits(imm,8)) {
9771 setMachineCodes(mi++, (byte) 0x83);
9772 // "register 0x1" is really part of the opcode
9773 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
9774 emitImm8((byte)imm);
9775 } else {
9776 setMachineCodes(mi++, (byte) 0x81);
9777 // "register 0x1" is really part of the opcode
9778 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
9779 emitImm32(imm);
9780 }
9781 if (lister != null) lister.RXDI(miStart, "OR", dstBase, dstIndex, dstScale, dstDisp, imm);
9782 }
9783
9784 /**
9785 * Generate a register(indirect)--immediate OR. That is,
9786 * <PRE>
9787 * [dstBase] |= imm
9788 * </PRE>
9789 *
9790 * @param dstBase the destination base register
9791 * @param imm immediate
9792 */
9793 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
9794 public final void emitOR_RegInd_Imm(GPR dstBase, int imm) {
9795 int miStart = mi;
9796 // no group 1 to 4 prefix byte
9797 generateREXprefix(false, null, null, dstBase);
9798 // single byte opcode
9799 if (fits(imm,8)) {
9800 setMachineCodes(mi++, (byte) 0x83);
9801 // "register 0x1" is really part of the opcode
9802 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x1));
9803 emitImm8((byte)imm);
9804 } else {
9805 setMachineCodes(mi++, (byte) 0x81);
9806 // "register 0x1" is really part of the opcode
9807 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x1));
9808 emitImm32(imm);
9809 }
9810 if (lister != null) lister.RNI(miStart, "OR", dstBase, imm);
9811 }
9812
9813 /**
9814 * Generate a register--immediate OR. That is,
9815 * <PRE>
9816 * dstReg |= (word) imm
9817 * </PRE>
9818 *
9819 * @param dstReg the destination register
9820 * @param imm immediate
9821 */
9822 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
9823 public final void emitOR_Reg_Imm_Word(GPR dstReg, int imm) {
9824 int miStart = mi;
9825 setMachineCodes(mi++, (byte) 0x66);
9826 generateREXprefix(false, null, null, dstReg);
9827 // single byte opcode
9828 if (fits(imm,8)) {
9829 setMachineCodes(mi++, (byte) 0x83);
9830 // "register 0x1" is really part of the opcode
9831 emitRegRegOperands(dstReg, GPR.getForOpcode(0x1));
9832 emitImm8((byte)imm);
9833 } else if (dstReg == EAX) {
9834 setMachineCodes(mi++, (byte) 0x0D);
9835 emitImm16(imm);
9836 } else {
9837 setMachineCodes(mi++, (byte) 0x81);
9838 // "register 0x1" is really part of the opcode
9839 emitRegRegOperands(dstReg, GPR.getForOpcode(0x1));
9840 emitImm16(imm);
9841 }
9842 if (lister != null) lister.RI(miStart, "OR", dstReg, imm);
9843 }
9844
9845 /**
9846 * Generate a register-displacement--immediate OR. That is,
9847 * <PRE>
9848 * [dstBase + dstDisp] |= (word) imm
9849 * </PRE>
9850 *
9851 * @param dstBase the destination register
9852 * @param dstDisp the destination displacement
9853 * @param imm immediate
9854 */
9855 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
9856 public final void emitOR_RegDisp_Imm_Word(GPR dstBase, Offset dstDisp, int imm) {
9857 int miStart = mi;
9858 setMachineCodes(mi++, (byte) 0x66);
9859 generateREXprefix(false, null, null, dstBase);
9860 // single byte opcode
9861 if (fits(imm,8)) {
9862 setMachineCodes(mi++, (byte) 0x83);
9863 // "register 0x1" is really part of the opcode
9864 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x1));
9865 emitImm8((byte)imm);
9866 } else {
9867 setMachineCodes(mi++, (byte) 0x81);
9868 // "register 0x1" is really part of the opcode
9869 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x1));
9870 emitImm16(imm);
9871 }
9872 if (lister != null) lister.RDI(miStart, "OR", dstBase, dstDisp, imm);
9873 }
9874
9875 /**
9876 * Generate a register-offset--immediate OR. That is,
9877 * <PRE>
9878 * [dstIndex<<dstScale + dstDisp] |= (word) imm
9879 * </PRE>
9880 *
9881 * @param dstIndex the destination index register
9882 * @param dstScale the destination shift amount
9883 * @param dstDisp the destination displacement
9884 * @param imm immediate
9885 */
9886 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
9887 public final void emitOR_RegOff_Imm_Word(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
9888 int miStart = mi;
9889 setMachineCodes(mi++, (byte) 0x66);
9890 generateREXprefix(false, null, dstIndex, null);
9891 // single byte opcode
9892 if (fits(imm,8)) {
9893 setMachineCodes(mi++, (byte) 0x83);
9894 // "register 0x1" is really part of the opcode
9895 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
9896 emitImm8((byte)imm);
9897 } else {
9898 setMachineCodes(mi++, (byte) 0x81);
9899 // "register 0x1" is really part of the opcode
9900 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
9901 emitImm16(imm);
9902 }
9903 if (lister != null) lister.RFDI(miStart, "OR", dstIndex, dstScale, dstDisp, imm);
9904 }
9905
9906 /**
9907 * Generate a absolute--immediate OR. That is,
9908 * <PRE>
9909 * [dstDisp] |= (word) imm
9910 * </PRE>
9911 *
9912 * @param dstDisp the destination displacement
9913 * @param imm immediate
9914 */
9915 public final void emitOR_Abs_Imm_Word(Address dstDisp, int imm) {
9916 int miStart = mi;
9917 setMachineCodes(mi++, (byte) 0x66);
9918 generateREXprefix(false, null, null, null);
9919 // single byte opcode
9920 if (fits(imm,8)) {
9921 setMachineCodes(mi++, (byte) 0x83);
9922 // "register 0x1" is really part of the opcode
9923 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x1));
9924 emitImm8((byte)imm);
9925 } else {
9926 setMachineCodes(mi++, (byte) 0x81);
9927 // "register 0x1" is really part of the opcode
9928 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x1));
9929 emitImm16(imm);
9930 }
9931 if (lister != null) lister.RAI(miStart, "OR", dstDisp, imm);
9932 }
9933
9934 /**
9935 * Generate a register-index--immediate OR. That is,
9936 * <PRE>
9937 * [dstBase + dstIndex<<dstScale + dstDisp] |= (word) imm
9938 * </PRE>
9939 *
9940 * @param dstBase the destination base register
9941 * @param dstIndex the destination index register
9942 * @param dstScale the destination shift amount
9943 * @param dstDisp the destination displacement
9944 * @param imm immediate
9945 */
9946 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
9947 public final void emitOR_RegIdx_Imm_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
9948 int miStart = mi;
9949 setMachineCodes(mi++, (byte) 0x66);
9950 generateREXprefix(false, null, dstIndex, dstBase);
9951 // single byte opcode
9952 if (fits(imm,8)) {
9953 setMachineCodes(mi++, (byte) 0x83);
9954 // "register 0x1" is really part of the opcode
9955 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
9956 emitImm8((byte)imm);
9957 } else {
9958 setMachineCodes(mi++, (byte) 0x81);
9959 // "register 0x1" is really part of the opcode
9960 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
9961 emitImm16(imm);
9962 }
9963 if (lister != null) lister.RXDI(miStart, "OR", dstBase, dstIndex, dstScale, dstDisp, imm);
9964 }
9965
9966 /**
9967 * Generate a register(indirect)--immediate OR. That is,
9968 * <PRE>
9969 * [dstBase] |= (word) imm
9970 * </PRE>
9971 *
9972 * @param dstBase the destination base register
9973 * @param imm immediate
9974 */
9975 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
9976 public final void emitOR_RegInd_Imm_Word(GPR dstBase, int imm) {
9977 int miStart = mi;
9978 setMachineCodes(mi++, (byte) 0x66);
9979 generateREXprefix(false, null, null, dstBase);
9980 // single byte opcode
9981 if (fits(imm,8)) {
9982 setMachineCodes(mi++, (byte) 0x83);
9983 // "register 0x1" is really part of the opcode
9984 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x1));
9985 emitImm8((byte)imm);
9986 } else {
9987 setMachineCodes(mi++, (byte) 0x81);
9988 // "register 0x1" is really part of the opcode
9989 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x1));
9990 emitImm16(imm);
9991 }
9992 if (lister != null) lister.RNI(miStart, "OR", dstBase, imm);
9993 }
9994
9995 /**
9996 * Generate a register--immediate OR. That is,
9997 * <PRE>
9998 * dstReg |= (quad) imm
9999 * </PRE>
10000 *
10001 * @param dstReg the destination register
10002 * @param imm immediate
10003 */
10004 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
10005 public final void emitOR_Reg_Imm_Quad(GPR dstReg, int imm) {
10006 int miStart = mi;
10007 // no group 1 to 4 prefix byte
10008 generateREXprefix(true, null, null, dstReg);
10009 // single byte opcode
10010 if (fits(imm,8)) {
10011 setMachineCodes(mi++, (byte) 0x83);
10012 // "register 0x1" is really part of the opcode
10013 emitRegRegOperands(dstReg, GPR.getForOpcode(0x1));
10014 emitImm8((byte)imm);
10015 } else if (dstReg == EAX) {
10016 setMachineCodes(mi++, (byte) 0x0D);
10017 emitImm32(imm);
10018 } else {
10019 setMachineCodes(mi++, (byte) 0x81);
10020 // "register 0x1" is really part of the opcode
10021 emitRegRegOperands(dstReg, GPR.getForOpcode(0x1));
10022 emitImm32(imm);
10023 }
10024 if (lister != null) lister.RI(miStart, "OR", dstReg, imm);
10025 }
10026
10027 /**
10028 * Generate a register-displacement--immediate OR. That is,
10029 * <PRE>
10030 * [dstBase + dstDisp] |= (quad) imm
10031 * </PRE>
10032 *
10033 * @param dstBase the destination register
10034 * @param dstDisp the destination displacement
10035 * @param imm immediate
10036 */
10037 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
10038 public final void emitOR_RegDisp_Imm_Quad(GPR dstBase, Offset dstDisp, int imm) {
10039 int miStart = mi;
10040 // no group 1 to 4 prefix byte
10041 generateREXprefix(true, null, null, dstBase);
10042 // single byte opcode
10043 if (fits(imm,8)) {
10044 setMachineCodes(mi++, (byte) 0x83);
10045 // "register 0x1" is really part of the opcode
10046 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x1));
10047 emitImm8((byte)imm);
10048 } else {
10049 setMachineCodes(mi++, (byte) 0x81);
10050 // "register 0x1" is really part of the opcode
10051 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x1));
10052 emitImm32(imm);
10053 }
10054 if (lister != null) lister.RDI(miStart, "OR", dstBase, dstDisp, imm);
10055 }
10056
10057 /**
10058 * Generate a register-offset--immediate OR. That is,
10059 * <PRE>
10060 * [dstIndex<<dstScale + dstDisp] |= (quad) imm
10061 * </PRE>
10062 *
10063 * @param dstIndex the destination index register
10064 * @param dstScale the destination shift amount
10065 * @param dstDisp the destination displacement
10066 * @param imm immediate
10067 */
10068 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
10069 public final void emitOR_RegOff_Imm_Quad(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
10070 int miStart = mi;
10071 // no group 1 to 4 prefix byte
10072 generateREXprefix(true, null, dstIndex, null);
10073 // single byte opcode
10074 if (fits(imm,8)) {
10075 setMachineCodes(mi++, (byte) 0x83);
10076 // "register 0x1" is really part of the opcode
10077 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
10078 emitImm8((byte)imm);
10079 } else {
10080 setMachineCodes(mi++, (byte) 0x81);
10081 // "register 0x1" is really part of the opcode
10082 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
10083 emitImm32(imm);
10084 }
10085 if (lister != null) lister.RFDI(miStart, "OR", dstIndex, dstScale, dstDisp, imm);
10086 }
10087
10088 /**
10089 * Generate a absolute--immediate OR. That is,
10090 * <PRE>
10091 * [dstDisp] |= (quad) imm
10092 * </PRE>
10093 *
10094 * @param dstDisp the destination displacement
10095 * @param imm immediate
10096 */
10097 public final void emitOR_Abs_Imm_Quad(Address dstDisp, int imm) {
10098 int miStart = mi;
10099 // no group 1 to 4 prefix byte
10100 generateREXprefix(true, null, null, null);
10101 // single byte opcode
10102 if (fits(imm,8)) {
10103 setMachineCodes(mi++, (byte) 0x83);
10104 // "register 0x1" is really part of the opcode
10105 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x1));
10106 emitImm8((byte)imm);
10107 } else {
10108 setMachineCodes(mi++, (byte) 0x81);
10109 // "register 0x1" is really part of the opcode
10110 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x1));
10111 emitImm32(imm);
10112 }
10113 if (lister != null) lister.RAI(miStart, "OR", dstDisp, imm);
10114 }
10115
10116 /**
10117 * Generate a register-index--immediate OR. That is,
10118 * <PRE>
10119 * [dstBase + dstIndex<<dstScale + dstDisp] |= (quad) imm
10120 * </PRE>
10121 *
10122 * @param dstBase the destination base register
10123 * @param dstIndex the destination index register
10124 * @param dstScale the destination shift amount
10125 * @param dstDisp the destination displacement
10126 * @param imm immediate
10127 */
10128 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
10129 public final void emitOR_RegIdx_Imm_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
10130 int miStart = mi;
10131 // no group 1 to 4 prefix byte
10132 generateREXprefix(true, null, dstIndex, dstBase);
10133 // single byte opcode
10134 if (fits(imm,8)) {
10135 setMachineCodes(mi++, (byte) 0x83);
10136 // "register 0x1" is really part of the opcode
10137 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
10138 emitImm8((byte)imm);
10139 } else {
10140 setMachineCodes(mi++, (byte) 0x81);
10141 // "register 0x1" is really part of the opcode
10142 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
10143 emitImm32(imm);
10144 }
10145 if (lister != null) lister.RXDI(miStart, "OR", dstBase, dstIndex, dstScale, dstDisp, imm);
10146 }
10147
10148 /**
10149 * Generate a register(indirect)--immediate OR. That is,
10150 * <PRE>
10151 * [dstBase] |= (quad) imm
10152 * </PRE>
10153 *
10154 * @param dstBase the destination base register
10155 * @param imm immediate
10156 */
10157 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
10158 public final void emitOR_RegInd_Imm_Quad(GPR dstBase, int imm) {
10159 int miStart = mi;
10160 // no group 1 to 4 prefix byte
10161 generateREXprefix(true, null, null, dstBase);
10162 // single byte opcode
10163 if (fits(imm,8)) {
10164 setMachineCodes(mi++, (byte) 0x83);
10165 // "register 0x1" is really part of the opcode
10166 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x1));
10167 emitImm8((byte)imm);
10168 } else {
10169 setMachineCodes(mi++, (byte) 0x81);
10170 // "register 0x1" is really part of the opcode
10171 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x1));
10172 emitImm32(imm);
10173 }
10174 if (lister != null) lister.RNI(miStart, "OR", dstBase, imm);
10175 }
10176
10177 /**
10178 * Generate a register--immediate OR. That is,
10179 * <PRE>
10180 * dstReg |= (byte) imm
10181 * </PRE>
10182 *
10183 * @param dstReg the destination register
10184 * @param imm immediate
10185 */
10186 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
10187 public final void emitOR_Reg_Imm_Byte(GPR dstReg, int imm) {
10188 int miStart = mi;
10189 if (dstReg == EAX) {
10190 setMachineCodes(mi++, (byte) 0x0C);
10191 emitImm8(imm);
10192 } else {
10193 generateREXprefix(false, null, null, dstReg);
10194 setMachineCodes(mi++, (byte) 0x80);
10195 // "register 0x1" is really part of the opcode
10196 emitRegRegOperands(dstReg, GPR.getForOpcode(0x1));
10197 emitImm8(imm);
10198 }
10199 if (lister != null) lister.RI(miStart, "OR", dstReg, imm);
10200 }
10201
10202 /**
10203 * Generate a register-displacement--immediate OR. That is,
10204 * <PRE>
10205 * [dstBase + dstDisp] |= (byte) imm
10206 * </PRE>
10207 *
10208 * @param dstBase the destination register
10209 * @param dstDisp the destination displacement
10210 * @param imm immediate
10211 */
10212 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
10213 public final void emitOR_RegDisp_Imm_Byte(GPR dstBase, Offset dstDisp, int imm) {
10214 int miStart = mi;
10215 generateREXprefix(false, null, null, dstBase);
10216 setMachineCodes(mi++, (byte) 0x80);
10217 // "register 0x1" is really part of the opcode
10218 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x1));
10219 emitImm8(imm);
10220 if (lister != null) lister.RDI(miStart, "OR", dstBase, dstDisp, imm);
10221 }
10222
10223 /**
10224 * Generate a register-index--immediate OR. That is,
10225 * <PRE>
10226 * [dstBase + dstIndex<<scale + dstDisp] |= (byte) imm
10227 * </PRE>
10228 *
10229 * @param dstBase the destination base register
10230 * @param dstIndex the destination index register
10231 * @param dstScale the destination shift amount
10232 * @param dstDisp the destination displacement
10233 * @param imm immediate
10234 */
10235 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
10236 public final void emitOR_RegIdx_Imm_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
10237 int miStart = mi;
10238 generateREXprefix(false, null, dstIndex, dstBase);
10239 setMachineCodes(mi++, (byte) 0x80);
10240 // "register 0x1" is really part of the opcode
10241 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
10242 emitImm8(imm);
10243 if (lister != null) lister.RXDI(miStart, "OR", dstBase, dstIndex, dstScale, dstDisp, imm);
10244 }
10245
10246 /**
10247 * Generate a register-offset--immediate OR. That is,
10248 * <PRE>
10249 * [dstIndex<<dstScale + dstDisp] |= (byte) imm
10250 * </PRE>
10251 *
10252 * @param dstIndex the destination index register
10253 * @param dstScale the destination shift amount
10254 * @param dstDisp the destination displacement
10255 * @param imm immediate
10256 */
10257 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
10258 public final void emitOR_RegOff_Imm_Byte(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
10259 int miStart = mi;
10260 generateREXprefix(false, null, dstIndex, null);
10261 setMachineCodes(mi++, (byte) 0x80);
10262 // "register 0x1" is really part of the opcode
10263 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
10264 emitImm8(imm);
10265 if (lister != null) lister.RFDI(miStart, "OR", dstIndex, dstScale, dstDisp, imm);
10266 }
10267
10268 /**
10269 * Generate a absolute--immediate OR. That is,
10270 * <PRE>
10271 * [dstDisp] |= (byte) imm
10272 * </PRE>
10273 *
10274 * @param dstDisp the destination displacement
10275 * @param imm immediate
10276 */
10277 public final void emitOR_Abs_Imm_Byte(Address dstDisp, int imm) {
10278 int miStart = mi;
10279 generateREXprefix(false, null, null, null);
10280 setMachineCodes(mi++, (byte) 0x80);
10281 // "register 0x1" is really part of the opcode
10282 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x1));
10283 emitImm8(imm);
10284 if (lister != null) lister.RAI(miStart, "OR", dstDisp, imm);
10285 }
10286
10287 /**
10288 * Generate a register(indirect)--immediate OR. That is,
10289 * <PRE>
10290 * [dstBase] |= (byte) imm
10291 * </PRE>
10292 *
10293 * @param dstBase the destination base register
10294 * @param imm immediate
10295 */
10296 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
10297 public final void emitOR_RegInd_Imm_Byte(GPR dstBase, int imm) {
10298 int miStart = mi;
10299 generateREXprefix(false, null, null, dstBase);
10300 setMachineCodes(mi++, (byte) 0x80);
10301 // "register 0x1" is really part of the opcode
10302 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x1));
10303 emitImm8(imm);
10304 if (lister != null) lister.RNI(miStart, "OR", dstBase, imm);
10305 }
10306
10307 /**
10308 * Generate a register(indirect)--register SBB. That is,
10309 * <PRE>
10310 * [dstBase] -CF= srcReg
10311 * </PRE>
10312 *
10313 * @param dstBase the destination base
10314 * @param srcReg the source register
10315 */
10316 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
10317 public final void emitSBB_RegInd_Reg(GPR dstBase, GPR srcReg) {
10318 int miStart = mi;
10319 // no group 1 to 4 prefix byte
10320 generateREXprefix(false, srcReg, null, dstBase);
10321 // single byte opcode
10322 setMachineCodes(mi++, (byte) 0x19);
10323 emitRegIndirectRegOperands(dstBase, srcReg);
10324 if (lister != null) lister.RNR(miStart, "SBB", dstBase, srcReg);
10325 }
10326
10327 /**
10328 * Generate a register-offset--register SBB. That is,
10329 * <PRE>
10330 * [dstReg<<dstScale + dstDisp] -CF= srcReg
10331 * </PRE>
10332 *
10333 * @param dstIndex the destination index register
10334 * @param dstScale the destination shift amount
10335 * @param dstDisp the destination displacement
10336 * @param srcReg the source register
10337 */
10338 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
10339 public final void emitSBB_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
10340 int miStart = mi;
10341 // no group 1 to 4 prefix byte
10342 generateREXprefix(false, srcReg, dstIndex, null);
10343 // single byte opcode
10344 setMachineCodes(mi++, (byte) 0x19);
10345 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
10346 if (lister != null) lister.RFDR(miStart, "SBB", dstIndex, dstScale, dstDisp, srcReg);
10347 }
10348
10349 /**
10350 * Generate a absolute--register SBB. That is,
10351 * <PRE>
10352 * [dstDisp] -CF= srcReg
10353 * </PRE>
10354 *
10355 * @param dstDisp the destination address
10356 * @param srcReg the source register
10357 */
10358 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
10359 public final void emitSBB_Abs_Reg(Address dstDisp, GPR srcReg) {
10360 int miStart = mi;
10361 // no group 1 to 4 prefix byte
10362 generateREXprefix(false, srcReg, null, null);
10363 // single byte opcode
10364 setMachineCodes(mi++, (byte) 0x19);
10365 emitAbsRegOperands(dstDisp, srcReg);
10366 if (lister != null) lister.RAR(miStart, "SBB", dstDisp, srcReg);
10367 }
10368
10369 /**
10370 * Generate a register-index--register SBB. That is,
10371 * <PRE>
10372 * [dstBase + dstIndex<<dstScale + dstDisp] -CF= srcReg
10373 * </PRE>
10374 *
10375 * @param dstBase the base register
10376 * @param dstIndex the destination index register
10377 * @param dstScale the destination shift amount
10378 * @param dstDisp the destination displacement
10379 * @param srcReg the source register
10380 */
10381 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
10382 public final void emitSBB_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
10383 int miStart = mi;
10384 // no group 1 to 4 prefix byte
10385 generateREXprefix(false, srcReg, dstIndex, dstBase);
10386 // single byte opcode
10387 setMachineCodes(mi++, (byte) 0x19);
10388 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
10389 if (lister != null) lister.RXDR(miStart, "SBB", dstBase, dstIndex, dstScale, dstDisp, srcReg);
10390 }
10391
10392 /**
10393 * Generate a register-displacement--register SBB. That is,
10394 * <PRE>
10395 * [dstBase + dstDisp] -CF= srcReg
10396 * </PRE>
10397 *
10398 * @param dstBase the base register
10399 * @param dstDisp the destination displacement
10400 * @param srcReg the source register
10401 */
10402 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
10403 public final void emitSBB_RegDisp_Reg(GPR dstBase, Offset dstDisp, GPR srcReg) {
10404 int miStart = mi;
10405 // no group 1 to 4 prefix byte
10406 generateREXprefix(false, srcReg, null, dstBase);
10407 // single byte opcode
10408 setMachineCodes(mi++, (byte) 0x19);
10409 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
10410 if (lister != null) lister.RDR(miStart, "SBB", dstBase, dstDisp, srcReg);
10411 }
10412
10413 /**
10414 * Generate a register--register SBB. That is,
10415 * <PRE>
10416 * dstReg -CF= srcReg
10417 * </PRE>
10418 *
10419 * @param dstReg the destination register
10420 * @param srcReg the source register
10421 */
10422 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
10423 public final void emitSBB_Reg_Reg(GPR dstReg, GPR srcReg) {
10424 int miStart = mi;
10425 // no group 1 to 4 prefix byte
10426 generateREXprefix(false, srcReg, null, dstReg);
10427 // single byte opcode
10428 setMachineCodes(mi++, (byte) 0x19);
10429 emitRegRegOperands(dstReg, srcReg);
10430 if (lister != null) lister.RR(miStart, "SBB", dstReg, srcReg);
10431 }
10432
10433 /**
10434 * Generate a register--register-displacement SBB. That is,
10435 * <PRE>
10436 * dstReg -CF= [srcReg + srcDisp]
10437 * </PRE>
10438 *
10439 * @param dstReg the destination register
10440 * @param srcBase the source register
10441 * @param srcDisp the source displacement
10442 */
10443 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
10444 public final void emitSBB_Reg_RegDisp(GPR dstReg, GPR srcBase, Offset srcDisp) {
10445 int miStart = mi;
10446 // no group 1 to 4 prefix byte
10447 generateREXprefix(false, dstReg, null, srcBase);
10448 // single byte opcode
10449 setMachineCodes(mi++, (byte) 0x1B);
10450 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
10451 if (lister != null) lister.RRD(miStart, "SBB", dstReg, srcBase, srcDisp);
10452 }
10453
10454 /**
10455 * Generate a register--register-offset SBB. That is,
10456 * <PRE>
10457 * dstReg -CF= [srcIndex<<srcScale + srcDisp]
10458 * </PRE>
10459 *
10460 * @param dstReg the destination register
10461 * @param srcIndex the source index register
10462 * @param srcScale the source shift amount
10463 * @param srcDisp the source displacement
10464 */
10465 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
10466 public final void emitSBB_Reg_RegOff(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
10467 int miStart = mi;
10468 // no group 1 to 4 prefix byte
10469 generateREXprefix(false, dstReg, srcIndex, null);
10470 // single byte opcode
10471 setMachineCodes(mi++, (byte) 0x1B);
10472 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
10473 if (lister != null) lister.RRFD(miStart, "SBB", dstReg, srcIndex, srcScale, srcDisp);
10474 }
10475
10476 /**
10477 * Generate a register--register-offset SBB. That is,
10478 * <PRE>
10479 * dstReg -CF= [srcDisp]
10480 * </PRE>
10481 *
10482 * @param dstReg the destination register
10483 * @param srcDisp the source displacement
10484 */
10485 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
10486 public final void emitSBB_Reg_Abs(GPR dstReg, Address srcDisp) {
10487 int miStart = mi;
10488 // no group 1 to 4 prefix byte
10489 generateREXprefix(false, dstReg, null, null);
10490 // single byte opcode
10491 setMachineCodes(mi++, (byte) 0x1B);
10492 emitAbsRegOperands(srcDisp, dstReg);
10493 if (lister != null) lister.RRA(miStart, "SBB", dstReg, srcDisp);
10494 }
10495
10496 /**
10497 * Generate a register--register-offset SBB. That is,
10498 * <PRE>
10499 * dstReg -CF= [srcBase + srcIndex<<srcScale + srcDisp]
10500 * </PRE>
10501 *
10502 * @param dstReg the destination register
10503 * @param srcBase the source base register
10504 * @param srcIndex the source index register
10505 * @param srcScale the source shift amount
10506 * @param srcDisp the source displacement
10507 */
10508 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
10509 public final void emitSBB_Reg_RegIdx(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
10510 int miStart = mi;
10511 // no group 1 to 4 prefix byte
10512 generateREXprefix(false, dstReg, srcIndex, srcBase);
10513 // single byte opcode
10514 setMachineCodes(mi++, (byte) 0x1B);
10515 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
10516 if (lister != null) lister.RRXD(miStart, "SBB", dstReg, srcBase, srcIndex, srcScale, srcDisp);
10517 }
10518
10519 /**
10520 * Generate a register--register(indirect) SBB. That is,
10521 * <PRE>
10522 * dstReg -CF= [srcBase]
10523 * </PRE>
10524 *
10525 * @param dstReg the destination register
10526 * @param srcBase the source base register
10527 */
10528 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
10529 public final void emitSBB_Reg_RegInd(GPR dstReg, GPR srcBase) {
10530 int miStart = mi;
10531 // no group 1 to 4 prefix byte
10532 generateREXprefix(false, dstReg, null, srcBase);
10533 // single byte opcode
10534 setMachineCodes(mi++, (byte) 0x1B);
10535 emitRegIndirectRegOperands(srcBase, dstReg);
10536 if (lister != null) lister.RRN(miStart, "SBB", dstReg, srcBase);
10537 }
10538
10539 /**
10540 * Generate a register(indirect)--register SBB. That is,
10541 * <PRE>
10542 * [dstBase] -CF= (word) srcReg
10543 * </PRE>
10544 *
10545 * @param dstBase the destination base
10546 * @param srcReg the source register
10547 */
10548 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
10549 public final void emitSBB_RegInd_Reg_Word(GPR dstBase, GPR srcReg) {
10550 int miStart = mi;
10551 setMachineCodes(mi++, (byte) 0x66);
10552 generateREXprefix(false, srcReg, null, dstBase);
10553 // single byte opcode
10554 setMachineCodes(mi++, (byte) 0x19);
10555 emitRegIndirectRegOperands(dstBase, srcReg);
10556 if (lister != null) lister.RNR(miStart, "SBB", dstBase, srcReg);
10557 }
10558
10559 /**
10560 * Generate a register-offset--register SBB. That is,
10561 * <PRE>
10562 * [dstReg<<dstScale + dstDisp] -CF= (word) srcReg
10563 * </PRE>
10564 *
10565 * @param dstIndex the destination index register
10566 * @param dstScale the destination shift amount
10567 * @param dstDisp the destination displacement
10568 * @param srcReg the source register
10569 */
10570 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
10571 public final void emitSBB_RegOff_Reg_Word(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
10572 int miStart = mi;
10573 setMachineCodes(mi++, (byte) 0x66);
10574 generateREXprefix(false, srcReg, dstIndex, null);
10575 // single byte opcode
10576 setMachineCodes(mi++, (byte) 0x19);
10577 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
10578 if (lister != null) lister.RFDR(miStart, "SBB", dstIndex, dstScale, dstDisp, srcReg);
10579 }
10580
10581 /**
10582 * Generate a absolute--register SBB. That is,
10583 * <PRE>
10584 * [dstDisp] -CF= (word) srcReg
10585 * </PRE>
10586 *
10587 * @param dstDisp the destination address
10588 * @param srcReg the source register
10589 */
10590 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
10591 public final void emitSBB_Abs_Reg_Word(Address dstDisp, GPR srcReg) {
10592 int miStart = mi;
10593 setMachineCodes(mi++, (byte) 0x66);
10594 generateREXprefix(false, srcReg, null, null);
10595 // single byte opcode
10596 setMachineCodes(mi++, (byte) 0x19);
10597 emitAbsRegOperands(dstDisp, srcReg);
10598 if (lister != null) lister.RAR(miStart, "SBB", dstDisp, srcReg);
10599 }
10600
10601 /**
10602 * Generate a register-index--register SBB. That is,
10603 * <PRE>
10604 * [dstBase + dstIndex<<dstScale + dstDisp] -CF= (word) srcReg
10605 * </PRE>
10606 *
10607 * @param dstBase the base register
10608 * @param dstIndex the destination index register
10609 * @param dstScale the destination shift amount
10610 * @param dstDisp the destination displacement
10611 * @param srcReg the source register
10612 */
10613 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
10614 public final void emitSBB_RegIdx_Reg_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
10615 int miStart = mi;
10616 setMachineCodes(mi++, (byte) 0x66);
10617 generateREXprefix(false, srcReg, dstIndex, dstBase);
10618 // single byte opcode
10619 setMachineCodes(mi++, (byte) 0x19);
10620 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
10621 if (lister != null) lister.RXDR(miStart, "SBB", dstBase, dstIndex, dstScale, dstDisp, srcReg);
10622 }
10623
10624 /**
10625 * Generate a register-displacement--register SBB. That is,
10626 * <PRE>
10627 * [dstBase + dstDisp] -CF= (word) srcReg
10628 * </PRE>
10629 *
10630 * @param dstBase the base register
10631 * @param dstDisp the destination displacement
10632 * @param srcReg the source register
10633 */
10634 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
10635 public final void emitSBB_RegDisp_Reg_Word(GPR dstBase, Offset dstDisp, GPR srcReg) {
10636 int miStart = mi;
10637 setMachineCodes(mi++, (byte) 0x66);
10638 generateREXprefix(false, srcReg, null, dstBase);
10639 // single byte opcode
10640 setMachineCodes(mi++, (byte) 0x19);
10641 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
10642 if (lister != null) lister.RDR(miStart, "SBB", dstBase, dstDisp, srcReg);
10643 }
10644
10645 /**
10646 * Generate a register--register SBB. That is,
10647 * <PRE>
10648 * dstReg -CF= (word) srcReg
10649 * </PRE>
10650 *
10651 * @param dstReg the destination register
10652 * @param srcReg the source register
10653 */
10654 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
10655 public final void emitSBB_Reg_Reg_Word(GPR dstReg, GPR srcReg) {
10656 int miStart = mi;
10657 setMachineCodes(mi++, (byte) 0x66);
10658 generateREXprefix(false, srcReg, null, dstReg);
10659 // single byte opcode
10660 setMachineCodes(mi++, (byte) 0x19);
10661 emitRegRegOperands(dstReg, srcReg);
10662 if (lister != null) lister.RR(miStart, "SBB", dstReg, srcReg);
10663 }
10664
10665 /**
10666 * Generate a register--register-displacement SBB. That is,
10667 * <PRE>
10668 * dstReg -CF= (word) [srcReg + srcDisp]
10669 * </PRE>
10670 *
10671 * @param dstReg the destination register
10672 * @param srcBase the source register
10673 * @param srcDisp the source displacement
10674 */
10675 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
10676 public final void emitSBB_Reg_RegDisp_Word(GPR dstReg, GPR srcBase, Offset srcDisp) {
10677 int miStart = mi;
10678 setMachineCodes(mi++, (byte) 0x66);
10679 generateREXprefix(false, dstReg, null, srcBase);
10680 // single byte opcode
10681 setMachineCodes(mi++, (byte) 0x1B);
10682 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
10683 if (lister != null) lister.RRD(miStart, "SBB", dstReg, srcBase, srcDisp);
10684 }
10685
10686 /**
10687 * Generate a register--register-offset SBB. That is,
10688 * <PRE>
10689 * dstReg -CF= (word) [srcIndex<<srcScale + srcDisp]
10690 * </PRE>
10691 *
10692 * @param dstReg the destination register
10693 * @param srcIndex the source index register
10694 * @param srcScale the source shift amount
10695 * @param srcDisp the source displacement
10696 */
10697 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
10698 public final void emitSBB_Reg_RegOff_Word(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
10699 int miStart = mi;
10700 setMachineCodes(mi++, (byte) 0x66);
10701 generateREXprefix(false, dstReg, srcIndex, null);
10702 // single byte opcode
10703 setMachineCodes(mi++, (byte) 0x1B);
10704 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
10705 if (lister != null) lister.RRFD(miStart, "SBB", dstReg, srcIndex, srcScale, srcDisp);
10706 }
10707
10708 /**
10709 * Generate a register--register-offset SBB. That is,
10710 * <PRE>
10711 * dstReg -CF= (word) [srcDisp]
10712 * </PRE>
10713 *
10714 * @param dstReg the destination register
10715 * @param srcDisp the source displacement
10716 */
10717 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
10718 public final void emitSBB_Reg_Abs_Word(GPR dstReg, Address srcDisp) {
10719 int miStart = mi;
10720 setMachineCodes(mi++, (byte) 0x66);
10721 generateREXprefix(false, dstReg, null, null);
10722 // single byte opcode
10723 setMachineCodes(mi++, (byte) 0x1B);
10724 emitAbsRegOperands(srcDisp, dstReg);
10725 if (lister != null) lister.RRA(miStart, "SBB", dstReg, srcDisp);
10726 }
10727
10728 /**
10729 * Generate a register--register-offset SBB. That is,
10730 * <PRE>
10731 * dstReg -CF= (word) [srcBase + srcIndex<<srcScale + srcDisp]
10732 * </PRE>
10733 *
10734 * @param dstReg the destination register
10735 * @param srcBase the source base register
10736 * @param srcIndex the source index register
10737 * @param srcScale the source shift amount
10738 * @param srcDisp the source displacement
10739 */
10740 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
10741 public final void emitSBB_Reg_RegIdx_Word(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
10742 int miStart = mi;
10743 setMachineCodes(mi++, (byte) 0x66);
10744 generateREXprefix(false, dstReg, srcIndex, srcBase);
10745 // single byte opcode
10746 setMachineCodes(mi++, (byte) 0x1B);
10747 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
10748 if (lister != null) lister.RRXD(miStart, "SBB", dstReg, srcBase, srcIndex, srcScale, srcDisp);
10749 }
10750
10751 /**
10752 * Generate a register--register(indirect) SBB. That is,
10753 * <PRE>
10754 * dstReg -CF= (word) [srcBase]
10755 * </PRE>
10756 *
10757 * @param dstReg the destination register
10758 * @param srcBase the source base register
10759 */
10760 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
10761 public final void emitSBB_Reg_RegInd_Word(GPR dstReg, GPR srcBase) {
10762 int miStart = mi;
10763 setMachineCodes(mi++, (byte) 0x66);
10764 generateREXprefix(false, dstReg, null, srcBase);
10765 // single byte opcode
10766 setMachineCodes(mi++, (byte) 0x1B);
10767 emitRegIndirectRegOperands(srcBase, dstReg);
10768 if (lister != null) lister.RRN(miStart, "SBB", dstReg, srcBase);
10769 }
10770
10771 /**
10772 * Generate a register(indirect)--register SBB. That is,
10773 * <PRE>
10774 * [dstBase] -CF= (quad) srcReg
10775 * </PRE>
10776 *
10777 * @param dstBase the destination base
10778 * @param srcReg the source register
10779 */
10780 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
10781 public final void emitSBB_RegInd_Reg_Quad(GPR dstBase, GPR srcReg) {
10782 int miStart = mi;
10783 // no group 1 to 4 prefix byte
10784 generateREXprefix(true, srcReg, null, dstBase);
10785 // single byte opcode
10786 setMachineCodes(mi++, (byte) 0x19);
10787 emitRegIndirectRegOperands(dstBase, srcReg);
10788 if (lister != null) lister.RNR(miStart, "SBB", dstBase, srcReg);
10789 }
10790
10791 /**
10792 * Generate a register-offset--register SBB. That is,
10793 * <PRE>
10794 * [dstReg<<dstScale + dstDisp] -CF= (quad) srcReg
10795 * </PRE>
10796 *
10797 * @param dstIndex the destination index register
10798 * @param dstScale the destination shift amount
10799 * @param dstDisp the destination displacement
10800 * @param srcReg the source register
10801 */
10802 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
10803 public final void emitSBB_RegOff_Reg_Quad(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
10804 int miStart = mi;
10805 // no group 1 to 4 prefix byte
10806 generateREXprefix(true, srcReg, dstIndex, null);
10807 // single byte opcode
10808 setMachineCodes(mi++, (byte) 0x19);
10809 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
10810 if (lister != null) lister.RFDR(miStart, "SBB", dstIndex, dstScale, dstDisp, srcReg);
10811 }
10812
10813 /**
10814 * Generate a absolute--register SBB. That is,
10815 * <PRE>
10816 * [dstDisp] -CF= (quad) srcReg
10817 * </PRE>
10818 *
10819 * @param dstDisp the destination address
10820 * @param srcReg the source register
10821 */
10822 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
10823 public final void emitSBB_Abs_Reg_Quad(Address dstDisp, GPR srcReg) {
10824 int miStart = mi;
10825 // no group 1 to 4 prefix byte
10826 generateREXprefix(true, srcReg, null, null);
10827 // single byte opcode
10828 setMachineCodes(mi++, (byte) 0x19);
10829 emitAbsRegOperands(dstDisp, srcReg);
10830 if (lister != null) lister.RAR(miStart, "SBB", dstDisp, srcReg);
10831 }
10832
10833 /**
10834 * Generate a register-index--register SBB. That is,
10835 * <PRE>
10836 * [dstBase + dstIndex<<dstScale + dstDisp] -CF= (quad) srcReg
10837 * </PRE>
10838 *
10839 * @param dstBase the base register
10840 * @param dstIndex the destination index register
10841 * @param dstScale the destination shift amount
10842 * @param dstDisp the destination displacement
10843 * @param srcReg the source register
10844 */
10845 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
10846 public final void emitSBB_RegIdx_Reg_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
10847 int miStart = mi;
10848 // no group 1 to 4 prefix byte
10849 generateREXprefix(true, srcReg, dstIndex, dstBase);
10850 // single byte opcode
10851 setMachineCodes(mi++, (byte) 0x19);
10852 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
10853 if (lister != null) lister.RXDR(miStart, "SBB", dstBase, dstIndex, dstScale, dstDisp, srcReg);
10854 }
10855
10856 /**
10857 * Generate a register-displacement--register SBB. That is,
10858 * <PRE>
10859 * [dstBase + dstDisp] -CF= (quad) srcReg
10860 * </PRE>
10861 *
10862 * @param dstBase the base register
10863 * @param dstDisp the destination displacement
10864 * @param srcReg the source register
10865 */
10866 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
10867 public final void emitSBB_RegDisp_Reg_Quad(GPR dstBase, Offset dstDisp, GPR srcReg) {
10868 int miStart = mi;
10869 // no group 1 to 4 prefix byte
10870 generateREXprefix(true, srcReg, null, dstBase);
10871 // single byte opcode
10872 setMachineCodes(mi++, (byte) 0x19);
10873 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
10874 if (lister != null) lister.RDR(miStart, "SBB", dstBase, dstDisp, srcReg);
10875 }
10876
10877 /**
10878 * Generate a register--register SBB. That is,
10879 * <PRE>
10880 * dstReg -CF= (quad) srcReg
10881 * </PRE>
10882 *
10883 * @param dstReg the destination register
10884 * @param srcReg the source register
10885 */
10886 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
10887 public final void emitSBB_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
10888 int miStart = mi;
10889 // no group 1 to 4 prefix byte
10890 generateREXprefix(true, srcReg, null, dstReg);
10891 // single byte opcode
10892 setMachineCodes(mi++, (byte) 0x19);
10893 emitRegRegOperands(dstReg, srcReg);
10894 if (lister != null) lister.RR(miStart, "SBB", dstReg, srcReg);
10895 }
10896
10897 /**
10898 * Generate a register--register-displacement SBB. That is,
10899 * <PRE>
10900 * dstReg -CF= (quad) [srcReg + srcDisp]
10901 * </PRE>
10902 *
10903 * @param dstReg the destination register
10904 * @param srcBase the source register
10905 * @param srcDisp the source displacement
10906 */
10907 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
10908 public final void emitSBB_Reg_RegDisp_Quad(GPR dstReg, GPR srcBase, Offset srcDisp) {
10909 int miStart = mi;
10910 // no group 1 to 4 prefix byte
10911 generateREXprefix(true, dstReg, null, srcBase);
10912 // single byte opcode
10913 setMachineCodes(mi++, (byte) 0x1B);
10914 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
10915 if (lister != null) lister.RRD(miStart, "SBB", dstReg, srcBase, srcDisp);
10916 }
10917
10918 /**
10919 * Generate a register--register-offset SBB. That is,
10920 * <PRE>
10921 * dstReg -CF= (quad) [srcIndex<<srcScale + srcDisp]
10922 * </PRE>
10923 *
10924 * @param dstReg the destination register
10925 * @param srcIndex the source index register
10926 * @param srcScale the source shift amount
10927 * @param srcDisp the source displacement
10928 */
10929 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
10930 public final void emitSBB_Reg_RegOff_Quad(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
10931 int miStart = mi;
10932 // no group 1 to 4 prefix byte
10933 generateREXprefix(true, dstReg, srcIndex, null);
10934 // single byte opcode
10935 setMachineCodes(mi++, (byte) 0x1B);
10936 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
10937 if (lister != null) lister.RRFD(miStart, "SBB", dstReg, srcIndex, srcScale, srcDisp);
10938 }
10939
10940 /**
10941 * Generate a register--register-offset SBB. That is,
10942 * <PRE>
10943 * dstReg -CF= (quad) [srcDisp]
10944 * </PRE>
10945 *
10946 * @param dstReg the destination register
10947 * @param srcDisp the source displacement
10948 */
10949 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
10950 public final void emitSBB_Reg_Abs_Quad(GPR dstReg, Address srcDisp) {
10951 int miStart = mi;
10952 // no group 1 to 4 prefix byte
10953 generateREXprefix(true, dstReg, null, null);
10954 // single byte opcode
10955 setMachineCodes(mi++, (byte) 0x1B);
10956 emitAbsRegOperands(srcDisp, dstReg);
10957 if (lister != null) lister.RRA(miStart, "SBB", dstReg, srcDisp);
10958 }
10959
10960 /**
10961 * Generate a register--register-offset SBB. That is,
10962 * <PRE>
10963 * dstReg -CF= (quad) [srcBase + srcIndex<<srcScale + srcDisp]
10964 * </PRE>
10965 *
10966 * @param dstReg the destination register
10967 * @param srcBase the source base register
10968 * @param srcIndex the source index register
10969 * @param srcScale the source shift amount
10970 * @param srcDisp the source displacement
10971 */
10972 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
10973 public final void emitSBB_Reg_RegIdx_Quad(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
10974 int miStart = mi;
10975 // no group 1 to 4 prefix byte
10976 generateREXprefix(true, dstReg, srcIndex, srcBase);
10977 // single byte opcode
10978 setMachineCodes(mi++, (byte) 0x1B);
10979 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
10980 if (lister != null) lister.RRXD(miStart, "SBB", dstReg, srcBase, srcIndex, srcScale, srcDisp);
10981 }
10982
10983 /**
10984 * Generate a register--register(indirect) SBB. That is,
10985 * <PRE>
10986 * dstReg -CF= (quad) [srcBase]
10987 * </PRE>
10988 *
10989 * @param dstReg the destination register
10990 * @param srcBase the source base register
10991 */
10992 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
10993 public final void emitSBB_Reg_RegInd_Quad(GPR dstReg, GPR srcBase) {
10994 int miStart = mi;
10995 // no group 1 to 4 prefix byte
10996 generateREXprefix(true, dstReg, null, srcBase);
10997 // single byte opcode
10998 setMachineCodes(mi++, (byte) 0x1B);
10999 emitRegIndirectRegOperands(srcBase, dstReg);
11000 if (lister != null) lister.RRN(miStart, "SBB", dstReg, srcBase);
11001 }
11002
11003 /**
11004 * Generate a register(indirect)--register SBB. That is,
11005 * <PRE>
11006 * [dstBase] -CF= (byte) srcReg
11007 * </PRE>
11008 *
11009 * @param dstBase the destination base
11010 * @param srcReg the source register
11011 */
11012 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
11013 public final void emitSBB_RegInd_Reg_Byte(GPR dstBase, GPR srcReg) {
11014 int miStart = mi;
11015 // no group 1 to 4 prefix byte
11016 generateREXprefix(false, srcReg, null, dstBase);
11017 // single byte opcode
11018 setMachineCodes(mi++, (byte) 0x18);
11019 emitRegIndirectRegOperands(dstBase, srcReg);
11020 if (lister != null) lister.RNR(miStart, "SBB", dstBase, srcReg);
11021 }
11022
11023 /**
11024 * Generate a register-offset--register SBB. That is,
11025 * <PRE>
11026 * [dstReg<<dstScale + dstDisp] -CF= (byte) srcReg
11027 * </PRE>
11028 *
11029 * @param dstIndex the destination index register
11030 * @param dstScale the destination shift amount
11031 * @param dstDisp the destination displacement
11032 * @param srcReg the source register
11033 */
11034 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
11035 public final void emitSBB_RegOff_Reg_Byte(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
11036 int miStart = mi;
11037 // no group 1 to 4 prefix byte
11038 generateREXprefix(false, srcReg, dstIndex, null);
11039 // single byte opcode
11040 setMachineCodes(mi++, (byte) 0x18);
11041 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
11042 if (lister != null) lister.RFDR(miStart, "SBB", dstIndex, dstScale, dstDisp, srcReg);
11043 }
11044
11045 /**
11046 * Generate a absolute--register SBB. That is,
11047 * <PRE>
11048 * [dstDisp] -CF= (byte) srcReg
11049 * </PRE>
11050 *
11051 * @param dstDisp the destination address
11052 * @param srcReg the source register
11053 */
11054 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
11055 public final void emitSBB_Abs_Reg_Byte(Address dstDisp, GPR srcReg) {
11056 int miStart = mi;
11057 // no group 1 to 4 prefix byte
11058 generateREXprefix(false, srcReg, null, null);
11059 // single byte opcode
11060 setMachineCodes(mi++, (byte) 0x18);
11061 emitAbsRegOperands(dstDisp, srcReg);
11062 if (lister != null) lister.RAR(miStart, "SBB", dstDisp, srcReg);
11063 }
11064
11065 /**
11066 * Generate a register-index--register SBB. That is,
11067 * <PRE>
11068 * [dstBase + dstIndex<<dstScale + dstDisp] -CF= (byte) srcReg
11069 * </PRE>
11070 *
11071 * @param dstBase the base register
11072 * @param dstIndex the destination index register
11073 * @param dstScale the destination shift amount
11074 * @param dstDisp the destination displacement
11075 * @param srcReg the source register
11076 */
11077 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
11078 public final void emitSBB_RegIdx_Reg_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
11079 int miStart = mi;
11080 // no group 1 to 4 prefix byte
11081 generateREXprefix(false, srcReg, dstIndex, dstBase);
11082 // single byte opcode
11083 setMachineCodes(mi++, (byte) 0x18);
11084 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
11085 if (lister != null) lister.RXDR(miStart, "SBB", dstBase, dstIndex, dstScale, dstDisp, srcReg);
11086 }
11087
11088 /**
11089 * Generate a register-displacement--register SBB. That is,
11090 * <PRE>
11091 * [dstBase + dstDisp] -CF= (byte) srcReg
11092 * </PRE>
11093 *
11094 * @param dstBase the base register
11095 * @param dstDisp the destination displacement
11096 * @param srcReg the source register
11097 */
11098 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
11099 public final void emitSBB_RegDisp_Reg_Byte(GPR dstBase, Offset dstDisp, GPR srcReg) {
11100 int miStart = mi;
11101 // no group 1 to 4 prefix byte
11102 generateREXprefix(false, srcReg, null, dstBase);
11103 // single byte opcode
11104 setMachineCodes(mi++, (byte) 0x18);
11105 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
11106 if (lister != null) lister.RDR(miStart, "SBB", dstBase, dstDisp, srcReg);
11107 }
11108
11109 /**
11110 * Generate a register--register SBB. That is,
11111 * <PRE>
11112 * dstReg -CF= (byte) srcReg
11113 * </PRE>
11114 *
11115 * @param dstReg the destination register
11116 * @param srcReg the source register
11117 */
11118 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
11119 public final void emitSBB_Reg_Reg_Byte(GPR dstReg, GPR srcReg) {
11120 int miStart = mi;
11121 // no group 1 to 4 prefix byte
11122 generateREXprefix(false, srcReg, null, dstReg);
11123 // single byte opcode
11124 setMachineCodes(mi++, (byte) 0x18);
11125 emitRegRegOperands(dstReg, srcReg);
11126 if (lister != null) lister.RR(miStart, "SBB", dstReg, srcReg);
11127 }
11128
11129 /**
11130 * Generate a register--register-displacement SBB. That is,
11131 * <PRE>
11132 * dstReg -CF= (byte) [srcReg + srcDisp]
11133 * </PRE>
11134 *
11135 * @param dstReg the destination register
11136 * @param srcBase the source register
11137 * @param srcDisp the source displacement
11138 */
11139 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
11140 public final void emitSBB_Reg_RegDisp_Byte(GPR dstReg, GPR srcBase, Offset srcDisp) {
11141 int miStart = mi;
11142 // no group 1 to 4 prefix byte
11143 generateREXprefix(false, dstReg, null, srcBase);
11144 // single byte opcode
11145 setMachineCodes(mi++, (byte) 0x1A);
11146 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
11147 if (lister != null) lister.RRD(miStart, "SBB", dstReg, srcBase, srcDisp);
11148 }
11149
11150 /**
11151 * Generate a register--register-offset SBB. That is,
11152 * <PRE>
11153 * dstReg -CF= (byte) [srcIndex<<srcScale + srcDisp]
11154 * </PRE>
11155 *
11156 * @param dstReg the destination register
11157 * @param srcIndex the source index register
11158 * @param srcScale the source shift amount
11159 * @param srcDisp the source displacement
11160 */
11161 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
11162 public final void emitSBB_Reg_RegOff_Byte(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
11163 int miStart = mi;
11164 // no group 1 to 4 prefix byte
11165 generateREXprefix(false, dstReg, srcIndex, null);
11166 // single byte opcode
11167 setMachineCodes(mi++, (byte) 0x1A);
11168 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
11169 if (lister != null) lister.RRFD(miStart, "SBB", dstReg, srcIndex, srcScale, srcDisp);
11170 }
11171
11172 /**
11173 * Generate a register--register-offset SBB. That is,
11174 * <PRE>
11175 * dstReg -CF= (byte) [srcDisp]
11176 * </PRE>
11177 *
11178 * @param dstReg the destination register
11179 * @param srcDisp the source displacement
11180 */
11181 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
11182 public final void emitSBB_Reg_Abs_Byte(GPR dstReg, Address srcDisp) {
11183 int miStart = mi;
11184 // no group 1 to 4 prefix byte
11185 generateREXprefix(false, dstReg, null, null);
11186 // single byte opcode
11187 setMachineCodes(mi++, (byte) 0x1A);
11188 emitAbsRegOperands(srcDisp, dstReg);
11189 if (lister != null) lister.RRA(miStart, "SBB", dstReg, srcDisp);
11190 }
11191
11192 /**
11193 * Generate a register--register-offset SBB. That is,
11194 * <PRE>
11195 * dstReg -CF= (byte) [srcBase + srcIndex<<srcScale + srcDisp]
11196 * </PRE>
11197 *
11198 * @param dstReg the destination register
11199 * @param srcBase the source base register
11200 * @param srcIndex the source index register
11201 * @param srcScale the source shift amount
11202 * @param srcDisp the source displacement
11203 */
11204 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
11205 public final void emitSBB_Reg_RegIdx_Byte(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
11206 int miStart = mi;
11207 // no group 1 to 4 prefix byte
11208 generateREXprefix(false, dstReg, srcIndex, srcBase);
11209 // single byte opcode
11210 setMachineCodes(mi++, (byte) 0x1A);
11211 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
11212 if (lister != null) lister.RRXD(miStart, "SBB", dstReg, srcBase, srcIndex, srcScale, srcDisp);
11213 }
11214
11215 /**
11216 * Generate a register--register(indirect) SBB. That is,
11217 * <PRE>
11218 * dstReg -CF= (byte) [srcBase]
11219 * </PRE>
11220 *
11221 * @param dstReg the destination register
11222 * @param srcBase the source base register
11223 */
11224 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
11225 public final void emitSBB_Reg_RegInd_Byte(GPR dstReg, GPR srcBase) {
11226 int miStart = mi;
11227 // no group 1 to 4 prefix byte
11228 generateREXprefix(false, dstReg, null, srcBase);
11229 // single byte opcode
11230 setMachineCodes(mi++, (byte) 0x1A);
11231 emitRegIndirectRegOperands(srcBase, dstReg);
11232 if (lister != null) lister.RRN(miStart, "SBB", dstReg, srcBase);
11233 }
11234
11235 /**
11236 * Generate a register--immediate SBB. That is,
11237 * <PRE>
11238 * dstReg -CF= imm
11239 * </PRE>
11240 *
11241 * @param dstReg the destination register
11242 * @param imm immediate
11243 */
11244 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
11245 public final void emitSBB_Reg_Imm(GPR dstReg, int imm) {
11246 int miStart = mi;
11247 // no group 1 to 4 prefix byte
11248 generateREXprefix(false, null, null, dstReg);
11249 // single byte opcode
11250 if (fits(imm,8)) {
11251 setMachineCodes(mi++, (byte) 0x83);
11252 // "register 0x3" is really part of the opcode
11253 emitRegRegOperands(dstReg, GPR.getForOpcode(0x3));
11254 emitImm8((byte)imm);
11255 } else if (dstReg == EAX) {
11256 setMachineCodes(mi++, (byte) 0x1D);
11257 emitImm32(imm);
11258 } else {
11259 setMachineCodes(mi++, (byte) 0x81);
11260 // "register 0x3" is really part of the opcode
11261 emitRegRegOperands(dstReg, GPR.getForOpcode(0x3));
11262 emitImm32(imm);
11263 }
11264 if (lister != null) lister.RI(miStart, "SBB", dstReg, imm);
11265 }
11266
11267 /**
11268 * Generate a register-displacement--immediate SBB. That is,
11269 * <PRE>
11270 * [dstBase + dstDisp] -CF= imm
11271 * </PRE>
11272 *
11273 * @param dstBase the destination register
11274 * @param dstDisp the destination displacement
11275 * @param imm immediate
11276 */
11277 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
11278 public final void emitSBB_RegDisp_Imm(GPR dstBase, Offset dstDisp, int imm) {
11279 int miStart = mi;
11280 // no group 1 to 4 prefix byte
11281 generateREXprefix(false, null, null, dstBase);
11282 // single byte opcode
11283 if (fits(imm,8)) {
11284 setMachineCodes(mi++, (byte) 0x83);
11285 // "register 0x3" is really part of the opcode
11286 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x3));
11287 emitImm8((byte)imm);
11288 } else {
11289 setMachineCodes(mi++, (byte) 0x81);
11290 // "register 0x3" is really part of the opcode
11291 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x3));
11292 emitImm32(imm);
11293 }
11294 if (lister != null) lister.RDI(miStart, "SBB", dstBase, dstDisp, imm);
11295 }
11296
11297 /**
11298 * Generate a register-offset--immediate SBB. That is,
11299 * <PRE>
11300 * [dstIndex<<dstScale + dstDisp] -CF= imm
11301 * </PRE>
11302 *
11303 * @param dstIndex the destination index register
11304 * @param dstScale the destination shift amount
11305 * @param dstDisp the destination displacement
11306 * @param imm immediate
11307 */
11308 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
11309 public final void emitSBB_RegOff_Imm(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
11310 int miStart = mi;
11311 // no group 1 to 4 prefix byte
11312 generateREXprefix(false, null, dstIndex, null);
11313 // single byte opcode
11314 if (fits(imm,8)) {
11315 setMachineCodes(mi++, (byte) 0x83);
11316 // "register 0x3" is really part of the opcode
11317 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
11318 emitImm8((byte)imm);
11319 } else {
11320 setMachineCodes(mi++, (byte) 0x81);
11321 // "register 0x3" is really part of the opcode
11322 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
11323 emitImm32(imm);
11324 }
11325 if (lister != null) lister.RFDI(miStart, "SBB", dstIndex, dstScale, dstDisp, imm);
11326 }
11327
11328 /**
11329 * Generate a absolute--immediate SBB. That is,
11330 * <PRE>
11331 * [dstDisp] -CF= imm
11332 * </PRE>
11333 *
11334 * @param dstDisp the destination displacement
11335 * @param imm immediate
11336 */
11337 public final void emitSBB_Abs_Imm(Address dstDisp, int imm) {
11338 int miStart = mi;
11339 // no group 1 to 4 prefix byte
11340 generateREXprefix(false, null, null, null);
11341 // single byte opcode
11342 if (fits(imm,8)) {
11343 setMachineCodes(mi++, (byte) 0x83);
11344 // "register 0x3" is really part of the opcode
11345 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x3));
11346 emitImm8((byte)imm);
11347 } else {
11348 setMachineCodes(mi++, (byte) 0x81);
11349 // "register 0x3" is really part of the opcode
11350 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x3));
11351 emitImm32(imm);
11352 }
11353 if (lister != null) lister.RAI(miStart, "SBB", dstDisp, imm);
11354 }
11355
11356 /**
11357 * Generate a register-index--immediate SBB. That is,
11358 * <PRE>
11359 * [dstBase + dstIndex<<dstScale + dstDisp] -CF= imm
11360 * </PRE>
11361 *
11362 * @param dstBase the destination base register
11363 * @param dstIndex the destination index register
11364 * @param dstScale the destination shift amount
11365 * @param dstDisp the destination displacement
11366 * @param imm immediate
11367 */
11368 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
11369 public final void emitSBB_RegIdx_Imm(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
11370 int miStart = mi;
11371 // no group 1 to 4 prefix byte
11372 generateREXprefix(false, null, dstIndex, dstBase);
11373 // single byte opcode
11374 if (fits(imm,8)) {
11375 setMachineCodes(mi++, (byte) 0x83);
11376 // "register 0x3" is really part of the opcode
11377 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
11378 emitImm8((byte)imm);
11379 } else {
11380 setMachineCodes(mi++, (byte) 0x81);
11381 // "register 0x3" is really part of the opcode
11382 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
11383 emitImm32(imm);
11384 }
11385 if (lister != null) lister.RXDI(miStart, "SBB", dstBase, dstIndex, dstScale, dstDisp, imm);
11386 }
11387
11388 /**
11389 * Generate a register(indirect)--immediate SBB. That is,
11390 * <PRE>
11391 * [dstBase] -CF= imm
11392 * </PRE>
11393 *
11394 * @param dstBase the destination base register
11395 * @param imm immediate
11396 */
11397 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
11398 public final void emitSBB_RegInd_Imm(GPR dstBase, int imm) {
11399 int miStart = mi;
11400 // no group 1 to 4 prefix byte
11401 generateREXprefix(false, null, null, dstBase);
11402 // single byte opcode
11403 if (fits(imm,8)) {
11404 setMachineCodes(mi++, (byte) 0x83);
11405 // "register 0x3" is really part of the opcode
11406 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x3));
11407 emitImm8((byte)imm);
11408 } else {
11409 setMachineCodes(mi++, (byte) 0x81);
11410 // "register 0x3" is really part of the opcode
11411 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x3));
11412 emitImm32(imm);
11413 }
11414 if (lister != null) lister.RNI(miStart, "SBB", dstBase, imm);
11415 }
11416
11417 /**
11418 * Generate a register--immediate SBB. That is,
11419 * <PRE>
11420 * dstReg -CF= (word) imm
11421 * </PRE>
11422 *
11423 * @param dstReg the destination register
11424 * @param imm immediate
11425 */
11426 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
11427 public final void emitSBB_Reg_Imm_Word(GPR dstReg, int imm) {
11428 int miStart = mi;
11429 setMachineCodes(mi++, (byte) 0x66);
11430 generateREXprefix(false, null, null, dstReg);
11431 // single byte opcode
11432 if (fits(imm,8)) {
11433 setMachineCodes(mi++, (byte) 0x83);
11434 // "register 0x3" is really part of the opcode
11435 emitRegRegOperands(dstReg, GPR.getForOpcode(0x3));
11436 emitImm8((byte)imm);
11437 } else if (dstReg == EAX) {
11438 setMachineCodes(mi++, (byte) 0x1D);
11439 emitImm16(imm);
11440 } else {
11441 setMachineCodes(mi++, (byte) 0x81);
11442 // "register 0x3" is really part of the opcode
11443 emitRegRegOperands(dstReg, GPR.getForOpcode(0x3));
11444 emitImm16(imm);
11445 }
11446 if (lister != null) lister.RI(miStart, "SBB", dstReg, imm);
11447 }
11448
11449 /**
11450 * Generate a register-displacement--immediate SBB. That is,
11451 * <PRE>
11452 * [dstBase + dstDisp] -CF= (word) imm
11453 * </PRE>
11454 *
11455 * @param dstBase the destination register
11456 * @param dstDisp the destination displacement
11457 * @param imm immediate
11458 */
11459 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
11460 public final void emitSBB_RegDisp_Imm_Word(GPR dstBase, Offset dstDisp, int imm) {
11461 int miStart = mi;
11462 setMachineCodes(mi++, (byte) 0x66);
11463 generateREXprefix(false, null, null, dstBase);
11464 // single byte opcode
11465 if (fits(imm,8)) {
11466 setMachineCodes(mi++, (byte) 0x83);
11467 // "register 0x3" is really part of the opcode
11468 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x3));
11469 emitImm8((byte)imm);
11470 } else {
11471 setMachineCodes(mi++, (byte) 0x81);
11472 // "register 0x3" is really part of the opcode
11473 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x3));
11474 emitImm16(imm);
11475 }
11476 if (lister != null) lister.RDI(miStart, "SBB", dstBase, dstDisp, imm);
11477 }
11478
11479 /**
11480 * Generate a register-offset--immediate SBB. That is,
11481 * <PRE>
11482 * [dstIndex<<dstScale + dstDisp] -CF= (word) imm
11483 * </PRE>
11484 *
11485 * @param dstIndex the destination index register
11486 * @param dstScale the destination shift amount
11487 * @param dstDisp the destination displacement
11488 * @param imm immediate
11489 */
11490 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
11491 public final void emitSBB_RegOff_Imm_Word(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
11492 int miStart = mi;
11493 setMachineCodes(mi++, (byte) 0x66);
11494 generateREXprefix(false, null, dstIndex, null);
11495 // single byte opcode
11496 if (fits(imm,8)) {
11497 setMachineCodes(mi++, (byte) 0x83);
11498 // "register 0x3" is really part of the opcode
11499 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
11500 emitImm8((byte)imm);
11501 } else {
11502 setMachineCodes(mi++, (byte) 0x81);
11503 // "register 0x3" is really part of the opcode
11504 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
11505 emitImm16(imm);
11506 }
11507 if (lister != null) lister.RFDI(miStart, "SBB", dstIndex, dstScale, dstDisp, imm);
11508 }
11509
11510 /**
11511 * Generate a absolute--immediate SBB. That is,
11512 * <PRE>
11513 * [dstDisp] -CF= (word) imm
11514 * </PRE>
11515 *
11516 * @param dstDisp the destination displacement
11517 * @param imm immediate
11518 */
11519 public final void emitSBB_Abs_Imm_Word(Address dstDisp, int imm) {
11520 int miStart = mi;
11521 setMachineCodes(mi++, (byte) 0x66);
11522 generateREXprefix(false, null, null, null);
11523 // single byte opcode
11524 if (fits(imm,8)) {
11525 setMachineCodes(mi++, (byte) 0x83);
11526 // "register 0x3" is really part of the opcode
11527 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x3));
11528 emitImm8((byte)imm);
11529 } else {
11530 setMachineCodes(mi++, (byte) 0x81);
11531 // "register 0x3" is really part of the opcode
11532 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x3));
11533 emitImm16(imm);
11534 }
11535 if (lister != null) lister.RAI(miStart, "SBB", dstDisp, imm);
11536 }
11537
11538 /**
11539 * Generate a register-index--immediate SBB. That is,
11540 * <PRE>
11541 * [dstBase + dstIndex<<dstScale + dstDisp] -CF= (word) imm
11542 * </PRE>
11543 *
11544 * @param dstBase the destination base register
11545 * @param dstIndex the destination index register
11546 * @param dstScale the destination shift amount
11547 * @param dstDisp the destination displacement
11548 * @param imm immediate
11549 */
11550 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
11551 public final void emitSBB_RegIdx_Imm_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
11552 int miStart = mi;
11553 setMachineCodes(mi++, (byte) 0x66);
11554 generateREXprefix(false, null, dstIndex, dstBase);
11555 // single byte opcode
11556 if (fits(imm,8)) {
11557 setMachineCodes(mi++, (byte) 0x83);
11558 // "register 0x3" is really part of the opcode
11559 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
11560 emitImm8((byte)imm);
11561 } else {
11562 setMachineCodes(mi++, (byte) 0x81);
11563 // "register 0x3" is really part of the opcode
11564 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
11565 emitImm16(imm);
11566 }
11567 if (lister != null) lister.RXDI(miStart, "SBB", dstBase, dstIndex, dstScale, dstDisp, imm);
11568 }
11569
11570 /**
11571 * Generate a register(indirect)--immediate SBB. That is,
11572 * <PRE>
11573 * [dstBase] -CF= (word) imm
11574 * </PRE>
11575 *
11576 * @param dstBase the destination base register
11577 * @param imm immediate
11578 */
11579 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
11580 public final void emitSBB_RegInd_Imm_Word(GPR dstBase, int imm) {
11581 int miStart = mi;
11582 setMachineCodes(mi++, (byte) 0x66);
11583 generateREXprefix(false, null, null, dstBase);
11584 // single byte opcode
11585 if (fits(imm,8)) {
11586 setMachineCodes(mi++, (byte) 0x83);
11587 // "register 0x3" is really part of the opcode
11588 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x3));
11589 emitImm8((byte)imm);
11590 } else {
11591 setMachineCodes(mi++, (byte) 0x81);
11592 // "register 0x3" is really part of the opcode
11593 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x3));
11594 emitImm16(imm);
11595 }
11596 if (lister != null) lister.RNI(miStart, "SBB", dstBase, imm);
11597 }
11598
11599 /**
11600 * Generate a register--immediate SBB. That is,
11601 * <PRE>
11602 * dstReg -CF= (quad) imm
11603 * </PRE>
11604 *
11605 * @param dstReg the destination register
11606 * @param imm immediate
11607 */
11608 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
11609 public final void emitSBB_Reg_Imm_Quad(GPR dstReg, int imm) {
11610 int miStart = mi;
11611 // no group 1 to 4 prefix byte
11612 generateREXprefix(true, null, null, dstReg);
11613 // single byte opcode
11614 if (fits(imm,8)) {
11615 setMachineCodes(mi++, (byte) 0x83);
11616 // "register 0x3" is really part of the opcode
11617 emitRegRegOperands(dstReg, GPR.getForOpcode(0x3));
11618 emitImm8((byte)imm);
11619 } else if (dstReg == EAX) {
11620 setMachineCodes(mi++, (byte) 0x1D);
11621 emitImm32(imm);
11622 } else {
11623 setMachineCodes(mi++, (byte) 0x81);
11624 // "register 0x3" is really part of the opcode
11625 emitRegRegOperands(dstReg, GPR.getForOpcode(0x3));
11626 emitImm32(imm);
11627 }
11628 if (lister != null) lister.RI(miStart, "SBB", dstReg, imm);
11629 }
11630
11631 /**
11632 * Generate a register-displacement--immediate SBB. That is,
11633 * <PRE>
11634 * [dstBase + dstDisp] -CF= (quad) imm
11635 * </PRE>
11636 *
11637 * @param dstBase the destination register
11638 * @param dstDisp the destination displacement
11639 * @param imm immediate
11640 */
11641 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
11642 public final void emitSBB_RegDisp_Imm_Quad(GPR dstBase, Offset dstDisp, int imm) {
11643 int miStart = mi;
11644 // no group 1 to 4 prefix byte
11645 generateREXprefix(true, null, null, dstBase);
11646 // single byte opcode
11647 if (fits(imm,8)) {
11648 setMachineCodes(mi++, (byte) 0x83);
11649 // "register 0x3" is really part of the opcode
11650 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x3));
11651 emitImm8((byte)imm);
11652 } else {
11653 setMachineCodes(mi++, (byte) 0x81);
11654 // "register 0x3" is really part of the opcode
11655 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x3));
11656 emitImm32(imm);
11657 }
11658 if (lister != null) lister.RDI(miStart, "SBB", dstBase, dstDisp, imm);
11659 }
11660
11661 /**
11662 * Generate a register-offset--immediate SBB. That is,
11663 * <PRE>
11664 * [dstIndex<<dstScale + dstDisp] -CF= (quad) imm
11665 * </PRE>
11666 *
11667 * @param dstIndex the destination index register
11668 * @param dstScale the destination shift amount
11669 * @param dstDisp the destination displacement
11670 * @param imm immediate
11671 */
11672 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
11673 public final void emitSBB_RegOff_Imm_Quad(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
11674 int miStart = mi;
11675 // no group 1 to 4 prefix byte
11676 generateREXprefix(true, null, dstIndex, null);
11677 // single byte opcode
11678 if (fits(imm,8)) {
11679 setMachineCodes(mi++, (byte) 0x83);
11680 // "register 0x3" is really part of the opcode
11681 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
11682 emitImm8((byte)imm);
11683 } else {
11684 setMachineCodes(mi++, (byte) 0x81);
11685 // "register 0x3" is really part of the opcode
11686 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
11687 emitImm32(imm);
11688 }
11689 if (lister != null) lister.RFDI(miStart, "SBB", dstIndex, dstScale, dstDisp, imm);
11690 }
11691
11692 /**
11693 * Generate a absolute--immediate SBB. That is,
11694 * <PRE>
11695 * [dstDisp] -CF= (quad) imm
11696 * </PRE>
11697 *
11698 * @param dstDisp the destination displacement
11699 * @param imm immediate
11700 */
11701 public final void emitSBB_Abs_Imm_Quad(Address dstDisp, int imm) {
11702 int miStart = mi;
11703 // no group 1 to 4 prefix byte
11704 generateREXprefix(true, null, null, null);
11705 // single byte opcode
11706 if (fits(imm,8)) {
11707 setMachineCodes(mi++, (byte) 0x83);
11708 // "register 0x3" is really part of the opcode
11709 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x3));
11710 emitImm8((byte)imm);
11711 } else {
11712 setMachineCodes(mi++, (byte) 0x81);
11713 // "register 0x3" is really part of the opcode
11714 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x3));
11715 emitImm32(imm);
11716 }
11717 if (lister != null) lister.RAI(miStart, "SBB", dstDisp, imm);
11718 }
11719
11720 /**
11721 * Generate a register-index--immediate SBB. That is,
11722 * <PRE>
11723 * [dstBase + dstIndex<<dstScale + dstDisp] -CF= (quad) imm
11724 * </PRE>
11725 *
11726 * @param dstBase the destination base register
11727 * @param dstIndex the destination index register
11728 * @param dstScale the destination shift amount
11729 * @param dstDisp the destination displacement
11730 * @param imm immediate
11731 */
11732 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
11733 public final void emitSBB_RegIdx_Imm_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
11734 int miStart = mi;
11735 // no group 1 to 4 prefix byte
11736 generateREXprefix(true, null, dstIndex, dstBase);
11737 // single byte opcode
11738 if (fits(imm,8)) {
11739 setMachineCodes(mi++, (byte) 0x83);
11740 // "register 0x3" is really part of the opcode
11741 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
11742 emitImm8((byte)imm);
11743 } else {
11744 setMachineCodes(mi++, (byte) 0x81);
11745 // "register 0x3" is really part of the opcode
11746 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
11747 emitImm32(imm);
11748 }
11749 if (lister != null) lister.RXDI(miStart, "SBB", dstBase, dstIndex, dstScale, dstDisp, imm);
11750 }
11751
11752 /**
11753 * Generate a register(indirect)--immediate SBB. That is,
11754 * <PRE>
11755 * [dstBase] -CF= (quad) imm
11756 * </PRE>
11757 *
11758 * @param dstBase the destination base register
11759 * @param imm immediate
11760 */
11761 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
11762 public final void emitSBB_RegInd_Imm_Quad(GPR dstBase, int imm) {
11763 int miStart = mi;
11764 // no group 1 to 4 prefix byte
11765 generateREXprefix(true, null, null, dstBase);
11766 // single byte opcode
11767 if (fits(imm,8)) {
11768 setMachineCodes(mi++, (byte) 0x83);
11769 // "register 0x3" is really part of the opcode
11770 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x3));
11771 emitImm8((byte)imm);
11772 } else {
11773 setMachineCodes(mi++, (byte) 0x81);
11774 // "register 0x3" is really part of the opcode
11775 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x3));
11776 emitImm32(imm);
11777 }
11778 if (lister != null) lister.RNI(miStart, "SBB", dstBase, imm);
11779 }
11780
11781 /**
11782 * Generate a register--immediate SBB. That is,
11783 * <PRE>
11784 * dstReg -CF= (byte) imm
11785 * </PRE>
11786 *
11787 * @param dstReg the destination register
11788 * @param imm immediate
11789 */
11790 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
11791 public final void emitSBB_Reg_Imm_Byte(GPR dstReg, int imm) {
11792 int miStart = mi;
11793 if (dstReg == EAX) {
11794 setMachineCodes(mi++, (byte) 0x1C);
11795 emitImm8(imm);
11796 } else {
11797 generateREXprefix(false, null, null, dstReg);
11798 setMachineCodes(mi++, (byte) 0x80);
11799 // "register 0x3" is really part of the opcode
11800 emitRegRegOperands(dstReg, GPR.getForOpcode(0x3));
11801 emitImm8(imm);
11802 }
11803 if (lister != null) lister.RI(miStart, "SBB", dstReg, imm);
11804 }
11805
11806 /**
11807 * Generate a register-displacement--immediate SBB. That is,
11808 * <PRE>
11809 * [dstBase + dstDisp] -CF= (byte) imm
11810 * </PRE>
11811 *
11812 * @param dstBase the destination register
11813 * @param dstDisp the destination displacement
11814 * @param imm immediate
11815 */
11816 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
11817 public final void emitSBB_RegDisp_Imm_Byte(GPR dstBase, Offset dstDisp, int imm) {
11818 int miStart = mi;
11819 generateREXprefix(false, null, null, dstBase);
11820 setMachineCodes(mi++, (byte) 0x80);
11821 // "register 0x3" is really part of the opcode
11822 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x3));
11823 emitImm8(imm);
11824 if (lister != null) lister.RDI(miStart, "SBB", dstBase, dstDisp, imm);
11825 }
11826
11827 /**
11828 * Generate a register-index--immediate SBB. That is,
11829 * <PRE>
11830 * [dstBase + dstIndex<<scale + dstDisp] -CF= (byte) imm
11831 * </PRE>
11832 *
11833 * @param dstBase the destination base register
11834 * @param dstIndex the destination index register
11835 * @param dstScale the destination shift amount
11836 * @param dstDisp the destination displacement
11837 * @param imm immediate
11838 */
11839 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
11840 public final void emitSBB_RegIdx_Imm_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
11841 int miStart = mi;
11842 generateREXprefix(false, null, dstIndex, dstBase);
11843 setMachineCodes(mi++, (byte) 0x80);
11844 // "register 0x3" is really part of the opcode
11845 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
11846 emitImm8(imm);
11847 if (lister != null) lister.RXDI(miStart, "SBB", dstBase, dstIndex, dstScale, dstDisp, imm);
11848 }
11849
11850 /**
11851 * Generate a register-offset--immediate SBB. That is,
11852 * <PRE>
11853 * [dstIndex<<dstScale + dstDisp] -CF= (byte) imm
11854 * </PRE>
11855 *
11856 * @param dstIndex the destination index register
11857 * @param dstScale the destination shift amount
11858 * @param dstDisp the destination displacement
11859 * @param imm immediate
11860 */
11861 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
11862 public final void emitSBB_RegOff_Imm_Byte(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
11863 int miStart = mi;
11864 generateREXprefix(false, null, dstIndex, null);
11865 setMachineCodes(mi++, (byte) 0x80);
11866 // "register 0x3" is really part of the opcode
11867 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
11868 emitImm8(imm);
11869 if (lister != null) lister.RFDI(miStart, "SBB", dstIndex, dstScale, dstDisp, imm);
11870 }
11871
11872 /**
11873 * Generate a absolute--immediate SBB. That is,
11874 * <PRE>
11875 * [dstDisp] -CF= (byte) imm
11876 * </PRE>
11877 *
11878 * @param dstDisp the destination displacement
11879 * @param imm immediate
11880 */
11881 public final void emitSBB_Abs_Imm_Byte(Address dstDisp, int imm) {
11882 int miStart = mi;
11883 generateREXprefix(false, null, null, null);
11884 setMachineCodes(mi++, (byte) 0x80);
11885 // "register 0x3" is really part of the opcode
11886 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x3));
11887 emitImm8(imm);
11888 if (lister != null) lister.RAI(miStart, "SBB", dstDisp, imm);
11889 }
11890
11891 /**
11892 * Generate a register(indirect)--immediate SBB. That is,
11893 * <PRE>
11894 * [dstBase] -CF= (byte) imm
11895 * </PRE>
11896 *
11897 * @param dstBase the destination base register
11898 * @param imm immediate
11899 */
11900 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
11901 public final void emitSBB_RegInd_Imm_Byte(GPR dstBase, int imm) {
11902 int miStart = mi;
11903 generateREXprefix(false, null, null, dstBase);
11904 setMachineCodes(mi++, (byte) 0x80);
11905 // "register 0x3" is really part of the opcode
11906 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x3));
11907 emitImm8(imm);
11908 if (lister != null) lister.RNI(miStart, "SBB", dstBase, imm);
11909 }
11910
11911 /**
11912 * Generate a register(indirect)--register SUB. That is,
11913 * <PRE>
11914 * [dstBase] -= srcReg
11915 * </PRE>
11916 *
11917 * @param dstBase the destination base
11918 * @param srcReg the source register
11919 */
11920 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
11921 public final void emitSUB_RegInd_Reg(GPR dstBase, GPR srcReg) {
11922 int miStart = mi;
11923 // no group 1 to 4 prefix byte
11924 generateREXprefix(false, srcReg, null, dstBase);
11925 // single byte opcode
11926 setMachineCodes(mi++, (byte) 0x29);
11927 emitRegIndirectRegOperands(dstBase, srcReg);
11928 if (lister != null) lister.RNR(miStart, "SUB", dstBase, srcReg);
11929 }
11930
11931 /**
11932 * Generate a register-offset--register SUB. That is,
11933 * <PRE>
11934 * [dstReg<<dstScale + dstDisp] -= srcReg
11935 * </PRE>
11936 *
11937 * @param dstIndex the destination index register
11938 * @param dstScale the destination shift amount
11939 * @param dstDisp the destination displacement
11940 * @param srcReg the source register
11941 */
11942 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
11943 public final void emitSUB_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
11944 int miStart = mi;
11945 // no group 1 to 4 prefix byte
11946 generateREXprefix(false, srcReg, dstIndex, null);
11947 // single byte opcode
11948 setMachineCodes(mi++, (byte) 0x29);
11949 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
11950 if (lister != null) lister.RFDR(miStart, "SUB", dstIndex, dstScale, dstDisp, srcReg);
11951 }
11952
11953 /**
11954 * Generate a absolute--register SUB. That is,
11955 * <PRE>
11956 * [dstDisp] -= srcReg
11957 * </PRE>
11958 *
11959 * @param dstDisp the destination address
11960 * @param srcReg the source register
11961 */
11962 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
11963 public final void emitSUB_Abs_Reg(Address dstDisp, GPR srcReg) {
11964 int miStart = mi;
11965 // no group 1 to 4 prefix byte
11966 generateREXprefix(false, srcReg, null, null);
11967 // single byte opcode
11968 setMachineCodes(mi++, (byte) 0x29);
11969 emitAbsRegOperands(dstDisp, srcReg);
11970 if (lister != null) lister.RAR(miStart, "SUB", dstDisp, srcReg);
11971 }
11972
11973 /**
11974 * Generate a register-index--register SUB. That is,
11975 * <PRE>
11976 * [dstBase + dstIndex<<dstScale + dstDisp] -= srcReg
11977 * </PRE>
11978 *
11979 * @param dstBase the base register
11980 * @param dstIndex the destination index register
11981 * @param dstScale the destination shift amount
11982 * @param dstDisp the destination displacement
11983 * @param srcReg the source register
11984 */
11985 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
11986 public final void emitSUB_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
11987 int miStart = mi;
11988 // no group 1 to 4 prefix byte
11989 generateREXprefix(false, srcReg, dstIndex, dstBase);
11990 // single byte opcode
11991 setMachineCodes(mi++, (byte) 0x29);
11992 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
11993 if (lister != null) lister.RXDR(miStart, "SUB", dstBase, dstIndex, dstScale, dstDisp, srcReg);
11994 }
11995
11996 /**
11997 * Generate a register-displacement--register SUB. That is,
11998 * <PRE>
11999 * [dstBase + dstDisp] -= srcReg
12000 * </PRE>
12001 *
12002 * @param dstBase the base register
12003 * @param dstDisp the destination displacement
12004 * @param srcReg the source register
12005 */
12006 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
12007 public final void emitSUB_RegDisp_Reg(GPR dstBase, Offset dstDisp, GPR srcReg) {
12008 int miStart = mi;
12009 // no group 1 to 4 prefix byte
12010 generateREXprefix(false, srcReg, null, dstBase);
12011 // single byte opcode
12012 setMachineCodes(mi++, (byte) 0x29);
12013 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
12014 if (lister != null) lister.RDR(miStart, "SUB", dstBase, dstDisp, srcReg);
12015 }
12016
12017 /**
12018 * Generate a register--register SUB. That is,
12019 * <PRE>
12020 * dstReg -= srcReg
12021 * </PRE>
12022 *
12023 * @param dstReg the destination register
12024 * @param srcReg the source register
12025 */
12026 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12027 public final void emitSUB_Reg_Reg(GPR dstReg, GPR srcReg) {
12028 int miStart = mi;
12029 // no group 1 to 4 prefix byte
12030 generateREXprefix(false, srcReg, null, dstReg);
12031 // single byte opcode
12032 setMachineCodes(mi++, (byte) 0x29);
12033 emitRegRegOperands(dstReg, srcReg);
12034 if (lister != null) lister.RR(miStart, "SUB", dstReg, srcReg);
12035 }
12036
12037 /**
12038 * Generate a register--register-displacement SUB. That is,
12039 * <PRE>
12040 * dstReg -= [srcReg + srcDisp]
12041 * </PRE>
12042 *
12043 * @param dstReg the destination register
12044 * @param srcBase the source register
12045 * @param srcDisp the source displacement
12046 */
12047 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12048 public final void emitSUB_Reg_RegDisp(GPR dstReg, GPR srcBase, Offset srcDisp) {
12049 int miStart = mi;
12050 // no group 1 to 4 prefix byte
12051 generateREXprefix(false, dstReg, null, srcBase);
12052 // single byte opcode
12053 setMachineCodes(mi++, (byte) 0x2B);
12054 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
12055 if (lister != null) lister.RRD(miStart, "SUB", dstReg, srcBase, srcDisp);
12056 }
12057
12058 /**
12059 * Generate a register--register-offset SUB. That is,
12060 * <PRE>
12061 * dstReg -= [srcIndex<<srcScale + srcDisp]
12062 * </PRE>
12063 *
12064 * @param dstReg the destination register
12065 * @param srcIndex the source index register
12066 * @param srcScale the source shift amount
12067 * @param srcDisp the source displacement
12068 */
12069 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12070 public final void emitSUB_Reg_RegOff(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
12071 int miStart = mi;
12072 // no group 1 to 4 prefix byte
12073 generateREXprefix(false, dstReg, srcIndex, null);
12074 // single byte opcode
12075 setMachineCodes(mi++, (byte) 0x2B);
12076 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
12077 if (lister != null) lister.RRFD(miStart, "SUB", dstReg, srcIndex, srcScale, srcDisp);
12078 }
12079
12080 /**
12081 * Generate a register--register-offset SUB. That is,
12082 * <PRE>
12083 * dstReg -= [srcDisp]
12084 * </PRE>
12085 *
12086 * @param dstReg the destination register
12087 * @param srcDisp the source displacement
12088 */
12089 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
12090 public final void emitSUB_Reg_Abs(GPR dstReg, Address srcDisp) {
12091 int miStart = mi;
12092 // no group 1 to 4 prefix byte
12093 generateREXprefix(false, dstReg, null, null);
12094 // single byte opcode
12095 setMachineCodes(mi++, (byte) 0x2B);
12096 emitAbsRegOperands(srcDisp, dstReg);
12097 if (lister != null) lister.RRA(miStart, "SUB", dstReg, srcDisp);
12098 }
12099
12100 /**
12101 * Generate a register--register-offset SUB. That is,
12102 * <PRE>
12103 * dstReg -= [srcBase + srcIndex<<srcScale + srcDisp]
12104 * </PRE>
12105 *
12106 * @param dstReg the destination register
12107 * @param srcBase the source base register
12108 * @param srcIndex the source index register
12109 * @param srcScale the source shift amount
12110 * @param srcDisp the source displacement
12111 */
12112 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
12113 public final void emitSUB_Reg_RegIdx(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
12114 int miStart = mi;
12115 // no group 1 to 4 prefix byte
12116 generateREXprefix(false, dstReg, srcIndex, srcBase);
12117 // single byte opcode
12118 setMachineCodes(mi++, (byte) 0x2B);
12119 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
12120 if (lister != null) lister.RRXD(miStart, "SUB", dstReg, srcBase, srcIndex, srcScale, srcDisp);
12121 }
12122
12123 /**
12124 * Generate a register--register(indirect) SUB. That is,
12125 * <PRE>
12126 * dstReg -= [srcBase]
12127 * </PRE>
12128 *
12129 * @param dstReg the destination register
12130 * @param srcBase the source base register
12131 */
12132 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12133 public final void emitSUB_Reg_RegInd(GPR dstReg, GPR srcBase) {
12134 int miStart = mi;
12135 // no group 1 to 4 prefix byte
12136 generateREXprefix(false, dstReg, null, srcBase);
12137 // single byte opcode
12138 setMachineCodes(mi++, (byte) 0x2B);
12139 emitRegIndirectRegOperands(srcBase, dstReg);
12140 if (lister != null) lister.RRN(miStart, "SUB", dstReg, srcBase);
12141 }
12142
12143 /**
12144 * Generate a register(indirect)--register SUB. That is,
12145 * <PRE>
12146 * [dstBase] -= (word) srcReg
12147 * </PRE>
12148 *
12149 * @param dstBase the destination base
12150 * @param srcReg the source register
12151 */
12152 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12153 public final void emitSUB_RegInd_Reg_Word(GPR dstBase, GPR srcReg) {
12154 int miStart = mi;
12155 setMachineCodes(mi++, (byte) 0x66);
12156 generateREXprefix(false, srcReg, null, dstBase);
12157 // single byte opcode
12158 setMachineCodes(mi++, (byte) 0x29);
12159 emitRegIndirectRegOperands(dstBase, srcReg);
12160 if (lister != null) lister.RNR(miStart, "SUB", dstBase, srcReg);
12161 }
12162
12163 /**
12164 * Generate a register-offset--register SUB. That is,
12165 * <PRE>
12166 * [dstReg<<dstScale + dstDisp] -= (word) srcReg
12167 * </PRE>
12168 *
12169 * @param dstIndex the destination index register
12170 * @param dstScale the destination shift amount
12171 * @param dstDisp the destination displacement
12172 * @param srcReg the source register
12173 */
12174 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
12175 public final void emitSUB_RegOff_Reg_Word(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
12176 int miStart = mi;
12177 setMachineCodes(mi++, (byte) 0x66);
12178 generateREXprefix(false, srcReg, dstIndex, null);
12179 // single byte opcode
12180 setMachineCodes(mi++, (byte) 0x29);
12181 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
12182 if (lister != null) lister.RFDR(miStart, "SUB", dstIndex, dstScale, dstDisp, srcReg);
12183 }
12184
12185 /**
12186 * Generate a absolute--register SUB. That is,
12187 * <PRE>
12188 * [dstDisp] -= (word) srcReg
12189 * </PRE>
12190 *
12191 * @param dstDisp the destination address
12192 * @param srcReg the source register
12193 */
12194 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
12195 public final void emitSUB_Abs_Reg_Word(Address dstDisp, GPR srcReg) {
12196 int miStart = mi;
12197 setMachineCodes(mi++, (byte) 0x66);
12198 generateREXprefix(false, srcReg, null, null);
12199 // single byte opcode
12200 setMachineCodes(mi++, (byte) 0x29);
12201 emitAbsRegOperands(dstDisp, srcReg);
12202 if (lister != null) lister.RAR(miStart, "SUB", dstDisp, srcReg);
12203 }
12204
12205 /**
12206 * Generate a register-index--register SUB. That is,
12207 * <PRE>
12208 * [dstBase + dstIndex<<dstScale + dstDisp] -= (word) srcReg
12209 * </PRE>
12210 *
12211 * @param dstBase the base register
12212 * @param dstIndex the destination index register
12213 * @param dstScale the destination shift amount
12214 * @param dstDisp the destination displacement
12215 * @param srcReg the source register
12216 */
12217 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
12218 public final void emitSUB_RegIdx_Reg_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
12219 int miStart = mi;
12220 setMachineCodes(mi++, (byte) 0x66);
12221 generateREXprefix(false, srcReg, dstIndex, dstBase);
12222 // single byte opcode
12223 setMachineCodes(mi++, (byte) 0x29);
12224 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
12225 if (lister != null) lister.RXDR(miStart, "SUB", dstBase, dstIndex, dstScale, dstDisp, srcReg);
12226 }
12227
12228 /**
12229 * Generate a register-displacement--register SUB. That is,
12230 * <PRE>
12231 * [dstBase + dstDisp] -= (word) srcReg
12232 * </PRE>
12233 *
12234 * @param dstBase the base register
12235 * @param dstDisp the destination displacement
12236 * @param srcReg the source register
12237 */
12238 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
12239 public final void emitSUB_RegDisp_Reg_Word(GPR dstBase, Offset dstDisp, GPR srcReg) {
12240 int miStart = mi;
12241 setMachineCodes(mi++, (byte) 0x66);
12242 generateREXprefix(false, srcReg, null, dstBase);
12243 // single byte opcode
12244 setMachineCodes(mi++, (byte) 0x29);
12245 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
12246 if (lister != null) lister.RDR(miStart, "SUB", dstBase, dstDisp, srcReg);
12247 }
12248
12249 /**
12250 * Generate a register--register SUB. That is,
12251 * <PRE>
12252 * dstReg -= (word) srcReg
12253 * </PRE>
12254 *
12255 * @param dstReg the destination register
12256 * @param srcReg the source register
12257 */
12258 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12259 public final void emitSUB_Reg_Reg_Word(GPR dstReg, GPR srcReg) {
12260 int miStart = mi;
12261 setMachineCodes(mi++, (byte) 0x66);
12262 generateREXprefix(false, srcReg, null, dstReg);
12263 // single byte opcode
12264 setMachineCodes(mi++, (byte) 0x29);
12265 emitRegRegOperands(dstReg, srcReg);
12266 if (lister != null) lister.RR(miStart, "SUB", dstReg, srcReg);
12267 }
12268
12269 /**
12270 * Generate a register--register-displacement SUB. That is,
12271 * <PRE>
12272 * dstReg -= (word) [srcReg + srcDisp]
12273 * </PRE>
12274 *
12275 * @param dstReg the destination register
12276 * @param srcBase the source register
12277 * @param srcDisp the source displacement
12278 */
12279 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12280 public final void emitSUB_Reg_RegDisp_Word(GPR dstReg, GPR srcBase, Offset srcDisp) {
12281 int miStart = mi;
12282 setMachineCodes(mi++, (byte) 0x66);
12283 generateREXprefix(false, dstReg, null, srcBase);
12284 // single byte opcode
12285 setMachineCodes(mi++, (byte) 0x2B);
12286 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
12287 if (lister != null) lister.RRD(miStart, "SUB", dstReg, srcBase, srcDisp);
12288 }
12289
12290 /**
12291 * Generate a register--register-offset SUB. That is,
12292 * <PRE>
12293 * dstReg -= (word) [srcIndex<<srcScale + srcDisp]
12294 * </PRE>
12295 *
12296 * @param dstReg the destination register
12297 * @param srcIndex the source index register
12298 * @param srcScale the source shift amount
12299 * @param srcDisp the source displacement
12300 */
12301 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12302 public final void emitSUB_Reg_RegOff_Word(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
12303 int miStart = mi;
12304 setMachineCodes(mi++, (byte) 0x66);
12305 generateREXprefix(false, dstReg, srcIndex, null);
12306 // single byte opcode
12307 setMachineCodes(mi++, (byte) 0x2B);
12308 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
12309 if (lister != null) lister.RRFD(miStart, "SUB", dstReg, srcIndex, srcScale, srcDisp);
12310 }
12311
12312 /**
12313 * Generate a register--register-offset SUB. That is,
12314 * <PRE>
12315 * dstReg -= (word) [srcDisp]
12316 * </PRE>
12317 *
12318 * @param dstReg the destination register
12319 * @param srcDisp the source displacement
12320 */
12321 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
12322 public final void emitSUB_Reg_Abs_Word(GPR dstReg, Address srcDisp) {
12323 int miStart = mi;
12324 setMachineCodes(mi++, (byte) 0x66);
12325 generateREXprefix(false, dstReg, null, null);
12326 // single byte opcode
12327 setMachineCodes(mi++, (byte) 0x2B);
12328 emitAbsRegOperands(srcDisp, dstReg);
12329 if (lister != null) lister.RRA(miStart, "SUB", dstReg, srcDisp);
12330 }
12331
12332 /**
12333 * Generate a register--register-offset SUB. That is,
12334 * <PRE>
12335 * dstReg -= (word) [srcBase + srcIndex<<srcScale + srcDisp]
12336 * </PRE>
12337 *
12338 * @param dstReg the destination register
12339 * @param srcBase the source base register
12340 * @param srcIndex the source index register
12341 * @param srcScale the source shift amount
12342 * @param srcDisp the source displacement
12343 */
12344 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
12345 public final void emitSUB_Reg_RegIdx_Word(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
12346 int miStart = mi;
12347 setMachineCodes(mi++, (byte) 0x66);
12348 generateREXprefix(false, dstReg, srcIndex, srcBase);
12349 // single byte opcode
12350 setMachineCodes(mi++, (byte) 0x2B);
12351 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
12352 if (lister != null) lister.RRXD(miStart, "SUB", dstReg, srcBase, srcIndex, srcScale, srcDisp);
12353 }
12354
12355 /**
12356 * Generate a register--register(indirect) SUB. That is,
12357 * <PRE>
12358 * dstReg -= (word) [srcBase]
12359 * </PRE>
12360 *
12361 * @param dstReg the destination register
12362 * @param srcBase the source base register
12363 */
12364 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12365 public final void emitSUB_Reg_RegInd_Word(GPR dstReg, GPR srcBase) {
12366 int miStart = mi;
12367 setMachineCodes(mi++, (byte) 0x66);
12368 generateREXprefix(false, dstReg, null, srcBase);
12369 // single byte opcode
12370 setMachineCodes(mi++, (byte) 0x2B);
12371 emitRegIndirectRegOperands(srcBase, dstReg);
12372 if (lister != null) lister.RRN(miStart, "SUB", dstReg, srcBase);
12373 }
12374
12375 /**
12376 * Generate a register(indirect)--register SUB. That is,
12377 * <PRE>
12378 * [dstBase] -= (quad) srcReg
12379 * </PRE>
12380 *
12381 * @param dstBase the destination base
12382 * @param srcReg the source register
12383 */
12384 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12385 public final void emitSUB_RegInd_Reg_Quad(GPR dstBase, GPR srcReg) {
12386 int miStart = mi;
12387 // no group 1 to 4 prefix byte
12388 generateREXprefix(true, srcReg, null, dstBase);
12389 // single byte opcode
12390 setMachineCodes(mi++, (byte) 0x29);
12391 emitRegIndirectRegOperands(dstBase, srcReg);
12392 if (lister != null) lister.RNR(miStart, "SUB", dstBase, srcReg);
12393 }
12394
12395 /**
12396 * Generate a register-offset--register SUB. That is,
12397 * <PRE>
12398 * [dstReg<<dstScale + dstDisp] -= (quad) srcReg
12399 * </PRE>
12400 *
12401 * @param dstIndex the destination index register
12402 * @param dstScale the destination shift amount
12403 * @param dstDisp the destination displacement
12404 * @param srcReg the source register
12405 */
12406 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
12407 public final void emitSUB_RegOff_Reg_Quad(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
12408 int miStart = mi;
12409 // no group 1 to 4 prefix byte
12410 generateREXprefix(true, srcReg, dstIndex, null);
12411 // single byte opcode
12412 setMachineCodes(mi++, (byte) 0x29);
12413 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
12414 if (lister != null) lister.RFDR(miStart, "SUB", dstIndex, dstScale, dstDisp, srcReg);
12415 }
12416
12417 /**
12418 * Generate a absolute--register SUB. That is,
12419 * <PRE>
12420 * [dstDisp] -= (quad) srcReg
12421 * </PRE>
12422 *
12423 * @param dstDisp the destination address
12424 * @param srcReg the source register
12425 */
12426 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
12427 public final void emitSUB_Abs_Reg_Quad(Address dstDisp, GPR srcReg) {
12428 int miStart = mi;
12429 // no group 1 to 4 prefix byte
12430 generateREXprefix(true, srcReg, null, null);
12431 // single byte opcode
12432 setMachineCodes(mi++, (byte) 0x29);
12433 emitAbsRegOperands(dstDisp, srcReg);
12434 if (lister != null) lister.RAR(miStart, "SUB", dstDisp, srcReg);
12435 }
12436
12437 /**
12438 * Generate a register-index--register SUB. That is,
12439 * <PRE>
12440 * [dstBase + dstIndex<<dstScale + dstDisp] -= (quad) srcReg
12441 * </PRE>
12442 *
12443 * @param dstBase the base register
12444 * @param dstIndex the destination index register
12445 * @param dstScale the destination shift amount
12446 * @param dstDisp the destination displacement
12447 * @param srcReg the source register
12448 */
12449 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
12450 public final void emitSUB_RegIdx_Reg_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
12451 int miStart = mi;
12452 // no group 1 to 4 prefix byte
12453 generateREXprefix(true, srcReg, dstIndex, dstBase);
12454 // single byte opcode
12455 setMachineCodes(mi++, (byte) 0x29);
12456 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
12457 if (lister != null) lister.RXDR(miStart, "SUB", dstBase, dstIndex, dstScale, dstDisp, srcReg);
12458 }
12459
12460 /**
12461 * Generate a register-displacement--register SUB. That is,
12462 * <PRE>
12463 * [dstBase + dstDisp] -= (quad) srcReg
12464 * </PRE>
12465 *
12466 * @param dstBase the base register
12467 * @param dstDisp the destination displacement
12468 * @param srcReg the source register
12469 */
12470 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
12471 public final void emitSUB_RegDisp_Reg_Quad(GPR dstBase, Offset dstDisp, GPR srcReg) {
12472 int miStart = mi;
12473 // no group 1 to 4 prefix byte
12474 generateREXprefix(true, srcReg, null, dstBase);
12475 // single byte opcode
12476 setMachineCodes(mi++, (byte) 0x29);
12477 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
12478 if (lister != null) lister.RDR(miStart, "SUB", dstBase, dstDisp, srcReg);
12479 }
12480
12481 /**
12482 * Generate a register--register SUB. That is,
12483 * <PRE>
12484 * dstReg -= (quad) srcReg
12485 * </PRE>
12486 *
12487 * @param dstReg the destination register
12488 * @param srcReg the source register
12489 */
12490 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12491 public final void emitSUB_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
12492 int miStart = mi;
12493 // no group 1 to 4 prefix byte
12494 generateREXprefix(true, srcReg, null, dstReg);
12495 // single byte opcode
12496 setMachineCodes(mi++, (byte) 0x29);
12497 emitRegRegOperands(dstReg, srcReg);
12498 if (lister != null) lister.RR(miStart, "SUB", dstReg, srcReg);
12499 }
12500
12501 /**
12502 * Generate a register--register-displacement SUB. That is,
12503 * <PRE>
12504 * dstReg -= (quad) [srcReg + srcDisp]
12505 * </PRE>
12506 *
12507 * @param dstReg the destination register
12508 * @param srcBase the source register
12509 * @param srcDisp the source displacement
12510 */
12511 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12512 public final void emitSUB_Reg_RegDisp_Quad(GPR dstReg, GPR srcBase, Offset srcDisp) {
12513 int miStart = mi;
12514 // no group 1 to 4 prefix byte
12515 generateREXprefix(true, dstReg, null, srcBase);
12516 // single byte opcode
12517 setMachineCodes(mi++, (byte) 0x2B);
12518 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
12519 if (lister != null) lister.RRD(miStart, "SUB", dstReg, srcBase, srcDisp);
12520 }
12521
12522 /**
12523 * Generate a register--register-offset SUB. That is,
12524 * <PRE>
12525 * dstReg -= (quad) [srcIndex<<srcScale + srcDisp]
12526 * </PRE>
12527 *
12528 * @param dstReg the destination register
12529 * @param srcIndex the source index register
12530 * @param srcScale the source shift amount
12531 * @param srcDisp the source displacement
12532 */
12533 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12534 public final void emitSUB_Reg_RegOff_Quad(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
12535 int miStart = mi;
12536 // no group 1 to 4 prefix byte
12537 generateREXprefix(true, dstReg, srcIndex, null);
12538 // single byte opcode
12539 setMachineCodes(mi++, (byte) 0x2B);
12540 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
12541 if (lister != null) lister.RRFD(miStart, "SUB", dstReg, srcIndex, srcScale, srcDisp);
12542 }
12543
12544 /**
12545 * Generate a register--register-offset SUB. That is,
12546 * <PRE>
12547 * dstReg -= (quad) [srcDisp]
12548 * </PRE>
12549 *
12550 * @param dstReg the destination register
12551 * @param srcDisp the source displacement
12552 */
12553 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
12554 public final void emitSUB_Reg_Abs_Quad(GPR dstReg, Address srcDisp) {
12555 int miStart = mi;
12556 // no group 1 to 4 prefix byte
12557 generateREXprefix(true, dstReg, null, null);
12558 // single byte opcode
12559 setMachineCodes(mi++, (byte) 0x2B);
12560 emitAbsRegOperands(srcDisp, dstReg);
12561 if (lister != null) lister.RRA(miStart, "SUB", dstReg, srcDisp);
12562 }
12563
12564 /**
12565 * Generate a register--register-offset SUB. That is,
12566 * <PRE>
12567 * dstReg -= (quad) [srcBase + srcIndex<<srcScale + srcDisp]
12568 * </PRE>
12569 *
12570 * @param dstReg the destination register
12571 * @param srcBase the source base register
12572 * @param srcIndex the source index register
12573 * @param srcScale the source shift amount
12574 * @param srcDisp the source displacement
12575 */
12576 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
12577 public final void emitSUB_Reg_RegIdx_Quad(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
12578 int miStart = mi;
12579 // no group 1 to 4 prefix byte
12580 generateREXprefix(true, dstReg, srcIndex, srcBase);
12581 // single byte opcode
12582 setMachineCodes(mi++, (byte) 0x2B);
12583 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
12584 if (lister != null) lister.RRXD(miStart, "SUB", dstReg, srcBase, srcIndex, srcScale, srcDisp);
12585 }
12586
12587 /**
12588 * Generate a register--register(indirect) SUB. That is,
12589 * <PRE>
12590 * dstReg -= (quad) [srcBase]
12591 * </PRE>
12592 *
12593 * @param dstReg the destination register
12594 * @param srcBase the source base register
12595 */
12596 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12597 public final void emitSUB_Reg_RegInd_Quad(GPR dstReg, GPR srcBase) {
12598 int miStart = mi;
12599 // no group 1 to 4 prefix byte
12600 generateREXprefix(true, dstReg, null, srcBase);
12601 // single byte opcode
12602 setMachineCodes(mi++, (byte) 0x2B);
12603 emitRegIndirectRegOperands(srcBase, dstReg);
12604 if (lister != null) lister.RRN(miStart, "SUB", dstReg, srcBase);
12605 }
12606
12607 /**
12608 * Generate a register(indirect)--register SUB. That is,
12609 * <PRE>
12610 * [dstBase] -= (byte) srcReg
12611 * </PRE>
12612 *
12613 * @param dstBase the destination base
12614 * @param srcReg the source register
12615 */
12616 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12617 public final void emitSUB_RegInd_Reg_Byte(GPR dstBase, GPR srcReg) {
12618 int miStart = mi;
12619 // no group 1 to 4 prefix byte
12620 generateREXprefix(false, srcReg, null, dstBase);
12621 // single byte opcode
12622 setMachineCodes(mi++, (byte) 0x28);
12623 emitRegIndirectRegOperands(dstBase, srcReg);
12624 if (lister != null) lister.RNR(miStart, "SUB", dstBase, srcReg);
12625 }
12626
12627 /**
12628 * Generate a register-offset--register SUB. That is,
12629 * <PRE>
12630 * [dstReg<<dstScale + dstDisp] -= (byte) srcReg
12631 * </PRE>
12632 *
12633 * @param dstIndex the destination index register
12634 * @param dstScale the destination shift amount
12635 * @param dstDisp the destination displacement
12636 * @param srcReg the source register
12637 */
12638 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
12639 public final void emitSUB_RegOff_Reg_Byte(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
12640 int miStart = mi;
12641 // no group 1 to 4 prefix byte
12642 generateREXprefix(false, srcReg, dstIndex, null);
12643 // single byte opcode
12644 setMachineCodes(mi++, (byte) 0x28);
12645 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
12646 if (lister != null) lister.RFDR(miStart, "SUB", dstIndex, dstScale, dstDisp, srcReg);
12647 }
12648
12649 /**
12650 * Generate a absolute--register SUB. That is,
12651 * <PRE>
12652 * [dstDisp] -= (byte) srcReg
12653 * </PRE>
12654 *
12655 * @param dstDisp the destination address
12656 * @param srcReg the source register
12657 */
12658 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
12659 public final void emitSUB_Abs_Reg_Byte(Address dstDisp, GPR srcReg) {
12660 int miStart = mi;
12661 // no group 1 to 4 prefix byte
12662 generateREXprefix(false, srcReg, null, null);
12663 // single byte opcode
12664 setMachineCodes(mi++, (byte) 0x28);
12665 emitAbsRegOperands(dstDisp, srcReg);
12666 if (lister != null) lister.RAR(miStart, "SUB", dstDisp, srcReg);
12667 }
12668
12669 /**
12670 * Generate a register-index--register SUB. That is,
12671 * <PRE>
12672 * [dstBase + dstIndex<<dstScale + dstDisp] -= (byte) srcReg
12673 * </PRE>
12674 *
12675 * @param dstBase the base register
12676 * @param dstIndex the destination index register
12677 * @param dstScale the destination shift amount
12678 * @param dstDisp the destination displacement
12679 * @param srcReg the source register
12680 */
12681 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
12682 public final void emitSUB_RegIdx_Reg_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
12683 int miStart = mi;
12684 // no group 1 to 4 prefix byte
12685 generateREXprefix(false, srcReg, dstIndex, dstBase);
12686 // single byte opcode
12687 setMachineCodes(mi++, (byte) 0x28);
12688 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
12689 if (lister != null) lister.RXDR(miStart, "SUB", dstBase, dstIndex, dstScale, dstDisp, srcReg);
12690 }
12691
12692 /**
12693 * Generate a register-displacement--register SUB. That is,
12694 * <PRE>
12695 * [dstBase + dstDisp] -= (byte) srcReg
12696 * </PRE>
12697 *
12698 * @param dstBase the base register
12699 * @param dstDisp the destination displacement
12700 * @param srcReg the source register
12701 */
12702 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
12703 public final void emitSUB_RegDisp_Reg_Byte(GPR dstBase, Offset dstDisp, GPR srcReg) {
12704 int miStart = mi;
12705 // no group 1 to 4 prefix byte
12706 generateREXprefix(false, srcReg, null, dstBase);
12707 // single byte opcode
12708 setMachineCodes(mi++, (byte) 0x28);
12709 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
12710 if (lister != null) lister.RDR(miStart, "SUB", dstBase, dstDisp, srcReg);
12711 }
12712
12713 /**
12714 * Generate a register--register SUB. That is,
12715 * <PRE>
12716 * dstReg -= (byte) srcReg
12717 * </PRE>
12718 *
12719 * @param dstReg the destination register
12720 * @param srcReg the source register
12721 */
12722 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12723 public final void emitSUB_Reg_Reg_Byte(GPR dstReg, GPR srcReg) {
12724 int miStart = mi;
12725 // no group 1 to 4 prefix byte
12726 generateREXprefix(false, srcReg, null, dstReg);
12727 // single byte opcode
12728 setMachineCodes(mi++, (byte) 0x28);
12729 emitRegRegOperands(dstReg, srcReg);
12730 if (lister != null) lister.RR(miStart, "SUB", dstReg, srcReg);
12731 }
12732
12733 /**
12734 * Generate a register--register-displacement SUB. That is,
12735 * <PRE>
12736 * dstReg -= (byte) [srcReg + srcDisp]
12737 * </PRE>
12738 *
12739 * @param dstReg the destination register
12740 * @param srcBase the source register
12741 * @param srcDisp the source displacement
12742 */
12743 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12744 public final void emitSUB_Reg_RegDisp_Byte(GPR dstReg, GPR srcBase, Offset srcDisp) {
12745 int miStart = mi;
12746 // no group 1 to 4 prefix byte
12747 generateREXprefix(false, dstReg, null, srcBase);
12748 // single byte opcode
12749 setMachineCodes(mi++, (byte) 0x2A);
12750 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
12751 if (lister != null) lister.RRD(miStart, "SUB", dstReg, srcBase, srcDisp);
12752 }
12753
12754 /**
12755 * Generate a register--register-offset SUB. That is,
12756 * <PRE>
12757 * dstReg -= (byte) [srcIndex<<srcScale + srcDisp]
12758 * </PRE>
12759 *
12760 * @param dstReg the destination register
12761 * @param srcIndex the source index register
12762 * @param srcScale the source shift amount
12763 * @param srcDisp the source displacement
12764 */
12765 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12766 public final void emitSUB_Reg_RegOff_Byte(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
12767 int miStart = mi;
12768 // no group 1 to 4 prefix byte
12769 generateREXprefix(false, dstReg, srcIndex, null);
12770 // single byte opcode
12771 setMachineCodes(mi++, (byte) 0x2A);
12772 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
12773 if (lister != null) lister.RRFD(miStart, "SUB", dstReg, srcIndex, srcScale, srcDisp);
12774 }
12775
12776 /**
12777 * Generate a register--register-offset SUB. That is,
12778 * <PRE>
12779 * dstReg -= (byte) [srcDisp]
12780 * </PRE>
12781 *
12782 * @param dstReg the destination register
12783 * @param srcDisp the source displacement
12784 */
12785 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
12786 public final void emitSUB_Reg_Abs_Byte(GPR dstReg, Address srcDisp) {
12787 int miStart = mi;
12788 // no group 1 to 4 prefix byte
12789 generateREXprefix(false, dstReg, null, null);
12790 // single byte opcode
12791 setMachineCodes(mi++, (byte) 0x2A);
12792 emitAbsRegOperands(srcDisp, dstReg);
12793 if (lister != null) lister.RRA(miStart, "SUB", dstReg, srcDisp);
12794 }
12795
12796 /**
12797 * Generate a register--register-offset SUB. That is,
12798 * <PRE>
12799 * dstReg -= (byte) [srcBase + srcIndex<<srcScale + srcDisp]
12800 * </PRE>
12801 *
12802 * @param dstReg the destination register
12803 * @param srcBase the source base register
12804 * @param srcIndex the source index register
12805 * @param srcScale the source shift amount
12806 * @param srcDisp the source displacement
12807 */
12808 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
12809 public final void emitSUB_Reg_RegIdx_Byte(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
12810 int miStart = mi;
12811 // no group 1 to 4 prefix byte
12812 generateREXprefix(false, dstReg, srcIndex, srcBase);
12813 // single byte opcode
12814 setMachineCodes(mi++, (byte) 0x2A);
12815 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
12816 if (lister != null) lister.RRXD(miStart, "SUB", dstReg, srcBase, srcIndex, srcScale, srcDisp);
12817 }
12818
12819 /**
12820 * Generate a register--register(indirect) SUB. That is,
12821 * <PRE>
12822 * dstReg -= (byte) [srcBase]
12823 * </PRE>
12824 *
12825 * @param dstReg the destination register
12826 * @param srcBase the source base register
12827 */
12828 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12829 public final void emitSUB_Reg_RegInd_Byte(GPR dstReg, GPR srcBase) {
12830 int miStart = mi;
12831 // no group 1 to 4 prefix byte
12832 generateREXprefix(false, dstReg, null, srcBase);
12833 // single byte opcode
12834 setMachineCodes(mi++, (byte) 0x2A);
12835 emitRegIndirectRegOperands(srcBase, dstReg);
12836 if (lister != null) lister.RRN(miStart, "SUB", dstReg, srcBase);
12837 }
12838
12839 /**
12840 * Generate a register--immediate SUB. That is,
12841 * <PRE>
12842 * dstReg -= imm
12843 * </PRE>
12844 *
12845 * @param dstReg the destination register
12846 * @param imm immediate
12847 */
12848 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
12849 public final void emitSUB_Reg_Imm(GPR dstReg, int imm) {
12850 int miStart = mi;
12851 // no group 1 to 4 prefix byte
12852 generateREXprefix(false, null, null, dstReg);
12853 // single byte opcode
12854 if (fits(imm,8)) {
12855 setMachineCodes(mi++, (byte) 0x83);
12856 // "register 0x5" is really part of the opcode
12857 emitRegRegOperands(dstReg, GPR.getForOpcode(0x5));
12858 emitImm8((byte)imm);
12859 } else if (dstReg == EAX) {
12860 setMachineCodes(mi++, (byte) 0x2D);
12861 emitImm32(imm);
12862 } else {
12863 setMachineCodes(mi++, (byte) 0x81);
12864 // "register 0x5" is really part of the opcode
12865 emitRegRegOperands(dstReg, GPR.getForOpcode(0x5));
12866 emitImm32(imm);
12867 }
12868 if (lister != null) lister.RI(miStart, "SUB", dstReg, imm);
12869 }
12870
12871 /**
12872 * Generate a register-displacement--immediate SUB. That is,
12873 * <PRE>
12874 * [dstBase + dstDisp] -= imm
12875 * </PRE>
12876 *
12877 * @param dstBase the destination register
12878 * @param dstDisp the destination displacement
12879 * @param imm immediate
12880 */
12881 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
12882 public final void emitSUB_RegDisp_Imm(GPR dstBase, Offset dstDisp, int imm) {
12883 int miStart = mi;
12884 // no group 1 to 4 prefix byte
12885 generateREXprefix(false, null, null, dstBase);
12886 // single byte opcode
12887 if (fits(imm,8)) {
12888 setMachineCodes(mi++, (byte) 0x83);
12889 // "register 0x5" is really part of the opcode
12890 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x5));
12891 emitImm8((byte)imm);
12892 } else {
12893 setMachineCodes(mi++, (byte) 0x81);
12894 // "register 0x5" is really part of the opcode
12895 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x5));
12896 emitImm32(imm);
12897 }
12898 if (lister != null) lister.RDI(miStart, "SUB", dstBase, dstDisp, imm);
12899 }
12900
12901 /**
12902 * Generate a register-offset--immediate SUB. That is,
12903 * <PRE>
12904 * [dstIndex<<dstScale + dstDisp] -= imm
12905 * </PRE>
12906 *
12907 * @param dstIndex the destination index register
12908 * @param dstScale the destination shift amount
12909 * @param dstDisp the destination displacement
12910 * @param imm immediate
12911 */
12912 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
12913 public final void emitSUB_RegOff_Imm(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
12914 int miStart = mi;
12915 // no group 1 to 4 prefix byte
12916 generateREXprefix(false, null, dstIndex, null);
12917 // single byte opcode
12918 if (fits(imm,8)) {
12919 setMachineCodes(mi++, (byte) 0x83);
12920 // "register 0x5" is really part of the opcode
12921 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
12922 emitImm8((byte)imm);
12923 } else {
12924 setMachineCodes(mi++, (byte) 0x81);
12925 // "register 0x5" is really part of the opcode
12926 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
12927 emitImm32(imm);
12928 }
12929 if (lister != null) lister.RFDI(miStart, "SUB", dstIndex, dstScale, dstDisp, imm);
12930 }
12931
12932 /**
12933 * Generate a absolute--immediate SUB. That is,
12934 * <PRE>
12935 * [dstDisp] -= imm
12936 * </PRE>
12937 *
12938 * @param dstDisp the destination displacement
12939 * @param imm immediate
12940 */
12941 public final void emitSUB_Abs_Imm(Address dstDisp, int imm) {
12942 int miStart = mi;
12943 // no group 1 to 4 prefix byte
12944 generateREXprefix(false, null, null, null);
12945 // single byte opcode
12946 if (fits(imm,8)) {
12947 setMachineCodes(mi++, (byte) 0x83);
12948 // "register 0x5" is really part of the opcode
12949 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x5));
12950 emitImm8((byte)imm);
12951 } else {
12952 setMachineCodes(mi++, (byte) 0x81);
12953 // "register 0x5" is really part of the opcode
12954 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x5));
12955 emitImm32(imm);
12956 }
12957 if (lister != null) lister.RAI(miStart, "SUB", dstDisp, imm);
12958 }
12959
12960 /**
12961 * Generate a register-index--immediate SUB. That is,
12962 * <PRE>
12963 * [dstBase + dstIndex<<dstScale + dstDisp] -= imm
12964 * </PRE>
12965 *
12966 * @param dstBase the destination base register
12967 * @param dstIndex the destination index register
12968 * @param dstScale the destination shift amount
12969 * @param dstDisp the destination displacement
12970 * @param imm immediate
12971 */
12972 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
12973 public final void emitSUB_RegIdx_Imm(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
12974 int miStart = mi;
12975 // no group 1 to 4 prefix byte
12976 generateREXprefix(false, null, dstIndex, dstBase);
12977 // single byte opcode
12978 if (fits(imm,8)) {
12979 setMachineCodes(mi++, (byte) 0x83);
12980 // "register 0x5" is really part of the opcode
12981 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
12982 emitImm8((byte)imm);
12983 } else {
12984 setMachineCodes(mi++, (byte) 0x81);
12985 // "register 0x5" is really part of the opcode
12986 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
12987 emitImm32(imm);
12988 }
12989 if (lister != null) lister.RXDI(miStart, "SUB", dstBase, dstIndex, dstScale, dstDisp, imm);
12990 }
12991
12992 /**
12993 * Generate a register(indirect)--immediate SUB. That is,
12994 * <PRE>
12995 * [dstBase] -= imm
12996 * </PRE>
12997 *
12998 * @param dstBase the destination base register
12999 * @param imm immediate
13000 */
13001 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
13002 public final void emitSUB_RegInd_Imm(GPR dstBase, int imm) {
13003 int miStart = mi;
13004 // no group 1 to 4 prefix byte
13005 generateREXprefix(false, null, null, dstBase);
13006 // single byte opcode
13007 if (fits(imm,8)) {
13008 setMachineCodes(mi++, (byte) 0x83);
13009 // "register 0x5" is really part of the opcode
13010 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x5));
13011 emitImm8((byte)imm);
13012 } else {
13013 setMachineCodes(mi++, (byte) 0x81);
13014 // "register 0x5" is really part of the opcode
13015 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x5));
13016 emitImm32(imm);
13017 }
13018 if (lister != null) lister.RNI(miStart, "SUB", dstBase, imm);
13019 }
13020
13021 /**
13022 * Generate a register--immediate SUB. That is,
13023 * <PRE>
13024 * dstReg -= (word) imm
13025 * </PRE>
13026 *
13027 * @param dstReg the destination register
13028 * @param imm immediate
13029 */
13030 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
13031 public final void emitSUB_Reg_Imm_Word(GPR dstReg, int imm) {
13032 int miStart = mi;
13033 setMachineCodes(mi++, (byte) 0x66);
13034 generateREXprefix(false, null, null, dstReg);
13035 // single byte opcode
13036 if (fits(imm,8)) {
13037 setMachineCodes(mi++, (byte) 0x83);
13038 // "register 0x5" is really part of the opcode
13039 emitRegRegOperands(dstReg, GPR.getForOpcode(0x5));
13040 emitImm8((byte)imm);
13041 } else if (dstReg == EAX) {
13042 setMachineCodes(mi++, (byte) 0x2D);
13043 emitImm16(imm);
13044 } else {
13045 setMachineCodes(mi++, (byte) 0x81);
13046 // "register 0x5" is really part of the opcode
13047 emitRegRegOperands(dstReg, GPR.getForOpcode(0x5));
13048 emitImm16(imm);
13049 }
13050 if (lister != null) lister.RI(miStart, "SUB", dstReg, imm);
13051 }
13052
13053 /**
13054 * Generate a register-displacement--immediate SUB. That is,
13055 * <PRE>
13056 * [dstBase + dstDisp] -= (word) imm
13057 * </PRE>
13058 *
13059 * @param dstBase the destination register
13060 * @param dstDisp the destination displacement
13061 * @param imm immediate
13062 */
13063 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
13064 public final void emitSUB_RegDisp_Imm_Word(GPR dstBase, Offset dstDisp, int imm) {
13065 int miStart = mi;
13066 setMachineCodes(mi++, (byte) 0x66);
13067 generateREXprefix(false, null, null, dstBase);
13068 // single byte opcode
13069 if (fits(imm,8)) {
13070 setMachineCodes(mi++, (byte) 0x83);
13071 // "register 0x5" is really part of the opcode
13072 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x5));
13073 emitImm8((byte)imm);
13074 } else {
13075 setMachineCodes(mi++, (byte) 0x81);
13076 // "register 0x5" is really part of the opcode
13077 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x5));
13078 emitImm16(imm);
13079 }
13080 if (lister != null) lister.RDI(miStart, "SUB", dstBase, dstDisp, imm);
13081 }
13082
13083 /**
13084 * Generate a register-offset--immediate SUB. That is,
13085 * <PRE>
13086 * [dstIndex<<dstScale + dstDisp] -= (word) imm
13087 * </PRE>
13088 *
13089 * @param dstIndex the destination index register
13090 * @param dstScale the destination shift amount
13091 * @param dstDisp the destination displacement
13092 * @param imm immediate
13093 */
13094 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
13095 public final void emitSUB_RegOff_Imm_Word(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
13096 int miStart = mi;
13097 setMachineCodes(mi++, (byte) 0x66);
13098 generateREXprefix(false, null, dstIndex, null);
13099 // single byte opcode
13100 if (fits(imm,8)) {
13101 setMachineCodes(mi++, (byte) 0x83);
13102 // "register 0x5" is really part of the opcode
13103 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
13104 emitImm8((byte)imm);
13105 } else {
13106 setMachineCodes(mi++, (byte) 0x81);
13107 // "register 0x5" is really part of the opcode
13108 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
13109 emitImm16(imm);
13110 }
13111 if (lister != null) lister.RFDI(miStart, "SUB", dstIndex, dstScale, dstDisp, imm);
13112 }
13113
13114 /**
13115 * Generate a absolute--immediate SUB. That is,
13116 * <PRE>
13117 * [dstDisp] -= (word) imm
13118 * </PRE>
13119 *
13120 * @param dstDisp the destination displacement
13121 * @param imm immediate
13122 */
13123 public final void emitSUB_Abs_Imm_Word(Address dstDisp, int imm) {
13124 int miStart = mi;
13125 setMachineCodes(mi++, (byte) 0x66);
13126 generateREXprefix(false, null, null, null);
13127 // single byte opcode
13128 if (fits(imm,8)) {
13129 setMachineCodes(mi++, (byte) 0x83);
13130 // "register 0x5" is really part of the opcode
13131 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x5));
13132 emitImm8((byte)imm);
13133 } else {
13134 setMachineCodes(mi++, (byte) 0x81);
13135 // "register 0x5" is really part of the opcode
13136 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x5));
13137 emitImm16(imm);
13138 }
13139 if (lister != null) lister.RAI(miStart, "SUB", dstDisp, imm);
13140 }
13141
13142 /**
13143 * Generate a register-index--immediate SUB. That is,
13144 * <PRE>
13145 * [dstBase + dstIndex<<dstScale + dstDisp] -= (word) imm
13146 * </PRE>
13147 *
13148 * @param dstBase the destination base register
13149 * @param dstIndex the destination index register
13150 * @param dstScale the destination shift amount
13151 * @param dstDisp the destination displacement
13152 * @param imm immediate
13153 */
13154 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
13155 public final void emitSUB_RegIdx_Imm_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
13156 int miStart = mi;
13157 setMachineCodes(mi++, (byte) 0x66);
13158 generateREXprefix(false, null, dstIndex, dstBase);
13159 // single byte opcode
13160 if (fits(imm,8)) {
13161 setMachineCodes(mi++, (byte) 0x83);
13162 // "register 0x5" is really part of the opcode
13163 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
13164 emitImm8((byte)imm);
13165 } else {
13166 setMachineCodes(mi++, (byte) 0x81);
13167 // "register 0x5" is really part of the opcode
13168 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
13169 emitImm16(imm);
13170 }
13171 if (lister != null) lister.RXDI(miStart, "SUB", dstBase, dstIndex, dstScale, dstDisp, imm);
13172 }
13173
13174 /**
13175 * Generate a register(indirect)--immediate SUB. That is,
13176 * <PRE>
13177 * [dstBase] -= (word) imm
13178 * </PRE>
13179 *
13180 * @param dstBase the destination base register
13181 * @param imm immediate
13182 */
13183 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
13184 public final void emitSUB_RegInd_Imm_Word(GPR dstBase, int imm) {
13185 int miStart = mi;
13186 setMachineCodes(mi++, (byte) 0x66);
13187 generateREXprefix(false, null, null, dstBase);
13188 // single byte opcode
13189 if (fits(imm,8)) {
13190 setMachineCodes(mi++, (byte) 0x83);
13191 // "register 0x5" is really part of the opcode
13192 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x5));
13193 emitImm8((byte)imm);
13194 } else {
13195 setMachineCodes(mi++, (byte) 0x81);
13196 // "register 0x5" is really part of the opcode
13197 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x5));
13198 emitImm16(imm);
13199 }
13200 if (lister != null) lister.RNI(miStart, "SUB", dstBase, imm);
13201 }
13202
13203 /**
13204 * Generate a register--immediate SUB. That is,
13205 * <PRE>
13206 * dstReg -= (quad) imm
13207 * </PRE>
13208 *
13209 * @param dstReg the destination register
13210 * @param imm immediate
13211 */
13212 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
13213 public final void emitSUB_Reg_Imm_Quad(GPR dstReg, int imm) {
13214 int miStart = mi;
13215 // no group 1 to 4 prefix byte
13216 generateREXprefix(true, null, null, dstReg);
13217 // single byte opcode
13218 if (fits(imm,8)) {
13219 setMachineCodes(mi++, (byte) 0x83);
13220 // "register 0x5" is really part of the opcode
13221 emitRegRegOperands(dstReg, GPR.getForOpcode(0x5));
13222 emitImm8((byte)imm);
13223 } else if (dstReg == EAX) {
13224 setMachineCodes(mi++, (byte) 0x2D);
13225 emitImm32(imm);
13226 } else {
13227 setMachineCodes(mi++, (byte) 0x81);
13228 // "register 0x5" is really part of the opcode
13229 emitRegRegOperands(dstReg, GPR.getForOpcode(0x5));
13230 emitImm32(imm);
13231 }
13232 if (lister != null) lister.RI(miStart, "SUB", dstReg, imm);
13233 }
13234
13235 /**
13236 * Generate a register-displacement--immediate SUB. That is,
13237 * <PRE>
13238 * [dstBase + dstDisp] -= (quad) imm
13239 * </PRE>
13240 *
13241 * @param dstBase the destination register
13242 * @param dstDisp the destination displacement
13243 * @param imm immediate
13244 */
13245 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
13246 public final void emitSUB_RegDisp_Imm_Quad(GPR dstBase, Offset dstDisp, int imm) {
13247 int miStart = mi;
13248 // no group 1 to 4 prefix byte
13249 generateREXprefix(true, null, null, dstBase);
13250 // single byte opcode
13251 if (fits(imm,8)) {
13252 setMachineCodes(mi++, (byte) 0x83);
13253 // "register 0x5" is really part of the opcode
13254 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x5));
13255 emitImm8((byte)imm);
13256 } else {
13257 setMachineCodes(mi++, (byte) 0x81);
13258 // "register 0x5" is really part of the opcode
13259 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x5));
13260 emitImm32(imm);
13261 }
13262 if (lister != null) lister.RDI(miStart, "SUB", dstBase, dstDisp, imm);
13263 }
13264
13265 /**
13266 * Generate a register-offset--immediate SUB. That is,
13267 * <PRE>
13268 * [dstIndex<<dstScale + dstDisp] -= (quad) imm
13269 * </PRE>
13270 *
13271 * @param dstIndex the destination index register
13272 * @param dstScale the destination shift amount
13273 * @param dstDisp the destination displacement
13274 * @param imm immediate
13275 */
13276 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
13277 public final void emitSUB_RegOff_Imm_Quad(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
13278 int miStart = mi;
13279 // no group 1 to 4 prefix byte
13280 generateREXprefix(true, null, dstIndex, null);
13281 // single byte opcode
13282 if (fits(imm,8)) {
13283 setMachineCodes(mi++, (byte) 0x83);
13284 // "register 0x5" is really part of the opcode
13285 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
13286 emitImm8((byte)imm);
13287 } else {
13288 setMachineCodes(mi++, (byte) 0x81);
13289 // "register 0x5" is really part of the opcode
13290 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
13291 emitImm32(imm);
13292 }
13293 if (lister != null) lister.RFDI(miStart, "SUB", dstIndex, dstScale, dstDisp, imm);
13294 }
13295
13296 /**
13297 * Generate a absolute--immediate SUB. That is,
13298 * <PRE>
13299 * [dstDisp] -= (quad) imm
13300 * </PRE>
13301 *
13302 * @param dstDisp the destination displacement
13303 * @param imm immediate
13304 */
13305 public final void emitSUB_Abs_Imm_Quad(Address dstDisp, int imm) {
13306 int miStart = mi;
13307 // no group 1 to 4 prefix byte
13308 generateREXprefix(true, null, null, null);
13309 // single byte opcode
13310 if (fits(imm,8)) {
13311 setMachineCodes(mi++, (byte) 0x83);
13312 // "register 0x5" is really part of the opcode
13313 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x5));
13314 emitImm8((byte)imm);
13315 } else {
13316 setMachineCodes(mi++, (byte) 0x81);
13317 // "register 0x5" is really part of the opcode
13318 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x5));
13319 emitImm32(imm);
13320 }
13321 if (lister != null) lister.RAI(miStart, "SUB", dstDisp, imm);
13322 }
13323
13324 /**
13325 * Generate a register-index--immediate SUB. That is,
13326 * <PRE>
13327 * [dstBase + dstIndex<<dstScale + dstDisp] -= (quad) imm
13328 * </PRE>
13329 *
13330 * @param dstBase the destination base register
13331 * @param dstIndex the destination index register
13332 * @param dstScale the destination shift amount
13333 * @param dstDisp the destination displacement
13334 * @param imm immediate
13335 */
13336 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
13337 public final void emitSUB_RegIdx_Imm_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
13338 int miStart = mi;
13339 // no group 1 to 4 prefix byte
13340 generateREXprefix(true, null, dstIndex, dstBase);
13341 // single byte opcode
13342 if (fits(imm,8)) {
13343 setMachineCodes(mi++, (byte) 0x83);
13344 // "register 0x5" is really part of the opcode
13345 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
13346 emitImm8((byte)imm);
13347 } else {
13348 setMachineCodes(mi++, (byte) 0x81);
13349 // "register 0x5" is really part of the opcode
13350 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
13351 emitImm32(imm);
13352 }
13353 if (lister != null) lister.RXDI(miStart, "SUB", dstBase, dstIndex, dstScale, dstDisp, imm);
13354 }
13355
13356 /**
13357 * Generate a register(indirect)--immediate SUB. That is,
13358 * <PRE>
13359 * [dstBase] -= (quad) imm
13360 * </PRE>
13361 *
13362 * @param dstBase the destination base register
13363 * @param imm immediate
13364 */
13365 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
13366 public final void emitSUB_RegInd_Imm_Quad(GPR dstBase, int imm) {
13367 int miStart = mi;
13368 // no group 1 to 4 prefix byte
13369 generateREXprefix(true, null, null, dstBase);
13370 // single byte opcode
13371 if (fits(imm,8)) {
13372 setMachineCodes(mi++, (byte) 0x83);
13373 // "register 0x5" is really part of the opcode
13374 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x5));
13375 emitImm8((byte)imm);
13376 } else {
13377 setMachineCodes(mi++, (byte) 0x81);
13378 // "register 0x5" is really part of the opcode
13379 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x5));
13380 emitImm32(imm);
13381 }
13382 if (lister != null) lister.RNI(miStart, "SUB", dstBase, imm);
13383 }
13384
13385 /**
13386 * Generate a register--immediate SUB. That is,
13387 * <PRE>
13388 * dstReg -= (byte) imm
13389 * </PRE>
13390 *
13391 * @param dstReg the destination register
13392 * @param imm immediate
13393 */
13394 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
13395 public final void emitSUB_Reg_Imm_Byte(GPR dstReg, int imm) {
13396 int miStart = mi;
13397 if (dstReg == EAX) {
13398 setMachineCodes(mi++, (byte) 0x2C);
13399 emitImm8(imm);
13400 } else {
13401 generateREXprefix(false, null, null, dstReg);
13402 setMachineCodes(mi++, (byte) 0x80);
13403 // "register 0x5" is really part of the opcode
13404 emitRegRegOperands(dstReg, GPR.getForOpcode(0x5));
13405 emitImm8(imm);
13406 }
13407 if (lister != null) lister.RI(miStart, "SUB", dstReg, imm);
13408 }
13409
13410 /**
13411 * Generate a register-displacement--immediate SUB. That is,
13412 * <PRE>
13413 * [dstBase + dstDisp] -= (byte) imm
13414 * </PRE>
13415 *
13416 * @param dstBase the destination register
13417 * @param dstDisp the destination displacement
13418 * @param imm immediate
13419 */
13420 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
13421 public final void emitSUB_RegDisp_Imm_Byte(GPR dstBase, Offset dstDisp, int imm) {
13422 int miStart = mi;
13423 generateREXprefix(false, null, null, dstBase);
13424 setMachineCodes(mi++, (byte) 0x80);
13425 // "register 0x5" is really part of the opcode
13426 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x5));
13427 emitImm8(imm);
13428 if (lister != null) lister.RDI(miStart, "SUB", dstBase, dstDisp, imm);
13429 }
13430
13431 /**
13432 * Generate a register-index--immediate SUB. That is,
13433 * <PRE>
13434 * [dstBase + dstIndex<<scale + dstDisp] -= (byte) imm
13435 * </PRE>
13436 *
13437 * @param dstBase the destination base register
13438 * @param dstIndex the destination index register
13439 * @param dstScale the destination shift amount
13440 * @param dstDisp the destination displacement
13441 * @param imm immediate
13442 */
13443 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
13444 public final void emitSUB_RegIdx_Imm_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
13445 int miStart = mi;
13446 generateREXprefix(false, null, dstIndex, dstBase);
13447 setMachineCodes(mi++, (byte) 0x80);
13448 // "register 0x5" is really part of the opcode
13449 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
13450 emitImm8(imm);
13451 if (lister != null) lister.RXDI(miStart, "SUB", dstBase, dstIndex, dstScale, dstDisp, imm);
13452 }
13453
13454 /**
13455 * Generate a register-offset--immediate SUB. That is,
13456 * <PRE>
13457 * [dstIndex<<dstScale + dstDisp] -= (byte) imm
13458 * </PRE>
13459 *
13460 * @param dstIndex the destination index register
13461 * @param dstScale the destination shift amount
13462 * @param dstDisp the destination displacement
13463 * @param imm immediate
13464 */
13465 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
13466 public final void emitSUB_RegOff_Imm_Byte(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
13467 int miStart = mi;
13468 generateREXprefix(false, null, dstIndex, null);
13469 setMachineCodes(mi++, (byte) 0x80);
13470 // "register 0x5" is really part of the opcode
13471 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
13472 emitImm8(imm);
13473 if (lister != null) lister.RFDI(miStart, "SUB", dstIndex, dstScale, dstDisp, imm);
13474 }
13475
13476 /**
13477 * Generate a absolute--immediate SUB. That is,
13478 * <PRE>
13479 * [dstDisp] -= (byte) imm
13480 * </PRE>
13481 *
13482 * @param dstDisp the destination displacement
13483 * @param imm immediate
13484 */
13485 public final void emitSUB_Abs_Imm_Byte(Address dstDisp, int imm) {
13486 int miStart = mi;
13487 generateREXprefix(false, null, null, null);
13488 setMachineCodes(mi++, (byte) 0x80);
13489 // "register 0x5" is really part of the opcode
13490 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x5));
13491 emitImm8(imm);
13492 if (lister != null) lister.RAI(miStart, "SUB", dstDisp, imm);
13493 }
13494
13495 /**
13496 * Generate a register(indirect)--immediate SUB. That is,
13497 * <PRE>
13498 * [dstBase] -= (byte) imm
13499 * </PRE>
13500 *
13501 * @param dstBase the destination base register
13502 * @param imm immediate
13503 */
13504 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
13505 public final void emitSUB_RegInd_Imm_Byte(GPR dstBase, int imm) {
13506 int miStart = mi;
13507 generateREXprefix(false, null, null, dstBase);
13508 setMachineCodes(mi++, (byte) 0x80);
13509 // "register 0x5" is really part of the opcode
13510 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x5));
13511 emitImm8(imm);
13512 if (lister != null) lister.RNI(miStart, "SUB", dstBase, imm);
13513 }
13514
13515 /**
13516 * Generate a register(indirect)--register TEST. That is,
13517 * <PRE>
13518 * [dstBase] &= srcReg
13519 * </PRE>
13520 *
13521 * @param dstBase the destination base
13522 * @param srcReg the source register
13523 */
13524 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
13525 public final void emitTEST_RegInd_Reg(GPR dstBase, GPR srcReg) {
13526 int miStart = mi;
13527 // no group 1 to 4 prefix byte
13528 generateREXprefix(false, srcReg, null, dstBase);
13529 // single byte opcode
13530 setMachineCodes(mi++, (byte) 0x85);
13531 emitRegIndirectRegOperands(dstBase, srcReg);
13532 if (lister != null) lister.RNR(miStart, "TEST", dstBase, srcReg);
13533 }
13534
13535 /**
13536 * Generate a register-offset--register TEST. That is,
13537 * <PRE>
13538 * [dstReg<<dstScale + dstDisp] &= srcReg
13539 * </PRE>
13540 *
13541 * @param dstIndex the destination index register
13542 * @param dstScale the destination shift amount
13543 * @param dstDisp the destination displacement
13544 * @param srcReg the source register
13545 */
13546 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
13547 public final void emitTEST_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
13548 int miStart = mi;
13549 // no group 1 to 4 prefix byte
13550 generateREXprefix(false, srcReg, dstIndex, null);
13551 // single byte opcode
13552 setMachineCodes(mi++, (byte) 0x85);
13553 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
13554 if (lister != null) lister.RFDR(miStart, "TEST", dstIndex, dstScale, dstDisp, srcReg);
13555 }
13556
13557 /**
13558 * Generate a absolute--register TEST. That is,
13559 * <PRE>
13560 * [dstDisp] &= srcReg
13561 * </PRE>
13562 *
13563 * @param dstDisp the destination address
13564 * @param srcReg the source register
13565 */
13566 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
13567 public final void emitTEST_Abs_Reg(Address dstDisp, GPR srcReg) {
13568 int miStart = mi;
13569 // no group 1 to 4 prefix byte
13570 generateREXprefix(false, srcReg, null, null);
13571 // single byte opcode
13572 setMachineCodes(mi++, (byte) 0x85);
13573 emitAbsRegOperands(dstDisp, srcReg);
13574 if (lister != null) lister.RAR(miStart, "TEST", dstDisp, srcReg);
13575 }
13576
13577 /**
13578 * Generate a register-index--register TEST. That is,
13579 * <PRE>
13580 * [dstBase + dstIndex<<dstScale + dstDisp] &= srcReg
13581 * </PRE>
13582 *
13583 * @param dstBase the base register
13584 * @param dstIndex the destination index register
13585 * @param dstScale the destination shift amount
13586 * @param dstDisp the destination displacement
13587 * @param srcReg the source register
13588 */
13589 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
13590 public final void emitTEST_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
13591 int miStart = mi;
13592 // no group 1 to 4 prefix byte
13593 generateREXprefix(false, srcReg, dstIndex, dstBase);
13594 // single byte opcode
13595 setMachineCodes(mi++, (byte) 0x85);
13596 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
13597 if (lister != null) lister.RXDR(miStart, "TEST", dstBase, dstIndex, dstScale, dstDisp, srcReg);
13598 }
13599
13600 /**
13601 * Generate a register-displacement--register TEST. That is,
13602 * <PRE>
13603 * [dstBase + dstDisp] &= srcReg
13604 * </PRE>
13605 *
13606 * @param dstBase the base register
13607 * @param dstDisp the destination displacement
13608 * @param srcReg the source register
13609 */
13610 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
13611 public final void emitTEST_RegDisp_Reg(GPR dstBase, Offset dstDisp, GPR srcReg) {
13612 int miStart = mi;
13613 // no group 1 to 4 prefix byte
13614 generateREXprefix(false, srcReg, null, dstBase);
13615 // single byte opcode
13616 setMachineCodes(mi++, (byte) 0x85);
13617 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
13618 if (lister != null) lister.RDR(miStart, "TEST", dstBase, dstDisp, srcReg);
13619 }
13620
13621 /**
13622 * Generate a register--register TEST. That is,
13623 * <PRE>
13624 * dstReg &= srcReg
13625 * </PRE>
13626 *
13627 * @param dstReg the destination register
13628 * @param srcReg the source register
13629 */
13630 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
13631 public final void emitTEST_Reg_Reg(GPR dstReg, GPR srcReg) {
13632 int miStart = mi;
13633 // no group 1 to 4 prefix byte
13634 generateREXprefix(false, srcReg, null, dstReg);
13635 // single byte opcode
13636 setMachineCodes(mi++, (byte) 0x85);
13637 emitRegRegOperands(dstReg, srcReg);
13638 if (lister != null) lister.RR(miStart, "TEST", dstReg, srcReg);
13639 }
13640
13641 /**
13642 * Generate a register(indirect)--register TEST. That is,
13643 * <PRE>
13644 * [dstBase] &= (word) srcReg
13645 * </PRE>
13646 *
13647 * @param dstBase the destination base
13648 * @param srcReg the source register
13649 */
13650 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
13651 public final void emitTEST_RegInd_Reg_Word(GPR dstBase, GPR srcReg) {
13652 int miStart = mi;
13653 setMachineCodes(mi++, (byte) 0x66);
13654 generateREXprefix(false, srcReg, null, dstBase);
13655 // single byte opcode
13656 setMachineCodes(mi++, (byte) 0x85);
13657 emitRegIndirectRegOperands(dstBase, srcReg);
13658 if (lister != null) lister.RNR(miStart, "TEST", dstBase, srcReg);
13659 }
13660
13661 /**
13662 * Generate a register-offset--register TEST. That is,
13663 * <PRE>
13664 * [dstReg<<dstScale + dstDisp] &= (word) srcReg
13665 * </PRE>
13666 *
13667 * @param dstIndex the destination index register
13668 * @param dstScale the destination shift amount
13669 * @param dstDisp the destination displacement
13670 * @param srcReg the source register
13671 */
13672 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
13673 public final void emitTEST_RegOff_Reg_Word(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
13674 int miStart = mi;
13675 setMachineCodes(mi++, (byte) 0x66);
13676 generateREXprefix(false, srcReg, dstIndex, null);
13677 // single byte opcode
13678 setMachineCodes(mi++, (byte) 0x85);
13679 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
13680 if (lister != null) lister.RFDR(miStart, "TEST", dstIndex, dstScale, dstDisp, srcReg);
13681 }
13682
13683 /**
13684 * Generate a absolute--register TEST. That is,
13685 * <PRE>
13686 * [dstDisp] &= (word) srcReg
13687 * </PRE>
13688 *
13689 * @param dstDisp the destination address
13690 * @param srcReg the source register
13691 */
13692 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
13693 public final void emitTEST_Abs_Reg_Word(Address dstDisp, GPR srcReg) {
13694 int miStart = mi;
13695 setMachineCodes(mi++, (byte) 0x66);
13696 generateREXprefix(false, srcReg, null, null);
13697 // single byte opcode
13698 setMachineCodes(mi++, (byte) 0x85);
13699 emitAbsRegOperands(dstDisp, srcReg);
13700 if (lister != null) lister.RAR(miStart, "TEST", dstDisp, srcReg);
13701 }
13702
13703 /**
13704 * Generate a register-index--register TEST. That is,
13705 * <PRE>
13706 * [dstBase + dstIndex<<dstScale + dstDisp] &= (word) srcReg
13707 * </PRE>
13708 *
13709 * @param dstBase the base register
13710 * @param dstIndex the destination index register
13711 * @param dstScale the destination shift amount
13712 * @param dstDisp the destination displacement
13713 * @param srcReg the source register
13714 */
13715 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
13716 public final void emitTEST_RegIdx_Reg_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
13717 int miStart = mi;
13718 setMachineCodes(mi++, (byte) 0x66);
13719 generateREXprefix(false, srcReg, dstIndex, dstBase);
13720 // single byte opcode
13721 setMachineCodes(mi++, (byte) 0x85);
13722 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
13723 if (lister != null) lister.RXDR(miStart, "TEST", dstBase, dstIndex, dstScale, dstDisp, srcReg);
13724 }
13725
13726 /**
13727 * Generate a register-displacement--register TEST. That is,
13728 * <PRE>
13729 * [dstBase + dstDisp] &= (word) srcReg
13730 * </PRE>
13731 *
13732 * @param dstBase the base register
13733 * @param dstDisp the destination displacement
13734 * @param srcReg the source register
13735 */
13736 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
13737 public final void emitTEST_RegDisp_Reg_Word(GPR dstBase, Offset dstDisp, GPR srcReg) {
13738 int miStart = mi;
13739 setMachineCodes(mi++, (byte) 0x66);
13740 generateREXprefix(false, srcReg, null, dstBase);
13741 // single byte opcode
13742 setMachineCodes(mi++, (byte) 0x85);
13743 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
13744 if (lister != null) lister.RDR(miStart, "TEST", dstBase, dstDisp, srcReg);
13745 }
13746
13747 /**
13748 * Generate a register--register TEST. That is,
13749 * <PRE>
13750 * dstReg &= (word) srcReg
13751 * </PRE>
13752 *
13753 * @param dstReg the destination register
13754 * @param srcReg the source register
13755 */
13756 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
13757 public final void emitTEST_Reg_Reg_Word(GPR dstReg, GPR srcReg) {
13758 int miStart = mi;
13759 setMachineCodes(mi++, (byte) 0x66);
13760 generateREXprefix(false, srcReg, null, dstReg);
13761 // single byte opcode
13762 setMachineCodes(mi++, (byte) 0x85);
13763 emitRegRegOperands(dstReg, srcReg);
13764 if (lister != null) lister.RR(miStart, "TEST", dstReg, srcReg);
13765 }
13766
13767 /**
13768 * Generate a register(indirect)--register TEST. That is,
13769 * <PRE>
13770 * [dstBase] &= (quad) srcReg
13771 * </PRE>
13772 *
13773 * @param dstBase the destination base
13774 * @param srcReg the source register
13775 */
13776 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
13777 public final void emitTEST_RegInd_Reg_Quad(GPR dstBase, GPR srcReg) {
13778 int miStart = mi;
13779 // no group 1 to 4 prefix byte
13780 generateREXprefix(true, srcReg, null, dstBase);
13781 // single byte opcode
13782 setMachineCodes(mi++, (byte) 0x85);
13783 emitRegIndirectRegOperands(dstBase, srcReg);
13784 if (lister != null) lister.RNR(miStart, "TEST", dstBase, srcReg);
13785 }
13786
13787 /**
13788 * Generate a register-offset--register TEST. That is,
13789 * <PRE>
13790 * [dstReg<<dstScale + dstDisp] &= (quad) srcReg
13791 * </PRE>
13792 *
13793 * @param dstIndex the destination index register
13794 * @param dstScale the destination shift amount
13795 * @param dstDisp the destination displacement
13796 * @param srcReg the source register
13797 */
13798 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
13799 public final void emitTEST_RegOff_Reg_Quad(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
13800 int miStart = mi;
13801 // no group 1 to 4 prefix byte
13802 generateREXprefix(true, srcReg, dstIndex, null);
13803 // single byte opcode
13804 setMachineCodes(mi++, (byte) 0x85);
13805 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
13806 if (lister != null) lister.RFDR(miStart, "TEST", dstIndex, dstScale, dstDisp, srcReg);
13807 }
13808
13809 /**
13810 * Generate a absolute--register TEST. That is,
13811 * <PRE>
13812 * [dstDisp] &= (quad) srcReg
13813 * </PRE>
13814 *
13815 * @param dstDisp the destination address
13816 * @param srcReg the source register
13817 */
13818 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
13819 public final void emitTEST_Abs_Reg_Quad(Address dstDisp, GPR srcReg) {
13820 int miStart = mi;
13821 // no group 1 to 4 prefix byte
13822 generateREXprefix(true, srcReg, null, null);
13823 // single byte opcode
13824 setMachineCodes(mi++, (byte) 0x85);
13825 emitAbsRegOperands(dstDisp, srcReg);
13826 if (lister != null) lister.RAR(miStart, "TEST", dstDisp, srcReg);
13827 }
13828
13829 /**
13830 * Generate a register-index--register TEST. That is,
13831 * <PRE>
13832 * [dstBase + dstIndex<<dstScale + dstDisp] &= (quad) srcReg
13833 * </PRE>
13834 *
13835 * @param dstBase the base register
13836 * @param dstIndex the destination index register
13837 * @param dstScale the destination shift amount
13838 * @param dstDisp the destination displacement
13839 * @param srcReg the source register
13840 */
13841 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
13842 public final void emitTEST_RegIdx_Reg_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
13843 int miStart = mi;
13844 // no group 1 to 4 prefix byte
13845 generateREXprefix(true, srcReg, dstIndex, dstBase);
13846 // single byte opcode
13847 setMachineCodes(mi++, (byte) 0x85);
13848 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
13849 if (lister != null) lister.RXDR(miStart, "TEST", dstBase, dstIndex, dstScale, dstDisp, srcReg);
13850 }
13851
13852 /**
13853 * Generate a register-displacement--register TEST. That is,
13854 * <PRE>
13855 * [dstBase + dstDisp] &= (quad) srcReg
13856 * </PRE>
13857 *
13858 * @param dstBase the base register
13859 * @param dstDisp the destination displacement
13860 * @param srcReg the source register
13861 */
13862 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
13863 public final void emitTEST_RegDisp_Reg_Quad(GPR dstBase, Offset dstDisp, GPR srcReg) {
13864 int miStart = mi;
13865 // no group 1 to 4 prefix byte
13866 generateREXprefix(true, srcReg, null, dstBase);
13867 // single byte opcode
13868 setMachineCodes(mi++, (byte) 0x85);
13869 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
13870 if (lister != null) lister.RDR(miStart, "TEST", dstBase, dstDisp, srcReg);
13871 }
13872
13873 /**
13874 * Generate a register--register TEST. That is,
13875 * <PRE>
13876 * dstReg &= (quad) srcReg
13877 * </PRE>
13878 *
13879 * @param dstReg the destination register
13880 * @param srcReg the source register
13881 */
13882 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
13883 public final void emitTEST_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
13884 int miStart = mi;
13885 // no group 1 to 4 prefix byte
13886 generateREXprefix(true, srcReg, null, dstReg);
13887 // single byte opcode
13888 setMachineCodes(mi++, (byte) 0x85);
13889 emitRegRegOperands(dstReg, srcReg);
13890 if (lister != null) lister.RR(miStart, "TEST", dstReg, srcReg);
13891 }
13892
13893 /**
13894 * Generate a register(indirect)--register TEST. That is,
13895 * <PRE>
13896 * [dstBase] &= (byte) srcReg
13897 * </PRE>
13898 *
13899 * @param dstBase the destination base
13900 * @param srcReg the source register
13901 */
13902 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
13903 public final void emitTEST_RegInd_Reg_Byte(GPR dstBase, GPR srcReg) {
13904 int miStart = mi;
13905 // no group 1 to 4 prefix byte
13906 generateREXprefix(false, srcReg, null, dstBase);
13907 // single byte opcode
13908 setMachineCodes(mi++, (byte) 0x84);
13909 emitRegIndirectRegOperands(dstBase, srcReg);
13910 if (lister != null) lister.RNR(miStart, "TEST", dstBase, srcReg);
13911 }
13912
13913 /**
13914 * Generate a register-offset--register TEST. That is,
13915 * <PRE>
13916 * [dstReg<<dstScale + dstDisp] &= (byte) srcReg
13917 * </PRE>
13918 *
13919 * @param dstIndex the destination index register
13920 * @param dstScale the destination shift amount
13921 * @param dstDisp the destination displacement
13922 * @param srcReg the source register
13923 */
13924 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
13925 public final void emitTEST_RegOff_Reg_Byte(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
13926 int miStart = mi;
13927 // no group 1 to 4 prefix byte
13928 generateREXprefix(false, srcReg, dstIndex, null);
13929 // single byte opcode
13930 setMachineCodes(mi++, (byte) 0x84);
13931 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
13932 if (lister != null) lister.RFDR(miStart, "TEST", dstIndex, dstScale, dstDisp, srcReg);
13933 }
13934
13935 /**
13936 * Generate a absolute--register TEST. That is,
13937 * <PRE>
13938 * [dstDisp] &= (byte) srcReg
13939 * </PRE>
13940 *
13941 * @param dstDisp the destination address
13942 * @param srcReg the source register
13943 */
13944 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
13945 public final void emitTEST_Abs_Reg_Byte(Address dstDisp, GPR srcReg) {
13946 int miStart = mi;
13947 // no group 1 to 4 prefix byte
13948 generateREXprefix(false, srcReg, null, null);
13949 // single byte opcode
13950 setMachineCodes(mi++, (byte) 0x84);
13951 emitAbsRegOperands(dstDisp, srcReg);
13952 if (lister != null) lister.RAR(miStart, "TEST", dstDisp, srcReg);
13953 }
13954
13955 /**
13956 * Generate a register-index--register TEST. That is,
13957 * <PRE>
13958 * [dstBase + dstIndex<<dstScale + dstDisp] &= (byte) srcReg
13959 * </PRE>
13960 *
13961 * @param dstBase the base register
13962 * @param dstIndex the destination index register
13963 * @param dstScale the destination shift amount
13964 * @param dstDisp the destination displacement
13965 * @param srcReg the source register
13966 */
13967 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
13968 public final void emitTEST_RegIdx_Reg_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
13969 int miStart = mi;
13970 // no group 1 to 4 prefix byte
13971 generateREXprefix(false, srcReg, dstIndex, dstBase);
13972 // single byte opcode
13973 setMachineCodes(mi++, (byte) 0x84);
13974 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
13975 if (lister != null) lister.RXDR(miStart, "TEST", dstBase, dstIndex, dstScale, dstDisp, srcReg);
13976 }
13977
13978 /**
13979 * Generate a register-displacement--register TEST. That is,
13980 * <PRE>
13981 * [dstBase + dstDisp] &= (byte) srcReg
13982 * </PRE>
13983 *
13984 * @param dstBase the base register
13985 * @param dstDisp the destination displacement
13986 * @param srcReg the source register
13987 */
13988 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
13989 public final void emitTEST_RegDisp_Reg_Byte(GPR dstBase, Offset dstDisp, GPR srcReg) {
13990 int miStart = mi;
13991 // no group 1 to 4 prefix byte
13992 generateREXprefix(false, srcReg, null, dstBase);
13993 // single byte opcode
13994 setMachineCodes(mi++, (byte) 0x84);
13995 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
13996 if (lister != null) lister.RDR(miStart, "TEST", dstBase, dstDisp, srcReg);
13997 }
13998
13999 /**
14000 * Generate a register--register TEST. That is,
14001 * <PRE>
14002 * dstReg &= (byte) srcReg
14003 * </PRE>
14004 *
14005 * @param dstReg the destination register
14006 * @param srcReg the source register
14007 */
14008 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
14009 public final void emitTEST_Reg_Reg_Byte(GPR dstReg, GPR srcReg) {
14010 int miStart = mi;
14011 // no group 1 to 4 prefix byte
14012 generateREXprefix(false, srcReg, null, dstReg);
14013 // single byte opcode
14014 setMachineCodes(mi++, (byte) 0x84);
14015 emitRegRegOperands(dstReg, srcReg);
14016 if (lister != null) lister.RR(miStart, "TEST", dstReg, srcReg);
14017 }
14018
14019 /**
14020 * Generate a register--immediate TEST. That is,
14021 * <PRE>
14022 * dstReg &= imm
14023 * </PRE>
14024 *
14025 * @param dstReg the destination register
14026 * @param imm immediate
14027 */
14028 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
14029 public final void emitTEST_Reg_Imm(GPR dstReg, int imm) {
14030 int miStart = mi;
14031 // no group 1 to 4 prefix byte
14032 generateREXprefix(false, null, null, dstReg);
14033 // single byte opcode
14034 if (false) {
14035 } else if (dstReg == EAX) {
14036 setMachineCodes(mi++, (byte) 0xA9);
14037 emitImm32(imm);
14038 } else {
14039 setMachineCodes(mi++, (byte) 0xF7);
14040 // "register 0x0" is really part of the opcode
14041 emitRegRegOperands(dstReg, GPR.getForOpcode(0x0));
14042 emitImm32(imm);
14043 }
14044 if (lister != null) lister.RI(miStart, "TEST", dstReg, imm);
14045 }
14046
14047 /**
14048 * Generate a register-displacement--immediate TEST. That is,
14049 * <PRE>
14050 * [dstBase + dstDisp] &= imm
14051 * </PRE>
14052 *
14053 * @param dstBase the destination register
14054 * @param dstDisp the destination displacement
14055 * @param imm immediate
14056 */
14057 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
14058 public final void emitTEST_RegDisp_Imm(GPR dstBase, Offset dstDisp, int imm) {
14059 int miStart = mi;
14060 // no group 1 to 4 prefix byte
14061 generateREXprefix(false, null, null, dstBase);
14062 // single byte opcode
14063 if (false) {
14064 } else {
14065 setMachineCodes(mi++, (byte) 0xF7);
14066 // "register 0x0" is really part of the opcode
14067 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
14068 emitImm32(imm);
14069 }
14070 if (lister != null) lister.RDI(miStart, "TEST", dstBase, dstDisp, imm);
14071 }
14072
14073 /**
14074 * Generate a register-offset--immediate TEST. That is,
14075 * <PRE>
14076 * [dstIndex<<dstScale + dstDisp] &= imm
14077 * </PRE>
14078 *
14079 * @param dstIndex the destination index register
14080 * @param dstScale the destination shift amount
14081 * @param dstDisp the destination displacement
14082 * @param imm immediate
14083 */
14084 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
14085 public final void emitTEST_RegOff_Imm(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
14086 int miStart = mi;
14087 // no group 1 to 4 prefix byte
14088 generateREXprefix(false, null, dstIndex, null);
14089 // single byte opcode
14090 if (false) {
14091 } else {
14092 setMachineCodes(mi++, (byte) 0xF7);
14093 // "register 0x0" is really part of the opcode
14094 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
14095 emitImm32(imm);
14096 }
14097 if (lister != null) lister.RFDI(miStart, "TEST", dstIndex, dstScale, dstDisp, imm);
14098 }
14099
14100 /**
14101 * Generate a absolute--immediate TEST. That is,
14102 * <PRE>
14103 * [dstDisp] &= imm
14104 * </PRE>
14105 *
14106 * @param dstDisp the destination displacement
14107 * @param imm immediate
14108 */
14109 public final void emitTEST_Abs_Imm(Address dstDisp, int imm) {
14110 int miStart = mi;
14111 // no group 1 to 4 prefix byte
14112 generateREXprefix(false, null, null, null);
14113 // single byte opcode
14114 if (false) {
14115 } else {
14116 setMachineCodes(mi++, (byte) 0xF7);
14117 // "register 0x0" is really part of the opcode
14118 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
14119 emitImm32(imm);
14120 }
14121 if (lister != null) lister.RAI(miStart, "TEST", dstDisp, imm);
14122 }
14123
14124 /**
14125 * Generate a register-index--immediate TEST. That is,
14126 * <PRE>
14127 * [dstBase + dstIndex<<dstScale + dstDisp] &= imm
14128 * </PRE>
14129 *
14130 * @param dstBase the destination base register
14131 * @param dstIndex the destination index register
14132 * @param dstScale the destination shift amount
14133 * @param dstDisp the destination displacement
14134 * @param imm immediate
14135 */
14136 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
14137 public final void emitTEST_RegIdx_Imm(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
14138 int miStart = mi;
14139 // no group 1 to 4 prefix byte
14140 generateREXprefix(false, null, dstIndex, dstBase);
14141 // single byte opcode
14142 if (false) {
14143 } else {
14144 setMachineCodes(mi++, (byte) 0xF7);
14145 // "register 0x0" is really part of the opcode
14146 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
14147 emitImm32(imm);
14148 }
14149 if (lister != null) lister.RXDI(miStart, "TEST", dstBase, dstIndex, dstScale, dstDisp, imm);
14150 }
14151
14152 /**
14153 * Generate a register(indirect)--immediate TEST. That is,
14154 * <PRE>
14155 * [dstBase] &= imm
14156 * </PRE>
14157 *
14158 * @param dstBase the destination base register
14159 * @param imm immediate
14160 */
14161 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
14162 public final void emitTEST_RegInd_Imm(GPR dstBase, int imm) {
14163 int miStart = mi;
14164 // no group 1 to 4 prefix byte
14165 generateREXprefix(false, null, null, dstBase);
14166 // single byte opcode
14167 if (false) {
14168 } else {
14169 setMachineCodes(mi++, (byte) 0xF7);
14170 // "register 0x0" is really part of the opcode
14171 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
14172 emitImm32(imm);
14173 }
14174 if (lister != null) lister.RNI(miStart, "TEST", dstBase, imm);
14175 }
14176
14177 /**
14178 * Generate a register--immediate TEST. That is,
14179 * <PRE>
14180 * dstReg &= (word) imm
14181 * </PRE>
14182 *
14183 * @param dstReg the destination register
14184 * @param imm immediate
14185 */
14186 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
14187 public final void emitTEST_Reg_Imm_Word(GPR dstReg, int imm) {
14188 int miStart = mi;
14189 setMachineCodes(mi++, (byte) 0x66);
14190 generateREXprefix(false, null, null, dstReg);
14191 // single byte opcode
14192 if (false) {
14193 } else if (dstReg == EAX) {
14194 setMachineCodes(mi++, (byte) 0xA9);
14195 emitImm16(imm);
14196 } else {
14197 setMachineCodes(mi++, (byte) 0xF7);
14198 // "register 0x0" is really part of the opcode
14199 emitRegRegOperands(dstReg, GPR.getForOpcode(0x0));
14200 emitImm16(imm);
14201 }
14202 if (lister != null) lister.RI(miStart, "TEST", dstReg, imm);
14203 }
14204
14205 /**
14206 * Generate a register-displacement--immediate TEST. That is,
14207 * <PRE>
14208 * [dstBase + dstDisp] &= (word) imm
14209 * </PRE>
14210 *
14211 * @param dstBase the destination register
14212 * @param dstDisp the destination displacement
14213 * @param imm immediate
14214 */
14215 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
14216 public final void emitTEST_RegDisp_Imm_Word(GPR dstBase, Offset dstDisp, int imm) {
14217 int miStart = mi;
14218 setMachineCodes(mi++, (byte) 0x66);
14219 generateREXprefix(false, null, null, dstBase);
14220 // single byte opcode
14221 if (false) {
14222 } else {
14223 setMachineCodes(mi++, (byte) 0xF7);
14224 // "register 0x0" is really part of the opcode
14225 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
14226 emitImm16(imm);
14227 }
14228 if (lister != null) lister.RDI(miStart, "TEST", dstBase, dstDisp, imm);
14229 }
14230
14231 /**
14232 * Generate a register-offset--immediate TEST. That is,
14233 * <PRE>
14234 * [dstIndex<<dstScale + dstDisp] &= (word) imm
14235 * </PRE>
14236 *
14237 * @param dstIndex the destination index register
14238 * @param dstScale the destination shift amount
14239 * @param dstDisp the destination displacement
14240 * @param imm immediate
14241 */
14242 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
14243 public final void emitTEST_RegOff_Imm_Word(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
14244 int miStart = mi;
14245 setMachineCodes(mi++, (byte) 0x66);
14246 generateREXprefix(false, null, dstIndex, null);
14247 // single byte opcode
14248 if (false) {
14249 } else {
14250 setMachineCodes(mi++, (byte) 0xF7);
14251 // "register 0x0" is really part of the opcode
14252 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
14253 emitImm16(imm);
14254 }
14255 if (lister != null) lister.RFDI(miStart, "TEST", dstIndex, dstScale, dstDisp, imm);
14256 }
14257
14258 /**
14259 * Generate a absolute--immediate TEST. That is,
14260 * <PRE>
14261 * [dstDisp] &= (word) imm
14262 * </PRE>
14263 *
14264 * @param dstDisp the destination displacement
14265 * @param imm immediate
14266 */
14267 public final void emitTEST_Abs_Imm_Word(Address dstDisp, int imm) {
14268 int miStart = mi;
14269 setMachineCodes(mi++, (byte) 0x66);
14270 generateREXprefix(false, null, null, null);
14271 // single byte opcode
14272 if (false) {
14273 } else {
14274 setMachineCodes(mi++, (byte) 0xF7);
14275 // "register 0x0" is really part of the opcode
14276 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
14277 emitImm16(imm);
14278 }
14279 if (lister != null) lister.RAI(miStart, "TEST", dstDisp, imm);
14280 }
14281
14282 /**
14283 * Generate a register-index--immediate TEST. That is,
14284 * <PRE>
14285 * [dstBase + dstIndex<<dstScale + dstDisp] &= (word) imm
14286 * </PRE>
14287 *
14288 * @param dstBase the destination base register
14289 * @param dstIndex the destination index register
14290 * @param dstScale the destination shift amount
14291 * @param dstDisp the destination displacement
14292 * @param imm immediate
14293 */
14294 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
14295 public final void emitTEST_RegIdx_Imm_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
14296 int miStart = mi;
14297 setMachineCodes(mi++, (byte) 0x66);
14298 generateREXprefix(false, null, dstIndex, dstBase);
14299 // single byte opcode
14300 if (false) {
14301 } else {
14302 setMachineCodes(mi++, (byte) 0xF7);
14303 // "register 0x0" is really part of the opcode
14304 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
14305 emitImm16(imm);
14306 }
14307 if (lister != null) lister.RXDI(miStart, "TEST", dstBase, dstIndex, dstScale, dstDisp, imm);
14308 }
14309
14310 /**
14311 * Generate a register(indirect)--immediate TEST. That is,
14312 * <PRE>
14313 * [dstBase] &= (word) imm
14314 * </PRE>
14315 *
14316 * @param dstBase the destination base register
14317 * @param imm immediate
14318 */
14319 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
14320 public final void emitTEST_RegInd_Imm_Word(GPR dstBase, int imm) {
14321 int miStart = mi;
14322 setMachineCodes(mi++, (byte) 0x66);
14323 generateREXprefix(false, null, null, dstBase);
14324 // single byte opcode
14325 if (false) {
14326 } else {
14327 setMachineCodes(mi++, (byte) 0xF7);
14328 // "register 0x0" is really part of the opcode
14329 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
14330 emitImm16(imm);
14331 }
14332 if (lister != null) lister.RNI(miStart, "TEST", dstBase, imm);
14333 }
14334
14335 /**
14336 * Generate a register--immediate TEST. That is,
14337 * <PRE>
14338 * dstReg &= (quad) imm
14339 * </PRE>
14340 *
14341 * @param dstReg the destination register
14342 * @param imm immediate
14343 */
14344 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
14345 public final void emitTEST_Reg_Imm_Quad(GPR dstReg, int imm) {
14346 int miStart = mi;
14347 // no group 1 to 4 prefix byte
14348 generateREXprefix(true, null, null, dstReg);
14349 // single byte opcode
14350 if (false) {
14351 } else if (dstReg == EAX) {
14352 setMachineCodes(mi++, (byte) 0xA9);
14353 emitImm32(imm);
14354 } else {
14355 setMachineCodes(mi++, (byte) 0xF7);
14356 // "register 0x0" is really part of the opcode
14357 emitRegRegOperands(dstReg, GPR.getForOpcode(0x0));
14358 emitImm32(imm);
14359 }
14360 if (lister != null) lister.RI(miStart, "TEST", dstReg, imm);
14361 }
14362
14363 /**
14364 * Generate a register-displacement--immediate TEST. That is,
14365 * <PRE>
14366 * [dstBase + dstDisp] &= (quad) imm
14367 * </PRE>
14368 *
14369 * @param dstBase the destination register
14370 * @param dstDisp the destination displacement
14371 * @param imm immediate
14372 */
14373 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
14374 public final void emitTEST_RegDisp_Imm_Quad(GPR dstBase, Offset dstDisp, int imm) {
14375 int miStart = mi;
14376 // no group 1 to 4 prefix byte
14377 generateREXprefix(true, null, null, dstBase);
14378 // single byte opcode
14379 if (false) {
14380 } else {
14381 setMachineCodes(mi++, (byte) 0xF7);
14382 // "register 0x0" is really part of the opcode
14383 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
14384 emitImm32(imm);
14385 }
14386 if (lister != null) lister.RDI(miStart, "TEST", dstBase, dstDisp, imm);
14387 }
14388
14389 /**
14390 * Generate a register-offset--immediate TEST. That is,
14391 * <PRE>
14392 * [dstIndex<<dstScale + dstDisp] &= (quad) imm
14393 * </PRE>
14394 *
14395 * @param dstIndex the destination index register
14396 * @param dstScale the destination shift amount
14397 * @param dstDisp the destination displacement
14398 * @param imm immediate
14399 */
14400 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
14401 public final void emitTEST_RegOff_Imm_Quad(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
14402 int miStart = mi;
14403 // no group 1 to 4 prefix byte
14404 generateREXprefix(true, null, dstIndex, null);
14405 // single byte opcode
14406 if (false) {
14407 } else {
14408 setMachineCodes(mi++, (byte) 0xF7);
14409 // "register 0x0" is really part of the opcode
14410 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
14411 emitImm32(imm);
14412 }
14413 if (lister != null) lister.RFDI(miStart, "TEST", dstIndex, dstScale, dstDisp, imm);
14414 }
14415
14416 /**
14417 * Generate a absolute--immediate TEST. That is,
14418 * <PRE>
14419 * [dstDisp] &= (quad) imm
14420 * </PRE>
14421 *
14422 * @param dstDisp the destination displacement
14423 * @param imm immediate
14424 */
14425 public final void emitTEST_Abs_Imm_Quad(Address dstDisp, int imm) {
14426 int miStart = mi;
14427 // no group 1 to 4 prefix byte
14428 generateREXprefix(true, null, null, null);
14429 // single byte opcode
14430 if (false) {
14431 } else {
14432 setMachineCodes(mi++, (byte) 0xF7);
14433 // "register 0x0" is really part of the opcode
14434 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
14435 emitImm32(imm);
14436 }
14437 if (lister != null) lister.RAI(miStart, "TEST", dstDisp, imm);
14438 }
14439
14440 /**
14441 * Generate a register-index--immediate TEST. That is,
14442 * <PRE>
14443 * [dstBase + dstIndex<<dstScale + dstDisp] &= (quad) imm
14444 * </PRE>
14445 *
14446 * @param dstBase the destination base register
14447 * @param dstIndex the destination index register
14448 * @param dstScale the destination shift amount
14449 * @param dstDisp the destination displacement
14450 * @param imm immediate
14451 */
14452 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
14453 public final void emitTEST_RegIdx_Imm_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
14454 int miStart = mi;
14455 // no group 1 to 4 prefix byte
14456 generateREXprefix(true, null, dstIndex, dstBase);
14457 // single byte opcode
14458 if (false) {
14459 } else {
14460 setMachineCodes(mi++, (byte) 0xF7);
14461 // "register 0x0" is really part of the opcode
14462 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
14463 emitImm32(imm);
14464 }
14465 if (lister != null) lister.RXDI(miStart, "TEST", dstBase, dstIndex, dstScale, dstDisp, imm);
14466 }
14467
14468 /**
14469 * Generate a register(indirect)--immediate TEST. That is,
14470 * <PRE>
14471 * [dstBase] &= (quad) imm
14472 * </PRE>
14473 *
14474 * @param dstBase the destination base register
14475 * @param imm immediate
14476 */
14477 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
14478 public final void emitTEST_RegInd_Imm_Quad(GPR dstBase, int imm) {
14479 int miStart = mi;
14480 // no group 1 to 4 prefix byte
14481 generateREXprefix(true, null, null, dstBase);
14482 // single byte opcode
14483 if (false) {
14484 } else {
14485 setMachineCodes(mi++, (byte) 0xF7);
14486 // "register 0x0" is really part of the opcode
14487 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
14488 emitImm32(imm);
14489 }
14490 if (lister != null) lister.RNI(miStart, "TEST", dstBase, imm);
14491 }
14492
14493 /**
14494 * Generate a register--immediate TEST. That is,
14495 * <PRE>
14496 * dstReg &= (byte) imm
14497 * </PRE>
14498 *
14499 * @param dstReg the destination register
14500 * @param imm immediate
14501 */
14502 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
14503 public final void emitTEST_Reg_Imm_Byte(GPR dstReg, int imm) {
14504 int miStart = mi;
14505 if (dstReg == EAX) {
14506 setMachineCodes(mi++, (byte) 0xA8);
14507 emitImm8(imm);
14508 } else {
14509 generateREXprefix(false, null, null, dstReg);
14510 setMachineCodes(mi++, (byte) 0xF6);
14511 // "register 0x0" is really part of the opcode
14512 emitRegRegOperands(dstReg, GPR.getForOpcode(0x0));
14513 emitImm8(imm);
14514 }
14515 if (lister != null) lister.RI(miStart, "TEST", dstReg, imm);
14516 }
14517
14518 /**
14519 * Generate a register-displacement--immediate TEST. That is,
14520 * <PRE>
14521 * [dstBase + dstDisp] &= (byte) imm
14522 * </PRE>
14523 *
14524 * @param dstBase the destination register
14525 * @param dstDisp the destination displacement
14526 * @param imm immediate
14527 */
14528 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
14529 public final void emitTEST_RegDisp_Imm_Byte(GPR dstBase, Offset dstDisp, int imm) {
14530 int miStart = mi;
14531 generateREXprefix(false, null, null, dstBase);
14532 setMachineCodes(mi++, (byte) 0xF6);
14533 // "register 0x0" is really part of the opcode
14534 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
14535 emitImm8(imm);
14536 if (lister != null) lister.RDI(miStart, "TEST", dstBase, dstDisp, imm);
14537 }
14538
14539 /**
14540 * Generate a register-index--immediate TEST. That is,
14541 * <PRE>
14542 * [dstBase + dstIndex<<scale + dstDisp] &= (byte) imm
14543 * </PRE>
14544 *
14545 * @param dstBase the destination base register
14546 * @param dstIndex the destination index register
14547 * @param dstScale the destination shift amount
14548 * @param dstDisp the destination displacement
14549 * @param imm immediate
14550 */
14551 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
14552 public final void emitTEST_RegIdx_Imm_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
14553 int miStart = mi;
14554 generateREXprefix(false, null, dstIndex, dstBase);
14555 setMachineCodes(mi++, (byte) 0xF6);
14556 // "register 0x0" is really part of the opcode
14557 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
14558 emitImm8(imm);
14559 if (lister != null) lister.RXDI(miStart, "TEST", dstBase, dstIndex, dstScale, dstDisp, imm);
14560 }
14561
14562 /**
14563 * Generate a register-offset--immediate TEST. That is,
14564 * <PRE>
14565 * [dstIndex<<dstScale + dstDisp] &= (byte) imm
14566 * </PRE>
14567 *
14568 * @param dstIndex the destination index register
14569 * @param dstScale the destination shift amount
14570 * @param dstDisp the destination displacement
14571 * @param imm immediate
14572 */
14573 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
14574 public final void emitTEST_RegOff_Imm_Byte(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
14575 int miStart = mi;
14576 generateREXprefix(false, null, dstIndex, null);
14577 setMachineCodes(mi++, (byte) 0xF6);
14578 // "register 0x0" is really part of the opcode
14579 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
14580 emitImm8(imm);
14581 if (lister != null) lister.RFDI(miStart, "TEST", dstIndex, dstScale, dstDisp, imm);
14582 }
14583
14584 /**
14585 * Generate a absolute--immediate TEST. That is,
14586 * <PRE>
14587 * [dstDisp] &= (byte) imm
14588 * </PRE>
14589 *
14590 * @param dstDisp the destination displacement
14591 * @param imm immediate
14592 */
14593 public final void emitTEST_Abs_Imm_Byte(Address dstDisp, int imm) {
14594 int miStart = mi;
14595 generateREXprefix(false, null, null, null);
14596 setMachineCodes(mi++, (byte) 0xF6);
14597 // "register 0x0" is really part of the opcode
14598 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
14599 emitImm8(imm);
14600 if (lister != null) lister.RAI(miStart, "TEST", dstDisp, imm);
14601 }
14602
14603 /**
14604 * Generate a register(indirect)--immediate TEST. That is,
14605 * <PRE>
14606 * [dstBase] &= (byte) imm
14607 * </PRE>
14608 *
14609 * @param dstBase the destination base register
14610 * @param imm immediate
14611 */
14612 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
14613 public final void emitTEST_RegInd_Imm_Byte(GPR dstBase, int imm) {
14614 int miStart = mi;
14615 generateREXprefix(false, null, null, dstBase);
14616 setMachineCodes(mi++, (byte) 0xF6);
14617 // "register 0x0" is really part of the opcode
14618 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
14619 emitImm8(imm);
14620 if (lister != null) lister.RNI(miStart, "TEST", dstBase, imm);
14621 }
14622
14623 /**
14624 * Generate a register(indirect)--register XOR. That is,
14625 * <PRE>
14626 * [dstBase] ~= srcReg
14627 * </PRE>
14628 *
14629 * @param dstBase the destination base
14630 * @param srcReg the source register
14631 */
14632 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
14633 public final void emitXOR_RegInd_Reg(GPR dstBase, GPR srcReg) {
14634 int miStart = mi;
14635 // no group 1 to 4 prefix byte
14636 generateREXprefix(false, srcReg, null, dstBase);
14637 // single byte opcode
14638 setMachineCodes(mi++, (byte) 0x31);
14639 emitRegIndirectRegOperands(dstBase, srcReg);
14640 if (lister != null) lister.RNR(miStart, "XOR", dstBase, srcReg);
14641 }
14642
14643 /**
14644 * Generate a register-offset--register XOR. That is,
14645 * <PRE>
14646 * [dstReg<<dstScale + dstDisp] ~= srcReg
14647 * </PRE>
14648 *
14649 * @param dstIndex the destination index register
14650 * @param dstScale the destination shift amount
14651 * @param dstDisp the destination displacement
14652 * @param srcReg the source register
14653 */
14654 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
14655 public final void emitXOR_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
14656 int miStart = mi;
14657 // no group 1 to 4 prefix byte
14658 generateREXprefix(false, srcReg, dstIndex, null);
14659 // single byte opcode
14660 setMachineCodes(mi++, (byte) 0x31);
14661 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
14662 if (lister != null) lister.RFDR(miStart, "XOR", dstIndex, dstScale, dstDisp, srcReg);
14663 }
14664
14665 /**
14666 * Generate a absolute--register XOR. That is,
14667 * <PRE>
14668 * [dstDisp] ~= srcReg
14669 * </PRE>
14670 *
14671 * @param dstDisp the destination address
14672 * @param srcReg the source register
14673 */
14674 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
14675 public final void emitXOR_Abs_Reg(Address dstDisp, GPR srcReg) {
14676 int miStart = mi;
14677 // no group 1 to 4 prefix byte
14678 generateREXprefix(false, srcReg, null, null);
14679 // single byte opcode
14680 setMachineCodes(mi++, (byte) 0x31);
14681 emitAbsRegOperands(dstDisp, srcReg);
14682 if (lister != null) lister.RAR(miStart, "XOR", dstDisp, srcReg);
14683 }
14684
14685 /**
14686 * Generate a register-index--register XOR. That is,
14687 * <PRE>
14688 * [dstBase + dstIndex<<dstScale + dstDisp] ~= srcReg
14689 * </PRE>
14690 *
14691 * @param dstBase the base register
14692 * @param dstIndex the destination index register
14693 * @param dstScale the destination shift amount
14694 * @param dstDisp the destination displacement
14695 * @param srcReg the source register
14696 */
14697 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
14698 public final void emitXOR_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
14699 int miStart = mi;
14700 // no group 1 to 4 prefix byte
14701 generateREXprefix(false, srcReg, dstIndex, dstBase);
14702 // single byte opcode
14703 setMachineCodes(mi++, (byte) 0x31);
14704 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
14705 if (lister != null) lister.RXDR(miStart, "XOR", dstBase, dstIndex, dstScale, dstDisp, srcReg);
14706 }
14707
14708 /**
14709 * Generate a register-displacement--register XOR. That is,
14710 * <PRE>
14711 * [dstBase + dstDisp] ~= srcReg
14712 * </PRE>
14713 *
14714 * @param dstBase the base register
14715 * @param dstDisp the destination displacement
14716 * @param srcReg the source register
14717 */
14718 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
14719 public final void emitXOR_RegDisp_Reg(GPR dstBase, Offset dstDisp, GPR srcReg) {
14720 int miStart = mi;
14721 // no group 1 to 4 prefix byte
14722 generateREXprefix(false, srcReg, null, dstBase);
14723 // single byte opcode
14724 setMachineCodes(mi++, (byte) 0x31);
14725 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
14726 if (lister != null) lister.RDR(miStart, "XOR", dstBase, dstDisp, srcReg);
14727 }
14728
14729 /**
14730 * Generate a register--register XOR. That is,
14731 * <PRE>
14732 * dstReg ~= srcReg
14733 * </PRE>
14734 *
14735 * @param dstReg the destination register
14736 * @param srcReg the source register
14737 */
14738 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
14739 public final void emitXOR_Reg_Reg(GPR dstReg, GPR srcReg) {
14740 int miStart = mi;
14741 // no group 1 to 4 prefix byte
14742 generateREXprefix(false, srcReg, null, dstReg);
14743 // single byte opcode
14744 setMachineCodes(mi++, (byte) 0x31);
14745 emitRegRegOperands(dstReg, srcReg);
14746 if (lister != null) lister.RR(miStart, "XOR", dstReg, srcReg);
14747 }
14748
14749 /**
14750 * Generate a register--register-displacement XOR. That is,
14751 * <PRE>
14752 * dstReg ~= [srcReg + srcDisp]
14753 * </PRE>
14754 *
14755 * @param dstReg the destination register
14756 * @param srcBase the source register
14757 * @param srcDisp the source displacement
14758 */
14759 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
14760 public final void emitXOR_Reg_RegDisp(GPR dstReg, GPR srcBase, Offset srcDisp) {
14761 int miStart = mi;
14762 // no group 1 to 4 prefix byte
14763 generateREXprefix(false, dstReg, null, srcBase);
14764 // single byte opcode
14765 setMachineCodes(mi++, (byte) 0x33);
14766 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
14767 if (lister != null) lister.RRD(miStart, "XOR", dstReg, srcBase, srcDisp);
14768 }
14769
14770 /**
14771 * Generate a register--register-offset XOR. That is,
14772 * <PRE>
14773 * dstReg ~= [srcIndex<<srcScale + srcDisp]
14774 * </PRE>
14775 *
14776 * @param dstReg the destination register
14777 * @param srcIndex the source index register
14778 * @param srcScale the source shift amount
14779 * @param srcDisp the source displacement
14780 */
14781 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
14782 public final void emitXOR_Reg_RegOff(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
14783 int miStart = mi;
14784 // no group 1 to 4 prefix byte
14785 generateREXprefix(false, dstReg, srcIndex, null);
14786 // single byte opcode
14787 setMachineCodes(mi++, (byte) 0x33);
14788 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
14789 if (lister != null) lister.RRFD(miStart, "XOR", dstReg, srcIndex, srcScale, srcDisp);
14790 }
14791
14792 /**
14793 * Generate a register--register-offset XOR. That is,
14794 * <PRE>
14795 * dstReg ~= [srcDisp]
14796 * </PRE>
14797 *
14798 * @param dstReg the destination register
14799 * @param srcDisp the source displacement
14800 */
14801 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
14802 public final void emitXOR_Reg_Abs(GPR dstReg, Address srcDisp) {
14803 int miStart = mi;
14804 // no group 1 to 4 prefix byte
14805 generateREXprefix(false, dstReg, null, null);
14806 // single byte opcode
14807 setMachineCodes(mi++, (byte) 0x33);
14808 emitAbsRegOperands(srcDisp, dstReg);
14809 if (lister != null) lister.RRA(miStart, "XOR", dstReg, srcDisp);
14810 }
14811
14812 /**
14813 * Generate a register--register-offset XOR. That is,
14814 * <PRE>
14815 * dstReg ~= [srcBase + srcIndex<<srcScale + srcDisp]
14816 * </PRE>
14817 *
14818 * @param dstReg the destination register
14819 * @param srcBase the source base register
14820 * @param srcIndex the source index register
14821 * @param srcScale the source shift amount
14822 * @param srcDisp the source displacement
14823 */
14824 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
14825 public final void emitXOR_Reg_RegIdx(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
14826 int miStart = mi;
14827 // no group 1 to 4 prefix byte
14828 generateREXprefix(false, dstReg, srcIndex, srcBase);
14829 // single byte opcode
14830 setMachineCodes(mi++, (byte) 0x33);
14831 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
14832 if (lister != null) lister.RRXD(miStart, "XOR", dstReg, srcBase, srcIndex, srcScale, srcDisp);
14833 }
14834
14835 /**
14836 * Generate a register--register(indirect) XOR. That is,
14837 * <PRE>
14838 * dstReg ~= [srcBase]
14839 * </PRE>
14840 *
14841 * @param dstReg the destination register
14842 * @param srcBase the source base register
14843 */
14844 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
14845 public final void emitXOR_Reg_RegInd(GPR dstReg, GPR srcBase) {
14846 int miStart = mi;
14847 // no group 1 to 4 prefix byte
14848 generateREXprefix(false, dstReg, null, srcBase);
14849 // single byte opcode
14850 setMachineCodes(mi++, (byte) 0x33);
14851 emitRegIndirectRegOperands(srcBase, dstReg);
14852 if (lister != null) lister.RRN(miStart, "XOR", dstReg, srcBase);
14853 }
14854
14855 /**
14856 * Generate a register(indirect)--register XOR. That is,
14857 * <PRE>
14858 * [dstBase] ~= (word) srcReg
14859 * </PRE>
14860 *
14861 * @param dstBase the destination base
14862 * @param srcReg the source register
14863 */
14864 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
14865 public final void emitXOR_RegInd_Reg_Word(GPR dstBase, GPR srcReg) {
14866 int miStart = mi;
14867 setMachineCodes(mi++, (byte) 0x66);
14868 generateREXprefix(false, srcReg, null, dstBase);
14869 // single byte opcode
14870 setMachineCodes(mi++, (byte) 0x31);
14871 emitRegIndirectRegOperands(dstBase, srcReg);
14872 if (lister != null) lister.RNR(miStart, "XOR", dstBase, srcReg);
14873 }
14874
14875 /**
14876 * Generate a register-offset--register XOR. That is,
14877 * <PRE>
14878 * [dstReg<<dstScale + dstDisp] ~= (word) srcReg
14879 * </PRE>
14880 *
14881 * @param dstIndex the destination index register
14882 * @param dstScale the destination shift amount
14883 * @param dstDisp the destination displacement
14884 * @param srcReg the source register
14885 */
14886 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
14887 public final void emitXOR_RegOff_Reg_Word(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
14888 int miStart = mi;
14889 setMachineCodes(mi++, (byte) 0x66);
14890 generateREXprefix(false, srcReg, dstIndex, null);
14891 // single byte opcode
14892 setMachineCodes(mi++, (byte) 0x31);
14893 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
14894 if (lister != null) lister.RFDR(miStart, "XOR", dstIndex, dstScale, dstDisp, srcReg);
14895 }
14896
14897 /**
14898 * Generate a absolute--register XOR. That is,
14899 * <PRE>
14900 * [dstDisp] ~= (word) srcReg
14901 * </PRE>
14902 *
14903 * @param dstDisp the destination address
14904 * @param srcReg the source register
14905 */
14906 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
14907 public final void emitXOR_Abs_Reg_Word(Address dstDisp, GPR srcReg) {
14908 int miStart = mi;
14909 setMachineCodes(mi++, (byte) 0x66);
14910 generateREXprefix(false, srcReg, null, null);
14911 // single byte opcode
14912 setMachineCodes(mi++, (byte) 0x31);
14913 emitAbsRegOperands(dstDisp, srcReg);
14914 if (lister != null) lister.RAR(miStart, "XOR", dstDisp, srcReg);
14915 }
14916
14917 /**
14918 * Generate a register-index--register XOR. That is,
14919 * <PRE>
14920 * [dstBase + dstIndex<<dstScale + dstDisp] ~= (word) srcReg
14921 * </PRE>
14922 *
14923 * @param dstBase the base register
14924 * @param dstIndex the destination index register
14925 * @param dstScale the destination shift amount
14926 * @param dstDisp the destination displacement
14927 * @param srcReg the source register
14928 */
14929 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
14930 public final void emitXOR_RegIdx_Reg_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
14931 int miStart = mi;
14932 setMachineCodes(mi++, (byte) 0x66);
14933 generateREXprefix(false, srcReg, dstIndex, dstBase);
14934 // single byte opcode
14935 setMachineCodes(mi++, (byte) 0x31);
14936 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
14937 if (lister != null) lister.RXDR(miStart, "XOR", dstBase, dstIndex, dstScale, dstDisp, srcReg);
14938 }
14939
14940 /**
14941 * Generate a register-displacement--register XOR. That is,
14942 * <PRE>
14943 * [dstBase + dstDisp] ~= (word) srcReg
14944 * </PRE>
14945 *
14946 * @param dstBase the base register
14947 * @param dstDisp the destination displacement
14948 * @param srcReg the source register
14949 */
14950 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
14951 public final void emitXOR_RegDisp_Reg_Word(GPR dstBase, Offset dstDisp, GPR srcReg) {
14952 int miStart = mi;
14953 setMachineCodes(mi++, (byte) 0x66);
14954 generateREXprefix(false, srcReg, null, dstBase);
14955 // single byte opcode
14956 setMachineCodes(mi++, (byte) 0x31);
14957 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
14958 if (lister != null) lister.RDR(miStart, "XOR", dstBase, dstDisp, srcReg);
14959 }
14960
14961 /**
14962 * Generate a register--register XOR. That is,
14963 * <PRE>
14964 * dstReg ~= (word) srcReg
14965 * </PRE>
14966 *
14967 * @param dstReg the destination register
14968 * @param srcReg the source register
14969 */
14970 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
14971 public final void emitXOR_Reg_Reg_Word(GPR dstReg, GPR srcReg) {
14972 int miStart = mi;
14973 setMachineCodes(mi++, (byte) 0x66);
14974 generateREXprefix(false, srcReg, null, dstReg);
14975 // single byte opcode
14976 setMachineCodes(mi++, (byte) 0x31);
14977 emitRegRegOperands(dstReg, srcReg);
14978 if (lister != null) lister.RR(miStart, "XOR", dstReg, srcReg);
14979 }
14980
14981 /**
14982 * Generate a register--register-displacement XOR. That is,
14983 * <PRE>
14984 * dstReg ~= (word) [srcReg + srcDisp]
14985 * </PRE>
14986 *
14987 * @param dstReg the destination register
14988 * @param srcBase the source register
14989 * @param srcDisp the source displacement
14990 */
14991 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
14992 public final void emitXOR_Reg_RegDisp_Word(GPR dstReg, GPR srcBase, Offset srcDisp) {
14993 int miStart = mi;
14994 setMachineCodes(mi++, (byte) 0x66);
14995 generateREXprefix(false, dstReg, null, srcBase);
14996 // single byte opcode
14997 setMachineCodes(mi++, (byte) 0x33);
14998 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
14999 if (lister != null) lister.RRD(miStart, "XOR", dstReg, srcBase, srcDisp);
15000 }
15001
15002 /**
15003 * Generate a register--register-offset XOR. That is,
15004 * <PRE>
15005 * dstReg ~= (word) [srcIndex<<srcScale + srcDisp]
15006 * </PRE>
15007 *
15008 * @param dstReg the destination register
15009 * @param srcIndex the source index register
15010 * @param srcScale the source shift amount
15011 * @param srcDisp the source displacement
15012 */
15013 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
15014 public final void emitXOR_Reg_RegOff_Word(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
15015 int miStart = mi;
15016 setMachineCodes(mi++, (byte) 0x66);
15017 generateREXprefix(false, dstReg, srcIndex, null);
15018 // single byte opcode
15019 setMachineCodes(mi++, (byte) 0x33);
15020 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
15021 if (lister != null) lister.RRFD(miStart, "XOR", dstReg, srcIndex, srcScale, srcDisp);
15022 }
15023
15024 /**
15025 * Generate a register--register-offset XOR. That is,
15026 * <PRE>
15027 * dstReg ~= (word) [srcDisp]
15028 * </PRE>
15029 *
15030 * @param dstReg the destination register
15031 * @param srcDisp the source displacement
15032 */
15033 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
15034 public final void emitXOR_Reg_Abs_Word(GPR dstReg, Address srcDisp) {
15035 int miStart = mi;
15036 setMachineCodes(mi++, (byte) 0x66);
15037 generateREXprefix(false, dstReg, null, null);
15038 // single byte opcode
15039 setMachineCodes(mi++, (byte) 0x33);
15040 emitAbsRegOperands(srcDisp, dstReg);
15041 if (lister != null) lister.RRA(miStart, "XOR", dstReg, srcDisp);
15042 }
15043
15044 /**
15045 * Generate a register--register-offset XOR. That is,
15046 * <PRE>
15047 * dstReg ~= (word) [srcBase + srcIndex<<srcScale + srcDisp]
15048 * </PRE>
15049 *
15050 * @param dstReg the destination register
15051 * @param srcBase the source base register
15052 * @param srcIndex the source index register
15053 * @param srcScale the source shift amount
15054 * @param srcDisp the source displacement
15055 */
15056 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
15057 public final void emitXOR_Reg_RegIdx_Word(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
15058 int miStart = mi;
15059 setMachineCodes(mi++, (byte) 0x66);
15060 generateREXprefix(false, dstReg, srcIndex, srcBase);
15061 // single byte opcode
15062 setMachineCodes(mi++, (byte) 0x33);
15063 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
15064 if (lister != null) lister.RRXD(miStart, "XOR", dstReg, srcBase, srcIndex, srcScale, srcDisp);
15065 }
15066
15067 /**
15068 * Generate a register--register(indirect) XOR. That is,
15069 * <PRE>
15070 * dstReg ~= (word) [srcBase]
15071 * </PRE>
15072 *
15073 * @param dstReg the destination register
15074 * @param srcBase the source base register
15075 */
15076 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
15077 public final void emitXOR_Reg_RegInd_Word(GPR dstReg, GPR srcBase) {
15078 int miStart = mi;
15079 setMachineCodes(mi++, (byte) 0x66);
15080 generateREXprefix(false, dstReg, null, srcBase);
15081 // single byte opcode
15082 setMachineCodes(mi++, (byte) 0x33);
15083 emitRegIndirectRegOperands(srcBase, dstReg);
15084 if (lister != null) lister.RRN(miStart, "XOR", dstReg, srcBase);
15085 }
15086
15087 /**
15088 * Generate a register(indirect)--register XOR. That is,
15089 * <PRE>
15090 * [dstBase] ~= (quad) srcReg
15091 * </PRE>
15092 *
15093 * @param dstBase the destination base
15094 * @param srcReg the source register
15095 */
15096 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
15097 public final void emitXOR_RegInd_Reg_Quad(GPR dstBase, GPR srcReg) {
15098 int miStart = mi;
15099 // no group 1 to 4 prefix byte
15100 generateREXprefix(true, srcReg, null, dstBase);
15101 // single byte opcode
15102 setMachineCodes(mi++, (byte) 0x31);
15103 emitRegIndirectRegOperands(dstBase, srcReg);
15104 if (lister != null) lister.RNR(miStart, "XOR", dstBase, srcReg);
15105 }
15106
15107 /**
15108 * Generate a register-offset--register XOR. That is,
15109 * <PRE>
15110 * [dstReg<<dstScale + dstDisp] ~= (quad) srcReg
15111 * </PRE>
15112 *
15113 * @param dstIndex the destination index register
15114 * @param dstScale the destination shift amount
15115 * @param dstDisp the destination displacement
15116 * @param srcReg the source register
15117 */
15118 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
15119 public final void emitXOR_RegOff_Reg_Quad(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
15120 int miStart = mi;
15121 // no group 1 to 4 prefix byte
15122 generateREXprefix(true, srcReg, dstIndex, null);
15123 // single byte opcode
15124 setMachineCodes(mi++, (byte) 0x31);
15125 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
15126 if (lister != null) lister.RFDR(miStart, "XOR", dstIndex, dstScale, dstDisp, srcReg);
15127 }
15128
15129 /**
15130 * Generate a absolute--register XOR. That is,
15131 * <PRE>
15132 * [dstDisp] ~= (quad) srcReg
15133 * </PRE>
15134 *
15135 * @param dstDisp the destination address
15136 * @param srcReg the source register
15137 */
15138 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
15139 public final void emitXOR_Abs_Reg_Quad(Address dstDisp, GPR srcReg) {
15140 int miStart = mi;
15141 // no group 1 to 4 prefix byte
15142 generateREXprefix(true, srcReg, null, null);
15143 // single byte opcode
15144 setMachineCodes(mi++, (byte) 0x31);
15145 emitAbsRegOperands(dstDisp, srcReg);
15146 if (lister != null) lister.RAR(miStart, "XOR", dstDisp, srcReg);
15147 }
15148
15149 /**
15150 * Generate a register-index--register XOR. That is,
15151 * <PRE>
15152 * [dstBase + dstIndex<<dstScale + dstDisp] ~= (quad) srcReg
15153 * </PRE>
15154 *
15155 * @param dstBase the base register
15156 * @param dstIndex the destination index register
15157 * @param dstScale the destination shift amount
15158 * @param dstDisp the destination displacement
15159 * @param srcReg the source register
15160 */
15161 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
15162 public final void emitXOR_RegIdx_Reg_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
15163 int miStart = mi;
15164 // no group 1 to 4 prefix byte
15165 generateREXprefix(true, srcReg, dstIndex, dstBase);
15166 // single byte opcode
15167 setMachineCodes(mi++, (byte) 0x31);
15168 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
15169 if (lister != null) lister.RXDR(miStart, "XOR", dstBase, dstIndex, dstScale, dstDisp, srcReg);
15170 }
15171
15172 /**
15173 * Generate a register-displacement--register XOR. That is,
15174 * <PRE>
15175 * [dstBase + dstDisp] ~= (quad) srcReg
15176 * </PRE>
15177 *
15178 * @param dstBase the base register
15179 * @param dstDisp the destination displacement
15180 * @param srcReg the source register
15181 */
15182 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
15183 public final void emitXOR_RegDisp_Reg_Quad(GPR dstBase, Offset dstDisp, GPR srcReg) {
15184 int miStart = mi;
15185 // no group 1 to 4 prefix byte
15186 generateREXprefix(true, srcReg, null, dstBase);
15187 // single byte opcode
15188 setMachineCodes(mi++, (byte) 0x31);
15189 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
15190 if (lister != null) lister.RDR(miStart, "XOR", dstBase, dstDisp, srcReg);
15191 }
15192
15193 /**
15194 * Generate a register--register XOR. That is,
15195 * <PRE>
15196 * dstReg ~= (quad) srcReg
15197 * </PRE>
15198 *
15199 * @param dstReg the destination register
15200 * @param srcReg the source register
15201 */
15202 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
15203 public final void emitXOR_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
15204 int miStart = mi;
15205 // no group 1 to 4 prefix byte
15206 generateREXprefix(true, srcReg, null, dstReg);
15207 // single byte opcode
15208 setMachineCodes(mi++, (byte) 0x31);
15209 emitRegRegOperands(dstReg, srcReg);
15210 if (lister != null) lister.RR(miStart, "XOR", dstReg, srcReg);
15211 }
15212
15213 /**
15214 * Generate a register--register-displacement XOR. That is,
15215 * <PRE>
15216 * dstReg ~= (quad) [srcReg + srcDisp]
15217 * </PRE>
15218 *
15219 * @param dstReg the destination register
15220 * @param srcBase the source register
15221 * @param srcDisp the source displacement
15222 */
15223 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
15224 public final void emitXOR_Reg_RegDisp_Quad(GPR dstReg, GPR srcBase, Offset srcDisp) {
15225 int miStart = mi;
15226 // no group 1 to 4 prefix byte
15227 generateREXprefix(true, dstReg, null, srcBase);
15228 // single byte opcode
15229 setMachineCodes(mi++, (byte) 0x33);
15230 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
15231 if (lister != null) lister.RRD(miStart, "XOR", dstReg, srcBase, srcDisp);
15232 }
15233
15234 /**
15235 * Generate a register--register-offset XOR. That is,
15236 * <PRE>
15237 * dstReg ~= (quad) [srcIndex<<srcScale + srcDisp]
15238 * </PRE>
15239 *
15240 * @param dstReg the destination register
15241 * @param srcIndex the source index register
15242 * @param srcScale the source shift amount
15243 * @param srcDisp the source displacement
15244 */
15245 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
15246 public final void emitXOR_Reg_RegOff_Quad(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
15247 int miStart = mi;
15248 // no group 1 to 4 prefix byte
15249 generateREXprefix(true, dstReg, srcIndex, null);
15250 // single byte opcode
15251 setMachineCodes(mi++, (byte) 0x33);
15252 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
15253 if (lister != null) lister.RRFD(miStart, "XOR", dstReg, srcIndex, srcScale, srcDisp);
15254 }
15255
15256 /**
15257 * Generate a register--register-offset XOR. That is,
15258 * <PRE>
15259 * dstReg ~= (quad) [srcDisp]
15260 * </PRE>
15261 *
15262 * @param dstReg the destination register
15263 * @param srcDisp the source displacement
15264 */
15265 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
15266 public final void emitXOR_Reg_Abs_Quad(GPR dstReg, Address srcDisp) {
15267 int miStart = mi;
15268 // no group 1 to 4 prefix byte
15269 generateREXprefix(true, dstReg, null, null);
15270 // single byte opcode
15271 setMachineCodes(mi++, (byte) 0x33);
15272 emitAbsRegOperands(srcDisp, dstReg);
15273 if (lister != null) lister.RRA(miStart, "XOR", dstReg, srcDisp);
15274 }
15275
15276 /**
15277 * Generate a register--register-offset XOR. That is,
15278 * <PRE>
15279 * dstReg ~= (quad) [srcBase + srcIndex<<srcScale + srcDisp]
15280 * </PRE>
15281 *
15282 * @param dstReg the destination register
15283 * @param srcBase the source base register
15284 * @param srcIndex the source index register
15285 * @param srcScale the source shift amount
15286 * @param srcDisp the source displacement
15287 */
15288 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
15289 public final void emitXOR_Reg_RegIdx_Quad(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
15290 int miStart = mi;
15291 // no group 1 to 4 prefix byte
15292 generateREXprefix(true, dstReg, srcIndex, srcBase);
15293 // single byte opcode
15294 setMachineCodes(mi++, (byte) 0x33);
15295 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
15296 if (lister != null) lister.RRXD(miStart, "XOR", dstReg, srcBase, srcIndex, srcScale, srcDisp);
15297 }
15298
15299 /**
15300 * Generate a register--register(indirect) XOR. That is,
15301 * <PRE>
15302 * dstReg ~= (quad) [srcBase]
15303 * </PRE>
15304 *
15305 * @param dstReg the destination register
15306 * @param srcBase the source base register
15307 */
15308 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
15309 public final void emitXOR_Reg_RegInd_Quad(GPR dstReg, GPR srcBase) {
15310 int miStart = mi;
15311 // no group 1 to 4 prefix byte
15312 generateREXprefix(true, dstReg, null, srcBase);
15313 // single byte opcode
15314 setMachineCodes(mi++, (byte) 0x33);
15315 emitRegIndirectRegOperands(srcBase, dstReg);
15316 if (lister != null) lister.RRN(miStart, "XOR", dstReg, srcBase);
15317 }
15318
15319 /**
15320 * Generate a register(indirect)--register XOR. That is,
15321 * <PRE>
15322 * [dstBase] ~= (byte) srcReg
15323 * </PRE>
15324 *
15325 * @param dstBase the destination base
15326 * @param srcReg the source register
15327 */
15328 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
15329 public final void emitXOR_RegInd_Reg_Byte(GPR dstBase, GPR srcReg) {
15330 int miStart = mi;
15331 // no group 1 to 4 prefix byte
15332 generateREXprefix(false, srcReg, null, dstBase);
15333 // single byte opcode
15334 setMachineCodes(mi++, (byte) 0x30);
15335 emitRegIndirectRegOperands(dstBase, srcReg);
15336 if (lister != null) lister.RNR(miStart, "XOR", dstBase, srcReg);
15337 }
15338
15339 /**
15340 * Generate a register-offset--register XOR. That is,
15341 * <PRE>
15342 * [dstReg<<dstScale + dstDisp] ~= (byte) srcReg
15343 * </PRE>
15344 *
15345 * @param dstIndex the destination index register
15346 * @param dstScale the destination shift amount
15347 * @param dstDisp the destination displacement
15348 * @param srcReg the source register
15349 */
15350 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
15351 public final void emitXOR_RegOff_Reg_Byte(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
15352 int miStart = mi;
15353 // no group 1 to 4 prefix byte
15354 generateREXprefix(false, srcReg, dstIndex, null);
15355 // single byte opcode
15356 setMachineCodes(mi++, (byte) 0x30);
15357 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
15358 if (lister != null) lister.RFDR(miStart, "XOR", dstIndex, dstScale, dstDisp, srcReg);
15359 }
15360
15361 /**
15362 * Generate a absolute--register XOR. That is,
15363 * <PRE>
15364 * [dstDisp] ~= (byte) srcReg
15365 * </PRE>
15366 *
15367 * @param dstDisp the destination address
15368 * @param srcReg the source register
15369 */
15370 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
15371 public final void emitXOR_Abs_Reg_Byte(Address dstDisp, GPR srcReg) {
15372 int miStart = mi;
15373 // no group 1 to 4 prefix byte
15374 generateREXprefix(false, srcReg, null, null);
15375 // single byte opcode
15376 setMachineCodes(mi++, (byte) 0x30);
15377 emitAbsRegOperands(dstDisp, srcReg);
15378 if (lister != null) lister.RAR(miStart, "XOR", dstDisp, srcReg);
15379 }
15380
15381 /**
15382 * Generate a register-index--register XOR. That is,
15383 * <PRE>
15384 * [dstBase + dstIndex<<dstScale + dstDisp] ~= (byte) srcReg
15385 * </PRE>
15386 *
15387 * @param dstBase the base register
15388 * @param dstIndex the destination index register
15389 * @param dstScale the destination shift amount
15390 * @param dstDisp the destination displacement
15391 * @param srcReg the source register
15392 */
15393 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
15394 public final void emitXOR_RegIdx_Reg_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
15395 int miStart = mi;
15396 // no group 1 to 4 prefix byte
15397 generateREXprefix(false, srcReg, dstIndex, dstBase);
15398 // single byte opcode
15399 setMachineCodes(mi++, (byte) 0x30);
15400 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
15401 if (lister != null) lister.RXDR(miStart, "XOR", dstBase, dstIndex, dstScale, dstDisp, srcReg);
15402 }
15403
15404 /**
15405 * Generate a register-displacement--register XOR. That is,
15406 * <PRE>
15407 * [dstBase + dstDisp] ~= (byte) srcReg
15408 * </PRE>
15409 *
15410 * @param dstBase the base register
15411 * @param dstDisp the destination displacement
15412 * @param srcReg the source register
15413 */
15414 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
15415 public final void emitXOR_RegDisp_Reg_Byte(GPR dstBase, Offset dstDisp, GPR srcReg) {
15416 int miStart = mi;
15417 // no group 1 to 4 prefix byte
15418 generateREXprefix(false, srcReg, null, dstBase);
15419 // single byte opcode
15420 setMachineCodes(mi++, (byte) 0x30);
15421 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
15422 if (lister != null) lister.RDR(miStart, "XOR", dstBase, dstDisp, srcReg);
15423 }
15424
15425 /**
15426 * Generate a register--register XOR. That is,
15427 * <PRE>
15428 * dstReg ~= (byte) srcReg
15429 * </PRE>
15430 *
15431 * @param dstReg the destination register
15432 * @param srcReg the source register
15433 */
15434 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
15435 public final void emitXOR_Reg_Reg_Byte(GPR dstReg, GPR srcReg) {
15436 int miStart = mi;
15437 // no group 1 to 4 prefix byte
15438 generateREXprefix(false, srcReg, null, dstReg);
15439 // single byte opcode
15440 setMachineCodes(mi++, (byte) 0x30);
15441 emitRegRegOperands(dstReg, srcReg);
15442 if (lister != null) lister.RR(miStart, "XOR", dstReg, srcReg);
15443 }
15444
15445 /**
15446 * Generate a register--register-displacement XOR. That is,
15447 * <PRE>
15448 * dstReg ~= (byte) [srcReg + srcDisp]
15449 * </PRE>
15450 *
15451 * @param dstReg the destination register
15452 * @param srcBase the source register
15453 * @param srcDisp the source displacement
15454 */
15455 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
15456 public final void emitXOR_Reg_RegDisp_Byte(GPR dstReg, GPR srcBase, Offset srcDisp) {
15457 int miStart = mi;
15458 // no group 1 to 4 prefix byte
15459 generateREXprefix(false, dstReg, null, srcBase);
15460 // single byte opcode
15461 setMachineCodes(mi++, (byte) 0x32);
15462 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
15463 if (lister != null) lister.RRD(miStart, "XOR", dstReg, srcBase, srcDisp);
15464 }
15465
15466 /**
15467 * Generate a register--register-offset XOR. That is,
15468 * <PRE>
15469 * dstReg ~= (byte) [srcIndex<<srcScale + srcDisp]
15470 * </PRE>
15471 *
15472 * @param dstReg the destination register
15473 * @param srcIndex the source index register
15474 * @param srcScale the source shift amount
15475 * @param srcDisp the source displacement
15476 */
15477 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
15478 public final void emitXOR_Reg_RegOff_Byte(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
15479 int miStart = mi;
15480 // no group 1 to 4 prefix byte
15481 generateREXprefix(false, dstReg, srcIndex, null);
15482 // single byte opcode
15483 setMachineCodes(mi++, (byte) 0x32);
15484 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
15485 if (lister != null) lister.RRFD(miStart, "XOR", dstReg, srcIndex, srcScale, srcDisp);
15486 }
15487
15488 /**
15489 * Generate a register--register-offset XOR. That is,
15490 * <PRE>
15491 * dstReg ~= (byte) [srcDisp]
15492 * </PRE>
15493 *
15494 * @param dstReg the destination register
15495 * @param srcDisp the source displacement
15496 */
15497 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
15498 public final void emitXOR_Reg_Abs_Byte(GPR dstReg, Address srcDisp) {
15499 int miStart = mi;
15500 // no group 1 to 4 prefix byte
15501 generateREXprefix(false, dstReg, null, null);
15502 // single byte opcode
15503 setMachineCodes(mi++, (byte) 0x32);
15504 emitAbsRegOperands(srcDisp, dstReg);
15505 if (lister != null) lister.RRA(miStart, "XOR", dstReg, srcDisp);
15506 }
15507
15508 /**
15509 * Generate a register--register-offset XOR. That is,
15510 * <PRE>
15511 * dstReg ~= (byte) [srcBase + srcIndex<<srcScale + srcDisp]
15512 * </PRE>
15513 *
15514 * @param dstReg the destination register
15515 * @param srcBase the source base register
15516 * @param srcIndex the source index register
15517 * @param srcScale the source shift amount
15518 * @param srcDisp the source displacement
15519 */
15520 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
15521 public final void emitXOR_Reg_RegIdx_Byte(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
15522 int miStart = mi;
15523 // no group 1 to 4 prefix byte
15524 generateREXprefix(false, dstReg, srcIndex, srcBase);
15525 // single byte opcode
15526 setMachineCodes(mi++, (byte) 0x32);
15527 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
15528 if (lister != null) lister.RRXD(miStart, "XOR", dstReg, srcBase, srcIndex, srcScale, srcDisp);
15529 }
15530
15531 /**
15532 * Generate a register--register(indirect) XOR. That is,
15533 * <PRE>
15534 * dstReg ~= (byte) [srcBase]
15535 * </PRE>
15536 *
15537 * @param dstReg the destination register
15538 * @param srcBase the source base register
15539 */
15540 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
15541 public final void emitXOR_Reg_RegInd_Byte(GPR dstReg, GPR srcBase) {
15542 int miStart = mi;
15543 // no group 1 to 4 prefix byte
15544 generateREXprefix(false, dstReg, null, srcBase);
15545 // single byte opcode
15546 setMachineCodes(mi++, (byte) 0x32);
15547 emitRegIndirectRegOperands(srcBase, dstReg);
15548 if (lister != null) lister.RRN(miStart, "XOR", dstReg, srcBase);
15549 }
15550
15551 /**
15552 * Generate a register--immediate XOR. That is,
15553 * <PRE>
15554 * dstReg ~= imm
15555 * </PRE>
15556 *
15557 * @param dstReg the destination register
15558 * @param imm immediate
15559 */
15560 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
15561 public final void emitXOR_Reg_Imm(GPR dstReg, int imm) {
15562 int miStart = mi;
15563 // no group 1 to 4 prefix byte
15564 generateREXprefix(false, null, null, dstReg);
15565 // single byte opcode
15566 if (fits(imm,8)) {
15567 setMachineCodes(mi++, (byte) 0x83);
15568 // "register 0x6" is really part of the opcode
15569 emitRegRegOperands(dstReg, GPR.getForOpcode(0x6));
15570 emitImm8((byte)imm);
15571 } else if (dstReg == EAX) {
15572 setMachineCodes(mi++, (byte) 0x35);
15573 emitImm32(imm);
15574 } else {
15575 setMachineCodes(mi++, (byte) 0x81);
15576 // "register 0x6" is really part of the opcode
15577 emitRegRegOperands(dstReg, GPR.getForOpcode(0x6));
15578 emitImm32(imm);
15579 }
15580 if (lister != null) lister.RI(miStart, "XOR", dstReg, imm);
15581 }
15582
15583 /**
15584 * Generate a register-displacement--immediate XOR. That is,
15585 * <PRE>
15586 * [dstBase + dstDisp] ~= imm
15587 * </PRE>
15588 *
15589 * @param dstBase the destination register
15590 * @param dstDisp the destination displacement
15591 * @param imm immediate
15592 */
15593 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
15594 public final void emitXOR_RegDisp_Imm(GPR dstBase, Offset dstDisp, int imm) {
15595 int miStart = mi;
15596 // no group 1 to 4 prefix byte
15597 generateREXprefix(false, null, null, dstBase);
15598 // single byte opcode
15599 if (fits(imm,8)) {
15600 setMachineCodes(mi++, (byte) 0x83);
15601 // "register 0x6" is really part of the opcode
15602 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x6));
15603 emitImm8((byte)imm);
15604 } else {
15605 setMachineCodes(mi++, (byte) 0x81);
15606 // "register 0x6" is really part of the opcode
15607 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x6));
15608 emitImm32(imm);
15609 }
15610 if (lister != null) lister.RDI(miStart, "XOR", dstBase, dstDisp, imm);
15611 }
15612
15613 /**
15614 * Generate a register-offset--immediate XOR. That is,
15615 * <PRE>
15616 * [dstIndex<<dstScale + dstDisp] ~= imm
15617 * </PRE>
15618 *
15619 * @param dstIndex the destination index register
15620 * @param dstScale the destination shift amount
15621 * @param dstDisp the destination displacement
15622 * @param imm immediate
15623 */
15624 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
15625 public final void emitXOR_RegOff_Imm(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
15626 int miStart = mi;
15627 // no group 1 to 4 prefix byte
15628 generateREXprefix(false, null, dstIndex, null);
15629 // single byte opcode
15630 if (fits(imm,8)) {
15631 setMachineCodes(mi++, (byte) 0x83);
15632 // "register 0x6" is really part of the opcode
15633 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x6));
15634 emitImm8((byte)imm);
15635 } else {
15636 setMachineCodes(mi++, (byte) 0x81);
15637 // "register 0x6" is really part of the opcode
15638 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x6));
15639 emitImm32(imm);
15640 }
15641 if (lister != null) lister.RFDI(miStart, "XOR", dstIndex, dstScale, dstDisp, imm);
15642 }
15643
15644 /**
15645 * Generate a absolute--immediate XOR. That is,
15646 * <PRE>
15647 * [dstDisp] ~= imm
15648 * </PRE>
15649 *
15650 * @param dstDisp the destination displacement
15651 * @param imm immediate
15652 */
15653 public final void emitXOR_Abs_Imm(Address dstDisp, int imm) {
15654 int miStart = mi;
15655 // no group 1 to 4 prefix byte
15656 generateREXprefix(false, null, null, null);
15657 // single byte opcode
15658 if (fits(imm,8)) {
15659 setMachineCodes(mi++, (byte) 0x83);
15660 // "register 0x6" is really part of the opcode
15661 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x6));
15662 emitImm8((byte)imm);
15663 } else {
15664 setMachineCodes(mi++, (byte) 0x81);
15665 // "register 0x6" is really part of the opcode
15666 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x6));
15667 emitImm32(imm);
15668 }
15669 if (lister != null) lister.RAI(miStart, "XOR", dstDisp, imm);
15670 }
15671
15672 /**
15673 * Generate a register-index--immediate XOR. That is,
15674 * <PRE>
15675 * [dstBase + dstIndex<<dstScale + dstDisp] ~= imm
15676 * </PRE>
15677 *
15678 * @param dstBase the destination base register
15679 * @param dstIndex the destination index register
15680 * @param dstScale the destination shift amount
15681 * @param dstDisp the destination displacement
15682 * @param imm immediate
15683 */
15684 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
15685 public final void emitXOR_RegIdx_Imm(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
15686 int miStart = mi;
15687 // no group 1 to 4 prefix byte
15688 generateREXprefix(false, null, dstIndex, dstBase);
15689 // single byte opcode
15690 if (fits(imm,8)) {
15691 setMachineCodes(mi++, (byte) 0x83);
15692 // "register 0x6" is really part of the opcode
15693 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x6));
15694 emitImm8((byte)imm);
15695 } else {
15696 setMachineCodes(mi++, (byte) 0x81);
15697 // "register 0x6" is really part of the opcode
15698 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x6));
15699 emitImm32(imm);
15700 }
15701 if (lister != null) lister.RXDI(miStart, "XOR", dstBase, dstIndex, dstScale, dstDisp, imm);
15702 }
15703
15704 /**
15705 * Generate a register(indirect)--immediate XOR. That is,
15706 * <PRE>
15707 * [dstBase] ~= imm
15708 * </PRE>
15709 *
15710 * @param dstBase the destination base register
15711 * @param imm immediate
15712 */
15713 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
15714 public final void emitXOR_RegInd_Imm(GPR dstBase, int imm) {
15715 int miStart = mi;
15716 // no group 1 to 4 prefix byte
15717 generateREXprefix(false, null, null, dstBase);
15718 // single byte opcode
15719 if (fits(imm,8)) {
15720 setMachineCodes(mi++, (byte) 0x83);
15721 // "register 0x6" is really part of the opcode
15722 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x6));
15723 emitImm8((byte)imm);
15724 } else {
15725 setMachineCodes(mi++, (byte) 0x81);
15726 // "register 0x6" is really part of the opcode
15727 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x6));
15728 emitImm32(imm);
15729 }
15730 if (lister != null) lister.RNI(miStart, "XOR", dstBase, imm);
15731 }
15732
15733 /**
15734 * Generate a register--immediate XOR. That is,
15735 * <PRE>
15736 * dstReg ~= (word) imm
15737 * </PRE>
15738 *
15739 * @param dstReg the destination register
15740 * @param imm immediate
15741 */
15742 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
15743 public final void emitXOR_Reg_Imm_Word(GPR dstReg, int imm) {
15744 int miStart = mi;
15745 setMachineCodes(mi++, (byte) 0x66);
15746 generateREXprefix(false, null, null, dstReg);
15747 // single byte opcode
15748 if (fits(imm,8)) {
15749 setMachineCodes(mi++, (byte) 0x83);
15750 // "register 0x6" is really part of the opcode
15751 emitRegRegOperands(dstReg, GPR.getForOpcode(0x6));
15752 emitImm8((byte)imm);
15753 } else if (dstReg == EAX) {
15754 setMachineCodes(mi++, (byte) 0x35);
15755 emitImm16(imm);
15756 } else {
15757 setMachineCodes(mi++, (byte) 0x81);
15758 // "register 0x6" is really part of the opcode
15759 emitRegRegOperands(dstReg, GPR.getForOpcode(0x6));
15760 emitImm16(imm);
15761 }
15762 if (lister != null) lister.RI(miStart, "XOR", dstReg, imm);
15763 }
15764
15765 /**
15766 * Generate a register-displacement--immediate XOR. That is,
15767 * <PRE>
15768 * [dstBase + dstDisp] ~= (word) imm
15769 * </PRE>
15770 *
15771 * @param dstBase the destination register
15772 * @param dstDisp the destination displacement
15773 * @param imm immediate
15774 */
15775 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
15776 public final void emitXOR_RegDisp_Imm_Word(GPR dstBase, Offset dstDisp, int imm) {
15777 int miStart = mi;
15778 setMachineCodes(mi++, (byte) 0x66);
15779 generateREXprefix(false, null, null, dstBase);
15780 // single byte opcode
15781 if (fits(imm,8)) {
15782 setMachineCodes(mi++, (byte) 0x83);
15783 // "register 0x6" is really part of the opcode
15784 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x6));
15785 emitImm8((byte)imm);
15786 } else {
15787 setMachineCodes(mi++, (byte) 0x81);
15788 // "register 0x6" is really part of the opcode
15789 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x6));
15790 emitImm16(imm);
15791 }
15792 if (lister != null) lister.RDI(miStart, "XOR", dstBase, dstDisp, imm);
15793 }
15794
15795 /**
15796 * Generate a register-offset--immediate XOR. That is,
15797 * <PRE>
15798 * [dstIndex<<dstScale + dstDisp] ~= (word) imm
15799 * </PRE>
15800 *
15801 * @param dstIndex the destination index register
15802 * @param dstScale the destination shift amount
15803 * @param dstDisp the destination displacement
15804 * @param imm immediate
15805 */
15806 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
15807 public final void emitXOR_RegOff_Imm_Word(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
15808 int miStart = mi;
15809 setMachineCodes(mi++, (byte) 0x66);
15810 generateREXprefix(false, null, dstIndex, null);
15811 // single byte opcode
15812 if (fits(imm,8)) {
15813 setMachineCodes(mi++, (byte) 0x83);
15814 // "register 0x6" is really part of the opcode
15815 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x6));
15816 emitImm8((byte)imm);
15817 } else {
15818 setMachineCodes(mi++, (byte) 0x81);
15819 // "register 0x6" is really part of the opcode
15820 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x6));
15821 emitImm16(imm);
15822 }
15823 if (lister != null) lister.RFDI(miStart, "XOR", dstIndex, dstScale, dstDisp, imm);
15824 }
15825
15826 /**
15827 * Generate a absolute--immediate XOR. That is,
15828 * <PRE>
15829 * [dstDisp] ~= (word) imm
15830 * </PRE>
15831 *
15832 * @param dstDisp the destination displacement
15833 * @param imm immediate
15834 */
15835 public final void emitXOR_Abs_Imm_Word(Address dstDisp, int imm) {
15836 int miStart = mi;
15837 setMachineCodes(mi++, (byte) 0x66);
15838 generateREXprefix(false, null, null, null);
15839 // single byte opcode
15840 if (fits(imm,8)) {
15841 setMachineCodes(mi++, (byte) 0x83);
15842 // "register 0x6" is really part of the opcode
15843 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x6));
15844 emitImm8((byte)imm);
15845 } else {
15846 setMachineCodes(mi++, (byte) 0x81);
15847 // "register 0x6" is really part of the opcode
15848 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x6));
15849 emitImm16(imm);
15850 }
15851 if (lister != null) lister.RAI(miStart, "XOR", dstDisp, imm);
15852 }
15853
15854 /**
15855 * Generate a register-index--immediate XOR. That is,
15856 * <PRE>
15857 * [dstBase + dstIndex<<dstScale + dstDisp] ~= (word) imm
15858 * </PRE>
15859 *
15860 * @param dstBase the destination base register
15861 * @param dstIndex the destination index register
15862 * @param dstScale the destination shift amount
15863 * @param dstDisp the destination displacement
15864 * @param imm immediate
15865 */
15866 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
15867 public final void emitXOR_RegIdx_Imm_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
15868 int miStart = mi;
15869 setMachineCodes(mi++, (byte) 0x66);
15870 generateREXprefix(false, null, dstIndex, dstBase);
15871 // single byte opcode
15872 if (fits(imm,8)) {
15873 setMachineCodes(mi++, (byte) 0x83);
15874 // "register 0x6" is really part of the opcode
15875 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x6));
15876 emitImm8((byte)imm);
15877 } else {
15878 setMachineCodes(mi++, (byte) 0x81);
15879 // "register 0x6" is really part of the opcode
15880 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x6));
15881 emitImm16(imm);
15882 }
15883 if (lister != null) lister.RXDI(miStart, "XOR", dstBase, dstIndex, dstScale, dstDisp, imm);
15884 }
15885
15886 /**
15887 * Generate a register(indirect)--immediate XOR. That is,
15888 * <PRE>
15889 * [dstBase] ~= (word) imm
15890 * </PRE>
15891 *
15892 * @param dstBase the destination base register
15893 * @param imm immediate
15894 */
15895 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
15896 public final void emitXOR_RegInd_Imm_Word(GPR dstBase, int imm) {
15897 int miStart = mi;
15898 setMachineCodes(mi++, (byte) 0x66);
15899 generateREXprefix(false, null, null, dstBase);
15900 // single byte opcode
15901 if (fits(imm,8)) {
15902 setMachineCodes(mi++, (byte) 0x83);
15903 // "register 0x6" is really part of the opcode
15904 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x6));
15905 emitImm8((byte)imm);
15906 } else {
15907 setMachineCodes(mi++, (byte) 0x81);
15908 // "register 0x6" is really part of the opcode
15909 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x6));
15910 emitImm16(imm);
15911 }
15912 if (lister != null) lister.RNI(miStart, "XOR", dstBase, imm);
15913 }
15914
15915 /**
15916 * Generate a register--immediate XOR. That is,
15917 * <PRE>
15918 * dstReg ~= (quad) imm
15919 * </PRE>
15920 *
15921 * @param dstReg the destination register
15922 * @param imm immediate
15923 */
15924 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
15925 public final void emitXOR_Reg_Imm_Quad(GPR dstReg, int imm) {
15926 int miStart = mi;
15927 // no group 1 to 4 prefix byte
15928 generateREXprefix(true, null, null, dstReg);
15929 // single byte opcode
15930 if (fits(imm,8)) {
15931 setMachineCodes(mi++, (byte) 0x83);
15932 // "register 0x6" is really part of the opcode
15933 emitRegRegOperands(dstReg, GPR.getForOpcode(0x6));
15934 emitImm8((byte)imm);
15935 } else if (dstReg == EAX) {
15936 setMachineCodes(mi++, (byte) 0x35);
15937 emitImm32(imm);
15938 } else {
15939 setMachineCodes(mi++, (byte) 0x81);
15940 // "register 0x6" is really part of the opcode
15941 emitRegRegOperands(dstReg, GPR.getForOpcode(0x6));
15942 emitImm32(imm);
15943 }
15944 if (lister != null) lister.RI(miStart, "XOR", dstReg, imm);
15945 }
15946
15947 /**
15948 * Generate a register-displacement--immediate XOR. That is,
15949 * <PRE>
15950 * [dstBase + dstDisp] ~= (quad) imm
15951 * </PRE>
15952 *
15953 * @param dstBase the destination register
15954 * @param dstDisp the destination displacement
15955 * @param imm immediate
15956 */
15957 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
15958 public final void emitXOR_RegDisp_Imm_Quad(GPR dstBase, Offset dstDisp, int imm) {
15959 int miStart = mi;
15960 // no group 1 to 4 prefix byte
15961 generateREXprefix(true, null, null, dstBase);
15962 // single byte opcode
15963 if (fits(imm,8)) {
15964 setMachineCodes(mi++, (byte) 0x83);
15965 // "register 0x6" is really part of the opcode
15966 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x6));
15967 emitImm8((byte)imm);
15968 } else {
15969 setMachineCodes(mi++, (byte) 0x81);
15970 // "register 0x6" is really part of the opcode
15971 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x6));
15972 emitImm32(imm);
15973 }
15974 if (lister != null) lister.RDI(miStart, "XOR", dstBase, dstDisp, imm);
15975 }
15976
15977 /**
15978 * Generate a register-offset--immediate XOR. That is,
15979 * <PRE>
15980 * [dstIndex<<dstScale + dstDisp] ~= (quad) imm
15981 * </PRE>
15982 *
15983 * @param dstIndex the destination index register
15984 * @param dstScale the destination shift amount
15985 * @param dstDisp the destination displacement
15986 * @param imm immediate
15987 */
15988 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
15989 public final void emitXOR_RegOff_Imm_Quad(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
15990 int miStart = mi;
15991 // no group 1 to 4 prefix byte
15992 generateREXprefix(true, null, dstIndex, null);
15993 // single byte opcode
15994 if (fits(imm,8)) {
15995 setMachineCodes(mi++, (byte) 0x83);
15996 // "register 0x6" is really part of the opcode
15997 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x6));
15998 emitImm8((byte)imm);
15999 } else {
16000 setMachineCodes(mi++, (byte) 0x81);
16001 // "register 0x6" is really part of the opcode
16002 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x6));
16003 emitImm32(imm);
16004 }
16005 if (lister != null) lister.RFDI(miStart, "XOR", dstIndex, dstScale, dstDisp, imm);
16006 }
16007
16008 /**
16009 * Generate a absolute--immediate XOR. That is,
16010 * <PRE>
16011 * [dstDisp] ~= (quad) imm
16012 * </PRE>
16013 *
16014 * @param dstDisp the destination displacement
16015 * @param imm immediate
16016 */
16017 public final void emitXOR_Abs_Imm_Quad(Address dstDisp, int imm) {
16018 int miStart = mi;
16019 // no group 1 to 4 prefix byte
16020 generateREXprefix(true, null, null, null);
16021 // single byte opcode
16022 if (fits(imm,8)) {
16023 setMachineCodes(mi++, (byte) 0x83);
16024 // "register 0x6" is really part of the opcode
16025 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x6));
16026 emitImm8((byte)imm);
16027 } else {
16028 setMachineCodes(mi++, (byte) 0x81);
16029 // "register 0x6" is really part of the opcode
16030 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x6));
16031 emitImm32(imm);
16032 }
16033 if (lister != null) lister.RAI(miStart, "XOR", dstDisp, imm);
16034 }
16035
16036 /**
16037 * Generate a register-index--immediate XOR. That is,
16038 * <PRE>
16039 * [dstBase + dstIndex<<dstScale + dstDisp] ~= (quad) imm
16040 * </PRE>
16041 *
16042 * @param dstBase the destination base register
16043 * @param dstIndex the destination index register
16044 * @param dstScale the destination shift amount
16045 * @param dstDisp the destination displacement
16046 * @param imm immediate
16047 */
16048 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
16049 public final void emitXOR_RegIdx_Imm_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
16050 int miStart = mi;
16051 // no group 1 to 4 prefix byte
16052 generateREXprefix(true, null, dstIndex, dstBase);
16053 // single byte opcode
16054 if (fits(imm,8)) {
16055 setMachineCodes(mi++, (byte) 0x83);
16056 // "register 0x6" is really part of the opcode
16057 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x6));
16058 emitImm8((byte)imm);
16059 } else {
16060 setMachineCodes(mi++, (byte) 0x81);
16061 // "register 0x6" is really part of the opcode
16062 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x6));
16063 emitImm32(imm);
16064 }
16065 if (lister != null) lister.RXDI(miStart, "XOR", dstBase, dstIndex, dstScale, dstDisp, imm);
16066 }
16067
16068 /**
16069 * Generate a register(indirect)--immediate XOR. That is,
16070 * <PRE>
16071 * [dstBase] ~= (quad) imm
16072 * </PRE>
16073 *
16074 * @param dstBase the destination base register
16075 * @param imm immediate
16076 */
16077 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
16078 public final void emitXOR_RegInd_Imm_Quad(GPR dstBase, int imm) {
16079 int miStart = mi;
16080 // no group 1 to 4 prefix byte
16081 generateREXprefix(true, null, null, dstBase);
16082 // single byte opcode
16083 if (fits(imm,8)) {
16084 setMachineCodes(mi++, (byte) 0x83);
16085 // "register 0x6" is really part of the opcode
16086 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x6));
16087 emitImm8((byte)imm);
16088 } else {
16089 setMachineCodes(mi++, (byte) 0x81);
16090 // "register 0x6" is really part of the opcode
16091 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x6));
16092 emitImm32(imm);
16093 }
16094 if (lister != null) lister.RNI(miStart, "XOR", dstBase, imm);
16095 }
16096
16097 /**
16098 * Generate a register--immediate XOR. That is,
16099 * <PRE>
16100 * dstReg ~= (byte) imm
16101 * </PRE>
16102 *
16103 * @param dstReg the destination register
16104 * @param imm immediate
16105 */
16106 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
16107 public final void emitXOR_Reg_Imm_Byte(GPR dstReg, int imm) {
16108 int miStart = mi;
16109 if (dstReg == EAX) {
16110 setMachineCodes(mi++, (byte) 0x34);
16111 emitImm8(imm);
16112 } else {
16113 generateREXprefix(false, null, null, dstReg);
16114 setMachineCodes(mi++, (byte) 0x80);
16115 // "register 0x6" is really part of the opcode
16116 emitRegRegOperands(dstReg, GPR.getForOpcode(0x6));
16117 emitImm8(imm);
16118 }
16119 if (lister != null) lister.RI(miStart, "XOR", dstReg, imm);
16120 }
16121
16122 /**
16123 * Generate a register-displacement--immediate XOR. That is,
16124 * <PRE>
16125 * [dstBase + dstDisp] ~= (byte) imm
16126 * </PRE>
16127 *
16128 * @param dstBase the destination register
16129 * @param dstDisp the destination displacement
16130 * @param imm immediate
16131 */
16132 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
16133 public final void emitXOR_RegDisp_Imm_Byte(GPR dstBase, Offset dstDisp, int imm) {
16134 int miStart = mi;
16135 generateREXprefix(false, null, null, dstBase);
16136 setMachineCodes(mi++, (byte) 0x80);
16137 // "register 0x6" is really part of the opcode
16138 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x6));
16139 emitImm8(imm);
16140 if (lister != null) lister.RDI(miStart, "XOR", dstBase, dstDisp, imm);
16141 }
16142
16143 /**
16144 * Generate a register-index--immediate XOR. That is,
16145 * <PRE>
16146 * [dstBase + dstIndex<<scale + dstDisp] ~= (byte) imm
16147 * </PRE>
16148 *
16149 * @param dstBase the destination base register
16150 * @param dstIndex the destination index register
16151 * @param dstScale the destination shift amount
16152 * @param dstDisp the destination displacement
16153 * @param imm immediate
16154 */
16155 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
16156 public final void emitXOR_RegIdx_Imm_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
16157 int miStart = mi;
16158 generateREXprefix(false, null, dstIndex, dstBase);
16159 setMachineCodes(mi++, (byte) 0x80);
16160 // "register 0x6" is really part of the opcode
16161 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x6));
16162 emitImm8(imm);
16163 if (lister != null) lister.RXDI(miStart, "XOR", dstBase, dstIndex, dstScale, dstDisp, imm);
16164 }
16165
16166 /**
16167 * Generate a register-offset--immediate XOR. That is,
16168 * <PRE>
16169 * [dstIndex<<dstScale + dstDisp] ~= (byte) imm
16170 * </PRE>
16171 *
16172 * @param dstIndex the destination index register
16173 * @param dstScale the destination shift amount
16174 * @param dstDisp the destination displacement
16175 * @param imm immediate
16176 */
16177 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
16178 public final void emitXOR_RegOff_Imm_Byte(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
16179 int miStart = mi;
16180 generateREXprefix(false, null, dstIndex, null);
16181 setMachineCodes(mi++, (byte) 0x80);
16182 // "register 0x6" is really part of the opcode
16183 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x6));
16184 emitImm8(imm);
16185 if (lister != null) lister.RFDI(miStart, "XOR", dstIndex, dstScale, dstDisp, imm);
16186 }
16187
16188 /**
16189 * Generate a absolute--immediate XOR. That is,
16190 * <PRE>
16191 * [dstDisp] ~= (byte) imm
16192 * </PRE>
16193 *
16194 * @param dstDisp the destination displacement
16195 * @param imm immediate
16196 */
16197 public final void emitXOR_Abs_Imm_Byte(Address dstDisp, int imm) {
16198 int miStart = mi;
16199 generateREXprefix(false, null, null, null);
16200 setMachineCodes(mi++, (byte) 0x80);
16201 // "register 0x6" is really part of the opcode
16202 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x6));
16203 emitImm8(imm);
16204 if (lister != null) lister.RAI(miStart, "XOR", dstDisp, imm);
16205 }
16206
16207 /**
16208 * Generate a register(indirect)--immediate XOR. That is,
16209 * <PRE>
16210 * [dstBase] ~= (byte) imm
16211 * </PRE>
16212 *
16213 * @param dstBase the destination base register
16214 * @param imm immediate
16215 */
16216 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
16217 public final void emitXOR_RegInd_Imm_Byte(GPR dstBase, int imm) {
16218 int miStart = mi;
16219 generateREXprefix(false, null, null, dstBase);
16220 setMachineCodes(mi++, (byte) 0x80);
16221 // "register 0x6" is really part of the opcode
16222 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x6));
16223 emitImm8(imm);
16224 if (lister != null) lister.RNI(miStart, "XOR", dstBase, imm);
16225 }
16226
16227 /**
16228 * Generate a register(indirect)--register BT. That is,
16229 * <PRE>
16230 * [dstBase] BT= srcReg
16231 * </PRE>
16232 *
16233 * @param dstBase the destination base
16234 * @param srcReg the source register
16235 */
16236 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
16237 public final void emitBT_RegInd_Reg(GPR dstBase, GPR srcReg) {
16238 int miStart = mi;
16239 // no group 1 to 4 prefix byte
16240 generateREXprefix(false, srcReg, null, dstBase);
16241 setMachineCodes(mi++, (byte) 0x0F);
16242 setMachineCodes(mi++, (byte) 0xA3);
16243 emitRegIndirectRegOperands(dstBase, srcReg);
16244 if (lister != null) lister.RNR(miStart, "BT", dstBase, srcReg);
16245 }
16246
16247 /**
16248 * Generate a register-offset--register BT. That is,
16249 * <PRE>
16250 * [dstReg<<dstScale + dstDisp] BT= srcReg
16251 * </PRE>
16252 *
16253 * @param dstIndex the destination index register
16254 * @param dstScale the destination shift amount
16255 * @param dstDisp the destination displacement
16256 * @param srcReg the source register
16257 */
16258 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
16259 public final void emitBT_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
16260 int miStart = mi;
16261 // no group 1 to 4 prefix byte
16262 generateREXprefix(false, srcReg, dstIndex, null);
16263 setMachineCodes(mi++, (byte) 0x0F);
16264 setMachineCodes(mi++, (byte) 0xA3);
16265 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
16266 if (lister != null) lister.RFDR(miStart, "BT", dstIndex, dstScale, dstDisp, srcReg);
16267 }
16268
16269 /**
16270 * Generate a absolute--register BT. That is,
16271 * <PRE>
16272 * [dstDisp] BT= srcReg
16273 * </PRE>
16274 *
16275 * @param dstDisp the destination address
16276 * @param srcReg the source register
16277 */
16278 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
16279 public final void emitBT_Abs_Reg(Address dstDisp, GPR srcReg) {
16280 int miStart = mi;
16281 // no group 1 to 4 prefix byte
16282 generateREXprefix(false, srcReg, null, null);
16283 setMachineCodes(mi++, (byte) 0x0F);
16284 setMachineCodes(mi++, (byte) 0xA3);
16285 emitAbsRegOperands(dstDisp, srcReg);
16286 if (lister != null) lister.RAR(miStart, "BT", dstDisp, srcReg);
16287 }
16288
16289 /**
16290 * Generate a register-index--register BT. That is,
16291 * <PRE>
16292 * [dstBase + dstIndex<<dstScale + dstDisp] BT= srcReg
16293 * </PRE>
16294 *
16295 * @param dstBase the base register
16296 * @param dstIndex the destination index register
16297 * @param dstScale the destination shift amount
16298 * @param dstDisp the destination displacement
16299 * @param srcReg the source register
16300 */
16301 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
16302 public final void emitBT_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
16303 int miStart = mi;
16304 // no group 1 to 4 prefix byte
16305 generateREXprefix(false, srcReg, dstIndex, dstBase);
16306 setMachineCodes(mi++, (byte) 0x0F);
16307 setMachineCodes(mi++, (byte) 0xA3);
16308 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
16309 if (lister != null) lister.RXDR(miStart, "BT", dstBase, dstIndex, dstScale, dstDisp, srcReg);
16310 }
16311
16312 /**
16313 * Generate a register-displacement--register BT. That is,
16314 * <PRE>
16315 * [dstBase + dstDisp] BT= srcReg
16316 * </PRE>
16317 *
16318 * @param dstBase the base register
16319 * @param dstDisp the destination displacement
16320 * @param srcReg the source register
16321 */
16322 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
16323 public final void emitBT_RegDisp_Reg(GPR dstBase, Offset dstDisp, GPR srcReg) {
16324 int miStart = mi;
16325 // no group 1 to 4 prefix byte
16326 generateREXprefix(false, srcReg, null, dstBase);
16327 setMachineCodes(mi++, (byte) 0x0F);
16328 setMachineCodes(mi++, (byte) 0xA3);
16329 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
16330 if (lister != null) lister.RDR(miStart, "BT", dstBase, dstDisp, srcReg);
16331 }
16332
16333 /**
16334 * Generate a register--register BT. That is,
16335 * <PRE>
16336 * dstReg BT= srcReg
16337 * </PRE>
16338 *
16339 * @param dstReg the destination register
16340 * @param srcReg the source register
16341 */
16342 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
16343 public final void emitBT_Reg_Reg(GPR dstReg, GPR srcReg) {
16344 int miStart = mi;
16345 // no group 1 to 4 prefix byte
16346 generateREXprefix(false, srcReg, null, dstReg);
16347 setMachineCodes(mi++, (byte) 0x0F);
16348 setMachineCodes(mi++, (byte) 0xA3);
16349 emitRegRegOperands(dstReg, srcReg);
16350 if (lister != null) lister.RR(miStart, "BT", dstReg, srcReg);
16351 }
16352
16353 /**
16354 * Generate a register--immediate BT. That is,
16355 * <PRE>
16356 * dstReg BT= imm
16357 * </PRE>
16358 *
16359 * @param dstReg the destination register
16360 * @param imm immediate
16361 */
16362 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
16363 public final void emitBT_Reg_Imm(GPR dstReg, int imm) {
16364 int miStart = mi;
16365 // no group 1 to 4 prefix byte
16366 generateREXprefix(false, null, null, dstReg);
16367 setMachineCodes(mi++, (byte) 0x0F);
16368 if (fits(imm,8)) {
16369 setMachineCodes(mi++, (byte) 0xBA);
16370 // "register 0x4" is really part of the opcode
16371 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
16372 emitImm8((byte)imm);
16373 } else {
16374 throw new InternalError("Data too large for BT instruction");
16375 }
16376 if (lister != null) lister.RI(miStart, "BT", dstReg, imm);
16377 }
16378
16379 /**
16380 * Generate a register-displacement--immediate BT. That is,
16381 * <PRE>
16382 * [dstBase + dstDisp] BT= imm
16383 * </PRE>
16384 *
16385 * @param dstBase the destination register
16386 * @param dstDisp the destination displacement
16387 * @param imm immediate
16388 */
16389 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
16390 public final void emitBT_RegDisp_Imm(GPR dstBase, Offset dstDisp, int imm) {
16391 int miStart = mi;
16392 // no group 1 to 4 prefix byte
16393 generateREXprefix(false, null, null, dstBase);
16394 setMachineCodes(mi++, (byte) 0x0F);
16395 if (fits(imm,8)) {
16396 setMachineCodes(mi++, (byte) 0xBA);
16397 // "register 0x4" is really part of the opcode
16398 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
16399 emitImm8((byte)imm);
16400 } else {
16401 throw new InternalError("Data too large for BT instruction");
16402 }
16403 if (lister != null) lister.RDI(miStart, "BT", dstBase, dstDisp, imm);
16404 }
16405
16406 /**
16407 * Generate a register-offset--immediate BT. That is,
16408 * <PRE>
16409 * [dstIndex<<dstScale + dstDisp] BT= imm
16410 * </PRE>
16411 *
16412 * @param dstIndex the destination index register
16413 * @param dstScale the destination shift amount
16414 * @param dstDisp the destination displacement
16415 * @param imm immediate
16416 */
16417 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
16418 public final void emitBT_RegOff_Imm(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
16419 int miStart = mi;
16420 // no group 1 to 4 prefix byte
16421 generateREXprefix(false, null, dstIndex, null);
16422 setMachineCodes(mi++, (byte) 0x0F);
16423 if (fits(imm,8)) {
16424 setMachineCodes(mi++, (byte) 0xBA);
16425 // "register 0x4" is really part of the opcode
16426 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
16427 emitImm8((byte)imm);
16428 } else {
16429 throw new InternalError("Data too large for BT instruction");
16430 }
16431 if (lister != null) lister.RFDI(miStart, "BT", dstIndex, dstScale, dstDisp, imm);
16432 }
16433
16434 /**
16435 * Generate a absolute--immediate BT. That is,
16436 * <PRE>
16437 * [dstDisp] BT= imm
16438 * </PRE>
16439 *
16440 * @param dstDisp the destination displacement
16441 * @param imm immediate
16442 */
16443 public final void emitBT_Abs_Imm(Address dstDisp, int imm) {
16444 int miStart = mi;
16445 // no group 1 to 4 prefix byte
16446 generateREXprefix(false, null, null, null);
16447 setMachineCodes(mi++, (byte) 0x0F);
16448 if (fits(imm,8)) {
16449 setMachineCodes(mi++, (byte) 0xBA);
16450 // "register 0x4" is really part of the opcode
16451 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
16452 emitImm8((byte)imm);
16453 } else {
16454 throw new InternalError("Data too large for BT instruction");
16455 }
16456 if (lister != null) lister.RAI(miStart, "BT", dstDisp, imm);
16457 }
16458
16459 /**
16460 * Generate a register-index--immediate BT. That is,
16461 * <PRE>
16462 * [dstBase + dstIndex<<dstScale + dstDisp] BT= imm
16463 * </PRE>
16464 *
16465 * @param dstBase the destination base register
16466 * @param dstIndex the destination index register
16467 * @param dstScale the destination shift amount
16468 * @param dstDisp the destination displacement
16469 * @param imm immediate
16470 */
16471 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
16472 public final void emitBT_RegIdx_Imm(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
16473 int miStart = mi;
16474 // no group 1 to 4 prefix byte
16475 generateREXprefix(false, null, dstIndex, dstBase);
16476 setMachineCodes(mi++, (byte) 0x0F);
16477 if (fits(imm,8)) {
16478 setMachineCodes(mi++, (byte) 0xBA);
16479 // "register 0x4" is really part of the opcode
16480 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
16481 emitImm8((byte)imm);
16482 } else {
16483 throw new InternalError("Data too large for BT instruction");
16484 }
16485 if (lister != null) lister.RXDI(miStart, "BT", dstBase, dstIndex, dstScale, dstDisp, imm);
16486 }
16487
16488 /**
16489 * Generate a register(indirect)--immediate BT. That is,
16490 * <PRE>
16491 * [dstBase] BT= imm
16492 * </PRE>
16493 *
16494 * @param dstBase the destination base register
16495 * @param imm immediate
16496 */
16497 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
16498 public final void emitBT_RegInd_Imm(GPR dstBase, int imm) {
16499 int miStart = mi;
16500 // no group 1 to 4 prefix byte
16501 generateREXprefix(false, null, null, dstBase);
16502 setMachineCodes(mi++, (byte) 0x0F);
16503 if (fits(imm,8)) {
16504 setMachineCodes(mi++, (byte) 0xBA);
16505 // "register 0x4" is really part of the opcode
16506 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
16507 emitImm8((byte)imm);
16508 } else {
16509 throw new InternalError("Data too large for BT instruction");
16510 }
16511 if (lister != null) lister.RNI(miStart, "BT", dstBase, imm);
16512 }
16513
16514 /**
16515 * Generate a register(indirect)--register BTC. That is,
16516 * <PRE>
16517 * [dstBase] BTC= srcReg
16518 * </PRE>
16519 *
16520 * @param dstBase the destination base
16521 * @param srcReg the source register
16522 */
16523 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
16524 public final void emitBTC_RegInd_Reg(GPR dstBase, GPR srcReg) {
16525 int miStart = mi;
16526 // no group 1 to 4 prefix byte
16527 generateREXprefix(false, srcReg, null, dstBase);
16528 setMachineCodes(mi++, (byte) 0x0F);
16529 setMachineCodes(mi++, (byte) 0xBB);
16530 emitRegIndirectRegOperands(dstBase, srcReg);
16531 if (lister != null) lister.RNR(miStart, "BTC", dstBase, srcReg);
16532 }
16533
16534 /**
16535 * Generate a register-offset--register BTC. That is,
16536 * <PRE>
16537 * [dstReg<<dstScale + dstDisp] BTC= srcReg
16538 * </PRE>
16539 *
16540 * @param dstIndex the destination index register
16541 * @param dstScale the destination shift amount
16542 * @param dstDisp the destination displacement
16543 * @param srcReg the source register
16544 */
16545 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
16546 public final void emitBTC_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
16547 int miStart = mi;
16548 // no group 1 to 4 prefix byte
16549 generateREXprefix(false, srcReg, dstIndex, null);
16550 setMachineCodes(mi++, (byte) 0x0F);
16551 setMachineCodes(mi++, (byte) 0xBB);
16552 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
16553 if (lister != null) lister.RFDR(miStart, "BTC", dstIndex, dstScale, dstDisp, srcReg);
16554 }
16555
16556 /**
16557 * Generate a absolute--register BTC. That is,
16558 * <PRE>
16559 * [dstDisp] BTC= srcReg
16560 * </PRE>
16561 *
16562 * @param dstDisp the destination address
16563 * @param srcReg the source register
16564 */
16565 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
16566 public final void emitBTC_Abs_Reg(Address dstDisp, GPR srcReg) {
16567 int miStart = mi;
16568 // no group 1 to 4 prefix byte
16569 generateREXprefix(false, srcReg, null, null);
16570 setMachineCodes(mi++, (byte) 0x0F);
16571 setMachineCodes(mi++, (byte) 0xBB);
16572 emitAbsRegOperands(dstDisp, srcReg);
16573 if (lister != null) lister.RAR(miStart, "BTC", dstDisp, srcReg);
16574 }
16575
16576 /**
16577 * Generate a register-index--register BTC. That is,
16578 * <PRE>
16579 * [dstBase + dstIndex<<dstScale + dstDisp] BTC= srcReg
16580 * </PRE>
16581 *
16582 * @param dstBase the base register
16583 * @param dstIndex the destination index register
16584 * @param dstScale the destination shift amount
16585 * @param dstDisp the destination displacement
16586 * @param srcReg the source register
16587 */
16588 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
16589 public final void emitBTC_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
16590 int miStart = mi;
16591 // no group 1 to 4 prefix byte
16592 generateREXprefix(false, srcReg, dstIndex, dstBase);
16593 setMachineCodes(mi++, (byte) 0x0F);
16594 setMachineCodes(mi++, (byte) 0xBB);
16595 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
16596 if (lister != null) lister.RXDR(miStart, "BTC", dstBase, dstIndex, dstScale, dstDisp, srcReg);
16597 }
16598
16599 /**
16600 * Generate a register-displacement--register BTC. That is,
16601 * <PRE>
16602 * [dstBase + dstDisp] BTC= srcReg
16603 * </PRE>
16604 *
16605 * @param dstBase the base register
16606 * @param dstDisp the destination displacement
16607 * @param srcReg the source register
16608 */
16609 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
16610 public final void emitBTC_RegDisp_Reg(GPR dstBase, Offset dstDisp, GPR srcReg) {
16611 int miStart = mi;
16612 // no group 1 to 4 prefix byte
16613 generateREXprefix(false, srcReg, null, dstBase);
16614 setMachineCodes(mi++, (byte) 0x0F);
16615 setMachineCodes(mi++, (byte) 0xBB);
16616 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
16617 if (lister != null) lister.RDR(miStart, "BTC", dstBase, dstDisp, srcReg);
16618 }
16619
16620 /**
16621 * Generate a register--register BTC. That is,
16622 * <PRE>
16623 * dstReg BTC= srcReg
16624 * </PRE>
16625 *
16626 * @param dstReg the destination register
16627 * @param srcReg the source register
16628 */
16629 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
16630 public final void emitBTC_Reg_Reg(GPR dstReg, GPR srcReg) {
16631 int miStart = mi;
16632 // no group 1 to 4 prefix byte
16633 generateREXprefix(false, srcReg, null, dstReg);
16634 setMachineCodes(mi++, (byte) 0x0F);
16635 setMachineCodes(mi++, (byte) 0xBB);
16636 emitRegRegOperands(dstReg, srcReg);
16637 if (lister != null) lister.RR(miStart, "BTC", dstReg, srcReg);
16638 }
16639
16640 /**
16641 * Generate a register--immediate BTC. That is,
16642 * <PRE>
16643 * dstReg BTC= imm
16644 * </PRE>
16645 *
16646 * @param dstReg the destination register
16647 * @param imm immediate
16648 */
16649 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
16650 public final void emitBTC_Reg_Imm(GPR dstReg, int imm) {
16651 int miStart = mi;
16652 // no group 1 to 4 prefix byte
16653 generateREXprefix(false, null, null, dstReg);
16654 setMachineCodes(mi++, (byte) 0x0F);
16655 if (fits(imm,8)) {
16656 setMachineCodes(mi++, (byte) 0xBA);
16657 // "register 0x7" is really part of the opcode
16658 emitRegRegOperands(dstReg, GPR.getForOpcode(0x7));
16659 emitImm8((byte)imm);
16660 } else {
16661 throw new InternalError("Data too large for BTC instruction");
16662 }
16663 if (lister != null) lister.RI(miStart, "BTC", dstReg, imm);
16664 }
16665
16666 /**
16667 * Generate a register-displacement--immediate BTC. That is,
16668 * <PRE>
16669 * [dstBase + dstDisp] BTC= imm
16670 * </PRE>
16671 *
16672 * @param dstBase the destination register
16673 * @param dstDisp the destination displacement
16674 * @param imm immediate
16675 */
16676 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
16677 public final void emitBTC_RegDisp_Imm(GPR dstBase, Offset dstDisp, int imm) {
16678 int miStart = mi;
16679 // no group 1 to 4 prefix byte
16680 generateREXprefix(false, null, null, dstBase);
16681 setMachineCodes(mi++, (byte) 0x0F);
16682 if (fits(imm,8)) {
16683 setMachineCodes(mi++, (byte) 0xBA);
16684 // "register 0x7" is really part of the opcode
16685 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x7));
16686 emitImm8((byte)imm);
16687 } else {
16688 throw new InternalError("Data too large for BTC instruction");
16689 }
16690 if (lister != null) lister.RDI(miStart, "BTC", dstBase, dstDisp, imm);
16691 }
16692
16693 /**
16694 * Generate a register-offset--immediate BTC. That is,
16695 * <PRE>
16696 * [dstIndex<<dstScale + dstDisp] BTC= imm
16697 * </PRE>
16698 *
16699 * @param dstIndex the destination index register
16700 * @param dstScale the destination shift amount
16701 * @param dstDisp the destination displacement
16702 * @param imm immediate
16703 */
16704 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
16705 public final void emitBTC_RegOff_Imm(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
16706 int miStart = mi;
16707 // no group 1 to 4 prefix byte
16708 generateREXprefix(false, null, dstIndex, null);
16709 setMachineCodes(mi++, (byte) 0x0F);
16710 if (fits(imm,8)) {
16711 setMachineCodes(mi++, (byte) 0xBA);
16712 // "register 0x7" is really part of the opcode
16713 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
16714 emitImm8((byte)imm);
16715 } else {
16716 throw new InternalError("Data too large for BTC instruction");
16717 }
16718 if (lister != null) lister.RFDI(miStart, "BTC", dstIndex, dstScale, dstDisp, imm);
16719 }
16720
16721 /**
16722 * Generate a absolute--immediate BTC. That is,
16723 * <PRE>
16724 * [dstDisp] BTC= imm
16725 * </PRE>
16726 *
16727 * @param dstDisp the destination displacement
16728 * @param imm immediate
16729 */
16730 public final void emitBTC_Abs_Imm(Address dstDisp, int imm) {
16731 int miStart = mi;
16732 // no group 1 to 4 prefix byte
16733 generateREXprefix(false, null, null, null);
16734 setMachineCodes(mi++, (byte) 0x0F);
16735 if (fits(imm,8)) {
16736 setMachineCodes(mi++, (byte) 0xBA);
16737 // "register 0x7" is really part of the opcode
16738 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x7));
16739 emitImm8((byte)imm);
16740 } else {
16741 throw new InternalError("Data too large for BTC instruction");
16742 }
16743 if (lister != null) lister.RAI(miStart, "BTC", dstDisp, imm);
16744 }
16745
16746 /**
16747 * Generate a register-index--immediate BTC. That is,
16748 * <PRE>
16749 * [dstBase + dstIndex<<dstScale + dstDisp] BTC= imm
16750 * </PRE>
16751 *
16752 * @param dstBase the destination base register
16753 * @param dstIndex the destination index register
16754 * @param dstScale the destination shift amount
16755 * @param dstDisp the destination displacement
16756 * @param imm immediate
16757 */
16758 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
16759 public final void emitBTC_RegIdx_Imm(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
16760 int miStart = mi;
16761 // no group 1 to 4 prefix byte
16762 generateREXprefix(false, null, dstIndex, dstBase);
16763 setMachineCodes(mi++, (byte) 0x0F);
16764 if (fits(imm,8)) {
16765 setMachineCodes(mi++, (byte) 0xBA);
16766 // "register 0x7" is really part of the opcode
16767 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
16768 emitImm8((byte)imm);
16769 } else {
16770 throw new InternalError("Data too large for BTC instruction");
16771 }
16772 if (lister != null) lister.RXDI(miStart, "BTC", dstBase, dstIndex, dstScale, dstDisp, imm);
16773 }
16774
16775 /**
16776 * Generate a register(indirect)--immediate BTC. That is,
16777 * <PRE>
16778 * [dstBase] BTC= imm
16779 * </PRE>
16780 *
16781 * @param dstBase the destination base register
16782 * @param imm immediate
16783 */
16784 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
16785 public final void emitBTC_RegInd_Imm(GPR dstBase, int imm) {
16786 int miStart = mi;
16787 // no group 1 to 4 prefix byte
16788 generateREXprefix(false, null, null, dstBase);
16789 setMachineCodes(mi++, (byte) 0x0F);
16790 if (fits(imm,8)) {
16791 setMachineCodes(mi++, (byte) 0xBA);
16792 // "register 0x7" is really part of the opcode
16793 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x7));
16794 emitImm8((byte)imm);
16795 } else {
16796 throw new InternalError("Data too large for BTC instruction");
16797 }
16798 if (lister != null) lister.RNI(miStart, "BTC", dstBase, imm);
16799 }
16800
16801 /**
16802 * Generate a register(indirect)--register BTR. That is,
16803 * <PRE>
16804 * [dstBase] BTR= srcReg
16805 * </PRE>
16806 *
16807 * @param dstBase the destination base
16808 * @param srcReg the source register
16809 */
16810 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
16811 public final void emitBTR_RegInd_Reg(GPR dstBase, GPR srcReg) {
16812 int miStart = mi;
16813 // no group 1 to 4 prefix byte
16814 generateREXprefix(false, srcReg, null, dstBase);
16815 setMachineCodes(mi++, (byte) 0x0F);
16816 setMachineCodes(mi++, (byte) 0xB3);
16817 emitRegIndirectRegOperands(dstBase, srcReg);
16818 if (lister != null) lister.RNR(miStart, "BTR", dstBase, srcReg);
16819 }
16820
16821 /**
16822 * Generate a register-offset--register BTR. That is,
16823 * <PRE>
16824 * [dstReg<<dstScale + dstDisp] BTR= srcReg
16825 * </PRE>
16826 *
16827 * @param dstIndex the destination index register
16828 * @param dstScale the destination shift amount
16829 * @param dstDisp the destination displacement
16830 * @param srcReg the source register
16831 */
16832 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
16833 public final void emitBTR_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
16834 int miStart = mi;
16835 // no group 1 to 4 prefix byte
16836 generateREXprefix(false, srcReg, dstIndex, null);
16837 setMachineCodes(mi++, (byte) 0x0F);
16838 setMachineCodes(mi++, (byte) 0xB3);
16839 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
16840 if (lister != null) lister.RFDR(miStart, "BTR", dstIndex, dstScale, dstDisp, srcReg);
16841 }
16842
16843 /**
16844 * Generate a absolute--register BTR. That is,
16845 * <PRE>
16846 * [dstDisp] BTR= srcReg
16847 * </PRE>
16848 *
16849 * @param dstDisp the destination address
16850 * @param srcReg the source register
16851 */
16852 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
16853 public final void emitBTR_Abs_Reg(Address dstDisp, GPR srcReg) {
16854 int miStart = mi;
16855 // no group 1 to 4 prefix byte
16856 generateREXprefix(false, srcReg, null, null);
16857 setMachineCodes(mi++, (byte) 0x0F);
16858 setMachineCodes(mi++, (byte) 0xB3);
16859 emitAbsRegOperands(dstDisp, srcReg);
16860 if (lister != null) lister.RAR(miStart, "BTR", dstDisp, srcReg);
16861 }
16862
16863 /**
16864 * Generate a register-index--register BTR. That is,
16865 * <PRE>
16866 * [dstBase + dstIndex<<dstScale + dstDisp] BTR= srcReg
16867 * </PRE>
16868 *
16869 * @param dstBase the base register
16870 * @param dstIndex the destination index register
16871 * @param dstScale the destination shift amount
16872 * @param dstDisp the destination displacement
16873 * @param srcReg the source register
16874 */
16875 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
16876 public final void emitBTR_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
16877 int miStart = mi;
16878 // no group 1 to 4 prefix byte
16879 generateREXprefix(false, srcReg, dstIndex, dstBase);
16880 setMachineCodes(mi++, (byte) 0x0F);
16881 setMachineCodes(mi++, (byte) 0xB3);
16882 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
16883 if (lister != null) lister.RXDR(miStart, "BTR", dstBase, dstIndex, dstScale, dstDisp, srcReg);
16884 }
16885
16886 /**
16887 * Generate a register-displacement--register BTR. That is,
16888 * <PRE>
16889 * [dstBase + dstDisp] BTR= srcReg
16890 * </PRE>
16891 *
16892 * @param dstBase the base register
16893 * @param dstDisp the destination displacement
16894 * @param srcReg the source register
16895 */
16896 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
16897 public final void emitBTR_RegDisp_Reg(GPR dstBase, Offset dstDisp, GPR srcReg) {
16898 int miStart = mi;
16899 // no group 1 to 4 prefix byte
16900 generateREXprefix(false, srcReg, null, dstBase);
16901 setMachineCodes(mi++, (byte) 0x0F);
16902 setMachineCodes(mi++, (byte) 0xB3);
16903 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
16904 if (lister != null) lister.RDR(miStart, "BTR", dstBase, dstDisp, srcReg);
16905 }
16906
16907 /**
16908 * Generate a register--register BTR. That is,
16909 * <PRE>
16910 * dstReg BTR= srcReg
16911 * </PRE>
16912 *
16913 * @param dstReg the destination register
16914 * @param srcReg the source register
16915 */
16916 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
16917 public final void emitBTR_Reg_Reg(GPR dstReg, GPR srcReg) {
16918 int miStart = mi;
16919 // no group 1 to 4 prefix byte
16920 generateREXprefix(false, srcReg, null, dstReg);
16921 setMachineCodes(mi++, (byte) 0x0F);
16922 setMachineCodes(mi++, (byte) 0xB3);
16923 emitRegRegOperands(dstReg, srcReg);
16924 if (lister != null) lister.RR(miStart, "BTR", dstReg, srcReg);
16925 }
16926
16927 /**
16928 * Generate a register--immediate BTR. That is,
16929 * <PRE>
16930 * dstReg BTR= imm
16931 * </PRE>
16932 *
16933 * @param dstReg the destination register
16934 * @param imm immediate
16935 */
16936 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
16937 public final void emitBTR_Reg_Imm(GPR dstReg, int imm) {
16938 int miStart = mi;
16939 // no group 1 to 4 prefix byte
16940 generateREXprefix(false, null, null, dstReg);
16941 setMachineCodes(mi++, (byte) 0x0F);
16942 if (fits(imm,8)) {
16943 setMachineCodes(mi++, (byte) 0xBA);
16944 // "register 0x6" is really part of the opcode
16945 emitRegRegOperands(dstReg, GPR.getForOpcode(0x6));
16946 emitImm8((byte)imm);
16947 } else {
16948 throw new InternalError("Data too large for BTR instruction");
16949 }
16950 if (lister != null) lister.RI(miStart, "BTR", dstReg, imm);
16951 }
16952
16953 /**
16954 * Generate a register-displacement--immediate BTR. That is,
16955 * <PRE>
16956 * [dstBase + dstDisp] BTR= imm
16957 * </PRE>
16958 *
16959 * @param dstBase the destination register
16960 * @param dstDisp the destination displacement
16961 * @param imm immediate
16962 */
16963 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
16964 public final void emitBTR_RegDisp_Imm(GPR dstBase, Offset dstDisp, int imm) {
16965 int miStart = mi;
16966 // no group 1 to 4 prefix byte
16967 generateREXprefix(false, null, null, dstBase);
16968 setMachineCodes(mi++, (byte) 0x0F);
16969 if (fits(imm,8)) {
16970 setMachineCodes(mi++, (byte) 0xBA);
16971 // "register 0x6" is really part of the opcode
16972 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x6));
16973 emitImm8((byte)imm);
16974 } else {
16975 throw new InternalError("Data too large for BTR instruction");
16976 }
16977 if (lister != null) lister.RDI(miStart, "BTR", dstBase, dstDisp, imm);
16978 }
16979
16980 /**
16981 * Generate a register-offset--immediate BTR. That is,
16982 * <PRE>
16983 * [dstIndex<<dstScale + dstDisp] BTR= imm
16984 * </PRE>
16985 *
16986 * @param dstIndex the destination index register
16987 * @param dstScale the destination shift amount
16988 * @param dstDisp the destination displacement
16989 * @param imm immediate
16990 */
16991 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
16992 public final void emitBTR_RegOff_Imm(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
16993 int miStart = mi;
16994 // no group 1 to 4 prefix byte
16995 generateREXprefix(false, null, dstIndex, null);
16996 setMachineCodes(mi++, (byte) 0x0F);
16997 if (fits(imm,8)) {
16998 setMachineCodes(mi++, (byte) 0xBA);
16999 // "register 0x6" is really part of the opcode
17000 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x6));
17001 emitImm8((byte)imm);
17002 } else {
17003 throw new InternalError("Data too large for BTR instruction");
17004 }
17005 if (lister != null) lister.RFDI(miStart, "BTR", dstIndex, dstScale, dstDisp, imm);
17006 }
17007
17008 /**
17009 * Generate a absolute--immediate BTR. That is,
17010 * <PRE>
17011 * [dstDisp] BTR= imm
17012 * </PRE>
17013 *
17014 * @param dstDisp the destination displacement
17015 * @param imm immediate
17016 */
17017 public final void emitBTR_Abs_Imm(Address dstDisp, int imm) {
17018 int miStart = mi;
17019 // no group 1 to 4 prefix byte
17020 generateREXprefix(false, null, null, null);
17021 setMachineCodes(mi++, (byte) 0x0F);
17022 if (fits(imm,8)) {
17023 setMachineCodes(mi++, (byte) 0xBA);
17024 // "register 0x6" is really part of the opcode
17025 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x6));
17026 emitImm8((byte)imm);
17027 } else {
17028 throw new InternalError("Data too large for BTR instruction");
17029 }
17030 if (lister != null) lister.RAI(miStart, "BTR", dstDisp, imm);
17031 }
17032
17033 /**
17034 * Generate a register-index--immediate BTR. That is,
17035 * <PRE>
17036 * [dstBase + dstIndex<<dstScale + dstDisp] BTR= imm
17037 * </PRE>
17038 *
17039 * @param dstBase the destination base register
17040 * @param dstIndex the destination index register
17041 * @param dstScale the destination shift amount
17042 * @param dstDisp the destination displacement
17043 * @param imm immediate
17044 */
17045 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
17046 public final void emitBTR_RegIdx_Imm(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
17047 int miStart = mi;
17048 // no group 1 to 4 prefix byte
17049 generateREXprefix(false, null, dstIndex, dstBase);
17050 setMachineCodes(mi++, (byte) 0x0F);
17051 if (fits(imm,8)) {
17052 setMachineCodes(mi++, (byte) 0xBA);
17053 // "register 0x6" is really part of the opcode
17054 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x6));
17055 emitImm8((byte)imm);
17056 } else {
17057 throw new InternalError("Data too large for BTR instruction");
17058 }
17059 if (lister != null) lister.RXDI(miStart, "BTR", dstBase, dstIndex, dstScale, dstDisp, imm);
17060 }
17061
17062 /**
17063 * Generate a register(indirect)--immediate BTR. That is,
17064 * <PRE>
17065 * [dstBase] BTR= imm
17066 * </PRE>
17067 *
17068 * @param dstBase the destination base register
17069 * @param imm immediate
17070 */
17071 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17072 public final void emitBTR_RegInd_Imm(GPR dstBase, int imm) {
17073 int miStart = mi;
17074 // no group 1 to 4 prefix byte
17075 generateREXprefix(false, null, null, dstBase);
17076 setMachineCodes(mi++, (byte) 0x0F);
17077 if (fits(imm,8)) {
17078 setMachineCodes(mi++, (byte) 0xBA);
17079 // "register 0x6" is really part of the opcode
17080 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x6));
17081 emitImm8((byte)imm);
17082 } else {
17083 throw new InternalError("Data too large for BTR instruction");
17084 }
17085 if (lister != null) lister.RNI(miStart, "BTR", dstBase, imm);
17086 }
17087
17088 /**
17089 * Generate a register(indirect)--register BTS. That is,
17090 * <PRE>
17091 * [dstBase] BTS= srcReg
17092 * </PRE>
17093 *
17094 * @param dstBase the destination base
17095 * @param srcReg the source register
17096 */
17097 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
17098 public final void emitBTS_RegInd_Reg(GPR dstBase, GPR srcReg) {
17099 int miStart = mi;
17100 // no group 1 to 4 prefix byte
17101 generateREXprefix(false, srcReg, null, dstBase);
17102 setMachineCodes(mi++, (byte) 0x0F);
17103 setMachineCodes(mi++, (byte) 0xAB);
17104 emitRegIndirectRegOperands(dstBase, srcReg);
17105 if (lister != null) lister.RNR(miStart, "BTS", dstBase, srcReg);
17106 }
17107
17108 /**
17109 * Generate a register-offset--register BTS. That is,
17110 * <PRE>
17111 * [dstReg<<dstScale + dstDisp] BTS= srcReg
17112 * </PRE>
17113 *
17114 * @param dstIndex the destination index register
17115 * @param dstScale the destination shift amount
17116 * @param dstDisp the destination displacement
17117 * @param srcReg the source register
17118 */
17119 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
17120 public final void emitBTS_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
17121 int miStart = mi;
17122 // no group 1 to 4 prefix byte
17123 generateREXprefix(false, srcReg, dstIndex, null);
17124 setMachineCodes(mi++, (byte) 0x0F);
17125 setMachineCodes(mi++, (byte) 0xAB);
17126 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
17127 if (lister != null) lister.RFDR(miStart, "BTS", dstIndex, dstScale, dstDisp, srcReg);
17128 }
17129
17130 /**
17131 * Generate a absolute--register BTS. That is,
17132 * <PRE>
17133 * [dstDisp] BTS= srcReg
17134 * </PRE>
17135 *
17136 * @param dstDisp the destination address
17137 * @param srcReg the source register
17138 */
17139 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
17140 public final void emitBTS_Abs_Reg(Address dstDisp, GPR srcReg) {
17141 int miStart = mi;
17142 // no group 1 to 4 prefix byte
17143 generateREXprefix(false, srcReg, null, null);
17144 setMachineCodes(mi++, (byte) 0x0F);
17145 setMachineCodes(mi++, (byte) 0xAB);
17146 emitAbsRegOperands(dstDisp, srcReg);
17147 if (lister != null) lister.RAR(miStart, "BTS", dstDisp, srcReg);
17148 }
17149
17150 /**
17151 * Generate a register-index--register BTS. That is,
17152 * <PRE>
17153 * [dstBase + dstIndex<<dstScale + dstDisp] BTS= srcReg
17154 * </PRE>
17155 *
17156 * @param dstBase the base register
17157 * @param dstIndex the destination index register
17158 * @param dstScale the destination shift amount
17159 * @param dstDisp the destination displacement
17160 * @param srcReg the source register
17161 */
17162 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
17163 public final void emitBTS_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
17164 int miStart = mi;
17165 // no group 1 to 4 prefix byte
17166 generateREXprefix(false, srcReg, dstIndex, dstBase);
17167 setMachineCodes(mi++, (byte) 0x0F);
17168 setMachineCodes(mi++, (byte) 0xAB);
17169 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
17170 if (lister != null) lister.RXDR(miStart, "BTS", dstBase, dstIndex, dstScale, dstDisp, srcReg);
17171 }
17172
17173 /**
17174 * Generate a register-displacement--register BTS. That is,
17175 * <PRE>
17176 * [dstBase + dstDisp] BTS= srcReg
17177 * </PRE>
17178 *
17179 * @param dstBase the base register
17180 * @param dstDisp the destination displacement
17181 * @param srcReg the source register
17182 */
17183 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
17184 public final void emitBTS_RegDisp_Reg(GPR dstBase, Offset dstDisp, GPR srcReg) {
17185 int miStart = mi;
17186 // no group 1 to 4 prefix byte
17187 generateREXprefix(false, srcReg, null, dstBase);
17188 setMachineCodes(mi++, (byte) 0x0F);
17189 setMachineCodes(mi++, (byte) 0xAB);
17190 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
17191 if (lister != null) lister.RDR(miStart, "BTS", dstBase, dstDisp, srcReg);
17192 }
17193
17194 /**
17195 * Generate a register--register BTS. That is,
17196 * <PRE>
17197 * dstReg BTS= srcReg
17198 * </PRE>
17199 *
17200 * @param dstReg the destination register
17201 * @param srcReg the source register
17202 */
17203 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
17204 public final void emitBTS_Reg_Reg(GPR dstReg, GPR srcReg) {
17205 int miStart = mi;
17206 // no group 1 to 4 prefix byte
17207 generateREXprefix(false, srcReg, null, dstReg);
17208 setMachineCodes(mi++, (byte) 0x0F);
17209 setMachineCodes(mi++, (byte) 0xAB);
17210 emitRegRegOperands(dstReg, srcReg);
17211 if (lister != null) lister.RR(miStart, "BTS", dstReg, srcReg);
17212 }
17213
17214 /**
17215 * Generate a register--immediate BTS. That is,
17216 * <PRE>
17217 * dstReg BTS= imm
17218 * </PRE>
17219 *
17220 * @param dstReg the destination register
17221 * @param imm immediate
17222 */
17223 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17224 public final void emitBTS_Reg_Imm(GPR dstReg, int imm) {
17225 int miStart = mi;
17226 // no group 1 to 4 prefix byte
17227 generateREXprefix(false, null, null, dstReg);
17228 setMachineCodes(mi++, (byte) 0x0F);
17229 if (fits(imm,8)) {
17230 setMachineCodes(mi++, (byte) 0xBA);
17231 // "register 0x5" is really part of the opcode
17232 emitRegRegOperands(dstReg, GPR.getForOpcode(0x5));
17233 emitImm8((byte)imm);
17234 } else {
17235 throw new InternalError("Data too large for BTS instruction");
17236 }
17237 if (lister != null) lister.RI(miStart, "BTS", dstReg, imm);
17238 }
17239
17240 /**
17241 * Generate a register-displacement--immediate BTS. That is,
17242 * <PRE>
17243 * [dstBase + dstDisp] BTS= imm
17244 * </PRE>
17245 *
17246 * @param dstBase the destination register
17247 * @param dstDisp the destination displacement
17248 * @param imm immediate
17249 */
17250 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17251 public final void emitBTS_RegDisp_Imm(GPR dstBase, Offset dstDisp, int imm) {
17252 int miStart = mi;
17253 // no group 1 to 4 prefix byte
17254 generateREXprefix(false, null, null, dstBase);
17255 setMachineCodes(mi++, (byte) 0x0F);
17256 if (fits(imm,8)) {
17257 setMachineCodes(mi++, (byte) 0xBA);
17258 // "register 0x5" is really part of the opcode
17259 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x5));
17260 emitImm8((byte)imm);
17261 } else {
17262 throw new InternalError("Data too large for BTS instruction");
17263 }
17264 if (lister != null) lister.RDI(miStart, "BTS", dstBase, dstDisp, imm);
17265 }
17266
17267 /**
17268 * Generate a register-offset--immediate BTS. That is,
17269 * <PRE>
17270 * [dstIndex<<dstScale + dstDisp] BTS= imm
17271 * </PRE>
17272 *
17273 * @param dstIndex the destination index register
17274 * @param dstScale the destination shift amount
17275 * @param dstDisp the destination displacement
17276 * @param imm immediate
17277 */
17278 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17279 public final void emitBTS_RegOff_Imm(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
17280 int miStart = mi;
17281 // no group 1 to 4 prefix byte
17282 generateREXprefix(false, null, dstIndex, null);
17283 setMachineCodes(mi++, (byte) 0x0F);
17284 if (fits(imm,8)) {
17285 setMachineCodes(mi++, (byte) 0xBA);
17286 // "register 0x5" is really part of the opcode
17287 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
17288 emitImm8((byte)imm);
17289 } else {
17290 throw new InternalError("Data too large for BTS instruction");
17291 }
17292 if (lister != null) lister.RFDI(miStart, "BTS", dstIndex, dstScale, dstDisp, imm);
17293 }
17294
17295 /**
17296 * Generate a absolute--immediate BTS. That is,
17297 * <PRE>
17298 * [dstDisp] BTS= imm
17299 * </PRE>
17300 *
17301 * @param dstDisp the destination displacement
17302 * @param imm immediate
17303 */
17304 public final void emitBTS_Abs_Imm(Address dstDisp, int imm) {
17305 int miStart = mi;
17306 // no group 1 to 4 prefix byte
17307 generateREXprefix(false, null, null, null);
17308 setMachineCodes(mi++, (byte) 0x0F);
17309 if (fits(imm,8)) {
17310 setMachineCodes(mi++, (byte) 0xBA);
17311 // "register 0x5" is really part of the opcode
17312 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x5));
17313 emitImm8((byte)imm);
17314 } else {
17315 throw new InternalError("Data too large for BTS instruction");
17316 }
17317 if (lister != null) lister.RAI(miStart, "BTS", dstDisp, imm);
17318 }
17319
17320 /**
17321 * Generate a register-index--immediate BTS. That is,
17322 * <PRE>
17323 * [dstBase + dstIndex<<dstScale + dstDisp] BTS= imm
17324 * </PRE>
17325 *
17326 * @param dstBase the destination base register
17327 * @param dstIndex the destination index register
17328 * @param dstScale the destination shift amount
17329 * @param dstDisp the destination displacement
17330 * @param imm immediate
17331 */
17332 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
17333 public final void emitBTS_RegIdx_Imm(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
17334 int miStart = mi;
17335 // no group 1 to 4 prefix byte
17336 generateREXprefix(false, null, dstIndex, dstBase);
17337 setMachineCodes(mi++, (byte) 0x0F);
17338 if (fits(imm,8)) {
17339 setMachineCodes(mi++, (byte) 0xBA);
17340 // "register 0x5" is really part of the opcode
17341 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
17342 emitImm8((byte)imm);
17343 } else {
17344 throw new InternalError("Data too large for BTS instruction");
17345 }
17346 if (lister != null) lister.RXDI(miStart, "BTS", dstBase, dstIndex, dstScale, dstDisp, imm);
17347 }
17348
17349 /**
17350 * Generate a register(indirect)--immediate BTS. That is,
17351 * <PRE>
17352 * [dstBase] BTS= imm
17353 * </PRE>
17354 *
17355 * @param dstBase the destination base register
17356 * @param imm immediate
17357 */
17358 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17359 public final void emitBTS_RegInd_Imm(GPR dstBase, int imm) {
17360 int miStart = mi;
17361 // no group 1 to 4 prefix byte
17362 generateREXprefix(false, null, null, dstBase);
17363 setMachineCodes(mi++, (byte) 0x0F);
17364 if (fits(imm,8)) {
17365 setMachineCodes(mi++, (byte) 0xBA);
17366 // "register 0x5" is really part of the opcode
17367 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x5));
17368 emitImm8((byte)imm);
17369 } else {
17370 throw new InternalError("Data too large for BTS instruction");
17371 }
17372 if (lister != null) lister.RNI(miStart, "BTS", dstBase, imm);
17373 }
17374
17375 /**
17376 * Generate a CALL to a label or immediate. That is,
17377 * <PRE>
17378 * pc = {future address from label | imm}
17379 * </PRE>
17380 *
17381 * @param imm offset to immediate CALL to. 0 means use
17382 * label. Immediate is assumed to be within current instructions.
17383 * @param label label to branch to (used when imm == 0)
17384 */
17385 public final void emitCALL_ImmOrLabel(int imm, int label) {
17386 if (imm == 0)
17387 emitCALL_Label(label);
17388 else
17389 emitCALL_Imm(imm);
17390 }
17391
17392 /**
17393 * Branch to the given target with a CALL instruction
17394 * <PRE>
17395 * IP = (instruction @ label)
17396 * </PRE>
17397 *
17398 * This emit method is expecting only a forward branch (that is
17399 * what the Label operand means); it creates a ForwardReference
17400 * to the given label, and puts it into the assembler's list of
17401 * references to resolve. This emitter knows the branch is
17402 * unconditional, so it uses
17403 * {@link org.jikesrvm.compilers.common.assembler.ForwardReference.UnconditionalBranch}
17404 * as the forward reference type to create.
17405 *
17406 * All forward branches have a label as the branch target; clients
17407 * can arbirarily associate labels and instructions, but must be
17408 * consistent in giving the chosen label as the target of branches
17409 * to an instruction and calling resolveForwardBranches with the
17410 * given label immediately before emitting the target instruction.
17411 * See the header comments of ForwardReference for more details.
17412 *
17413 * @param label the label associated with the branch target instrucion
17414 */
17415 public final void emitCALL_Label(int label) {
17416 int miStart = mi;
17417 ForwardReference r =
17418 new ForwardReference.UnconditionalBranch(mi, label);
17419 forwardRefs = ForwardReference.enqueue(forwardRefs, r);
17420 setMachineCodes(mi++, (byte) 0xE8);
17421 mi += 4; // leave space for displacement
17422 if (lister != null) lister.I(miStart, "CALL", label);
17423 }
17424
17425 /**
17426 * Generate a CALL to immediate. That is,
17427 * <PRE>
17428 * pc = imm
17429 * </PRE>
17430 *
17431 * @param imm offset to immediate CALL to (within current instructions)
17432 */
17433 public final void emitCALL_Imm(int imm) {
17434 int miStart = mi;
17435 setMachineCodes(mi++, (byte) 0xE8);
17436 // offset of next instruction (this instruction is 5 bytes,
17437 // but we just accounted for one of them in the mi++ above)
17438 emitImm32(imm - (mi + 4));
17439 if (lister != null) lister.I(miStart, "CALL", imm);
17440 }
17441
17442 /**
17443 * Generate a CALL to register. That is,
17444 * <PRE>
17445 * pc = dstReg
17446 * </PRE>
17447 *
17448 * @param dstReg register containing destination address
17449 */
17450 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17451 public final void emitCALL_Reg(GPR dstReg) {
17452 int miStart = mi;
17453 generateREXprefix(false, null, null, dstReg);
17454 setMachineCodes(mi++, (byte) 0xFF);
17455 // "register 0x2" is really part of the CALL opcode
17456 emitRegRegOperands(dstReg, GPR.getForOpcode(0x2));
17457 if (lister != null) lister.R(miStart, "CALL", dstReg);
17458 }
17459
17460 /**
17461 * Generate a CALL to register and displacement. That is,
17462 * <PRE>
17463 * pc = [dstBase + dstDisp]
17464 * </PRE>
17465 *
17466 * @param dstBase the destination base address register
17467 * @param dstDisp the destination displacement
17468 */
17469 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17470 public final void emitCALL_RegDisp(GPR dstBase, Offset dstDisp) {
17471 int miStart = mi;
17472 generateREXprefix(false, null, null, dstBase);
17473 setMachineCodes(mi++, (byte) 0xFF);
17474 // "register 0x2" is really part of the CALL opcode
17475 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x2));
17476 if (lister != null) lister.RD(miStart, "CALL", dstBase, dstDisp);
17477 }
17478
17479 /**
17480 * Generate a CALL to register indirect. That is,
17481 * <PRE>
17482 * pc = [dstBase]
17483 * </PRE>
17484 *
17485 * @param dstBase the destination base address register
17486 */
17487 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17488 public final void emitCALL_RegInd(GPR dstBase) {
17489 int miStart = mi;
17490 generateREXprefix(false, null, null, dstBase);
17491 setMachineCodes(mi++, (byte) 0xFF);
17492 // "register 0x2" is really part of the CALL opcode
17493 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x2));
17494 if (lister != null) lister.RN(miStart, "CALL", dstBase);
17495 }
17496
17497 /**
17498 * Generate a CALL to register offset. That is,
17499 * <PRE>
17500 * pc = [dstIndex<<dstScale + dstDisp]
17501 * </PRE>
17502 *
17503 * @param dstIndex the destination index register
17504 * @param dstScale the destination shift amount
17505 * @param dstDisp the destination displacement
17506 */
17507 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17508 public final void emitCALL_RegOff(GPR dstIndex, short dstScale, Offset dstDisp) {
17509 int miStart = mi;
17510 generateREXprefix(false, null, dstIndex, null);
17511 setMachineCodes(mi++, (byte) 0xFF);
17512 // "register 0x2" is really part of the CALL opcode
17513 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
17514 if (lister != null) lister.RFD(miStart, "CALL", dstIndex, dstScale, dstDisp);
17515 }
17516
17517 /**
17518 * Generate a CALL to absolute address. That is,
17519 * <PRE>
17520 * pc = [dstDisp]
17521 * </PRE>
17522 *
17523 * @param dstDisp the destination displacement
17524 */
17525 public final void emitCALL_Abs(Address dstDisp) {
17526 int miStart = mi;
17527 setMachineCodes(mi++, (byte) 0xFF);
17528 // "register 0x2" is really part of the CALL opcode
17529 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x2));
17530 if (lister != null) lister.RA(miStart, "CALL", dstDisp);
17531 }
17532
17533 /**
17534 * Generate a CALL to register offset. That is,
17535 * <PRE>
17536 * pc = [dstBase + dstIndex<<dstScale + dstDisp]
17537 * </PRE>
17538 *
17539 * @param dstBase the destination base register
17540 * @param dstIndex the destination index register
17541 * @param dstScale the destination shift amount
17542 * @param dstDisp the destination displacement
17543 */
17544 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
17545 public final void emitCALL_RegIdx(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp) {
17546 int miStart = mi;
17547 generateREXprefix(false, null, dstIndex, dstBase);
17548 setMachineCodes(mi++, (byte) 0xFF);
17549 // "register 0x2" is really part of the CALL opcode
17550 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
17551 if (lister != null) lister.RXD(miStart, "CALL", dstBase, dstIndex, dstScale, dstDisp);
17552 }
17553
17554 /**
17555 * Generate a JMP to a label or immediate. That is,
17556 * <PRE>
17557 * pc = {future address from label | imm}
17558 * </PRE>
17559 *
17560 * @param imm offset to immediate JMP to. 0 means use
17561 * label. Immediate is assumed to be within current instructions.
17562 * @param label label to branch to (used when imm == 0)
17563 */
17564 public final void emitJMP_ImmOrLabel(int imm, int label) {
17565 if (imm == 0)
17566 emitJMP_Label(label);
17567 else
17568 emitJMP_Imm(imm);
17569 }
17570
17571 /**
17572 * Branch to the given target with a JMP instruction
17573 * <PRE>
17574 * IP = (instruction @ label)
17575 * </PRE>
17576 *
17577 * This emit method is expecting only a forward branch (that is
17578 * what the Label operand means); it creates a ForwardReference
17579 * to the given label, and puts it into the assembler's list of
17580 * references to resolve. This emitter knows the branch is
17581 * unconditional, so it uses
17582 * {@link org.jikesrvm.compilers.common.assembler.ForwardReference.UnconditionalBranch}
17583 * as the forward reference type to create.
17584 *
17585 * All forward branches have a label as the branch target; clients
17586 * can arbirarily associate labels and instructions, but must be
17587 * consistent in giving the chosen label as the target of branches
17588 * to an instruction and calling resolveForwardBranches with the
17589 * given label immediately before emitting the target instruction.
17590 * See the header comments of ForwardReference for more details.
17591 *
17592 * @param label the label associated with the branch target instrucion
17593 */
17594 public final void emitJMP_Label(int label) {
17595 int miStart = mi;
17596 ForwardReference r =
17597 new ForwardReference.UnconditionalBranch(mi, label);
17598 forwardRefs = ForwardReference.enqueue(forwardRefs, r);
17599 setMachineCodes(mi++, (byte) 0xE9);
17600 mi += 4; // leave space for displacement
17601 if (lister != null) lister.I(miStart, "JMP", label);
17602 }
17603
17604 /**
17605 * Generate a JMP to immediate. That is,
17606 * <PRE>
17607 * pc = imm
17608 * </PRE>
17609 *
17610 * @param imm offset to immediate JMP to (within current instructions)
17611 */
17612 public final void emitJMP_Imm(int imm) {
17613 int miStart = mi;
17614 // can we fit the offset from the next instruction into 8
17615 // bits, assuming this instruction is 2 bytes (which it will
17616 // be if the offset fits into 8 bits)?
17617 int relOffset = imm - (mi + 2);
17618 if (fits(relOffset,8)) {
17619 // yes, so use short form.
17620 setMachineCodes(mi++, (byte) 0xEB);
17621 emitImm8((byte) relOffset);
17622 } else {
17623 // no, must use 32 bit offset and ignore relOffset to
17624 // account for the fact that this instruction now has to
17625 // be 5 bytes long.
17626 setMachineCodes(mi++, (byte) 0xE9);
17627 // offset of next instruction (this instruction is 5 bytes,
17628 // but we just accounted for one of them in the mi++ above)
17629 emitImm32(imm - (mi + 4));
17630 }
17631 if (lister != null) lister.I(miStart, "JMP", imm);
17632 }
17633
17634 /**
17635 * Generate a JMP to register. That is,
17636 * <PRE>
17637 * pc = dstReg
17638 * </PRE>
17639 *
17640 * @param dstReg register containing destination address
17641 */
17642 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17643 public final void emitJMP_Reg(GPR dstReg) {
17644 int miStart = mi;
17645 generateREXprefix(false, null, null, dstReg);
17646 setMachineCodes(mi++, (byte) 0xFF);
17647 // "register 0x4" is really part of the JMP opcode
17648 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
17649 if (lister != null) lister.R(miStart, "JMP", dstReg);
17650 }
17651
17652 /**
17653 * Generate a JMP to register and displacement. That is,
17654 * <PRE>
17655 * pc = [dstBase + dstDisp]
17656 * </PRE>
17657 *
17658 * @param dstBase the destination base address register
17659 * @param dstDisp the destination displacement
17660 */
17661 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17662 public final void emitJMP_RegDisp(GPR dstBase, Offset dstDisp) {
17663 int miStart = mi;
17664 generateREXprefix(false, null, null, dstBase);
17665 setMachineCodes(mi++, (byte) 0xFF);
17666 // "register 0x4" is really part of the JMP opcode
17667 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
17668 if (lister != null) lister.RD(miStart, "JMP", dstBase, dstDisp);
17669 }
17670
17671 /**
17672 * Generate a JMP to register indirect. That is,
17673 * <PRE>
17674 * pc = [dstBase]
17675 * </PRE>
17676 *
17677 * @param dstBase the destination base address register
17678 */
17679 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17680 public final void emitJMP_RegInd(GPR dstBase) {
17681 int miStart = mi;
17682 generateREXprefix(false, null, null, dstBase);
17683 setMachineCodes(mi++, (byte) 0xFF);
17684 // "register 0x4" is really part of the JMP opcode
17685 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
17686 if (lister != null) lister.RN(miStart, "JMP", dstBase);
17687 }
17688
17689 /**
17690 * Generate a JMP to register offset. That is,
17691 * <PRE>
17692 * pc = [dstIndex<<dstScale + dstDisp]
17693 * </PRE>
17694 *
17695 * @param dstIndex the destination index register
17696 * @param dstScale the destination shift amount
17697 * @param dstDisp the destination displacement
17698 */
17699 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17700 public final void emitJMP_RegOff(GPR dstIndex, short dstScale, Offset dstDisp) {
17701 int miStart = mi;
17702 generateREXprefix(false, null, dstIndex, null);
17703 setMachineCodes(mi++, (byte) 0xFF);
17704 // "register 0x4" is really part of the JMP opcode
17705 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
17706 if (lister != null) lister.RFD(miStart, "JMP", dstIndex, dstScale, dstDisp);
17707 }
17708
17709 /**
17710 * Generate a JMP to absolute address. That is,
17711 * <PRE>
17712 * pc = [dstDisp]
17713 * </PRE>
17714 *
17715 * @param dstDisp the destination displacement
17716 */
17717 public final void emitJMP_Abs(Address dstDisp) {
17718 int miStart = mi;
17719 setMachineCodes(mi++, (byte) 0xFF);
17720 // "register 0x4" is really part of the JMP opcode
17721 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
17722 if (lister != null) lister.RA(miStart, "JMP", dstDisp);
17723 }
17724
17725 /**
17726 * Generate a JMP to register offset. That is,
17727 * <PRE>
17728 * pc = [dstBase + dstIndex<<dstScale + dstDisp]
17729 * </PRE>
17730 *
17731 * @param dstBase the destination base register
17732 * @param dstIndex the destination index register
17733 * @param dstScale the destination shift amount
17734 * @param dstDisp the destination displacement
17735 */
17736 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
17737 public final void emitJMP_RegIdx(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp) {
17738 int miStart = mi;
17739 generateREXprefix(false, null, dstIndex, dstBase);
17740 setMachineCodes(mi++, (byte) 0xFF);
17741 // "register 0x4" is really part of the JMP opcode
17742 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
17743 if (lister != null) lister.RXD(miStart, "JMP", dstBase, dstIndex, dstScale, dstDisp);
17744 }
17745
17746 /**
17747 * Generate a DEC on a register. That is,
17748 * <PRE>
17749 * -- reg
17750 * </PRE>
17751 *
17752 * @param reg register to operate upon
17753 */
17754 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17755 public void emitDEC_Reg(GPR reg) {
17756 int miStart = mi;
17757 // no group 1 to 4 prefix byte
17758 generateREXprefix(false, null, null, reg);
17759 if (!VM.buildFor32Addr()) {
17760 setMachineCodes(mi++, (byte) (0xFF));
17761 emitRegRegOperands(reg, GPR.getForOpcode(0x1));
17762 } else {
17763 setMachineCodes(mi++, (byte) (0x48 | (reg.value() & 7)));
17764 }
17765 if (lister != null) lister.R(miStart, "DEC", reg);
17766 }
17767 /**
17768 * Generate a DEC to register-displacement offset. That is,
17769 * <PRE>
17770 * -- [base + disp]
17771 * </PRE>
17772 *
17773 * @param base the destination base register
17774 * @param disp the destination displacement
17775 */
17776 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17777 public final void emitDEC_RegDisp(GPR base, Offset disp) {
17778 int miStart = mi;
17779 // no group 1 to 4 prefix byte
17780 generateREXprefix(false, null, null, base);
17781 setMachineCodes(mi++, (byte) 0xFF);
17782 // "register 0x1" is really part of the opcode
17783 emitRegDispRegOperands(base, disp, GPR.getForOpcode(0x1));
17784 if (lister != null) lister.RD(miStart, "DEC", base, disp);
17785 }
17786
17787 /**
17788 * Generate a DEC to register indirect. That is,
17789 * <PRE>
17790 * -- [reg]
17791 * </PRE>
17792 *
17793 * @param base the destination base register
17794 */
17795 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17796 public final void emitDEC_RegInd(GPR base) {
17797 int miStart = mi;
17798 // no group 1 to 4 prefix byte
17799 generateREXprefix(false, null, null, base);
17800 setMachineCodes(mi++, (byte) 0xFF);
17801 // "register 0x1" is really part of the opcode
17802 emitRegIndirectRegOperands(base, GPR.getForOpcode(0x1));
17803 if (lister != null) lister.RN(miStart, "DEC", base);
17804 }
17805
17806 /**
17807 * Generate a DEC to register offset. That is,
17808 * <PRE>
17809 * -- [index<<scale + disp]
17810 * </PRE>
17811 *
17812 * @param index the destination index register
17813 * @param scale the destination shift amount
17814 * @param disp the destination displacement
17815 */
17816 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17817 public final void emitDEC_RegOff(GPR index, short scale, Offset disp) {
17818 int miStart = mi;
17819 // no group 1 to 4 prefix byte
17820 generateREXprefix(false, null, index, null);
17821 setMachineCodes(mi++, (byte) 0xFF);
17822 // "register 0x1" is really part of the opcode
17823 emitRegOffRegOperands(index, scale, disp, GPR.getForOpcode(0x1));
17824 if (lister != null) lister.RFD(miStart, "DEC", index, scale, disp);
17825 }
17826
17827 /**
17828 * Generate a DEC to absolute address. That is,
17829 * <PRE>
17830 * -- [disp]
17831 * </PRE>
17832 *
17833 * @param disp the destination displacement
17834 */
17835 public final void emitDEC_Abs(Address disp) {
17836 int miStart = mi;
17837 // no group 1 to 4 prefix byte
17838 generateREXprefix(false, null, null, null);
17839 setMachineCodes(mi++, (byte) 0xFF);
17840 // "register 0x1" is really part of the opcode
17841 emitAbsRegOperands(disp, GPR.getForOpcode(0x1));
17842 if (lister != null) lister.RA(miStart, "DEC", disp);
17843 }
17844
17845 /**
17846 * Generate a DEC to register offset. That is,
17847 * <PRE>
17848 * -- [base + index<<scale + disp]
17849 * </PRE>
17850 *
17851 * @param base the destination base register
17852 * @param index the destination index register
17853 * @param scale the destination shift amount
17854 * @param disp the destination displacement
17855 */
17856 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
17857 public final void emitDEC_RegIdx(GPR base, GPR index, short scale, Offset disp) {
17858 int miStart = mi;
17859 // no group 1 to 4 prefix byte
17860 generateREXprefix(false, null, index, base);
17861 setMachineCodes(mi++, (byte) 0xFF);
17862 // "register 0x1" is really part of the opcode
17863 emitSIBRegOperands(base, index, scale, disp, GPR.getForOpcode(0x1));
17864 if (lister != null) lister.RXD(miStart, "DEC", base, index, scale, disp);
17865 }
17866
17867 /**
17868 * Generate a DEC on a register. That is,
17869 * <PRE>
17870 * -- (byte) reg
17871 * </PRE>
17872 *
17873 * @param reg register to operate upon
17874 */
17875 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17876 public final void emitDEC_Reg_Byte(GPR reg) {
17877 int miStart = mi;
17878 // no group 1 to 4 prefix byte
17879 generateREXprefix(false, null, null, reg);
17880 setMachineCodes(mi++, (byte) 0xFE);
17881 emitRegRegOperands(reg, GPR.getForOpcode(0x1));
17882 if (lister != null) lister.R(miStart, "DEC", reg);
17883 }
17884 /**
17885 * Generate a DEC to register-displacement offset. That is,
17886 * <PRE>
17887 * -- (byte) [base + disp]
17888 * </PRE>
17889 *
17890 * @param base the destination base register
17891 * @param disp the destination displacement
17892 */
17893 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17894 public final void emitDEC_RegDisp_Byte(GPR base, Offset disp) {
17895 int miStart = mi;
17896 // no group 1 to 4 prefix byte
17897 generateREXprefix(false, null, null, base);
17898 setMachineCodes(mi++, (byte) 0xFE);
17899 // "register 0x1" is really part of the opcode
17900 emitRegDispRegOperands(base, disp, GPR.getForOpcode(0x1));
17901 if (lister != null) lister.RD(miStart, "DEC", base, disp);
17902 }
17903
17904 /**
17905 * Generate a DEC to register indirect. That is,
17906 * <PRE>
17907 * -- (byte) [reg]
17908 * </PRE>
17909 *
17910 * @param base the destination base register
17911 */
17912 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17913 public final void emitDEC_RegInd_Byte(GPR base) {
17914 int miStart = mi;
17915 // no group 1 to 4 prefix byte
17916 generateREXprefix(false, null, null, base);
17917 setMachineCodes(mi++, (byte) 0xFE);
17918 // "register 0x1" is really part of the opcode
17919 emitRegIndirectRegOperands(base, GPR.getForOpcode(0x1));
17920 if (lister != null) lister.RN(miStart, "DEC", base);
17921 }
17922
17923 /**
17924 * Generate a DEC to register offset. That is,
17925 * <PRE>
17926 * -- (byte) [index<<scale + disp]
17927 * </PRE>
17928 *
17929 * @param index the destination index register
17930 * @param scale the destination shift amount
17931 * @param disp the destination displacement
17932 */
17933 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17934 public final void emitDEC_RegOff_Byte(GPR index, short scale, Offset disp) {
17935 int miStart = mi;
17936 // no group 1 to 4 prefix byte
17937 generateREXprefix(false, null, index, null);
17938 setMachineCodes(mi++, (byte) 0xFE);
17939 // "register 0x1" is really part of the opcode
17940 emitRegOffRegOperands(index, scale, disp, GPR.getForOpcode(0x1));
17941 if (lister != null) lister.RFD(miStart, "DEC", index, scale, disp);
17942 }
17943
17944 /**
17945 * Generate a DEC to absolute address. That is,
17946 * <PRE>
17947 * -- (byte) [disp]
17948 * </PRE>
17949 *
17950 * @param disp the destination displacement
17951 */
17952 public final void emitDEC_Abs_Byte(Address disp) {
17953 int miStart = mi;
17954 // no group 1 to 4 prefix byte
17955 generateREXprefix(false, null, null, null);
17956 setMachineCodes(mi++, (byte) 0xFE);
17957 // "register 0x1" is really part of the opcode
17958 emitAbsRegOperands(disp, GPR.getForOpcode(0x1));
17959 if (lister != null) lister.RA(miStart, "DEC", disp);
17960 }
17961
17962 /**
17963 * Generate a DEC to register offset. That is,
17964 * <PRE>
17965 * -- (byte) [base + index<<scale + disp]
17966 * </PRE>
17967 *
17968 * @param base the destination base register
17969 * @param index the destination index register
17970 * @param scale the destination shift amount
17971 * @param disp the destination displacement
17972 */
17973 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
17974 public final void emitDEC_RegIdx_Byte(GPR base, GPR index, short scale, Offset disp) {
17975 int miStart = mi;
17976 // no group 1 to 4 prefix byte
17977 generateREXprefix(false, null, index, base);
17978 setMachineCodes(mi++, (byte) 0xFE);
17979 // "register 0x1" is really part of the opcode
17980 emitSIBRegOperands(base, index, scale, disp, GPR.getForOpcode(0x1));
17981 if (lister != null) lister.RXD(miStart, "DEC", base, index, scale, disp);
17982 }
17983
17984 /**
17985 * Generate a DEC on a register. That is,
17986 * <PRE>
17987 * -- (word) reg
17988 * </PRE>
17989 *
17990 * @param reg register to operate upon
17991 */
17992 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
17993 public void emitDEC_Reg_Word(GPR reg) {
17994 int miStart = mi;
17995 setMachineCodes(mi++, (byte) 0x66);
17996 generateREXprefix(false, null, null, reg);
17997 if (!VM.buildFor32Addr()) {
17998 setMachineCodes(mi++, (byte) (0xFF));
17999 emitRegRegOperands(reg, GPR.getForOpcode(0x1));
18000 } else {
18001 setMachineCodes(mi++, (byte) (0x48 | (reg.value() & 7)));
18002 }
18003 if (lister != null) lister.R(miStart, "DEC", reg);
18004 }
18005 /**
18006 * Generate a DEC to register-displacement offset. That is,
18007 * <PRE>
18008 * -- (word) [base + disp]
18009 * </PRE>
18010 *
18011 * @param base the destination base register
18012 * @param disp the destination displacement
18013 */
18014 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18015 public final void emitDEC_RegDisp_Word(GPR base, Offset disp) {
18016 int miStart = mi;
18017 setMachineCodes(mi++, (byte) 0x66);
18018 generateREXprefix(false, null, null, base);
18019 setMachineCodes(mi++, (byte) 0xFF);
18020 // "register 0x1" is really part of the opcode
18021 emitRegDispRegOperands(base, disp, GPR.getForOpcode(0x1));
18022 if (lister != null) lister.RD(miStart, "DEC", base, disp);
18023 }
18024
18025 /**
18026 * Generate a DEC to register indirect. That is,
18027 * <PRE>
18028 * -- (word) [reg]
18029 * </PRE>
18030 *
18031 * @param base the destination base register
18032 */
18033 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18034 public final void emitDEC_RegInd_Word(GPR base) {
18035 int miStart = mi;
18036 setMachineCodes(mi++, (byte) 0x66);
18037 generateREXprefix(false, null, null, base);
18038 setMachineCodes(mi++, (byte) 0xFF);
18039 // "register 0x1" is really part of the opcode
18040 emitRegIndirectRegOperands(base, GPR.getForOpcode(0x1));
18041 if (lister != null) lister.RN(miStart, "DEC", base);
18042 }
18043
18044 /**
18045 * Generate a DEC to register offset. That is,
18046 * <PRE>
18047 * -- (word) [index<<scale + disp]
18048 * </PRE>
18049 *
18050 * @param index the destination index register
18051 * @param scale the destination shift amount
18052 * @param disp the destination displacement
18053 */
18054 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18055 public final void emitDEC_RegOff_Word(GPR index, short scale, Offset disp) {
18056 int miStart = mi;
18057 setMachineCodes(mi++, (byte) 0x66);
18058 generateREXprefix(false, null, index, null);
18059 setMachineCodes(mi++, (byte) 0xFF);
18060 // "register 0x1" is really part of the opcode
18061 emitRegOffRegOperands(index, scale, disp, GPR.getForOpcode(0x1));
18062 if (lister != null) lister.RFD(miStart, "DEC", index, scale, disp);
18063 }
18064
18065 /**
18066 * Generate a DEC to absolute address. That is,
18067 * <PRE>
18068 * -- (word) [disp]
18069 * </PRE>
18070 *
18071 * @param disp the destination displacement
18072 */
18073 public final void emitDEC_Abs_Word(Address disp) {
18074 int miStart = mi;
18075 setMachineCodes(mi++, (byte) 0x66);
18076 generateREXprefix(false, null, null, null);
18077 setMachineCodes(mi++, (byte) 0xFF);
18078 // "register 0x1" is really part of the opcode
18079 emitAbsRegOperands(disp, GPR.getForOpcode(0x1));
18080 if (lister != null) lister.RA(miStart, "DEC", disp);
18081 }
18082
18083 /**
18084 * Generate a DEC to register offset. That is,
18085 * <PRE>
18086 * -- (word) [base + index<<scale + disp]
18087 * </PRE>
18088 *
18089 * @param base the destination base register
18090 * @param index the destination index register
18091 * @param scale the destination shift amount
18092 * @param disp the destination displacement
18093 */
18094 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
18095 public final void emitDEC_RegIdx_Word(GPR base, GPR index, short scale, Offset disp) {
18096 int miStart = mi;
18097 setMachineCodes(mi++, (byte) 0x66);
18098 generateREXprefix(false, null, index, base);
18099 setMachineCodes(mi++, (byte) 0xFF);
18100 // "register 0x1" is really part of the opcode
18101 emitSIBRegOperands(base, index, scale, disp, GPR.getForOpcode(0x1));
18102 if (lister != null) lister.RXD(miStart, "DEC", base, index, scale, disp);
18103 }
18104
18105 /**
18106 * Generate a DEC on a register. That is,
18107 * <PRE>
18108 * -- (quad) reg
18109 * </PRE>
18110 *
18111 * @param reg register to operate upon
18112 */
18113 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18114 public void emitDEC_Reg_Quad(GPR reg) {
18115 int miStart = mi;
18116 // no group 1 to 4 prefix byte
18117 generateREXprefix(true, null, null, reg);
18118 if (!VM.buildFor32Addr()) {
18119 setMachineCodes(mi++, (byte) (0xFF));
18120 emitRegRegOperands(reg, GPR.getForOpcode(0x1));
18121 } else {
18122 setMachineCodes(mi++, (byte) (0x48 | (reg.value() & 7)));
18123 }
18124 if (lister != null) lister.R(miStart, "DEC", reg);
18125 }
18126 /**
18127 * Generate a DEC to register-displacement offset. That is,
18128 * <PRE>
18129 * -- (quad) [base + disp]
18130 * </PRE>
18131 *
18132 * @param base the destination base register
18133 * @param disp the destination displacement
18134 */
18135 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18136 public final void emitDEC_RegDisp_Quad(GPR base, Offset disp) {
18137 int miStart = mi;
18138 // no group 1 to 4 prefix byte
18139 generateREXprefix(true, null, null, base);
18140 setMachineCodes(mi++, (byte) 0xFF);
18141 // "register 0x1" is really part of the opcode
18142 emitRegDispRegOperands(base, disp, GPR.getForOpcode(0x1));
18143 if (lister != null) lister.RD(miStart, "DEC", base, disp);
18144 }
18145
18146 /**
18147 * Generate a DEC to register indirect. That is,
18148 * <PRE>
18149 * -- (quad) [reg]
18150 * </PRE>
18151 *
18152 * @param base the destination base register
18153 */
18154 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18155 public final void emitDEC_RegInd_Quad(GPR base) {
18156 int miStart = mi;
18157 // no group 1 to 4 prefix byte
18158 generateREXprefix(true, null, null, base);
18159 setMachineCodes(mi++, (byte) 0xFF);
18160 // "register 0x1" is really part of the opcode
18161 emitRegIndirectRegOperands(base, GPR.getForOpcode(0x1));
18162 if (lister != null) lister.RN(miStart, "DEC", base);
18163 }
18164
18165 /**
18166 * Generate a DEC to register offset. That is,
18167 * <PRE>
18168 * -- (quad) [index<<scale + disp]
18169 * </PRE>
18170 *
18171 * @param index the destination index register
18172 * @param scale the destination shift amount
18173 * @param disp the destination displacement
18174 */
18175 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18176 public final void emitDEC_RegOff_Quad(GPR index, short scale, Offset disp) {
18177 int miStart = mi;
18178 // no group 1 to 4 prefix byte
18179 generateREXprefix(true, null, index, null);
18180 setMachineCodes(mi++, (byte) 0xFF);
18181 // "register 0x1" is really part of the opcode
18182 emitRegOffRegOperands(index, scale, disp, GPR.getForOpcode(0x1));
18183 if (lister != null) lister.RFD(miStart, "DEC", index, scale, disp);
18184 }
18185
18186 /**
18187 * Generate a DEC to absolute address. That is,
18188 * <PRE>
18189 * -- (quad) [disp]
18190 * </PRE>
18191 *
18192 * @param disp the destination displacement
18193 */
18194 public final void emitDEC_Abs_Quad(Address disp) {
18195 int miStart = mi;
18196 // no group 1 to 4 prefix byte
18197 generateREXprefix(true, null, null, null);
18198 setMachineCodes(mi++, (byte) 0xFF);
18199 // "register 0x1" is really part of the opcode
18200 emitAbsRegOperands(disp, GPR.getForOpcode(0x1));
18201 if (lister != null) lister.RA(miStart, "DEC", disp);
18202 }
18203
18204 /**
18205 * Generate a DEC to register offset. That is,
18206 * <PRE>
18207 * -- (quad) [base + index<<scale + disp]
18208 * </PRE>
18209 *
18210 * @param base the destination base register
18211 * @param index the destination index register
18212 * @param scale the destination shift amount
18213 * @param disp the destination displacement
18214 */
18215 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
18216 public final void emitDEC_RegIdx_Quad(GPR base, GPR index, short scale, Offset disp) {
18217 int miStart = mi;
18218 // no group 1 to 4 prefix byte
18219 generateREXprefix(true, null, index, base);
18220 setMachineCodes(mi++, (byte) 0xFF);
18221 // "register 0x1" is really part of the opcode
18222 emitSIBRegOperands(base, index, scale, disp, GPR.getForOpcode(0x1));
18223 if (lister != null) lister.RXD(miStart, "DEC", base, index, scale, disp);
18224 }
18225
18226 /**
18227 * Generate a INC on a register. That is,
18228 * <PRE>
18229 * ++ reg
18230 * </PRE>
18231 *
18232 * @param reg register to operate upon
18233 */
18234 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18235 public void emitINC_Reg(GPR reg) {
18236 int miStart = mi;
18237 // no group 1 to 4 prefix byte
18238 generateREXprefix(false, null, null, reg);
18239 if (!VM.buildFor32Addr()) {
18240 setMachineCodes(mi++, (byte) (0xFF));
18241 emitRegRegOperands(reg, GPR.getForOpcode(0x0));
18242 } else {
18243 setMachineCodes(mi++, (byte) (0x40 | (reg.value() & 7)));
18244 }
18245 if (lister != null) lister.R(miStart, "INC", reg);
18246 }
18247 /**
18248 * Generate a INC to register-displacement offset. That is,
18249 * <PRE>
18250 * ++ [base + disp]
18251 * </PRE>
18252 *
18253 * @param base the destination base register
18254 * @param disp the destination displacement
18255 */
18256 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18257 public final void emitINC_RegDisp(GPR base, Offset disp) {
18258 int miStart = mi;
18259 // no group 1 to 4 prefix byte
18260 generateREXprefix(false, null, null, base);
18261 setMachineCodes(mi++, (byte) 0xFF);
18262 // "register 0x0" is really part of the opcode
18263 emitRegDispRegOperands(base, disp, GPR.getForOpcode(0x0));
18264 if (lister != null) lister.RD(miStart, "INC", base, disp);
18265 }
18266
18267 /**
18268 * Generate a INC to register indirect. That is,
18269 * <PRE>
18270 * ++ [reg]
18271 * </PRE>
18272 *
18273 * @param base the destination base register
18274 */
18275 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18276 public final void emitINC_RegInd(GPR base) {
18277 int miStart = mi;
18278 // no group 1 to 4 prefix byte
18279 generateREXprefix(false, null, null, base);
18280 setMachineCodes(mi++, (byte) 0xFF);
18281 // "register 0x0" is really part of the opcode
18282 emitRegIndirectRegOperands(base, GPR.getForOpcode(0x0));
18283 if (lister != null) lister.RN(miStart, "INC", base);
18284 }
18285
18286 /**
18287 * Generate a INC to register offset. That is,
18288 * <PRE>
18289 * ++ [index<<scale + disp]
18290 * </PRE>
18291 *
18292 * @param index the destination index register
18293 * @param scale the destination shift amount
18294 * @param disp the destination displacement
18295 */
18296 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18297 public final void emitINC_RegOff(GPR index, short scale, Offset disp) {
18298 int miStart = mi;
18299 // no group 1 to 4 prefix byte
18300 generateREXprefix(false, null, index, null);
18301 setMachineCodes(mi++, (byte) 0xFF);
18302 // "register 0x0" is really part of the opcode
18303 emitRegOffRegOperands(index, scale, disp, GPR.getForOpcode(0x0));
18304 if (lister != null) lister.RFD(miStart, "INC", index, scale, disp);
18305 }
18306
18307 /**
18308 * Generate a INC to absolute address. That is,
18309 * <PRE>
18310 * ++ [disp]
18311 * </PRE>
18312 *
18313 * @param disp the destination displacement
18314 */
18315 public final void emitINC_Abs(Address disp) {
18316 int miStart = mi;
18317 // no group 1 to 4 prefix byte
18318 generateREXprefix(false, null, null, null);
18319 setMachineCodes(mi++, (byte) 0xFF);
18320 // "register 0x0" is really part of the opcode
18321 emitAbsRegOperands(disp, GPR.getForOpcode(0x0));
18322 if (lister != null) lister.RA(miStart, "INC", disp);
18323 }
18324
18325 /**
18326 * Generate a INC to register offset. That is,
18327 * <PRE>
18328 * ++ [base + index<<scale + disp]
18329 * </PRE>
18330 *
18331 * @param base the destination base register
18332 * @param index the destination index register
18333 * @param scale the destination shift amount
18334 * @param disp the destination displacement
18335 */
18336 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
18337 public final void emitINC_RegIdx(GPR base, GPR index, short scale, Offset disp) {
18338 int miStart = mi;
18339 // no group 1 to 4 prefix byte
18340 generateREXprefix(false, null, index, base);
18341 setMachineCodes(mi++, (byte) 0xFF);
18342 // "register 0x0" is really part of the opcode
18343 emitSIBRegOperands(base, index, scale, disp, GPR.getForOpcode(0x0));
18344 if (lister != null) lister.RXD(miStart, "INC", base, index, scale, disp);
18345 }
18346
18347 /**
18348 * Generate a INC on a register. That is,
18349 * <PRE>
18350 * ++ (byte) reg
18351 * </PRE>
18352 *
18353 * @param reg register to operate upon
18354 */
18355 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18356 public final void emitINC_Reg_Byte(GPR reg) {
18357 int miStart = mi;
18358 // no group 1 to 4 prefix byte
18359 generateREXprefix(false, null, null, reg);
18360 setMachineCodes(mi++, (byte) 0xFE);
18361 emitRegRegOperands(reg, GPR.getForOpcode(0x0));
18362 if (lister != null) lister.R(miStart, "INC", reg);
18363 }
18364 /**
18365 * Generate a INC to register-displacement offset. That is,
18366 * <PRE>
18367 * ++ (byte) [base + disp]
18368 * </PRE>
18369 *
18370 * @param base the destination base register
18371 * @param disp the destination displacement
18372 */
18373 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18374 public final void emitINC_RegDisp_Byte(GPR base, Offset disp) {
18375 int miStart = mi;
18376 // no group 1 to 4 prefix byte
18377 generateREXprefix(false, null, null, base);
18378 setMachineCodes(mi++, (byte) 0xFE);
18379 // "register 0x0" is really part of the opcode
18380 emitRegDispRegOperands(base, disp, GPR.getForOpcode(0x0));
18381 if (lister != null) lister.RD(miStart, "INC", base, disp);
18382 }
18383
18384 /**
18385 * Generate a INC to register indirect. That is,
18386 * <PRE>
18387 * ++ (byte) [reg]
18388 * </PRE>
18389 *
18390 * @param base the destination base register
18391 */
18392 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18393 public final void emitINC_RegInd_Byte(GPR base) {
18394 int miStart = mi;
18395 // no group 1 to 4 prefix byte
18396 generateREXprefix(false, null, null, base);
18397 setMachineCodes(mi++, (byte) 0xFE);
18398 // "register 0x0" is really part of the opcode
18399 emitRegIndirectRegOperands(base, GPR.getForOpcode(0x0));
18400 if (lister != null) lister.RN(miStart, "INC", base);
18401 }
18402
18403 /**
18404 * Generate a INC to register offset. That is,
18405 * <PRE>
18406 * ++ (byte) [index<<scale + disp]
18407 * </PRE>
18408 *
18409 * @param index the destination index register
18410 * @param scale the destination shift amount
18411 * @param disp the destination displacement
18412 */
18413 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18414 public final void emitINC_RegOff_Byte(GPR index, short scale, Offset disp) {
18415 int miStart = mi;
18416 // no group 1 to 4 prefix byte
18417 generateREXprefix(false, null, index, null);
18418 setMachineCodes(mi++, (byte) 0xFE);
18419 // "register 0x0" is really part of the opcode
18420 emitRegOffRegOperands(index, scale, disp, GPR.getForOpcode(0x0));
18421 if (lister != null) lister.RFD(miStart, "INC", index, scale, disp);
18422 }
18423
18424 /**
18425 * Generate a INC to absolute address. That is,
18426 * <PRE>
18427 * ++ (byte) [disp]
18428 * </PRE>
18429 *
18430 * @param disp the destination displacement
18431 */
18432 public final void emitINC_Abs_Byte(Address disp) {
18433 int miStart = mi;
18434 // no group 1 to 4 prefix byte
18435 generateREXprefix(false, null, null, null);
18436 setMachineCodes(mi++, (byte) 0xFE);
18437 // "register 0x0" is really part of the opcode
18438 emitAbsRegOperands(disp, GPR.getForOpcode(0x0));
18439 if (lister != null) lister.RA(miStart, "INC", disp);
18440 }
18441
18442 /**
18443 * Generate a INC to register offset. That is,
18444 * <PRE>
18445 * ++ (byte) [base + index<<scale + disp]
18446 * </PRE>
18447 *
18448 * @param base the destination base register
18449 * @param index the destination index register
18450 * @param scale the destination shift amount
18451 * @param disp the destination displacement
18452 */
18453 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
18454 public final void emitINC_RegIdx_Byte(GPR base, GPR index, short scale, Offset disp) {
18455 int miStart = mi;
18456 // no group 1 to 4 prefix byte
18457 generateREXprefix(false, null, index, base);
18458 setMachineCodes(mi++, (byte) 0xFE);
18459 // "register 0x0" is really part of the opcode
18460 emitSIBRegOperands(base, index, scale, disp, GPR.getForOpcode(0x0));
18461 if (lister != null) lister.RXD(miStart, "INC", base, index, scale, disp);
18462 }
18463
18464 /**
18465 * Generate a INC on a register. That is,
18466 * <PRE>
18467 * ++ (word) reg
18468 * </PRE>
18469 *
18470 * @param reg register to operate upon
18471 */
18472 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18473 public void emitINC_Reg_Word(GPR reg) {
18474 int miStart = mi;
18475 setMachineCodes(mi++, (byte) 0x66);
18476 generateREXprefix(false, null, null, reg);
18477 if (!VM.buildFor32Addr()) {
18478 setMachineCodes(mi++, (byte) (0xFF));
18479 emitRegRegOperands(reg, GPR.getForOpcode(0x0));
18480 } else {
18481 setMachineCodes(mi++, (byte) (0x40 | (reg.value() & 7)));
18482 }
18483 if (lister != null) lister.R(miStart, "INC", reg);
18484 }
18485 /**
18486 * Generate a INC to register-displacement offset. That is,
18487 * <PRE>
18488 * ++ (word) [base + disp]
18489 * </PRE>
18490 *
18491 * @param base the destination base register
18492 * @param disp the destination displacement
18493 */
18494 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18495 public final void emitINC_RegDisp_Word(GPR base, Offset disp) {
18496 int miStart = mi;
18497 setMachineCodes(mi++, (byte) 0x66);
18498 generateREXprefix(false, null, null, base);
18499 setMachineCodes(mi++, (byte) 0xFF);
18500 // "register 0x0" is really part of the opcode
18501 emitRegDispRegOperands(base, disp, GPR.getForOpcode(0x0));
18502 if (lister != null) lister.RD(miStart, "INC", base, disp);
18503 }
18504
18505 /**
18506 * Generate a INC to register indirect. That is,
18507 * <PRE>
18508 * ++ (word) [reg]
18509 * </PRE>
18510 *
18511 * @param base the destination base register
18512 */
18513 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18514 public final void emitINC_RegInd_Word(GPR base) {
18515 int miStart = mi;
18516 setMachineCodes(mi++, (byte) 0x66);
18517 generateREXprefix(false, null, null, base);
18518 setMachineCodes(mi++, (byte) 0xFF);
18519 // "register 0x0" is really part of the opcode
18520 emitRegIndirectRegOperands(base, GPR.getForOpcode(0x0));
18521 if (lister != null) lister.RN(miStart, "INC", base);
18522 }
18523
18524 /**
18525 * Generate a INC to register offset. That is,
18526 * <PRE>
18527 * ++ (word) [index<<scale + disp]
18528 * </PRE>
18529 *
18530 * @param index the destination index register
18531 * @param scale the destination shift amount
18532 * @param disp the destination displacement
18533 */
18534 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18535 public final void emitINC_RegOff_Word(GPR index, short scale, Offset disp) {
18536 int miStart = mi;
18537 setMachineCodes(mi++, (byte) 0x66);
18538 generateREXprefix(false, null, index, null);
18539 setMachineCodes(mi++, (byte) 0xFF);
18540 // "register 0x0" is really part of the opcode
18541 emitRegOffRegOperands(index, scale, disp, GPR.getForOpcode(0x0));
18542 if (lister != null) lister.RFD(miStart, "INC", index, scale, disp);
18543 }
18544
18545 /**
18546 * Generate a INC to absolute address. That is,
18547 * <PRE>
18548 * ++ (word) [disp]
18549 * </PRE>
18550 *
18551 * @param disp the destination displacement
18552 */
18553 public final void emitINC_Abs_Word(Address disp) {
18554 int miStart = mi;
18555 setMachineCodes(mi++, (byte) 0x66);
18556 generateREXprefix(false, null, null, null);
18557 setMachineCodes(mi++, (byte) 0xFF);
18558 // "register 0x0" is really part of the opcode
18559 emitAbsRegOperands(disp, GPR.getForOpcode(0x0));
18560 if (lister != null) lister.RA(miStart, "INC", disp);
18561 }
18562
18563 /**
18564 * Generate a INC to register offset. That is,
18565 * <PRE>
18566 * ++ (word) [base + index<<scale + disp]
18567 * </PRE>
18568 *
18569 * @param base the destination base register
18570 * @param index the destination index register
18571 * @param scale the destination shift amount
18572 * @param disp the destination displacement
18573 */
18574 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
18575 public final void emitINC_RegIdx_Word(GPR base, GPR index, short scale, Offset disp) {
18576 int miStart = mi;
18577 setMachineCodes(mi++, (byte) 0x66);
18578 generateREXprefix(false, null, index, base);
18579 setMachineCodes(mi++, (byte) 0xFF);
18580 // "register 0x0" is really part of the opcode
18581 emitSIBRegOperands(base, index, scale, disp, GPR.getForOpcode(0x0));
18582 if (lister != null) lister.RXD(miStart, "INC", base, index, scale, disp);
18583 }
18584
18585 /**
18586 * Generate a INC on a register. That is,
18587 * <PRE>
18588 * ++ (quad) reg
18589 * </PRE>
18590 *
18591 * @param reg register to operate upon
18592 */
18593 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18594 public void emitINC_Reg_Quad(GPR reg) {
18595 int miStart = mi;
18596 // no group 1 to 4 prefix byte
18597 generateREXprefix(true, null, null, reg);
18598 if (!VM.buildFor32Addr()) {
18599 setMachineCodes(mi++, (byte) (0xFF));
18600 emitRegRegOperands(reg, GPR.getForOpcode(0x0));
18601 } else {
18602 setMachineCodes(mi++, (byte) (0x40 | (reg.value() & 7)));
18603 }
18604 if (lister != null) lister.R(miStart, "INC", reg);
18605 }
18606 /**
18607 * Generate a INC to register-displacement offset. That is,
18608 * <PRE>
18609 * ++ (quad) [base + disp]
18610 * </PRE>
18611 *
18612 * @param base the destination base register
18613 * @param disp the destination displacement
18614 */
18615 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18616 public final void emitINC_RegDisp_Quad(GPR base, Offset disp) {
18617 int miStart = mi;
18618 // no group 1 to 4 prefix byte
18619 generateREXprefix(true, null, null, base);
18620 setMachineCodes(mi++, (byte) 0xFF);
18621 // "register 0x0" is really part of the opcode
18622 emitRegDispRegOperands(base, disp, GPR.getForOpcode(0x0));
18623 if (lister != null) lister.RD(miStart, "INC", base, disp);
18624 }
18625
18626 /**
18627 * Generate a INC to register indirect. That is,
18628 * <PRE>
18629 * ++ (quad) [reg]
18630 * </PRE>
18631 *
18632 * @param base the destination base register
18633 */
18634 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18635 public final void emitINC_RegInd_Quad(GPR base) {
18636 int miStart = mi;
18637 // no group 1 to 4 prefix byte
18638 generateREXprefix(true, null, null, base);
18639 setMachineCodes(mi++, (byte) 0xFF);
18640 // "register 0x0" is really part of the opcode
18641 emitRegIndirectRegOperands(base, GPR.getForOpcode(0x0));
18642 if (lister != null) lister.RN(miStart, "INC", base);
18643 }
18644
18645 /**
18646 * Generate a INC to register offset. That is,
18647 * <PRE>
18648 * ++ (quad) [index<<scale + disp]
18649 * </PRE>
18650 *
18651 * @param index the destination index register
18652 * @param scale the destination shift amount
18653 * @param disp the destination displacement
18654 */
18655 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18656 public final void emitINC_RegOff_Quad(GPR index, short scale, Offset disp) {
18657 int miStart = mi;
18658 // no group 1 to 4 prefix byte
18659 generateREXprefix(true, null, index, null);
18660 setMachineCodes(mi++, (byte) 0xFF);
18661 // "register 0x0" is really part of the opcode
18662 emitRegOffRegOperands(index, scale, disp, GPR.getForOpcode(0x0));
18663 if (lister != null) lister.RFD(miStart, "INC", index, scale, disp);
18664 }
18665
18666 /**
18667 * Generate a INC to absolute address. That is,
18668 * <PRE>
18669 * ++ (quad) [disp]
18670 * </PRE>
18671 *
18672 * @param disp the destination displacement
18673 */
18674 public final void emitINC_Abs_Quad(Address disp) {
18675 int miStart = mi;
18676 // no group 1 to 4 prefix byte
18677 generateREXprefix(true, null, null, null);
18678 setMachineCodes(mi++, (byte) 0xFF);
18679 // "register 0x0" is really part of the opcode
18680 emitAbsRegOperands(disp, GPR.getForOpcode(0x0));
18681 if (lister != null) lister.RA(miStart, "INC", disp);
18682 }
18683
18684 /**
18685 * Generate a INC to register offset. That is,
18686 * <PRE>
18687 * ++ (quad) [base + index<<scale + disp]
18688 * </PRE>
18689 *
18690 * @param base the destination base register
18691 * @param index the destination index register
18692 * @param scale the destination shift amount
18693 * @param disp the destination displacement
18694 */
18695 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
18696 public final void emitINC_RegIdx_Quad(GPR base, GPR index, short scale, Offset disp) {
18697 int miStart = mi;
18698 // no group 1 to 4 prefix byte
18699 generateREXprefix(true, null, index, base);
18700 setMachineCodes(mi++, (byte) 0xFF);
18701 // "register 0x0" is really part of the opcode
18702 emitSIBRegOperands(base, index, scale, disp, GPR.getForOpcode(0x0));
18703 if (lister != null) lister.RXD(miStart, "INC", base, index, scale, disp);
18704 }
18705
18706 /**
18707 * Generate a NEG on a register. That is,
18708 * <PRE>
18709 * - reg
18710 * </PRE>
18711 *
18712 * @param reg register to operate upon
18713 */
18714 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18715 public final void emitNEG_Reg(GPR reg) {
18716 int miStart = mi;
18717 // no group 1 to 4 prefix byte
18718 generateREXprefix(false, null, null, reg);
18719 setMachineCodes(mi++, (byte) 0xF7);
18720 emitRegRegOperands(reg, GPR.getForOpcode(0x3));
18721 if (lister != null) lister.R(miStart, "NEG", reg);
18722 }
18723 /**
18724 * Generate a NEG to register-displacement offset. That is,
18725 * <PRE>
18726 * - [base + disp]
18727 * </PRE>
18728 *
18729 * @param base the destination base register
18730 * @param disp the destination displacement
18731 */
18732 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18733 public final void emitNEG_RegDisp(GPR base, Offset disp) {
18734 int miStart = mi;
18735 // no group 1 to 4 prefix byte
18736 generateREXprefix(false, null, null, base);
18737 setMachineCodes(mi++, (byte) 0xF7);
18738 // "register 0x3" is really part of the opcode
18739 emitRegDispRegOperands(base, disp, GPR.getForOpcode(0x3));
18740 if (lister != null) lister.RD(miStart, "NEG", base, disp);
18741 }
18742
18743 /**
18744 * Generate a NEG to register indirect. That is,
18745 * <PRE>
18746 * - [reg]
18747 * </PRE>
18748 *
18749 * @param base the destination base register
18750 */
18751 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18752 public final void emitNEG_RegInd(GPR base) {
18753 int miStart = mi;
18754 // no group 1 to 4 prefix byte
18755 generateREXprefix(false, null, null, base);
18756 setMachineCodes(mi++, (byte) 0xF7);
18757 // "register 0x3" is really part of the opcode
18758 emitRegIndirectRegOperands(base, GPR.getForOpcode(0x3));
18759 if (lister != null) lister.RN(miStart, "NEG", base);
18760 }
18761
18762 /**
18763 * Generate a NEG to register offset. That is,
18764 * <PRE>
18765 * - [index<<scale + disp]
18766 * </PRE>
18767 *
18768 * @param index the destination index register
18769 * @param scale the destination shift amount
18770 * @param disp the destination displacement
18771 */
18772 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18773 public final void emitNEG_RegOff(GPR index, short scale, Offset disp) {
18774 int miStart = mi;
18775 // no group 1 to 4 prefix byte
18776 generateREXprefix(false, null, index, null);
18777 setMachineCodes(mi++, (byte) 0xF7);
18778 // "register 0x3" is really part of the opcode
18779 emitRegOffRegOperands(index, scale, disp, GPR.getForOpcode(0x3));
18780 if (lister != null) lister.RFD(miStart, "NEG", index, scale, disp);
18781 }
18782
18783 /**
18784 * Generate a NEG to absolute address. That is,
18785 * <PRE>
18786 * - [disp]
18787 * </PRE>
18788 *
18789 * @param disp the destination displacement
18790 */
18791 public final void emitNEG_Abs(Address disp) {
18792 int miStart = mi;
18793 // no group 1 to 4 prefix byte
18794 generateREXprefix(false, null, null, null);
18795 setMachineCodes(mi++, (byte) 0xF7);
18796 // "register 0x3" is really part of the opcode
18797 emitAbsRegOperands(disp, GPR.getForOpcode(0x3));
18798 if (lister != null) lister.RA(miStart, "NEG", disp);
18799 }
18800
18801 /**
18802 * Generate a NEG to register offset. That is,
18803 * <PRE>
18804 * - [base + index<<scale + disp]
18805 * </PRE>
18806 *
18807 * @param base the destination base register
18808 * @param index the destination index register
18809 * @param scale the destination shift amount
18810 * @param disp the destination displacement
18811 */
18812 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
18813 public final void emitNEG_RegIdx(GPR base, GPR index, short scale, Offset disp) {
18814 int miStart = mi;
18815 // no group 1 to 4 prefix byte
18816 generateREXprefix(false, null, index, base);
18817 setMachineCodes(mi++, (byte) 0xF7);
18818 // "register 0x3" is really part of the opcode
18819 emitSIBRegOperands(base, index, scale, disp, GPR.getForOpcode(0x3));
18820 if (lister != null) lister.RXD(miStart, "NEG", base, index, scale, disp);
18821 }
18822
18823 /**
18824 * Generate a NEG on a register. That is,
18825 * <PRE>
18826 * - (byte) reg
18827 * </PRE>
18828 *
18829 * @param reg register to operate upon
18830 */
18831 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18832 public final void emitNEG_Reg_Byte(GPR reg) {
18833 int miStart = mi;
18834 // no group 1 to 4 prefix byte
18835 generateREXprefix(false, null, null, reg);
18836 setMachineCodes(mi++, (byte) 0xF6);
18837 emitRegRegOperands(reg, GPR.getForOpcode(0x3));
18838 if (lister != null) lister.R(miStart, "NEG", reg);
18839 }
18840 /**
18841 * Generate a NEG to register-displacement offset. That is,
18842 * <PRE>
18843 * - (byte) [base + disp]
18844 * </PRE>
18845 *
18846 * @param base the destination base register
18847 * @param disp the destination displacement
18848 */
18849 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18850 public final void emitNEG_RegDisp_Byte(GPR base, Offset disp) {
18851 int miStart = mi;
18852 // no group 1 to 4 prefix byte
18853 generateREXprefix(false, null, null, base);
18854 setMachineCodes(mi++, (byte) 0xF6);
18855 // "register 0x3" is really part of the opcode
18856 emitRegDispRegOperands(base, disp, GPR.getForOpcode(0x3));
18857 if (lister != null) lister.RD(miStart, "NEG", base, disp);
18858 }
18859
18860 /**
18861 * Generate a NEG to register indirect. That is,
18862 * <PRE>
18863 * - (byte) [reg]
18864 * </PRE>
18865 *
18866 * @param base the destination base register
18867 */
18868 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18869 public final void emitNEG_RegInd_Byte(GPR base) {
18870 int miStart = mi;
18871 // no group 1 to 4 prefix byte
18872 generateREXprefix(false, null, null, base);
18873 setMachineCodes(mi++, (byte) 0xF6);
18874 // "register 0x3" is really part of the opcode
18875 emitRegIndirectRegOperands(base, GPR.getForOpcode(0x3));
18876 if (lister != null) lister.RN(miStart, "NEG", base);
18877 }
18878
18879 /**
18880 * Generate a NEG to register offset. That is,
18881 * <PRE>
18882 * - (byte) [index<<scale + disp]
18883 * </PRE>
18884 *
18885 * @param index the destination index register
18886 * @param scale the destination shift amount
18887 * @param disp the destination displacement
18888 */
18889 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18890 public final void emitNEG_RegOff_Byte(GPR index, short scale, Offset disp) {
18891 int miStart = mi;
18892 // no group 1 to 4 prefix byte
18893 generateREXprefix(false, null, index, null);
18894 setMachineCodes(mi++, (byte) 0xF6);
18895 // "register 0x3" is really part of the opcode
18896 emitRegOffRegOperands(index, scale, disp, GPR.getForOpcode(0x3));
18897 if (lister != null) lister.RFD(miStart, "NEG", index, scale, disp);
18898 }
18899
18900 /**
18901 * Generate a NEG to absolute address. That is,
18902 * <PRE>
18903 * - (byte) [disp]
18904 * </PRE>
18905 *
18906 * @param disp the destination displacement
18907 */
18908 public final void emitNEG_Abs_Byte(Address disp) {
18909 int miStart = mi;
18910 // no group 1 to 4 prefix byte
18911 generateREXprefix(false, null, null, null);
18912 setMachineCodes(mi++, (byte) 0xF6);
18913 // "register 0x3" is really part of the opcode
18914 emitAbsRegOperands(disp, GPR.getForOpcode(0x3));
18915 if (lister != null) lister.RA(miStart, "NEG", disp);
18916 }
18917
18918 /**
18919 * Generate a NEG to register offset. That is,
18920 * <PRE>
18921 * - (byte) [base + index<<scale + disp]
18922 * </PRE>
18923 *
18924 * @param base the destination base register
18925 * @param index the destination index register
18926 * @param scale the destination shift amount
18927 * @param disp the destination displacement
18928 */
18929 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
18930 public final void emitNEG_RegIdx_Byte(GPR base, GPR index, short scale, Offset disp) {
18931 int miStart = mi;
18932 // no group 1 to 4 prefix byte
18933 generateREXprefix(false, null, index, base);
18934 setMachineCodes(mi++, (byte) 0xF6);
18935 // "register 0x3" is really part of the opcode
18936 emitSIBRegOperands(base, index, scale, disp, GPR.getForOpcode(0x3));
18937 if (lister != null) lister.RXD(miStart, "NEG", base, index, scale, disp);
18938 }
18939
18940 /**
18941 * Generate a NEG on a register. That is,
18942 * <PRE>
18943 * - (word) reg
18944 * </PRE>
18945 *
18946 * @param reg register to operate upon
18947 */
18948 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18949 public final void emitNEG_Reg_Word(GPR reg) {
18950 int miStart = mi;
18951 setMachineCodes(mi++, (byte) 0x66);
18952 generateREXprefix(false, null, null, reg);
18953 setMachineCodes(mi++, (byte) 0xF7);
18954 emitRegRegOperands(reg, GPR.getForOpcode(0x3));
18955 if (lister != null) lister.R(miStart, "NEG", reg);
18956 }
18957 /**
18958 * Generate a NEG to register-displacement offset. That is,
18959 * <PRE>
18960 * - (word) [base + disp]
18961 * </PRE>
18962 *
18963 * @param base the destination base register
18964 * @param disp the destination displacement
18965 */
18966 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18967 public final void emitNEG_RegDisp_Word(GPR base, Offset disp) {
18968 int miStart = mi;
18969 setMachineCodes(mi++, (byte) 0x66);
18970 generateREXprefix(false, null, null, base);
18971 setMachineCodes(mi++, (byte) 0xF7);
18972 // "register 0x3" is really part of the opcode
18973 emitRegDispRegOperands(base, disp, GPR.getForOpcode(0x3));
18974 if (lister != null) lister.RD(miStart, "NEG", base, disp);
18975 }
18976
18977 /**
18978 * Generate a NEG to register indirect. That is,
18979 * <PRE>
18980 * - (word) [reg]
18981 * </PRE>
18982 *
18983 * @param base the destination base register
18984 */
18985 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
18986 public final void emitNEG_RegInd_Word(GPR base) {
18987 int miStart = mi;
18988 setMachineCodes(mi++, (byte) 0x66);
18989 generateREXprefix(false, null, null, base);
18990 setMachineCodes(mi++, (byte) 0xF7);
18991 // "register 0x3" is really part of the opcode
18992 emitRegIndirectRegOperands(base, GPR.getForOpcode(0x3));
18993 if (lister != null) lister.RN(miStart, "NEG", base);
18994 }
18995
18996 /**
18997 * Generate a NEG to register offset. That is,
18998 * <PRE>
18999 * - (word) [index<<scale + disp]
19000 * </PRE>
19001 *
19002 * @param index the destination index register
19003 * @param scale the destination shift amount
19004 * @param disp the destination displacement
19005 */
19006 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19007 public final void emitNEG_RegOff_Word(GPR index, short scale, Offset disp) {
19008 int miStart = mi;
19009 setMachineCodes(mi++, (byte) 0x66);
19010 generateREXprefix(false, null, index, null);
19011 setMachineCodes(mi++, (byte) 0xF7);
19012 // "register 0x3" is really part of the opcode
19013 emitRegOffRegOperands(index, scale, disp, GPR.getForOpcode(0x3));
19014 if (lister != null) lister.RFD(miStart, "NEG", index, scale, disp);
19015 }
19016
19017 /**
19018 * Generate a NEG to absolute address. That is,
19019 * <PRE>
19020 * - (word) [disp]
19021 * </PRE>
19022 *
19023 * @param disp the destination displacement
19024 */
19025 public final void emitNEG_Abs_Word(Address disp) {
19026 int miStart = mi;
19027 setMachineCodes(mi++, (byte) 0x66);
19028 generateREXprefix(false, null, null, null);
19029 setMachineCodes(mi++, (byte) 0xF7);
19030 // "register 0x3" is really part of the opcode
19031 emitAbsRegOperands(disp, GPR.getForOpcode(0x3));
19032 if (lister != null) lister.RA(miStart, "NEG", disp);
19033 }
19034
19035 /**
19036 * Generate a NEG to register offset. That is,
19037 * <PRE>
19038 * - (word) [base + index<<scale + disp]
19039 * </PRE>
19040 *
19041 * @param base the destination base register
19042 * @param index the destination index register
19043 * @param scale the destination shift amount
19044 * @param disp the destination displacement
19045 */
19046 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
19047 public final void emitNEG_RegIdx_Word(GPR base, GPR index, short scale, Offset disp) {
19048 int miStart = mi;
19049 setMachineCodes(mi++, (byte) 0x66);
19050 generateREXprefix(false, null, index, base);
19051 setMachineCodes(mi++, (byte) 0xF7);
19052 // "register 0x3" is really part of the opcode
19053 emitSIBRegOperands(base, index, scale, disp, GPR.getForOpcode(0x3));
19054 if (lister != null) lister.RXD(miStart, "NEG", base, index, scale, disp);
19055 }
19056
19057 /**
19058 * Generate a NEG on a register. That is,
19059 * <PRE>
19060 * - (quad) reg
19061 * </PRE>
19062 *
19063 * @param reg register to operate upon
19064 */
19065 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19066 public final void emitNEG_Reg_Quad(GPR reg) {
19067 int miStart = mi;
19068 // no group 1 to 4 prefix byte
19069 generateREXprefix(true, null, null, reg);
19070 setMachineCodes(mi++, (byte) 0xF7);
19071 emitRegRegOperands(reg, GPR.getForOpcode(0x3));
19072 if (lister != null) lister.R(miStart, "NEG", reg);
19073 }
19074 /**
19075 * Generate a NEG to register-displacement offset. That is,
19076 * <PRE>
19077 * - (quad) [base + disp]
19078 * </PRE>
19079 *
19080 * @param base the destination base register
19081 * @param disp the destination displacement
19082 */
19083 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19084 public final void emitNEG_RegDisp_Quad(GPR base, Offset disp) {
19085 int miStart = mi;
19086 // no group 1 to 4 prefix byte
19087 generateREXprefix(true, null, null, base);
19088 setMachineCodes(mi++, (byte) 0xF7);
19089 // "register 0x3" is really part of the opcode
19090 emitRegDispRegOperands(base, disp, GPR.getForOpcode(0x3));
19091 if (lister != null) lister.RD(miStart, "NEG", base, disp);
19092 }
19093
19094 /**
19095 * Generate a NEG to register indirect. That is,
19096 * <PRE>
19097 * - (quad) [reg]
19098 * </PRE>
19099 *
19100 * @param base the destination base register
19101 */
19102 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19103 public final void emitNEG_RegInd_Quad(GPR base) {
19104 int miStart = mi;
19105 // no group 1 to 4 prefix byte
19106 generateREXprefix(true, null, null, base);
19107 setMachineCodes(mi++, (byte) 0xF7);
19108 // "register 0x3" is really part of the opcode
19109 emitRegIndirectRegOperands(base, GPR.getForOpcode(0x3));
19110 if (lister != null) lister.RN(miStart, "NEG", base);
19111 }
19112
19113 /**
19114 * Generate a NEG to register offset. That is,
19115 * <PRE>
19116 * - (quad) [index<<scale + disp]
19117 * </PRE>
19118 *
19119 * @param index the destination index register
19120 * @param scale the destination shift amount
19121 * @param disp the destination displacement
19122 */
19123 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19124 public final void emitNEG_RegOff_Quad(GPR index, short scale, Offset disp) {
19125 int miStart = mi;
19126 // no group 1 to 4 prefix byte
19127 generateREXprefix(true, null, index, null);
19128 setMachineCodes(mi++, (byte) 0xF7);
19129 // "register 0x3" is really part of the opcode
19130 emitRegOffRegOperands(index, scale, disp, GPR.getForOpcode(0x3));
19131 if (lister != null) lister.RFD(miStart, "NEG", index, scale, disp);
19132 }
19133
19134 /**
19135 * Generate a NEG to absolute address. That is,
19136 * <PRE>
19137 * - (quad) [disp]
19138 * </PRE>
19139 *
19140 * @param disp the destination displacement
19141 */
19142 public final void emitNEG_Abs_Quad(Address disp) {
19143 int miStart = mi;
19144 // no group 1 to 4 prefix byte
19145 generateREXprefix(true, null, null, null);
19146 setMachineCodes(mi++, (byte) 0xF7);
19147 // "register 0x3" is really part of the opcode
19148 emitAbsRegOperands(disp, GPR.getForOpcode(0x3));
19149 if (lister != null) lister.RA(miStart, "NEG", disp);
19150 }
19151
19152 /**
19153 * Generate a NEG to register offset. That is,
19154 * <PRE>
19155 * - (quad) [base + index<<scale + disp]
19156 * </PRE>
19157 *
19158 * @param base the destination base register
19159 * @param index the destination index register
19160 * @param scale the destination shift amount
19161 * @param disp the destination displacement
19162 */
19163 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
19164 public final void emitNEG_RegIdx_Quad(GPR base, GPR index, short scale, Offset disp) {
19165 int miStart = mi;
19166 // no group 1 to 4 prefix byte
19167 generateREXprefix(true, null, index, base);
19168 setMachineCodes(mi++, (byte) 0xF7);
19169 // "register 0x3" is really part of the opcode
19170 emitSIBRegOperands(base, index, scale, disp, GPR.getForOpcode(0x3));
19171 if (lister != null) lister.RXD(miStart, "NEG", base, index, scale, disp);
19172 }
19173
19174 /**
19175 * Generate a NOT on a register. That is,
19176 * <PRE>
19177 * ~ reg
19178 * </PRE>
19179 *
19180 * @param reg register to operate upon
19181 */
19182 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19183 public final void emitNOT_Reg(GPR reg) {
19184 int miStart = mi;
19185 // no group 1 to 4 prefix byte
19186 generateREXprefix(false, null, null, reg);
19187 setMachineCodes(mi++, (byte) 0xF7);
19188 emitRegRegOperands(reg, GPR.getForOpcode(0x2));
19189 if (lister != null) lister.R(miStart, "NOT", reg);
19190 }
19191 /**
19192 * Generate a NOT to register-displacement offset. That is,
19193 * <PRE>
19194 * ~ [base + disp]
19195 * </PRE>
19196 *
19197 * @param base the destination base register
19198 * @param disp the destination displacement
19199 */
19200 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19201 public final void emitNOT_RegDisp(GPR base, Offset disp) {
19202 int miStart = mi;
19203 // no group 1 to 4 prefix byte
19204 generateREXprefix(false, null, null, base);
19205 setMachineCodes(mi++, (byte) 0xF7);
19206 // "register 0x2" is really part of the opcode
19207 emitRegDispRegOperands(base, disp, GPR.getForOpcode(0x2));
19208 if (lister != null) lister.RD(miStart, "NOT", base, disp);
19209 }
19210
19211 /**
19212 * Generate a NOT to register indirect. That is,
19213 * <PRE>
19214 * ~ [reg]
19215 * </PRE>
19216 *
19217 * @param base the destination base register
19218 */
19219 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19220 public final void emitNOT_RegInd(GPR base) {
19221 int miStart = mi;
19222 // no group 1 to 4 prefix byte
19223 generateREXprefix(false, null, null, base);
19224 setMachineCodes(mi++, (byte) 0xF7);
19225 // "register 0x2" is really part of the opcode
19226 emitRegIndirectRegOperands(base, GPR.getForOpcode(0x2));
19227 if (lister != null) lister.RN(miStart, "NOT", base);
19228 }
19229
19230 /**
19231 * Generate a NOT to register offset. That is,
19232 * <PRE>
19233 * ~ [index<<scale + disp]
19234 * </PRE>
19235 *
19236 * @param index the destination index register
19237 * @param scale the destination shift amount
19238 * @param disp the destination displacement
19239 */
19240 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19241 public final void emitNOT_RegOff(GPR index, short scale, Offset disp) {
19242 int miStart = mi;
19243 // no group 1 to 4 prefix byte
19244 generateREXprefix(false, null, index, null);
19245 setMachineCodes(mi++, (byte) 0xF7);
19246 // "register 0x2" is really part of the opcode
19247 emitRegOffRegOperands(index, scale, disp, GPR.getForOpcode(0x2));
19248 if (lister != null) lister.RFD(miStart, "NOT", index, scale, disp);
19249 }
19250
19251 /**
19252 * Generate a NOT to absolute address. That is,
19253 * <PRE>
19254 * ~ [disp]
19255 * </PRE>
19256 *
19257 * @param disp the destination displacement
19258 */
19259 public final void emitNOT_Abs(Address disp) {
19260 int miStart = mi;
19261 // no group 1 to 4 prefix byte
19262 generateREXprefix(false, null, null, null);
19263 setMachineCodes(mi++, (byte) 0xF7);
19264 // "register 0x2" is really part of the opcode
19265 emitAbsRegOperands(disp, GPR.getForOpcode(0x2));
19266 if (lister != null) lister.RA(miStart, "NOT", disp);
19267 }
19268
19269 /**
19270 * Generate a NOT to register offset. That is,
19271 * <PRE>
19272 * ~ [base + index<<scale + disp]
19273 * </PRE>
19274 *
19275 * @param base the destination base register
19276 * @param index the destination index register
19277 * @param scale the destination shift amount
19278 * @param disp the destination displacement
19279 */
19280 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
19281 public final void emitNOT_RegIdx(GPR base, GPR index, short scale, Offset disp) {
19282 int miStart = mi;
19283 // no group 1 to 4 prefix byte
19284 generateREXprefix(false, null, index, base);
19285 setMachineCodes(mi++, (byte) 0xF7);
19286 // "register 0x2" is really part of the opcode
19287 emitSIBRegOperands(base, index, scale, disp, GPR.getForOpcode(0x2));
19288 if (lister != null) lister.RXD(miStart, "NOT", base, index, scale, disp);
19289 }
19290
19291 /**
19292 * Generate a NOT on a register. That is,
19293 * <PRE>
19294 * ~ (byte) reg
19295 * </PRE>
19296 *
19297 * @param reg register to operate upon
19298 */
19299 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19300 public final void emitNOT_Reg_Byte(GPR reg) {
19301 int miStart = mi;
19302 // no group 1 to 4 prefix byte
19303 generateREXprefix(false, null, null, reg);
19304 setMachineCodes(mi++, (byte) 0xF6);
19305 emitRegRegOperands(reg, GPR.getForOpcode(0x2));
19306 if (lister != null) lister.R(miStart, "NOT", reg);
19307 }
19308 /**
19309 * Generate a NOT to register-displacement offset. That is,
19310 * <PRE>
19311 * ~ (byte) [base + disp]
19312 * </PRE>
19313 *
19314 * @param base the destination base register
19315 * @param disp the destination displacement
19316 */
19317 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19318 public final void emitNOT_RegDisp_Byte(GPR base, Offset disp) {
19319 int miStart = mi;
19320 // no group 1 to 4 prefix byte
19321 generateREXprefix(false, null, null, base);
19322 setMachineCodes(mi++, (byte) 0xF6);
19323 // "register 0x2" is really part of the opcode
19324 emitRegDispRegOperands(base, disp, GPR.getForOpcode(0x2));
19325 if (lister != null) lister.RD(miStart, "NOT", base, disp);
19326 }
19327
19328 /**
19329 * Generate a NOT to register indirect. That is,
19330 * <PRE>
19331 * ~ (byte) [reg]
19332 * </PRE>
19333 *
19334 * @param base the destination base register
19335 */
19336 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19337 public final void emitNOT_RegInd_Byte(GPR base) {
19338 int miStart = mi;
19339 // no group 1 to 4 prefix byte
19340 generateREXprefix(false, null, null, base);
19341 setMachineCodes(mi++, (byte) 0xF6);
19342 // "register 0x2" is really part of the opcode
19343 emitRegIndirectRegOperands(base, GPR.getForOpcode(0x2));
19344 if (lister != null) lister.RN(miStart, "NOT", base);
19345 }
19346
19347 /**
19348 * Generate a NOT to register offset. That is,
19349 * <PRE>
19350 * ~ (byte) [index<<scale + disp]
19351 * </PRE>
19352 *
19353 * @param index the destination index register
19354 * @param scale the destination shift amount
19355 * @param disp the destination displacement
19356 */
19357 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19358 public final void emitNOT_RegOff_Byte(GPR index, short scale, Offset disp) {
19359 int miStart = mi;
19360 // no group 1 to 4 prefix byte
19361 generateREXprefix(false, null, index, null);
19362 setMachineCodes(mi++, (byte) 0xF6);
19363 // "register 0x2" is really part of the opcode
19364 emitRegOffRegOperands(index, scale, disp, GPR.getForOpcode(0x2));
19365 if (lister != null) lister.RFD(miStart, "NOT", index, scale, disp);
19366 }
19367
19368 /**
19369 * Generate a NOT to absolute address. That is,
19370 * <PRE>
19371 * ~ (byte) [disp]
19372 * </PRE>
19373 *
19374 * @param disp the destination displacement
19375 */
19376 public final void emitNOT_Abs_Byte(Address disp) {
19377 int miStart = mi;
19378 // no group 1 to 4 prefix byte
19379 generateREXprefix(false, null, null, null);
19380 setMachineCodes(mi++, (byte) 0xF6);
19381 // "register 0x2" is really part of the opcode
19382 emitAbsRegOperands(disp, GPR.getForOpcode(0x2));
19383 if (lister != null) lister.RA(miStart, "NOT", disp);
19384 }
19385
19386 /**
19387 * Generate a NOT to register offset. That is,
19388 * <PRE>
19389 * ~ (byte) [base + index<<scale + disp]
19390 * </PRE>
19391 *
19392 * @param base the destination base register
19393 * @param index the destination index register
19394 * @param scale the destination shift amount
19395 * @param disp the destination displacement
19396 */
19397 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
19398 public final void emitNOT_RegIdx_Byte(GPR base, GPR index, short scale, Offset disp) {
19399 int miStart = mi;
19400 // no group 1 to 4 prefix byte
19401 generateREXprefix(false, null, index, base);
19402 setMachineCodes(mi++, (byte) 0xF6);
19403 // "register 0x2" is really part of the opcode
19404 emitSIBRegOperands(base, index, scale, disp, GPR.getForOpcode(0x2));
19405 if (lister != null) lister.RXD(miStart, "NOT", base, index, scale, disp);
19406 }
19407
19408 /**
19409 * Generate a NOT on a register. That is,
19410 * <PRE>
19411 * ~ (word) reg
19412 * </PRE>
19413 *
19414 * @param reg register to operate upon
19415 */
19416 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19417 public final void emitNOT_Reg_Word(GPR reg) {
19418 int miStart = mi;
19419 setMachineCodes(mi++, (byte) 0x66);
19420 generateREXprefix(false, null, null, reg);
19421 setMachineCodes(mi++, (byte) 0xF7);
19422 emitRegRegOperands(reg, GPR.getForOpcode(0x2));
19423 if (lister != null) lister.R(miStart, "NOT", reg);
19424 }
19425 /**
19426 * Generate a NOT to register-displacement offset. That is,
19427 * <PRE>
19428 * ~ (word) [base + disp]
19429 * </PRE>
19430 *
19431 * @param base the destination base register
19432 * @param disp the destination displacement
19433 */
19434 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19435 public final void emitNOT_RegDisp_Word(GPR base, Offset disp) {
19436 int miStart = mi;
19437 setMachineCodes(mi++, (byte) 0x66);
19438 generateREXprefix(false, null, null, base);
19439 setMachineCodes(mi++, (byte) 0xF7);
19440 // "register 0x2" is really part of the opcode
19441 emitRegDispRegOperands(base, disp, GPR.getForOpcode(0x2));
19442 if (lister != null) lister.RD(miStart, "NOT", base, disp);
19443 }
19444
19445 /**
19446 * Generate a NOT to register indirect. That is,
19447 * <PRE>
19448 * ~ (word) [reg]
19449 * </PRE>
19450 *
19451 * @param base the destination base register
19452 */
19453 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19454 public final void emitNOT_RegInd_Word(GPR base) {
19455 int miStart = mi;
19456 setMachineCodes(mi++, (byte) 0x66);
19457 generateREXprefix(false, null, null, base);
19458 setMachineCodes(mi++, (byte) 0xF7);
19459 // "register 0x2" is really part of the opcode
19460 emitRegIndirectRegOperands(base, GPR.getForOpcode(0x2));
19461 if (lister != null) lister.RN(miStart, "NOT", base);
19462 }
19463
19464 /**
19465 * Generate a NOT to register offset. That is,
19466 * <PRE>
19467 * ~ (word) [index<<scale + disp]
19468 * </PRE>
19469 *
19470 * @param index the destination index register
19471 * @param scale the destination shift amount
19472 * @param disp the destination displacement
19473 */
19474 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19475 public final void emitNOT_RegOff_Word(GPR index, short scale, Offset disp) {
19476 int miStart = mi;
19477 setMachineCodes(mi++, (byte) 0x66);
19478 generateREXprefix(false, null, index, null);
19479 setMachineCodes(mi++, (byte) 0xF7);
19480 // "register 0x2" is really part of the opcode
19481 emitRegOffRegOperands(index, scale, disp, GPR.getForOpcode(0x2));
19482 if (lister != null) lister.RFD(miStart, "NOT", index, scale, disp);
19483 }
19484
19485 /**
19486 * Generate a NOT to absolute address. That is,
19487 * <PRE>
19488 * ~ (word) [disp]
19489 * </PRE>
19490 *
19491 * @param disp the destination displacement
19492 */
19493 public final void emitNOT_Abs_Word(Address disp) {
19494 int miStart = mi;
19495 setMachineCodes(mi++, (byte) 0x66);
19496 generateREXprefix(false, null, null, null);
19497 setMachineCodes(mi++, (byte) 0xF7);
19498 // "register 0x2" is really part of the opcode
19499 emitAbsRegOperands(disp, GPR.getForOpcode(0x2));
19500 if (lister != null) lister.RA(miStart, "NOT", disp);
19501 }
19502
19503 /**
19504 * Generate a NOT to register offset. That is,
19505 * <PRE>
19506 * ~ (word) [base + index<<scale + disp]
19507 * </PRE>
19508 *
19509 * @param base the destination base register
19510 * @param index the destination index register
19511 * @param scale the destination shift amount
19512 * @param disp the destination displacement
19513 */
19514 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
19515 public final void emitNOT_RegIdx_Word(GPR base, GPR index, short scale, Offset disp) {
19516 int miStart = mi;
19517 setMachineCodes(mi++, (byte) 0x66);
19518 generateREXprefix(false, null, index, base);
19519 setMachineCodes(mi++, (byte) 0xF7);
19520 // "register 0x2" is really part of the opcode
19521 emitSIBRegOperands(base, index, scale, disp, GPR.getForOpcode(0x2));
19522 if (lister != null) lister.RXD(miStart, "NOT", base, index, scale, disp);
19523 }
19524
19525 /**
19526 * Generate a NOT on a register. That is,
19527 * <PRE>
19528 * ~ (quad) reg
19529 * </PRE>
19530 *
19531 * @param reg register to operate upon
19532 */
19533 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19534 public final void emitNOT_Reg_Quad(GPR reg) {
19535 int miStart = mi;
19536 // no group 1 to 4 prefix byte
19537 generateREXprefix(true, null, null, reg);
19538 setMachineCodes(mi++, (byte) 0xF7);
19539 emitRegRegOperands(reg, GPR.getForOpcode(0x2));
19540 if (lister != null) lister.R(miStart, "NOT", reg);
19541 }
19542 /**
19543 * Generate a NOT to register-displacement offset. That is,
19544 * <PRE>
19545 * ~ (quad) [base + disp]
19546 * </PRE>
19547 *
19548 * @param base the destination base register
19549 * @param disp the destination displacement
19550 */
19551 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19552 public final void emitNOT_RegDisp_Quad(GPR base, Offset disp) {
19553 int miStart = mi;
19554 // no group 1 to 4 prefix byte
19555 generateREXprefix(true, null, null, base);
19556 setMachineCodes(mi++, (byte) 0xF7);
19557 // "register 0x2" is really part of the opcode
19558 emitRegDispRegOperands(base, disp, GPR.getForOpcode(0x2));
19559 if (lister != null) lister.RD(miStart, "NOT", base, disp);
19560 }
19561
19562 /**
19563 * Generate a NOT to register indirect. That is,
19564 * <PRE>
19565 * ~ (quad) [reg]
19566 * </PRE>
19567 *
19568 * @param base the destination base register
19569 */
19570 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19571 public final void emitNOT_RegInd_Quad(GPR base) {
19572 int miStart = mi;
19573 // no group 1 to 4 prefix byte
19574 generateREXprefix(true, null, null, base);
19575 setMachineCodes(mi++, (byte) 0xF7);
19576 // "register 0x2" is really part of the opcode
19577 emitRegIndirectRegOperands(base, GPR.getForOpcode(0x2));
19578 if (lister != null) lister.RN(miStart, "NOT", base);
19579 }
19580
19581 /**
19582 * Generate a NOT to register offset. That is,
19583 * <PRE>
19584 * ~ (quad) [index<<scale + disp]
19585 * </PRE>
19586 *
19587 * @param index the destination index register
19588 * @param scale the destination shift amount
19589 * @param disp the destination displacement
19590 */
19591 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19592 public final void emitNOT_RegOff_Quad(GPR index, short scale, Offset disp) {
19593 int miStart = mi;
19594 // no group 1 to 4 prefix byte
19595 generateREXprefix(true, null, index, null);
19596 setMachineCodes(mi++, (byte) 0xF7);
19597 // "register 0x2" is really part of the opcode
19598 emitRegOffRegOperands(index, scale, disp, GPR.getForOpcode(0x2));
19599 if (lister != null) lister.RFD(miStart, "NOT", index, scale, disp);
19600 }
19601
19602 /**
19603 * Generate a NOT to absolute address. That is,
19604 * <PRE>
19605 * ~ (quad) [disp]
19606 * </PRE>
19607 *
19608 * @param disp the destination displacement
19609 */
19610 public final void emitNOT_Abs_Quad(Address disp) {
19611 int miStart = mi;
19612 // no group 1 to 4 prefix byte
19613 generateREXprefix(true, null, null, null);
19614 setMachineCodes(mi++, (byte) 0xF7);
19615 // "register 0x2" is really part of the opcode
19616 emitAbsRegOperands(disp, GPR.getForOpcode(0x2));
19617 if (lister != null) lister.RA(miStart, "NOT", disp);
19618 }
19619
19620 /**
19621 * Generate a NOT to register offset. That is,
19622 * <PRE>
19623 * ~ (quad) [base + index<<scale + disp]
19624 * </PRE>
19625 *
19626 * @param base the destination base register
19627 * @param index the destination index register
19628 * @param scale the destination shift amount
19629 * @param disp the destination displacement
19630 */
19631 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
19632 public final void emitNOT_RegIdx_Quad(GPR base, GPR index, short scale, Offset disp) {
19633 int miStart = mi;
19634 // no group 1 to 4 prefix byte
19635 generateREXprefix(true, null, index, base);
19636 setMachineCodes(mi++, (byte) 0xF7);
19637 // "register 0x2" is really part of the opcode
19638 emitSIBRegOperands(base, index, scale, disp, GPR.getForOpcode(0x2));
19639 if (lister != null) lister.RXD(miStart, "NOT", base, index, scale, disp);
19640 }
19641
19642 /**
19643 * Generate a MUL by register. That is,
19644 * <PRE>
19645 * EAX:EDX = EAX * srcReg
19646 * </PRE>
19647 *
19648 * @param dstReg must always be EAX/R0
19649 * @param srcReg the source register
19650 */
19651 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
19652 public final void emitMUL_Reg_Reg(GPR dstReg, GPR srcReg) {
19653 int miStart = mi;
19654 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
19655 generateREXprefix(false, null, null, srcReg);
19656 setMachineCodes(mi++, (byte) 0xF7);
19657 emitRegRegOperands(srcReg, GPR.getForOpcode(0x4));
19658 if (lister != null) lister.RR(miStart, "MUL", dstReg, srcReg);
19659 }
19660
19661 /**
19662 * Generate a MUL by register displacement. That is,
19663 * <PRE>
19664 * EAX:EDX = EAX * [srcBase + srcDisp]
19665 * </PRE>
19666 *
19667 * @param dstReg must always be EAX/R0
19668 * @param srcBase the source base register
19669 * @param srcDisp the source displacement
19670 */
19671 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
19672 public final void emitMUL_Reg_RegDisp(GPR dstReg, GPR srcBase, Offset srcDisp) {
19673 int miStart = mi;
19674 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
19675 generateREXprefix(false, null, null, srcBase);
19676 setMachineCodes(mi++, (byte) 0xF7);
19677 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(0x4));
19678 if (lister != null) lister.RRD(miStart, "MUL", dstReg, srcBase, srcDisp);
19679 }
19680
19681 /**
19682 * Generate a MUL by register indirect. That is,
19683 * <PRE>
19684 * EAX:EDX = EAX * [srcBase]
19685 * </PRE>
19686 *
19687 * @param dstReg must always be EAX/R0
19688 * @param srcBase the source base register
19689 */
19690 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
19691 public final void emitMUL_Reg_RegInd(GPR dstReg, GPR srcBase) {
19692 int miStart = mi;
19693 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
19694 generateREXprefix(false, null, null, srcBase);
19695 setMachineCodes(mi++, (byte) 0xF7);
19696 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(0x4));
19697 if (lister != null) lister.RRN(miStart, "MUL", dstReg, srcBase);
19698 }
19699
19700 /**
19701 * Generate a MUL by register indexed. That is,
19702 * <PRE>
19703 * EAX:EDX = EAX * [srcBase + srcIndex<<srcScale + srcDisp]
19704 * </PRE>
19705 *
19706 * @param dstReg must always be EAX/R0
19707 * @param srcBase the source base register
19708 * @param srcIndex the source index register
19709 * @param srcScale the source scale of the index
19710 * @param srcDisp the source displacement
19711 */
19712 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
19713 public final void emitMUL_Reg_RegIdx(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
19714 int miStart = mi;
19715 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
19716 generateREXprefix(false, null, srcIndex, srcBase);
19717 setMachineCodes(mi++, (byte) 0xF7);
19718 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(0x4));
19719 if (lister != null) lister.RRXD(miStart, "MUL", dstReg, srcBase, srcIndex, srcScale, srcDisp);
19720 }
19721
19722 /**
19723 * Generate a MUL by register offseted. That is,
19724 * <PRE>
19725 * EAX:EDX = EAX * [srcIndex<<srcScale + srcDisp]
19726 * </PRE>
19727 *
19728 * @param dstReg must always be EAX/R0
19729 * @param srcIndex the source index register
19730 * @param srcScale the source scale of the index
19731 * @param srcDisp the source displacement
19732 */
19733 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
19734 public final void emitMUL_Reg_RegOff(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
19735 int miStart = mi;
19736 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
19737 generateREXprefix(false, null, srcIndex, null);
19738 setMachineCodes(mi++, (byte) 0xF7);
19739 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(0x4));
19740 if (lister != null) lister.RRFD(miStart, "MUL", dstReg, srcIndex, srcScale, srcDisp);
19741 }
19742
19743 /**
19744 * Generate a MUL by absolute address. That is,
19745 * <PRE>
19746 * EAX:EDX = EAX * [srcDisp]
19747 * </PRE>
19748 *
19749 * @param dstReg must always be EAX/R0
19750 * @param srcDisp the source displacement
19751 */
19752 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19753 public final void emitMUL_Reg_Abs(GPR dstReg, Address srcDisp) {
19754 int miStart = mi;
19755 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
19756 generateREXprefix(false, null, null, null);
19757 setMachineCodes(mi++, (byte) 0xF7);
19758 emitAbsRegOperands(srcDisp, GPR.getForOpcode(0x4));
19759 if (lister != null) lister.RRA(miStart, "MUL", dstReg, srcDisp);
19760 }
19761
19762 /**
19763 * Generate a MUL by register. That is,
19764 * <PRE>
19765 * EAX:EDX = EAX * srcReg
19766 * </PRE>
19767 *
19768 * @param dstReg must always be EAX/R0
19769 * @param srcReg the source register
19770 */
19771 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
19772 public final void emitMUL_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
19773 int miStart = mi;
19774 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
19775 generateREXprefix(true, null, null, srcReg);
19776 setMachineCodes(mi++, (byte) 0xF7);
19777 emitRegRegOperands(srcReg, GPR.getForOpcode(0x4));
19778 if (lister != null) lister.RR(miStart, "MUL", dstReg, srcReg);
19779 }
19780
19781 /**
19782 * Generate a MUL by register displacement. That is,
19783 * <PRE>
19784 * EAX:EDX = EAX * [srcBase + srcDisp]
19785 * </PRE>
19786 *
19787 * @param dstReg must always be EAX/R0
19788 * @param srcBase the source base register
19789 * @param srcDisp the source displacement
19790 */
19791 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
19792 public final void emitMUL_Reg_RegDisp_Quad(GPR dstReg, GPR srcBase, Offset srcDisp) {
19793 int miStart = mi;
19794 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
19795 generateREXprefix(true, null, null, srcBase);
19796 setMachineCodes(mi++, (byte) 0xF7);
19797 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(0x4));
19798 if (lister != null) lister.RRD(miStart, "MUL", dstReg, srcBase, srcDisp);
19799 }
19800
19801 /**
19802 * Generate a MUL by register indirect. That is,
19803 * <PRE>
19804 * EAX:EDX = EAX * [srcBase]
19805 * </PRE>
19806 *
19807 * @param dstReg must always be EAX/R0
19808 * @param srcBase the source base register
19809 */
19810 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
19811 public final void emitMUL_Reg_RegInd_Quad(GPR dstReg, GPR srcBase) {
19812 int miStart = mi;
19813 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
19814 generateREXprefix(true, null, null, srcBase);
19815 setMachineCodes(mi++, (byte) 0xF7);
19816 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(0x4));
19817 if (lister != null) lister.RRN(miStart, "MUL", dstReg, srcBase);
19818 }
19819
19820 /**
19821 * Generate a MUL by register indexed. That is,
19822 * <PRE>
19823 * EAX:EDX = EAX * [srcBase + srcIndex<<srcScale + srcDisp]
19824 * </PRE>
19825 *
19826 * @param dstReg must always be EAX/R0
19827 * @param srcBase the source base register
19828 * @param srcIndex the source index register
19829 * @param srcScale the source scale of the index
19830 * @param srcDisp the source displacement
19831 */
19832 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
19833 public final void emitMUL_Reg_RegIdx_Quad(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
19834 int miStart = mi;
19835 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
19836 generateREXprefix(true, null, srcIndex, srcBase);
19837 setMachineCodes(mi++, (byte) 0xF7);
19838 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(0x4));
19839 if (lister != null) lister.RRXD(miStart, "MUL", dstReg, srcBase, srcIndex, srcScale, srcDisp);
19840 }
19841
19842 /**
19843 * Generate a MUL by register offseted. That is,
19844 * <PRE>
19845 * EAX:EDX = EAX * [srcIndex<<srcScale + srcDisp]
19846 * </PRE>
19847 *
19848 * @param dstReg must always be EAX/R0
19849 * @param srcIndex the source index register
19850 * @param srcScale the source scale of the index
19851 * @param srcDisp the source displacement
19852 */
19853 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
19854 public final void emitMUL_Reg_RegOff_Quad(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
19855 int miStart = mi;
19856 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
19857 generateREXprefix(true, null, srcIndex, null);
19858 setMachineCodes(mi++, (byte) 0xF7);
19859 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(0x4));
19860 if (lister != null) lister.RRFD(miStart, "MUL", dstReg, srcIndex, srcScale, srcDisp);
19861 }
19862
19863 /**
19864 * Generate a MUL by absolute address. That is,
19865 * <PRE>
19866 * EAX:EDX = EAX * [srcDisp]
19867 * </PRE>
19868 *
19869 * @param dstReg must always be EAX/R0
19870 * @param srcDisp the source displacement
19871 */
19872 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19873 public final void emitMUL_Reg_Abs_Quad(GPR dstReg, Address srcDisp) {
19874 int miStart = mi;
19875 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
19876 generateREXprefix(true, null, null, null);
19877 setMachineCodes(mi++, (byte) 0xF7);
19878 emitAbsRegOperands(srcDisp, GPR.getForOpcode(0x4));
19879 if (lister != null) lister.RRA(miStart, "MUL", dstReg, srcDisp);
19880 }
19881
19882 /**
19883 * Generate a IMUL1 by register. That is,
19884 * <PRE>
19885 * EAX:EDX = EAX * srcReg
19886 * </PRE>
19887 *
19888 * @param dstReg must always be EAX/R0
19889 * @param srcReg the source register
19890 */
19891 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
19892 public final void emitIMUL1_Reg_Reg(GPR dstReg, GPR srcReg) {
19893 int miStart = mi;
19894 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
19895 generateREXprefix(false, null, null, srcReg);
19896 setMachineCodes(mi++, (byte) 0xF7);
19897 emitRegRegOperands(srcReg, GPR.getForOpcode(0x5));
19898 if (lister != null) lister.RR(miStart, "IMUL1", dstReg, srcReg);
19899 }
19900
19901 /**
19902 * Generate a IMUL1 by register displacement. That is,
19903 * <PRE>
19904 * EAX:EDX = EAX * [srcBase + srcDisp]
19905 * </PRE>
19906 *
19907 * @param dstReg must always be EAX/R0
19908 * @param srcBase the source base register
19909 * @param srcDisp the source displacement
19910 */
19911 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
19912 public final void emitIMUL1_Reg_RegDisp(GPR dstReg, GPR srcBase, Offset srcDisp) {
19913 int miStart = mi;
19914 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
19915 generateREXprefix(false, null, null, srcBase);
19916 setMachineCodes(mi++, (byte) 0xF7);
19917 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(0x5));
19918 if (lister != null) lister.RRD(miStart, "IMUL1", dstReg, srcBase, srcDisp);
19919 }
19920
19921 /**
19922 * Generate a IMUL1 by register indirect. That is,
19923 * <PRE>
19924 * EAX:EDX = EAX * [srcBase]
19925 * </PRE>
19926 *
19927 * @param dstReg must always be EAX/R0
19928 * @param srcBase the source base register
19929 */
19930 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
19931 public final void emitIMUL1_Reg_RegInd(GPR dstReg, GPR srcBase) {
19932 int miStart = mi;
19933 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
19934 generateREXprefix(false, null, null, srcBase);
19935 setMachineCodes(mi++, (byte) 0xF7);
19936 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(0x5));
19937 if (lister != null) lister.RRN(miStart, "IMUL1", dstReg, srcBase);
19938 }
19939
19940 /**
19941 * Generate a IMUL1 by register indexed. That is,
19942 * <PRE>
19943 * EAX:EDX = EAX * [srcBase + srcIndex<<srcScale + srcDisp]
19944 * </PRE>
19945 *
19946 * @param dstReg must always be EAX/R0
19947 * @param srcBase the source base register
19948 * @param srcIndex the source index register
19949 * @param srcScale the source scale of the index
19950 * @param srcDisp the source displacement
19951 */
19952 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
19953 public final void emitIMUL1_Reg_RegIdx(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
19954 int miStart = mi;
19955 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
19956 generateREXprefix(false, null, srcIndex, srcBase);
19957 setMachineCodes(mi++, (byte) 0xF7);
19958 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(0x5));
19959 if (lister != null) lister.RRXD(miStart, "IMUL1", dstReg, srcBase, srcIndex, srcScale, srcDisp);
19960 }
19961
19962 /**
19963 * Generate a IMUL1 by register offseted. That is,
19964 * <PRE>
19965 * EAX:EDX = EAX * [srcIndex<<srcScale + srcDisp]
19966 * </PRE>
19967 *
19968 * @param dstReg must always be EAX/R0
19969 * @param srcIndex the source index register
19970 * @param srcScale the source scale of the index
19971 * @param srcDisp the source displacement
19972 */
19973 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
19974 public final void emitIMUL1_Reg_RegOff(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
19975 int miStart = mi;
19976 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
19977 generateREXprefix(false, null, srcIndex, null);
19978 setMachineCodes(mi++, (byte) 0xF7);
19979 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(0x5));
19980 if (lister != null) lister.RRFD(miStart, "IMUL1", dstReg, srcIndex, srcScale, srcDisp);
19981 }
19982
19983 /**
19984 * Generate a IMUL1 by absolute address. That is,
19985 * <PRE>
19986 * EAX:EDX = EAX * [srcDisp]
19987 * </PRE>
19988 *
19989 * @param dstReg must always be EAX/R0
19990 * @param srcDisp the source displacement
19991 */
19992 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
19993 public final void emitIMUL1_Reg_Abs(GPR dstReg, Address srcDisp) {
19994 int miStart = mi;
19995 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
19996 generateREXprefix(false, null, null, null);
19997 setMachineCodes(mi++, (byte) 0xF7);
19998 emitAbsRegOperands(srcDisp, GPR.getForOpcode(0x5));
19999 if (lister != null) lister.RRA(miStart, "IMUL1", dstReg, srcDisp);
20000 }
20001
20002 /**
20003 * Generate a IMUL1 by register. That is,
20004 * <PRE>
20005 * EAX:EDX = EAX * srcReg
20006 * </PRE>
20007 *
20008 * @param dstReg must always be EAX/R0
20009 * @param srcReg the source register
20010 */
20011 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20012 public final void emitIMUL1_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
20013 int miStart = mi;
20014 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20015 generateREXprefix(true, null, null, srcReg);
20016 setMachineCodes(mi++, (byte) 0xF7);
20017 emitRegRegOperands(srcReg, GPR.getForOpcode(0x5));
20018 if (lister != null) lister.RR(miStart, "IMUL1", dstReg, srcReg);
20019 }
20020
20021 /**
20022 * Generate a IMUL1 by register displacement. That is,
20023 * <PRE>
20024 * EAX:EDX = EAX * [srcBase + srcDisp]
20025 * </PRE>
20026 *
20027 * @param dstReg must always be EAX/R0
20028 * @param srcBase the source base register
20029 * @param srcDisp the source displacement
20030 */
20031 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20032 public final void emitIMUL1_Reg_RegDisp_Quad(GPR dstReg, GPR srcBase, Offset srcDisp) {
20033 int miStart = mi;
20034 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20035 generateREXprefix(true, null, null, srcBase);
20036 setMachineCodes(mi++, (byte) 0xF7);
20037 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(0x5));
20038 if (lister != null) lister.RRD(miStart, "IMUL1", dstReg, srcBase, srcDisp);
20039 }
20040
20041 /**
20042 * Generate a IMUL1 by register indirect. That is,
20043 * <PRE>
20044 * EAX:EDX = EAX * [srcBase]
20045 * </PRE>
20046 *
20047 * @param dstReg must always be EAX/R0
20048 * @param srcBase the source base register
20049 */
20050 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20051 public final void emitIMUL1_Reg_RegInd_Quad(GPR dstReg, GPR srcBase) {
20052 int miStart = mi;
20053 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20054 generateREXprefix(true, null, null, srcBase);
20055 setMachineCodes(mi++, (byte) 0xF7);
20056 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(0x5));
20057 if (lister != null) lister.RRN(miStart, "IMUL1", dstReg, srcBase);
20058 }
20059
20060 /**
20061 * Generate a IMUL1 by register indexed. That is,
20062 * <PRE>
20063 * EAX:EDX = EAX * [srcBase + srcIndex<<srcScale + srcDisp]
20064 * </PRE>
20065 *
20066 * @param dstReg must always be EAX/R0
20067 * @param srcBase the source base register
20068 * @param srcIndex the source index register
20069 * @param srcScale the source scale of the index
20070 * @param srcDisp the source displacement
20071 */
20072 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
20073 public final void emitIMUL1_Reg_RegIdx_Quad(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
20074 int miStart = mi;
20075 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20076 generateREXprefix(true, null, srcIndex, srcBase);
20077 setMachineCodes(mi++, (byte) 0xF7);
20078 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(0x5));
20079 if (lister != null) lister.RRXD(miStart, "IMUL1", dstReg, srcBase, srcIndex, srcScale, srcDisp);
20080 }
20081
20082 /**
20083 * Generate a IMUL1 by register offseted. That is,
20084 * <PRE>
20085 * EAX:EDX = EAX * [srcIndex<<srcScale + srcDisp]
20086 * </PRE>
20087 *
20088 * @param dstReg must always be EAX/R0
20089 * @param srcIndex the source index register
20090 * @param srcScale the source scale of the index
20091 * @param srcDisp the source displacement
20092 */
20093 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20094 public final void emitIMUL1_Reg_RegOff_Quad(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
20095 int miStart = mi;
20096 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20097 generateREXprefix(true, null, srcIndex, null);
20098 setMachineCodes(mi++, (byte) 0xF7);
20099 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(0x5));
20100 if (lister != null) lister.RRFD(miStart, "IMUL1", dstReg, srcIndex, srcScale, srcDisp);
20101 }
20102
20103 /**
20104 * Generate a IMUL1 by absolute address. That is,
20105 * <PRE>
20106 * EAX:EDX = EAX * [srcDisp]
20107 * </PRE>
20108 *
20109 * @param dstReg must always be EAX/R0
20110 * @param srcDisp the source displacement
20111 */
20112 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
20113 public final void emitIMUL1_Reg_Abs_Quad(GPR dstReg, Address srcDisp) {
20114 int miStart = mi;
20115 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20116 generateREXprefix(true, null, null, null);
20117 setMachineCodes(mi++, (byte) 0xF7);
20118 emitAbsRegOperands(srcDisp, GPR.getForOpcode(0x5));
20119 if (lister != null) lister.RRA(miStart, "IMUL1", dstReg, srcDisp);
20120 }
20121
20122 /**
20123 * Generate a DIV by register. That is,
20124 * <PRE>
20125 * EAX:EDX = EAX / srcReg
20126 * </PRE>
20127 *
20128 * @param dstReg must always be EAX/R0
20129 * @param srcReg the source register
20130 */
20131 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20132 public final void emitDIV_Reg_Reg(GPR dstReg, GPR srcReg) {
20133 int miStart = mi;
20134 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20135 generateREXprefix(false, null, null, srcReg);
20136 setMachineCodes(mi++, (byte) 0xF7);
20137 emitRegRegOperands(srcReg, GPR.getForOpcode(0x6));
20138 if (lister != null) lister.RR(miStart, "DIV", dstReg, srcReg);
20139 }
20140
20141 /**
20142 * Generate a DIV by register displacement. That is,
20143 * <PRE>
20144 * EAX:EDX = EAX / [srcBase + srcDisp]
20145 * </PRE>
20146 *
20147 * @param dstReg must always be EAX/R0
20148 * @param srcBase the source base register
20149 * @param srcDisp the source displacement
20150 */
20151 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20152 public final void emitDIV_Reg_RegDisp(GPR dstReg, GPR srcBase, Offset srcDisp) {
20153 int miStart = mi;
20154 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20155 generateREXprefix(false, null, null, srcBase);
20156 setMachineCodes(mi++, (byte) 0xF7);
20157 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(0x6));
20158 if (lister != null) lister.RRD(miStart, "DIV", dstReg, srcBase, srcDisp);
20159 }
20160
20161 /**
20162 * Generate a DIV by register indirect. That is,
20163 * <PRE>
20164 * EAX:EDX = EAX / [srcBase]
20165 * </PRE>
20166 *
20167 * @param dstReg must always be EAX/R0
20168 * @param srcBase the source base register
20169 */
20170 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20171 public final void emitDIV_Reg_RegInd(GPR dstReg, GPR srcBase) {
20172 int miStart = mi;
20173 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20174 generateREXprefix(false, null, null, srcBase);
20175 setMachineCodes(mi++, (byte) 0xF7);
20176 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(0x6));
20177 if (lister != null) lister.RRN(miStart, "DIV", dstReg, srcBase);
20178 }
20179
20180 /**
20181 * Generate a DIV by register indexed. That is,
20182 * <PRE>
20183 * EAX:EDX = EAX / [srcBase + srcIndex<<srcScale + srcDisp]
20184 * </PRE>
20185 *
20186 * @param dstReg must always be EAX/R0
20187 * @param srcBase the source base register
20188 * @param srcIndex the source index register
20189 * @param srcScale the source scale of the index
20190 * @param srcDisp the source displacement
20191 */
20192 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
20193 public final void emitDIV_Reg_RegIdx(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
20194 int miStart = mi;
20195 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20196 generateREXprefix(false, null, srcIndex, srcBase);
20197 setMachineCodes(mi++, (byte) 0xF7);
20198 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(0x6));
20199 if (lister != null) lister.RRXD(miStart, "DIV", dstReg, srcBase, srcIndex, srcScale, srcDisp);
20200 }
20201
20202 /**
20203 * Generate a DIV by register offseted. That is,
20204 * <PRE>
20205 * EAX:EDX = EAX / [srcIndex<<srcScale + srcDisp]
20206 * </PRE>
20207 *
20208 * @param dstReg must always be EAX/R0
20209 * @param srcIndex the source index register
20210 * @param srcScale the source scale of the index
20211 * @param srcDisp the source displacement
20212 */
20213 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20214 public final void emitDIV_Reg_RegOff(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
20215 int miStart = mi;
20216 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20217 generateREXprefix(false, null, srcIndex, null);
20218 setMachineCodes(mi++, (byte) 0xF7);
20219 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(0x6));
20220 if (lister != null) lister.RRFD(miStart, "DIV", dstReg, srcIndex, srcScale, srcDisp);
20221 }
20222
20223 /**
20224 * Generate a DIV by absolute address. That is,
20225 * <PRE>
20226 * EAX:EDX = EAX / [srcDisp]
20227 * </PRE>
20228 *
20229 * @param dstReg must always be EAX/R0
20230 * @param srcDisp the source displacement
20231 */
20232 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
20233 public final void emitDIV_Reg_Abs(GPR dstReg, Address srcDisp) {
20234 int miStart = mi;
20235 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20236 generateREXprefix(false, null, null, null);
20237 setMachineCodes(mi++, (byte) 0xF7);
20238 emitAbsRegOperands(srcDisp, GPR.getForOpcode(0x6));
20239 if (lister != null) lister.RRA(miStart, "DIV", dstReg, srcDisp);
20240 }
20241
20242 /**
20243 * Generate a DIV by register. That is,
20244 * <PRE>
20245 * EAX:EDX = EAX / srcReg
20246 * </PRE>
20247 *
20248 * @param dstReg must always be EAX/R0
20249 * @param srcReg the source register
20250 */
20251 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20252 public final void emitDIV_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
20253 int miStart = mi;
20254 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20255 generateREXprefix(true, null, null, srcReg);
20256 setMachineCodes(mi++, (byte) 0xF7);
20257 emitRegRegOperands(srcReg, GPR.getForOpcode(0x6));
20258 if (lister != null) lister.RR(miStart, "DIV", dstReg, srcReg);
20259 }
20260
20261 /**
20262 * Generate a DIV by register displacement. That is,
20263 * <PRE>
20264 * EAX:EDX = EAX / [srcBase + srcDisp]
20265 * </PRE>
20266 *
20267 * @param dstReg must always be EAX/R0
20268 * @param srcBase the source base register
20269 * @param srcDisp the source displacement
20270 */
20271 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20272 public final void emitDIV_Reg_RegDisp_Quad(GPR dstReg, GPR srcBase, Offset srcDisp) {
20273 int miStart = mi;
20274 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20275 generateREXprefix(true, null, null, srcBase);
20276 setMachineCodes(mi++, (byte) 0xF7);
20277 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(0x6));
20278 if (lister != null) lister.RRD(miStart, "DIV", dstReg, srcBase, srcDisp);
20279 }
20280
20281 /**
20282 * Generate a DIV by register indirect. That is,
20283 * <PRE>
20284 * EAX:EDX = EAX / [srcBase]
20285 * </PRE>
20286 *
20287 * @param dstReg must always be EAX/R0
20288 * @param srcBase the source base register
20289 */
20290 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20291 public final void emitDIV_Reg_RegInd_Quad(GPR dstReg, GPR srcBase) {
20292 int miStart = mi;
20293 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20294 generateREXprefix(true, null, null, srcBase);
20295 setMachineCodes(mi++, (byte) 0xF7);
20296 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(0x6));
20297 if (lister != null) lister.RRN(miStart, "DIV", dstReg, srcBase);
20298 }
20299
20300 /**
20301 * Generate a DIV by register indexed. That is,
20302 * <PRE>
20303 * EAX:EDX = EAX / [srcBase + srcIndex<<srcScale + srcDisp]
20304 * </PRE>
20305 *
20306 * @param dstReg must always be EAX/R0
20307 * @param srcBase the source base register
20308 * @param srcIndex the source index register
20309 * @param srcScale the source scale of the index
20310 * @param srcDisp the source displacement
20311 */
20312 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
20313 public final void emitDIV_Reg_RegIdx_Quad(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
20314 int miStart = mi;
20315 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20316 generateREXprefix(true, null, srcIndex, srcBase);
20317 setMachineCodes(mi++, (byte) 0xF7);
20318 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(0x6));
20319 if (lister != null) lister.RRXD(miStart, "DIV", dstReg, srcBase, srcIndex, srcScale, srcDisp);
20320 }
20321
20322 /**
20323 * Generate a DIV by register offseted. That is,
20324 * <PRE>
20325 * EAX:EDX = EAX / [srcIndex<<srcScale + srcDisp]
20326 * </PRE>
20327 *
20328 * @param dstReg must always be EAX/R0
20329 * @param srcIndex the source index register
20330 * @param srcScale the source scale of the index
20331 * @param srcDisp the source displacement
20332 */
20333 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20334 public final void emitDIV_Reg_RegOff_Quad(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
20335 int miStart = mi;
20336 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20337 generateREXprefix(true, null, srcIndex, null);
20338 setMachineCodes(mi++, (byte) 0xF7);
20339 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(0x6));
20340 if (lister != null) lister.RRFD(miStart, "DIV", dstReg, srcIndex, srcScale, srcDisp);
20341 }
20342
20343 /**
20344 * Generate a DIV by absolute address. That is,
20345 * <PRE>
20346 * EAX:EDX = EAX / [srcDisp]
20347 * </PRE>
20348 *
20349 * @param dstReg must always be EAX/R0
20350 * @param srcDisp the source displacement
20351 */
20352 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
20353 public final void emitDIV_Reg_Abs_Quad(GPR dstReg, Address srcDisp) {
20354 int miStart = mi;
20355 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20356 generateREXprefix(true, null, null, null);
20357 setMachineCodes(mi++, (byte) 0xF7);
20358 emitAbsRegOperands(srcDisp, GPR.getForOpcode(0x6));
20359 if (lister != null) lister.RRA(miStart, "DIV", dstReg, srcDisp);
20360 }
20361
20362 /**
20363 * Generate a IDIV by register. That is,
20364 * <PRE>
20365 * EAX:EDX = EAX u/ srcReg
20366 * </PRE>
20367 *
20368 * @param dstReg must always be EAX/R0
20369 * @param srcReg the source register
20370 */
20371 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20372 public final void emitIDIV_Reg_Reg(GPR dstReg, GPR srcReg) {
20373 int miStart = mi;
20374 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20375 generateREXprefix(false, null, null, srcReg);
20376 setMachineCodes(mi++, (byte) 0xF7);
20377 emitRegRegOperands(srcReg, GPR.getForOpcode(0x7));
20378 if (lister != null) lister.RR(miStart, "IDIV", dstReg, srcReg);
20379 }
20380
20381 /**
20382 * Generate a IDIV by register displacement. That is,
20383 * <PRE>
20384 * EAX:EDX = EAX u/ [srcBase + srcDisp]
20385 * </PRE>
20386 *
20387 * @param dstReg must always be EAX/R0
20388 * @param srcBase the source base register
20389 * @param srcDisp the source displacement
20390 */
20391 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20392 public final void emitIDIV_Reg_RegDisp(GPR dstReg, GPR srcBase, Offset srcDisp) {
20393 int miStart = mi;
20394 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20395 generateREXprefix(false, null, null, srcBase);
20396 setMachineCodes(mi++, (byte) 0xF7);
20397 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(0x7));
20398 if (lister != null) lister.RRD(miStart, "IDIV", dstReg, srcBase, srcDisp);
20399 }
20400
20401 /**
20402 * Generate a IDIV by register indirect. That is,
20403 * <PRE>
20404 * EAX:EDX = EAX u/ [srcBase]
20405 * </PRE>
20406 *
20407 * @param dstReg must always be EAX/R0
20408 * @param srcBase the source base register
20409 */
20410 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20411 public final void emitIDIV_Reg_RegInd(GPR dstReg, GPR srcBase) {
20412 int miStart = mi;
20413 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20414 generateREXprefix(false, null, null, srcBase);
20415 setMachineCodes(mi++, (byte) 0xF7);
20416 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(0x7));
20417 if (lister != null) lister.RRN(miStart, "IDIV", dstReg, srcBase);
20418 }
20419
20420 /**
20421 * Generate a IDIV by register indexed. That is,
20422 * <PRE>
20423 * EAX:EDX = EAX u/ [srcBase + srcIndex<<srcScale + srcDisp]
20424 * </PRE>
20425 *
20426 * @param dstReg must always be EAX/R0
20427 * @param srcBase the source base register
20428 * @param srcIndex the source index register
20429 * @param srcScale the source scale of the index
20430 * @param srcDisp the source displacement
20431 */
20432 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
20433 public final void emitIDIV_Reg_RegIdx(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
20434 int miStart = mi;
20435 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20436 generateREXprefix(false, null, srcIndex, srcBase);
20437 setMachineCodes(mi++, (byte) 0xF7);
20438 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(0x7));
20439 if (lister != null) lister.RRXD(miStart, "IDIV", dstReg, srcBase, srcIndex, srcScale, srcDisp);
20440 }
20441
20442 /**
20443 * Generate a IDIV by register offseted. That is,
20444 * <PRE>
20445 * EAX:EDX = EAX u/ [srcIndex<<srcScale + srcDisp]
20446 * </PRE>
20447 *
20448 * @param dstReg must always be EAX/R0
20449 * @param srcIndex the source index register
20450 * @param srcScale the source scale of the index
20451 * @param srcDisp the source displacement
20452 */
20453 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20454 public final void emitIDIV_Reg_RegOff(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
20455 int miStart = mi;
20456 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20457 generateREXprefix(false, null, srcIndex, null);
20458 setMachineCodes(mi++, (byte) 0xF7);
20459 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(0x7));
20460 if (lister != null) lister.RRFD(miStart, "IDIV", dstReg, srcIndex, srcScale, srcDisp);
20461 }
20462
20463 /**
20464 * Generate a IDIV by absolute address. That is,
20465 * <PRE>
20466 * EAX:EDX = EAX u/ [srcDisp]
20467 * </PRE>
20468 *
20469 * @param dstReg must always be EAX/R0
20470 * @param srcDisp the source displacement
20471 */
20472 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
20473 public final void emitIDIV_Reg_Abs(GPR dstReg, Address srcDisp) {
20474 int miStart = mi;
20475 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20476 generateREXprefix(false, null, null, null);
20477 setMachineCodes(mi++, (byte) 0xF7);
20478 emitAbsRegOperands(srcDisp, GPR.getForOpcode(0x7));
20479 if (lister != null) lister.RRA(miStart, "IDIV", dstReg, srcDisp);
20480 }
20481
20482 /**
20483 * Generate a IDIV by register. That is,
20484 * <PRE>
20485 * EAX:EDX = EAX u/ srcReg
20486 * </PRE>
20487 *
20488 * @param dstReg must always be EAX/R0
20489 * @param srcReg the source register
20490 */
20491 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20492 public final void emitIDIV_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
20493 int miStart = mi;
20494 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20495 generateREXprefix(true, null, null, srcReg);
20496 setMachineCodes(mi++, (byte) 0xF7);
20497 emitRegRegOperands(srcReg, GPR.getForOpcode(0x7));
20498 if (lister != null) lister.RR(miStart, "IDIV", dstReg, srcReg);
20499 }
20500
20501 /**
20502 * Generate a IDIV by register displacement. That is,
20503 * <PRE>
20504 * EAX:EDX = EAX u/ [srcBase + srcDisp]
20505 * </PRE>
20506 *
20507 * @param dstReg must always be EAX/R0
20508 * @param srcBase the source base register
20509 * @param srcDisp the source displacement
20510 */
20511 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20512 public final void emitIDIV_Reg_RegDisp_Quad(GPR dstReg, GPR srcBase, Offset srcDisp) {
20513 int miStart = mi;
20514 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20515 generateREXprefix(true, null, null, srcBase);
20516 setMachineCodes(mi++, (byte) 0xF7);
20517 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(0x7));
20518 if (lister != null) lister.RRD(miStart, "IDIV", dstReg, srcBase, srcDisp);
20519 }
20520
20521 /**
20522 * Generate a IDIV by register indirect. That is,
20523 * <PRE>
20524 * EAX:EDX = EAX u/ [srcBase]
20525 * </PRE>
20526 *
20527 * @param dstReg must always be EAX/R0
20528 * @param srcBase the source base register
20529 */
20530 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20531 public final void emitIDIV_Reg_RegInd_Quad(GPR dstReg, GPR srcBase) {
20532 int miStart = mi;
20533 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20534 generateREXprefix(true, null, null, srcBase);
20535 setMachineCodes(mi++, (byte) 0xF7);
20536 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(0x7));
20537 if (lister != null) lister.RRN(miStart, "IDIV", dstReg, srcBase);
20538 }
20539
20540 /**
20541 * Generate a IDIV by register indexed. That is,
20542 * <PRE>
20543 * EAX:EDX = EAX u/ [srcBase + srcIndex<<srcScale + srcDisp]
20544 * </PRE>
20545 *
20546 * @param dstReg must always be EAX/R0
20547 * @param srcBase the source base register
20548 * @param srcIndex the source index register
20549 * @param srcScale the source scale of the index
20550 * @param srcDisp the source displacement
20551 */
20552 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
20553 public final void emitIDIV_Reg_RegIdx_Quad(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
20554 int miStart = mi;
20555 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20556 generateREXprefix(true, null, srcIndex, srcBase);
20557 setMachineCodes(mi++, (byte) 0xF7);
20558 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(0x7));
20559 if (lister != null) lister.RRXD(miStart, "IDIV", dstReg, srcBase, srcIndex, srcScale, srcDisp);
20560 }
20561
20562 /**
20563 * Generate a IDIV by register offseted. That is,
20564 * <PRE>
20565 * EAX:EDX = EAX u/ [srcIndex<<srcScale + srcDisp]
20566 * </PRE>
20567 *
20568 * @param dstReg must always be EAX/R0
20569 * @param srcIndex the source index register
20570 * @param srcScale the source scale of the index
20571 * @param srcDisp the source displacement
20572 */
20573 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20574 public final void emitIDIV_Reg_RegOff_Quad(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
20575 int miStart = mi;
20576 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20577 generateREXprefix(true, null, srcIndex, null);
20578 setMachineCodes(mi++, (byte) 0xF7);
20579 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(0x7));
20580 if (lister != null) lister.RRFD(miStart, "IDIV", dstReg, srcIndex, srcScale, srcDisp);
20581 }
20582
20583 /**
20584 * Generate a IDIV by absolute address. That is,
20585 * <PRE>
20586 * EAX:EDX = EAX u/ [srcDisp]
20587 * </PRE>
20588 *
20589 * @param dstReg must always be EAX/R0
20590 * @param srcDisp the source displacement
20591 */
20592 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
20593 public final void emitIDIV_Reg_Abs_Quad(GPR dstReg, Address srcDisp) {
20594 int miStart = mi;
20595 if (VM.VerifyAssertions) VM._assert(dstReg == EAX);
20596 generateREXprefix(true, null, null, null);
20597 setMachineCodes(mi++, (byte) 0xF7);
20598 emitAbsRegOperands(srcDisp, GPR.getForOpcode(0x7));
20599 if (lister != null) lister.RRA(miStart, "IDIV", dstReg, srcDisp);
20600 }
20601
20602 /**
20603 * Generate a register(indirect)--register MOV. That is,
20604 * <PRE>
20605 * [dstBase] := srcReg
20606 * </PRE>
20607 *
20608 * @param dstBase the destination base
20609 * @param srcReg the source register
20610 */
20611 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20612 public final void emitMOV_RegInd_Reg(GPR dstBase, GPR srcReg) {
20613 int miStart = mi;
20614 // no group 1 to 4 prefix byte
20615 generateREXprefix(false, srcReg, null, dstBase);
20616 // single byte opcode
20617 setMachineCodes(mi++, (byte) 0x89);
20618 emitRegIndirectRegOperands(dstBase, srcReg);
20619 if (lister != null) lister.RNR(miStart, "MOV", dstBase, srcReg);
20620 }
20621
20622 /**
20623 * Generate a register-offset--register MOV. That is,
20624 * <PRE>
20625 * [dstReg<<dstScale + dstDisp] := srcReg
20626 * </PRE>
20627 *
20628 * @param dstIndex the destination index register
20629 * @param dstScale the destination shift amount
20630 * @param dstDisp the destination displacement
20631 * @param srcReg the source register
20632 */
20633 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
20634 public final void emitMOV_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
20635 int miStart = mi;
20636 // no group 1 to 4 prefix byte
20637 generateREXprefix(false, srcReg, dstIndex, null);
20638 // single byte opcode
20639 setMachineCodes(mi++, (byte) 0x89);
20640 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
20641 if (lister != null) lister.RFDR(miStart, "MOV", dstIndex, dstScale, dstDisp, srcReg);
20642 }
20643
20644 /**
20645 * Generate a absolute--register MOV. That is,
20646 * <PRE>
20647 * [dstDisp] := srcReg
20648 * </PRE>
20649 *
20650 * @param dstDisp the destination address
20651 * @param srcReg the source register
20652 */
20653 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
20654 public final void emitMOV_Abs_Reg(Address dstDisp, GPR srcReg) {
20655 int miStart = mi;
20656 // no group 1 to 4 prefix byte
20657 generateREXprefix(false, srcReg, null, null);
20658 // single byte opcode
20659 setMachineCodes(mi++, (byte) 0x89);
20660 emitAbsRegOperands(dstDisp, srcReg);
20661 if (lister != null) lister.RAR(miStart, "MOV", dstDisp, srcReg);
20662 }
20663
20664 /**
20665 * Generate a register-index--register MOV. That is,
20666 * <PRE>
20667 * [dstBase + dstIndex<<dstScale + dstDisp] := srcReg
20668 * </PRE>
20669 *
20670 * @param dstBase the base register
20671 * @param dstIndex the destination index register
20672 * @param dstScale the destination shift amount
20673 * @param dstDisp the destination displacement
20674 * @param srcReg the source register
20675 */
20676 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
20677 public final void emitMOV_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
20678 int miStart = mi;
20679 // no group 1 to 4 prefix byte
20680 generateREXprefix(false, srcReg, dstIndex, dstBase);
20681 // single byte opcode
20682 setMachineCodes(mi++, (byte) 0x89);
20683 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
20684 if (lister != null) lister.RXDR(miStart, "MOV", dstBase, dstIndex, dstScale, dstDisp, srcReg);
20685 }
20686
20687 /**
20688 * Generate a register-displacement--register MOV. That is,
20689 * <PRE>
20690 * [dstBase + dstDisp] := srcReg
20691 * </PRE>
20692 *
20693 * @param dstBase the base register
20694 * @param dstDisp the destination displacement
20695 * @param srcReg the source register
20696 */
20697 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
20698 public final void emitMOV_RegDisp_Reg(GPR dstBase, Offset dstDisp, GPR srcReg) {
20699 int miStart = mi;
20700 // no group 1 to 4 prefix byte
20701 generateREXprefix(false, srcReg, null, dstBase);
20702 // single byte opcode
20703 setMachineCodes(mi++, (byte) 0x89);
20704 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
20705 if (lister != null) lister.RDR(miStart, "MOV", dstBase, dstDisp, srcReg);
20706 }
20707
20708 /**
20709 * Generate a register--register MOV. That is,
20710 * <PRE>
20711 * dstReg := srcReg
20712 * </PRE>
20713 *
20714 * @param dstReg the destination register
20715 * @param srcReg the source register
20716 */
20717 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20718 public final void emitMOV_Reg_Reg(GPR dstReg, GPR srcReg) {
20719 int miStart = mi;
20720 // no group 1 to 4 prefix byte
20721 generateREXprefix(false, srcReg, null, dstReg);
20722 // single byte opcode
20723 setMachineCodes(mi++, (byte) 0x89);
20724 emitRegRegOperands(dstReg, srcReg);
20725 if (lister != null) lister.RR(miStart, "MOV", dstReg, srcReg);
20726 }
20727
20728 /**
20729 * Generate a register--register-displacement MOV. That is,
20730 * <PRE>
20731 * dstReg := [srcReg + srcDisp]
20732 * </PRE>
20733 *
20734 * @param dstReg the destination register
20735 * @param srcBase the source register
20736 * @param srcDisp the source displacement
20737 */
20738 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20739 public final void emitMOV_Reg_RegDisp(GPR dstReg, GPR srcBase, Offset srcDisp) {
20740 int miStart = mi;
20741 // no group 1 to 4 prefix byte
20742 generateREXprefix(false, dstReg, null, srcBase);
20743 // single byte opcode
20744 setMachineCodes(mi++, (byte) 0x8B);
20745 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
20746 if (lister != null) lister.RRD(miStart, "MOV", dstReg, srcBase, srcDisp);
20747 }
20748
20749 /**
20750 * Generate a register--register-offset MOV. That is,
20751 * <PRE>
20752 * dstReg := [srcIndex<<srcScale + srcDisp]
20753 * </PRE>
20754 *
20755 * @param dstReg the destination register
20756 * @param srcIndex the source index register
20757 * @param srcScale the source shift amount
20758 * @param srcDisp the source displacement
20759 */
20760 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20761 public final void emitMOV_Reg_RegOff(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
20762 int miStart = mi;
20763 // no group 1 to 4 prefix byte
20764 generateREXprefix(false, dstReg, srcIndex, null);
20765 // single byte opcode
20766 setMachineCodes(mi++, (byte) 0x8B);
20767 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
20768 if (lister != null) lister.RRFD(miStart, "MOV", dstReg, srcIndex, srcScale, srcDisp);
20769 }
20770
20771 /**
20772 * Generate a register--register-offset MOV. That is,
20773 * <PRE>
20774 * dstReg := [srcDisp]
20775 * </PRE>
20776 *
20777 * @param dstReg the destination register
20778 * @param srcDisp the source displacement
20779 */
20780 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
20781 public final void emitMOV_Reg_Abs(GPR dstReg, Address srcDisp) {
20782 int miStart = mi;
20783 // no group 1 to 4 prefix byte
20784 generateREXprefix(false, dstReg, null, null);
20785 // single byte opcode
20786 setMachineCodes(mi++, (byte) 0x8B);
20787 emitAbsRegOperands(srcDisp, dstReg);
20788 if (lister != null) lister.RRA(miStart, "MOV", dstReg, srcDisp);
20789 }
20790
20791 /**
20792 * Generate a register--register-offset MOV. That is,
20793 * <PRE>
20794 * dstReg := [srcBase + srcIndex<<srcScale + srcDisp]
20795 * </PRE>
20796 *
20797 * @param dstReg the destination register
20798 * @param srcBase the source base register
20799 * @param srcIndex the source index register
20800 * @param srcScale the source shift amount
20801 * @param srcDisp the source displacement
20802 */
20803 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
20804 public final void emitMOV_Reg_RegIdx(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
20805 int miStart = mi;
20806 // no group 1 to 4 prefix byte
20807 generateREXprefix(false, dstReg, srcIndex, srcBase);
20808 // single byte opcode
20809 setMachineCodes(mi++, (byte) 0x8B);
20810 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
20811 if (lister != null) lister.RRXD(miStart, "MOV", dstReg, srcBase, srcIndex, srcScale, srcDisp);
20812 }
20813
20814 /**
20815 * Generate a register--register(indirect) MOV. That is,
20816 * <PRE>
20817 * dstReg := [srcBase]
20818 * </PRE>
20819 *
20820 * @param dstReg the destination register
20821 * @param srcBase the source base register
20822 */
20823 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20824 public final void emitMOV_Reg_RegInd(GPR dstReg, GPR srcBase) {
20825 int miStart = mi;
20826 // no group 1 to 4 prefix byte
20827 generateREXprefix(false, dstReg, null, srcBase);
20828 // single byte opcode
20829 setMachineCodes(mi++, (byte) 0x8B);
20830 emitRegIndirectRegOperands(srcBase, dstReg);
20831 if (lister != null) lister.RRN(miStart, "MOV", dstReg, srcBase);
20832 }
20833
20834 /**
20835 * Generate a register(indirect)--register MOV. That is,
20836 * <PRE>
20837 * [dstBase] := (byte) srcReg
20838 * </PRE>
20839 *
20840 * @param dstBase the destination base
20841 * @param srcReg the source register
20842 */
20843 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20844 public final void emitMOV_RegInd_Reg_Byte(GPR dstBase, GPR srcReg) {
20845 int miStart = mi;
20846 // no group 1 to 4 prefix byte
20847 generateREXprefix(false, srcReg, null, dstBase);
20848 // single byte opcode
20849 setMachineCodes(mi++, (byte) 0x88);
20850 emitRegIndirectRegOperands(dstBase, srcReg);
20851 if (lister != null) lister.RNR(miStart, "MOV", dstBase, srcReg);
20852 }
20853
20854 /**
20855 * Generate a register-offset--register MOV. That is,
20856 * <PRE>
20857 * [dstReg<<dstScale + dstDisp] := (byte) srcReg
20858 * </PRE>
20859 *
20860 * @param dstIndex the destination index register
20861 * @param dstScale the destination shift amount
20862 * @param dstDisp the destination displacement
20863 * @param srcReg the source register
20864 */
20865 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
20866 public final void emitMOV_RegOff_Reg_Byte(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
20867 int miStart = mi;
20868 // no group 1 to 4 prefix byte
20869 generateREXprefix(false, srcReg, dstIndex, null);
20870 // single byte opcode
20871 setMachineCodes(mi++, (byte) 0x88);
20872 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
20873 if (lister != null) lister.RFDR(miStart, "MOV", dstIndex, dstScale, dstDisp, srcReg);
20874 }
20875
20876 /**
20877 * Generate a absolute--register MOV. That is,
20878 * <PRE>
20879 * [dstDisp] := (byte) srcReg
20880 * </PRE>
20881 *
20882 * @param dstDisp the destination address
20883 * @param srcReg the source register
20884 */
20885 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
20886 public final void emitMOV_Abs_Reg_Byte(Address dstDisp, GPR srcReg) {
20887 int miStart = mi;
20888 // no group 1 to 4 prefix byte
20889 generateREXprefix(false, srcReg, null, null);
20890 // single byte opcode
20891 setMachineCodes(mi++, (byte) 0x88);
20892 emitAbsRegOperands(dstDisp, srcReg);
20893 if (lister != null) lister.RAR(miStart, "MOV", dstDisp, srcReg);
20894 }
20895
20896 /**
20897 * Generate a register-index--register MOV. That is,
20898 * <PRE>
20899 * [dstBase + dstIndex<<dstScale + dstDisp] := (byte) srcReg
20900 * </PRE>
20901 *
20902 * @param dstBase the base register
20903 * @param dstIndex the destination index register
20904 * @param dstScale the destination shift amount
20905 * @param dstDisp the destination displacement
20906 * @param srcReg the source register
20907 */
20908 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
20909 public final void emitMOV_RegIdx_Reg_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
20910 int miStart = mi;
20911 // no group 1 to 4 prefix byte
20912 generateREXprefix(false, srcReg, dstIndex, dstBase);
20913 // single byte opcode
20914 setMachineCodes(mi++, (byte) 0x88);
20915 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
20916 if (lister != null) lister.RXDR(miStart, "MOV", dstBase, dstIndex, dstScale, dstDisp, srcReg);
20917 }
20918
20919 /**
20920 * Generate a register-displacement--register MOV. That is,
20921 * <PRE>
20922 * [dstBase + dstDisp] := (byte) srcReg
20923 * </PRE>
20924 *
20925 * @param dstBase the base register
20926 * @param dstDisp the destination displacement
20927 * @param srcReg the source register
20928 */
20929 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
20930 public final void emitMOV_RegDisp_Reg_Byte(GPR dstBase, Offset dstDisp, GPR srcReg) {
20931 int miStart = mi;
20932 // no group 1 to 4 prefix byte
20933 generateREXprefix(false, srcReg, null, dstBase);
20934 // single byte opcode
20935 setMachineCodes(mi++, (byte) 0x88);
20936 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
20937 if (lister != null) lister.RDR(miStart, "MOV", dstBase, dstDisp, srcReg);
20938 }
20939
20940 /**
20941 * Generate a register--register MOV. That is,
20942 * <PRE>
20943 * dstReg := (byte) srcReg
20944 * </PRE>
20945 *
20946 * @param dstReg the destination register
20947 * @param srcReg the source register
20948 */
20949 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20950 public final void emitMOV_Reg_Reg_Byte(GPR dstReg, GPR srcReg) {
20951 int miStart = mi;
20952 // no group 1 to 4 prefix byte
20953 generateREXprefix(false, srcReg, null, dstReg);
20954 // single byte opcode
20955 setMachineCodes(mi++, (byte) 0x88);
20956 emitRegRegOperands(dstReg, srcReg);
20957 if (lister != null) lister.RR(miStart, "MOV", dstReg, srcReg);
20958 }
20959
20960 /**
20961 * Generate a register--register-displacement MOV. That is,
20962 * <PRE>
20963 * dstReg := (byte) [srcReg + srcDisp]
20964 * </PRE>
20965 *
20966 * @param dstReg the destination register
20967 * @param srcBase the source register
20968 * @param srcDisp the source displacement
20969 */
20970 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20971 public final void emitMOV_Reg_RegDisp_Byte(GPR dstReg, GPR srcBase, Offset srcDisp) {
20972 int miStart = mi;
20973 // no group 1 to 4 prefix byte
20974 generateREXprefix(false, dstReg, null, srcBase);
20975 // single byte opcode
20976 setMachineCodes(mi++, (byte) 0x8A);
20977 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
20978 if (lister != null) lister.RRD(miStart, "MOV", dstReg, srcBase, srcDisp);
20979 }
20980
20981 /**
20982 * Generate a register--register-offset MOV. That is,
20983 * <PRE>
20984 * dstReg := (byte) [srcIndex<<srcScale + srcDisp]
20985 * </PRE>
20986 *
20987 * @param dstReg the destination register
20988 * @param srcIndex the source index register
20989 * @param srcScale the source shift amount
20990 * @param srcDisp the source displacement
20991 */
20992 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
20993 public final void emitMOV_Reg_RegOff_Byte(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
20994 int miStart = mi;
20995 // no group 1 to 4 prefix byte
20996 generateREXprefix(false, dstReg, srcIndex, null);
20997 // single byte opcode
20998 setMachineCodes(mi++, (byte) 0x8A);
20999 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
21000 if (lister != null) lister.RRFD(miStart, "MOV", dstReg, srcIndex, srcScale, srcDisp);
21001 }
21002
21003 /**
21004 * Generate a register--register-offset MOV. That is,
21005 * <PRE>
21006 * dstReg := (byte) [srcDisp]
21007 * </PRE>
21008 *
21009 * @param dstReg the destination register
21010 * @param srcDisp the source displacement
21011 */
21012 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
21013 public final void emitMOV_Reg_Abs_Byte(GPR dstReg, Address srcDisp) {
21014 int miStart = mi;
21015 // no group 1 to 4 prefix byte
21016 generateREXprefix(false, dstReg, null, null);
21017 // single byte opcode
21018 setMachineCodes(mi++, (byte) 0x8A);
21019 emitAbsRegOperands(srcDisp, dstReg);
21020 if (lister != null) lister.RRA(miStart, "MOV", dstReg, srcDisp);
21021 }
21022
21023 /**
21024 * Generate a register--register-offset MOV. That is,
21025 * <PRE>
21026 * dstReg := (byte) [srcBase + srcIndex<<srcScale + srcDisp]
21027 * </PRE>
21028 *
21029 * @param dstReg the destination register
21030 * @param srcBase the source base register
21031 * @param srcIndex the source index register
21032 * @param srcScale the source shift amount
21033 * @param srcDisp the source displacement
21034 */
21035 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
21036 public final void emitMOV_Reg_RegIdx_Byte(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
21037 int miStart = mi;
21038 // no group 1 to 4 prefix byte
21039 generateREXprefix(false, dstReg, srcIndex, srcBase);
21040 // single byte opcode
21041 setMachineCodes(mi++, (byte) 0x8A);
21042 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
21043 if (lister != null) lister.RRXD(miStart, "MOV", dstReg, srcBase, srcIndex, srcScale, srcDisp);
21044 }
21045
21046 /**
21047 * Generate a register--register(indirect) MOV. That is,
21048 * <PRE>
21049 * dstReg := (byte) [srcBase]
21050 * </PRE>
21051 *
21052 * @param dstReg the destination register
21053 * @param srcBase the source base register
21054 */
21055 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
21056 public final void emitMOV_Reg_RegInd_Byte(GPR dstReg, GPR srcBase) {
21057 int miStart = mi;
21058 // no group 1 to 4 prefix byte
21059 generateREXprefix(false, dstReg, null, srcBase);
21060 // single byte opcode
21061 setMachineCodes(mi++, (byte) 0x8A);
21062 emitRegIndirectRegOperands(srcBase, dstReg);
21063 if (lister != null) lister.RRN(miStart, "MOV", dstReg, srcBase);
21064 }
21065
21066 /**
21067 * Generate a register(indirect)--register MOV. That is,
21068 * <PRE>
21069 * [dstBase] := (word) srcReg
21070 * </PRE>
21071 *
21072 * @param dstBase the destination base
21073 * @param srcReg the source register
21074 */
21075 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
21076 public final void emitMOV_RegInd_Reg_Word(GPR dstBase, GPR srcReg) {
21077 int miStart = mi;
21078 setMachineCodes(mi++, (byte) 0x66);
21079 generateREXprefix(false, srcReg, null, dstBase);
21080 // single byte opcode
21081 setMachineCodes(mi++, (byte) 0x89);
21082 emitRegIndirectRegOperands(dstBase, srcReg);
21083 if (lister != null) lister.RNR(miStart, "MOV", dstBase, srcReg);
21084 }
21085
21086 /**
21087 * Generate a register-offset--register MOV. That is,
21088 * <PRE>
21089 * [dstReg<<dstScale + dstDisp] := (word) srcReg
21090 * </PRE>
21091 *
21092 * @param dstIndex the destination index register
21093 * @param dstScale the destination shift amount
21094 * @param dstDisp the destination displacement
21095 * @param srcReg the source register
21096 */
21097 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
21098 public final void emitMOV_RegOff_Reg_Word(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
21099 int miStart = mi;
21100 setMachineCodes(mi++, (byte) 0x66);
21101 generateREXprefix(false, srcReg, dstIndex, null);
21102 // single byte opcode
21103 setMachineCodes(mi++, (byte) 0x89);
21104 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
21105 if (lister != null) lister.RFDR(miStart, "MOV", dstIndex, dstScale, dstDisp, srcReg);
21106 }
21107
21108 /**
21109 * Generate a absolute--register MOV. That is,
21110 * <PRE>
21111 * [dstDisp] := (word) srcReg
21112 * </PRE>
21113 *
21114 * @param dstDisp the destination address
21115 * @param srcReg the source register
21116 */
21117 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
21118 public final void emitMOV_Abs_Reg_Word(Address dstDisp, GPR srcReg) {
21119 int miStart = mi;
21120 setMachineCodes(mi++, (byte) 0x66);
21121 generateREXprefix(false, srcReg, null, null);
21122 // single byte opcode
21123 setMachineCodes(mi++, (byte) 0x89);
21124 emitAbsRegOperands(dstDisp, srcReg);
21125 if (lister != null) lister.RAR(miStart, "MOV", dstDisp, srcReg);
21126 }
21127
21128 /**
21129 * Generate a register-index--register MOV. That is,
21130 * <PRE>
21131 * [dstBase + dstIndex<<dstScale + dstDisp] := (word) srcReg
21132 * </PRE>
21133 *
21134 * @param dstBase the base register
21135 * @param dstIndex the destination index register
21136 * @param dstScale the destination shift amount
21137 * @param dstDisp the destination displacement
21138 * @param srcReg the source register
21139 */
21140 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
21141 public final void emitMOV_RegIdx_Reg_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
21142 int miStart = mi;
21143 setMachineCodes(mi++, (byte) 0x66);
21144 generateREXprefix(false, srcReg, dstIndex, dstBase);
21145 // single byte opcode
21146 setMachineCodes(mi++, (byte) 0x89);
21147 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
21148 if (lister != null) lister.RXDR(miStart, "MOV", dstBase, dstIndex, dstScale, dstDisp, srcReg);
21149 }
21150
21151 /**
21152 * Generate a register-displacement--register MOV. That is,
21153 * <PRE>
21154 * [dstBase + dstDisp] := (word) srcReg
21155 * </PRE>
21156 *
21157 * @param dstBase the base register
21158 * @param dstDisp the destination displacement
21159 * @param srcReg the source register
21160 */
21161 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
21162 public final void emitMOV_RegDisp_Reg_Word(GPR dstBase, Offset dstDisp, GPR srcReg) {
21163 int miStart = mi;
21164 setMachineCodes(mi++, (byte) 0x66);
21165 generateREXprefix(false, srcReg, null, dstBase);
21166 // single byte opcode
21167 setMachineCodes(mi++, (byte) 0x89);
21168 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
21169 if (lister != null) lister.RDR(miStart, "MOV", dstBase, dstDisp, srcReg);
21170 }
21171
21172 /**
21173 * Generate a register--register MOV. That is,
21174 * <PRE>
21175 * dstReg := (word) srcReg
21176 * </PRE>
21177 *
21178 * @param dstReg the destination register
21179 * @param srcReg the source register
21180 */
21181 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
21182 public final void emitMOV_Reg_Reg_Word(GPR dstReg, GPR srcReg) {
21183 int miStart = mi;
21184 setMachineCodes(mi++, (byte) 0x66);
21185 generateREXprefix(false, srcReg, null, dstReg);
21186 // single byte opcode
21187 setMachineCodes(mi++, (byte) 0x89);
21188 emitRegRegOperands(dstReg, srcReg);
21189 if (lister != null) lister.RR(miStart, "MOV", dstReg, srcReg);
21190 }
21191
21192 /**
21193 * Generate a register--register-displacement MOV. That is,
21194 * <PRE>
21195 * dstReg := (word) [srcReg + srcDisp]
21196 * </PRE>
21197 *
21198 * @param dstReg the destination register
21199 * @param srcBase the source register
21200 * @param srcDisp the source displacement
21201 */
21202 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
21203 public final void emitMOV_Reg_RegDisp_Word(GPR dstReg, GPR srcBase, Offset srcDisp) {
21204 int miStart = mi;
21205 setMachineCodes(mi++, (byte) 0x66);
21206 generateREXprefix(false, dstReg, null, srcBase);
21207 // single byte opcode
21208 setMachineCodes(mi++, (byte) 0x8B);
21209 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
21210 if (lister != null) lister.RRD(miStart, "MOV", dstReg, srcBase, srcDisp);
21211 }
21212
21213 /**
21214 * Generate a register--register-offset MOV. That is,
21215 * <PRE>
21216 * dstReg := (word) [srcIndex<<srcScale + srcDisp]
21217 * </PRE>
21218 *
21219 * @param dstReg the destination register
21220 * @param srcIndex the source index register
21221 * @param srcScale the source shift amount
21222 * @param srcDisp the source displacement
21223 */
21224 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
21225 public final void emitMOV_Reg_RegOff_Word(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
21226 int miStart = mi;
21227 setMachineCodes(mi++, (byte) 0x66);
21228 generateREXprefix(false, dstReg, srcIndex, null);
21229 // single byte opcode
21230 setMachineCodes(mi++, (byte) 0x8B);
21231 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
21232 if (lister != null) lister.RRFD(miStart, "MOV", dstReg, srcIndex, srcScale, srcDisp);
21233 }
21234
21235 /**
21236 * Generate a register--register-offset MOV. That is,
21237 * <PRE>
21238 * dstReg := (word) [srcDisp]
21239 * </PRE>
21240 *
21241 * @param dstReg the destination register
21242 * @param srcDisp the source displacement
21243 */
21244 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
21245 public final void emitMOV_Reg_Abs_Word(GPR dstReg, Address srcDisp) {
21246 int miStart = mi;
21247 setMachineCodes(mi++, (byte) 0x66);
21248 generateREXprefix(false, dstReg, null, null);
21249 // single byte opcode
21250 setMachineCodes(mi++, (byte) 0x8B);
21251 emitAbsRegOperands(srcDisp, dstReg);
21252 if (lister != null) lister.RRA(miStart, "MOV", dstReg, srcDisp);
21253 }
21254
21255 /**
21256 * Generate a register--register-offset MOV. That is,
21257 * <PRE>
21258 * dstReg := (word) [srcBase + srcIndex<<srcScale + srcDisp]
21259 * </PRE>
21260 *
21261 * @param dstReg the destination register
21262 * @param srcBase the source base register
21263 * @param srcIndex the source index register
21264 * @param srcScale the source shift amount
21265 * @param srcDisp the source displacement
21266 */
21267 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
21268 public final void emitMOV_Reg_RegIdx_Word(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
21269 int miStart = mi;
21270 setMachineCodes(mi++, (byte) 0x66);
21271 generateREXprefix(false, dstReg, srcIndex, srcBase);
21272 // single byte opcode
21273 setMachineCodes(mi++, (byte) 0x8B);
21274 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
21275 if (lister != null) lister.RRXD(miStart, "MOV", dstReg, srcBase, srcIndex, srcScale, srcDisp);
21276 }
21277
21278 /**
21279 * Generate a register--register(indirect) MOV. That is,
21280 * <PRE>
21281 * dstReg := (word) [srcBase]
21282 * </PRE>
21283 *
21284 * @param dstReg the destination register
21285 * @param srcBase the source base register
21286 */
21287 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
21288 public final void emitMOV_Reg_RegInd_Word(GPR dstReg, GPR srcBase) {
21289 int miStart = mi;
21290 setMachineCodes(mi++, (byte) 0x66);
21291 generateREXprefix(false, dstReg, null, srcBase);
21292 // single byte opcode
21293 setMachineCodes(mi++, (byte) 0x8B);
21294 emitRegIndirectRegOperands(srcBase, dstReg);
21295 if (lister != null) lister.RRN(miStart, "MOV", dstReg, srcBase);
21296 }
21297
21298 /**
21299 * Generate a register(indirect)--register MOV. That is,
21300 * <PRE>
21301 * [dstBase] := (quad) srcReg
21302 * </PRE>
21303 *
21304 * @param dstBase the destination base
21305 * @param srcReg the source register
21306 */
21307 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
21308 public final void emitMOV_RegInd_Reg_Quad(GPR dstBase, GPR srcReg) {
21309 int miStart = mi;
21310 // no group 1 to 4 prefix byte
21311 generateREXprefix(true, srcReg, null, dstBase);
21312 // single byte opcode
21313 setMachineCodes(mi++, (byte) 0x89);
21314 emitRegIndirectRegOperands(dstBase, srcReg);
21315 if (lister != null) lister.RNR(miStart, "MOV", dstBase, srcReg);
21316 }
21317
21318 /**
21319 * Generate a register-offset--register MOV. That is,
21320 * <PRE>
21321 * [dstReg<<dstScale + dstDisp] := (quad) srcReg
21322 * </PRE>
21323 *
21324 * @param dstIndex the destination index register
21325 * @param dstScale the destination shift amount
21326 * @param dstDisp the destination displacement
21327 * @param srcReg the source register
21328 */
21329 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
21330 public final void emitMOV_RegOff_Reg_Quad(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
21331 int miStart = mi;
21332 // no group 1 to 4 prefix byte
21333 generateREXprefix(true, srcReg, dstIndex, null);
21334 // single byte opcode
21335 setMachineCodes(mi++, (byte) 0x89);
21336 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
21337 if (lister != null) lister.RFDR(miStart, "MOV", dstIndex, dstScale, dstDisp, srcReg);
21338 }
21339
21340 /**
21341 * Generate a absolute--register MOV. That is,
21342 * <PRE>
21343 * [dstDisp] := (quad) srcReg
21344 * </PRE>
21345 *
21346 * @param dstDisp the destination address
21347 * @param srcReg the source register
21348 */
21349 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
21350 public final void emitMOV_Abs_Reg_Quad(Address dstDisp, GPR srcReg) {
21351 int miStart = mi;
21352 // no group 1 to 4 prefix byte
21353 generateREXprefix(true, srcReg, null, null);
21354 // single byte opcode
21355 setMachineCodes(mi++, (byte) 0x89);
21356 emitAbsRegOperands(dstDisp, srcReg);
21357 if (lister != null) lister.RAR(miStart, "MOV", dstDisp, srcReg);
21358 }
21359
21360 /**
21361 * Generate a register-index--register MOV. That is,
21362 * <PRE>
21363 * [dstBase + dstIndex<<dstScale + dstDisp] := (quad) srcReg
21364 * </PRE>
21365 *
21366 * @param dstBase the base register
21367 * @param dstIndex the destination index register
21368 * @param dstScale the destination shift amount
21369 * @param dstDisp the destination displacement
21370 * @param srcReg the source register
21371 */
21372 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
21373 public final void emitMOV_RegIdx_Reg_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
21374 int miStart = mi;
21375 // no group 1 to 4 prefix byte
21376 generateREXprefix(true, srcReg, dstIndex, dstBase);
21377 // single byte opcode
21378 setMachineCodes(mi++, (byte) 0x89);
21379 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
21380 if (lister != null) lister.RXDR(miStart, "MOV", dstBase, dstIndex, dstScale, dstDisp, srcReg);
21381 }
21382
21383 /**
21384 * Generate a register-displacement--register MOV. That is,
21385 * <PRE>
21386 * [dstBase + dstDisp] := (quad) srcReg
21387 * </PRE>
21388 *
21389 * @param dstBase the base register
21390 * @param dstDisp the destination displacement
21391 * @param srcReg the source register
21392 */
21393 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
21394 public final void emitMOV_RegDisp_Reg_Quad(GPR dstBase, Offset dstDisp, GPR srcReg) {
21395 int miStart = mi;
21396 // no group 1 to 4 prefix byte
21397 generateREXprefix(true, srcReg, null, dstBase);
21398 // single byte opcode
21399 setMachineCodes(mi++, (byte) 0x89);
21400 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
21401 if (lister != null) lister.RDR(miStart, "MOV", dstBase, dstDisp, srcReg);
21402 }
21403
21404 /**
21405 * Generate a register--register MOV. That is,
21406 * <PRE>
21407 * dstReg := (quad) srcReg
21408 * </PRE>
21409 *
21410 * @param dstReg the destination register
21411 * @param srcReg the source register
21412 */
21413 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
21414 public final void emitMOV_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
21415 int miStart = mi;
21416 // no group 1 to 4 prefix byte
21417 generateREXprefix(true, srcReg, null, dstReg);
21418 // single byte opcode
21419 setMachineCodes(mi++, (byte) 0x89);
21420 emitRegRegOperands(dstReg, srcReg);
21421 if (lister != null) lister.RR(miStart, "MOV", dstReg, srcReg);
21422 }
21423
21424 /**
21425 * Generate a register--register-displacement MOV. That is,
21426 * <PRE>
21427 * dstReg := (quad) [srcReg + srcDisp]
21428 * </PRE>
21429 *
21430 * @param dstReg the destination register
21431 * @param srcBase the source register
21432 * @param srcDisp the source displacement
21433 */
21434 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
21435 public final void emitMOV_Reg_RegDisp_Quad(GPR dstReg, GPR srcBase, Offset srcDisp) {
21436 int miStart = mi;
21437 // no group 1 to 4 prefix byte
21438 generateREXprefix(true, dstReg, null, srcBase);
21439 // single byte opcode
21440 setMachineCodes(mi++, (byte) 0x8B);
21441 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
21442 if (lister != null) lister.RRD(miStart, "MOV", dstReg, srcBase, srcDisp);
21443 }
21444
21445 /**
21446 * Generate a register--register-offset MOV. That is,
21447 * <PRE>
21448 * dstReg := (quad) [srcIndex<<srcScale + srcDisp]
21449 * </PRE>
21450 *
21451 * @param dstReg the destination register
21452 * @param srcIndex the source index register
21453 * @param srcScale the source shift amount
21454 * @param srcDisp the source displacement
21455 */
21456 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
21457 public final void emitMOV_Reg_RegOff_Quad(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
21458 int miStart = mi;
21459 // no group 1 to 4 prefix byte
21460 generateREXprefix(true, dstReg, srcIndex, null);
21461 // single byte opcode
21462 setMachineCodes(mi++, (byte) 0x8B);
21463 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
21464 if (lister != null) lister.RRFD(miStart, "MOV", dstReg, srcIndex, srcScale, srcDisp);
21465 }
21466
21467 /**
21468 * Generate a register--register-offset MOV. That is,
21469 * <PRE>
21470 * dstReg := (quad) [srcDisp]
21471 * </PRE>
21472 *
21473 * @param dstReg the destination register
21474 * @param srcDisp the source displacement
21475 */
21476 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
21477 public final void emitMOV_Reg_Abs_Quad(GPR dstReg, Address srcDisp) {
21478 int miStart = mi;
21479 // no group 1 to 4 prefix byte
21480 generateREXprefix(true, dstReg, null, null);
21481 // single byte opcode
21482 setMachineCodes(mi++, (byte) 0x8B);
21483 emitAbsRegOperands(srcDisp, dstReg);
21484 if (lister != null) lister.RRA(miStart, "MOV", dstReg, srcDisp);
21485 }
21486
21487 /**
21488 * Generate a register--register-offset MOV. That is,
21489 * <PRE>
21490 * dstReg := (quad) [srcBase + srcIndex<<srcScale + srcDisp]
21491 * </PRE>
21492 *
21493 * @param dstReg the destination register
21494 * @param srcBase the source base register
21495 * @param srcIndex the source index register
21496 * @param srcScale the source shift amount
21497 * @param srcDisp the source displacement
21498 */
21499 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
21500 public final void emitMOV_Reg_RegIdx_Quad(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
21501 int miStart = mi;
21502 // no group 1 to 4 prefix byte
21503 generateREXprefix(true, dstReg, srcIndex, srcBase);
21504 // single byte opcode
21505 setMachineCodes(mi++, (byte) 0x8B);
21506 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
21507 if (lister != null) lister.RRXD(miStart, "MOV", dstReg, srcBase, srcIndex, srcScale, srcDisp);
21508 }
21509
21510 /**
21511 * Generate a register--register(indirect) MOV. That is,
21512 * <PRE>
21513 * dstReg := (quad) [srcBase]
21514 * </PRE>
21515 *
21516 * @param dstReg the destination register
21517 * @param srcBase the source base register
21518 */
21519 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
21520 public final void emitMOV_Reg_RegInd_Quad(GPR dstReg, GPR srcBase) {
21521 int miStart = mi;
21522 // no group 1 to 4 prefix byte
21523 generateREXprefix(true, dstReg, null, srcBase);
21524 // single byte opcode
21525 setMachineCodes(mi++, (byte) 0x8B);
21526 emitRegIndirectRegOperands(srcBase, dstReg);
21527 if (lister != null) lister.RRN(miStart, "MOV", dstReg, srcBase);
21528 }
21529
21530 /**
21531 * Generate a register-indirect--immediate MOV. That is,
21532 * <PRE>
21533 * [dstBase] MOV = imm
21534 * </PRE>
21535 *
21536 * @param dstBase the destination base register
21537 * @param imm immediate
21538 */
21539 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
21540 public final void emitMOV_RegInd_Imm_Byte(GPR dstBase, int imm) {
21541 int miStart = mi;
21542 // no prefix byte
21543 generateREXprefix(false, null, null, dstBase);
21544 setMachineCodes(mi++, (byte) 0xC6);
21545 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
21546 emitImm8(imm);
21547 if (lister != null) lister.RNI(miStart, "MOV", dstBase, imm);
21548 }
21549
21550 /**
21551 * Generate a register-displacement--immediate MOV. That is,
21552 * <PRE>
21553 * [dstBase + dstDisp] MOV = imm
21554 * </PRE>
21555 *
21556 * @param dstBase the destination base register
21557 * @param dstDisp the destination displacement
21558 * @param imm immediate
21559 */
21560 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
21561 public final void emitMOV_RegDisp_Imm_Byte(GPR dstBase, Offset dstDisp, int imm) {
21562 int miStart = mi;
21563 // no prefix byte
21564 generateREXprefix(false, null, null, dstBase);
21565 setMachineCodes(mi++, (byte) 0xC6);
21566 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
21567 emitImm8(imm);
21568 if (lister != null) lister.RDI(miStart, "MOV", dstBase, dstDisp, imm);
21569 }
21570
21571 /**
21572 * Generate a register-index--immediate MOV. That is,
21573 * <PRE>
21574 * [dstBase + dstIndex<<scale + dstDisp] MOV = imm
21575 * </PRE>
21576 *
21577 * @param dstBase the destination base register
21578 * @param dstIndex the destination index register
21579 * @param dstScale the destination shift amount
21580 * @param dstDisp the destination displacement
21581 * @param imm immediate
21582 */
21583 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
21584 public final void emitMOV_RegIdx_Imm_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
21585 int miStart = mi;
21586 // no prefix byte
21587 generateREXprefix(false, null, dstIndex, dstBase);
21588 setMachineCodes(mi++, (byte) 0xC6);
21589 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
21590 emitImm8(imm);
21591 if (lister != null) lister.RXDI(miStart, "MOV", dstBase, dstIndex, dstScale, dstDisp, imm);
21592 }
21593
21594 /**
21595 * Generate a register-index--immediate MOV. That is,
21596 * <PRE>
21597 * [dstIndex<<scale + dstDisp] MOV = imm
21598 * </PRE>
21599 *
21600 * @param dstIndex the destination index register
21601 * @param dstScale the destination shift amount
21602 * @param dstDisp the destination displacement
21603 * @param imm immediate
21604 */
21605 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
21606 public final void emitMOV_RegOff_Imm_Byte(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
21607 int miStart = mi;
21608 // no prefix byte
21609 generateREXprefix(false, null, dstIndex, null);
21610 setMachineCodes(mi++, (byte) 0xC6);
21611 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
21612 emitImm8(imm);
21613 if (lister != null) lister.RFDI(miStart, "MOV", dstIndex, dstScale, dstDisp, imm);
21614 }
21615
21616 /**
21617 * Generate an absolute MOV. That is,
21618 * <PRE>
21619 * [dstDisp] MOV = imm
21620 * </PRE>
21621 *
21622 * @param dstDisp the destination displacement
21623 * @param imm immediate
21624 */
21625 public final void emitMOV_Abs_Imm_Byte(Address dstDisp, int imm) {
21626 int miStart = mi;
21627 // no prefix byte
21628 generateREXprefix(false, null, null, null);
21629 setMachineCodes(mi++, (byte) 0xC6);
21630 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
21631 emitImm8(imm);
21632 if (lister != null) lister.RAI(miStart, "MOV", dstDisp, imm);
21633 }
21634
21635 /**
21636 * Generate a register-indirect--immediate MOV. That is,
21637 * <PRE>
21638 * [dstBase] MOV = imm
21639 * </PRE>
21640 *
21641 * @param dstBase the destination base register
21642 * @param imm immediate
21643 */
21644 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
21645 public final void emitMOV_RegInd_Imm_Word(GPR dstBase, int imm) {
21646 int miStart = mi;
21647 setMachineCodes(mi++, (byte) 0x66);
21648 generateREXprefix(false, null, null, dstBase);
21649 setMachineCodes(mi++, (byte) 0xC7);
21650 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
21651 emitImm16(imm);
21652 if (lister != null) lister.RNI(miStart, "MOV", dstBase, imm);
21653 }
21654
21655 /**
21656 * Generate a register-displacement--immediate MOV. That is,
21657 * <PRE>
21658 * [dstBase + dstDisp] MOV = imm
21659 * </PRE>
21660 *
21661 * @param dstBase the destination base register
21662 * @param dstDisp the destination displacement
21663 * @param imm immediate
21664 */
21665 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
21666 public final void emitMOV_RegDisp_Imm_Word(GPR dstBase, Offset dstDisp, int imm) {
21667 int miStart = mi;
21668 setMachineCodes(mi++, (byte) 0x66);
21669 generateREXprefix(false, null, null, dstBase);
21670 setMachineCodes(mi++, (byte) 0xC7);
21671 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
21672 emitImm16(imm);
21673 if (lister != null) lister.RDI(miStart, "MOV", dstBase, dstDisp, imm);
21674 }
21675
21676 /**
21677 * Generate a register-index--immediate MOV. That is,
21678 * <PRE>
21679 * [dstBase + dstIndex<<scale + dstDisp] MOV = imm
21680 * </PRE>
21681 *
21682 * @param dstBase the destination base register
21683 * @param dstIndex the destination index register
21684 * @param dstScale the destination shift amount
21685 * @param dstDisp the destination displacement
21686 * @param imm immediate
21687 */
21688 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
21689 public final void emitMOV_RegIdx_Imm_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
21690 int miStart = mi;
21691 setMachineCodes(mi++, (byte) 0x66);
21692 generateREXprefix(false, null, dstIndex, dstBase);
21693 setMachineCodes(mi++, (byte) 0xC7);
21694 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
21695 emitImm16(imm);
21696 if (lister != null) lister.RXDI(miStart, "MOV", dstBase, dstIndex, dstScale, dstDisp, imm);
21697 }
21698
21699 /**
21700 * Generate a register-index--immediate MOV. That is,
21701 * <PRE>
21702 * [dstIndex<<scale + dstDisp] MOV = imm
21703 * </PRE>
21704 *
21705 * @param dstIndex the destination index register
21706 * @param dstScale the destination shift amount
21707 * @param dstDisp the destination displacement
21708 * @param imm immediate
21709 */
21710 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
21711 public final void emitMOV_RegOff_Imm_Word(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
21712 int miStart = mi;
21713 setMachineCodes(mi++, (byte) 0x66);
21714 generateREXprefix(false, null, dstIndex, null);
21715 setMachineCodes(mi++, (byte) 0xC7);
21716 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
21717 emitImm16(imm);
21718 if (lister != null) lister.RFDI(miStart, "MOV", dstIndex, dstScale, dstDisp, imm);
21719 }
21720
21721 /**
21722 * Generate an absolute MOV. That is,
21723 * <PRE>
21724 * [dstDisp] MOV = imm
21725 * </PRE>
21726 *
21727 * @param dstDisp the destination displacement
21728 * @param imm immediate
21729 */
21730 public final void emitMOV_Abs_Imm_Word(Address dstDisp, int imm) {
21731 int miStart = mi;
21732 setMachineCodes(mi++, (byte) 0x66);
21733 generateREXprefix(false, null, null, null);
21734 setMachineCodes(mi++, (byte) 0xC7);
21735 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
21736 emitImm16(imm);
21737 if (lister != null) lister.RAI(miStart, "MOV", dstDisp, imm);
21738 }
21739
21740 /**
21741 * Generate a register-indirect--immediate MOV. That is,
21742 * <PRE>
21743 * [dstBase] MOV = imm
21744 * </PRE>
21745 *
21746 * @param dstBase the destination base register
21747 * @param imm immediate
21748 */
21749 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
21750 public final void emitMOV_RegInd_Imm(GPR dstBase, int imm) {
21751 int miStart = mi;
21752 // no prefix byte
21753 generateREXprefix(false, null, null, dstBase);
21754 setMachineCodes(mi++, (byte) 0xC7);
21755 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
21756 emitImm32(imm);
21757 if (lister != null) lister.RNI(miStart, "MOV", dstBase, imm);
21758 }
21759
21760 /**
21761 * Generate a register-displacement--immediate MOV. That is,
21762 * <PRE>
21763 * [dstBase + dstDisp] MOV = imm
21764 * </PRE>
21765 *
21766 * @param dstBase the destination base register
21767 * @param dstDisp the destination displacement
21768 * @param imm immediate
21769 */
21770 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
21771 public final void emitMOV_RegDisp_Imm(GPR dstBase, Offset dstDisp, int imm) {
21772 int miStart = mi;
21773 // no prefix byte
21774 generateREXprefix(false, null, null, dstBase);
21775 setMachineCodes(mi++, (byte) 0xC7);
21776 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
21777 emitImm32(imm);
21778 if (lister != null) lister.RDI(miStart, "MOV", dstBase, dstDisp, imm);
21779 }
21780
21781 /**
21782 * Generate a register-index--immediate MOV. That is,
21783 * <PRE>
21784 * [dstBase + dstIndex<<scale + dstDisp] MOV = imm
21785 * </PRE>
21786 *
21787 * @param dstBase the destination base register
21788 * @param dstIndex the destination index register
21789 * @param dstScale the destination shift amount
21790 * @param dstDisp the destination displacement
21791 * @param imm immediate
21792 */
21793 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
21794 public final void emitMOV_RegIdx_Imm(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
21795 int miStart = mi;
21796 // no prefix byte
21797 generateREXprefix(false, null, dstIndex, dstBase);
21798 setMachineCodes(mi++, (byte) 0xC7);
21799 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
21800 emitImm32(imm);
21801 if (lister != null) lister.RXDI(miStart, "MOV", dstBase, dstIndex, dstScale, dstDisp, imm);
21802 }
21803
21804 /**
21805 * Generate a register-index--immediate MOV. That is,
21806 * <PRE>
21807 * [dstIndex<<scale + dstDisp] MOV = imm
21808 * </PRE>
21809 *
21810 * @param dstIndex the destination index register
21811 * @param dstScale the destination shift amount
21812 * @param dstDisp the destination displacement
21813 * @param imm immediate
21814 */
21815 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
21816 public final void emitMOV_RegOff_Imm(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
21817 int miStart = mi;
21818 // no prefix byte
21819 generateREXprefix(false, null, dstIndex, null);
21820 setMachineCodes(mi++, (byte) 0xC7);
21821 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
21822 emitImm32(imm);
21823 if (lister != null) lister.RFDI(miStart, "MOV", dstIndex, dstScale, dstDisp, imm);
21824 }
21825
21826 /**
21827 * Generate an absolute MOV. That is,
21828 * <PRE>
21829 * [dstDisp] MOV = imm
21830 * </PRE>
21831 *
21832 * @param dstDisp the destination displacement
21833 * @param imm immediate
21834 */
21835 public final void emitMOV_Abs_Imm(Address dstDisp, int imm) {
21836 int miStart = mi;
21837 // no prefix byte
21838 generateREXprefix(false, null, null, null);
21839 setMachineCodes(mi++, (byte) 0xC7);
21840 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
21841 emitImm32(imm);
21842 if (lister != null) lister.RAI(miStart, "MOV", dstDisp, imm);
21843 }
21844
21845 /**
21846 * Generate a register-indirect--immediate MOV. That is,
21847 * <PRE>
21848 * [dstBase] MOV = imm
21849 * </PRE>
21850 *
21851 * @param dstBase the destination base register
21852 * @param imm immediate
21853 */
21854 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
21855 public final void emitMOV_RegInd_Imm_Quad(GPR dstBase, int imm) {
21856 int miStart = mi;
21857 // no prefix byte
21858 generateREXprefix(true, null, null, dstBase);
21859 setMachineCodes(mi++, (byte) 0xC7);
21860 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
21861 emitImm32(imm);
21862 if (lister != null) lister.RNI(miStart, "MOV", dstBase, imm);
21863 }
21864
21865 /**
21866 * Generate a register-displacement--immediate MOV. That is,
21867 * <PRE>
21868 * [dstBase + dstDisp] MOV = imm
21869 * </PRE>
21870 *
21871 * @param dstBase the destination base register
21872 * @param dstDisp the destination displacement
21873 * @param imm immediate
21874 */
21875 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
21876 public final void emitMOV_RegDisp_Imm_Quad(GPR dstBase, Offset dstDisp, int imm) {
21877 int miStart = mi;
21878 // no prefix byte
21879 generateREXprefix(true, null, null, dstBase);
21880 setMachineCodes(mi++, (byte) 0xC7);
21881 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
21882 emitImm32(imm);
21883 if (lister != null) lister.RDI(miStart, "MOV", dstBase, dstDisp, imm);
21884 }
21885
21886 /**
21887 * Generate a register-index--immediate MOV. That is,
21888 * <PRE>
21889 * [dstBase + dstIndex<<scale + dstDisp] MOV = imm
21890 * </PRE>
21891 *
21892 * @param dstBase the destination base register
21893 * @param dstIndex the destination index register
21894 * @param dstScale the destination shift amount
21895 * @param dstDisp the destination displacement
21896 * @param imm immediate
21897 */
21898 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
21899 public final void emitMOV_RegIdx_Imm_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
21900 int miStart = mi;
21901 // no prefix byte
21902 generateREXprefix(true, null, dstIndex, dstBase);
21903 setMachineCodes(mi++, (byte) 0xC7);
21904 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
21905 emitImm32(imm);
21906 if (lister != null) lister.RXDI(miStart, "MOV", dstBase, dstIndex, dstScale, dstDisp, imm);
21907 }
21908
21909 /**
21910 * Generate a register-index--immediate MOV. That is,
21911 * <PRE>
21912 * [dstIndex<<scale + dstDisp] MOV = imm
21913 * </PRE>
21914 *
21915 * @param dstIndex the destination index register
21916 * @param dstScale the destination shift amount
21917 * @param dstDisp the destination displacement
21918 * @param imm immediate
21919 */
21920 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
21921 public final void emitMOV_RegOff_Imm_Quad(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
21922 int miStart = mi;
21923 // no prefix byte
21924 generateREXprefix(true, null, dstIndex, null);
21925 setMachineCodes(mi++, (byte) 0xC7);
21926 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
21927 emitImm32(imm);
21928 if (lister != null) lister.RFDI(miStart, "MOV", dstIndex, dstScale, dstDisp, imm);
21929 }
21930
21931 /**
21932 * Generate an absolute MOV. That is,
21933 * <PRE>
21934 * [dstDisp] MOV = imm
21935 * </PRE>
21936 *
21937 * @param dstDisp the destination displacement
21938 * @param imm immediate
21939 */
21940 public final void emitMOV_Abs_Imm_Quad(Address dstDisp, int imm) {
21941 int miStart = mi;
21942 // no prefix byte
21943 generateREXprefix(true, null, null, null);
21944 setMachineCodes(mi++, (byte) 0xC7);
21945 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
21946 emitImm32(imm);
21947 if (lister != null) lister.RAI(miStart, "MOV", dstDisp, imm);
21948 }
21949
21950 /**
21951 * Generate a move sign extended from register. That is,
21952 * <PRE>
21953 * dstReg := (byte) srcReg (sign extended)
21954 * </PRE>
21955 *
21956 * @param dstReg the destination register
21957 * @param srcReg the source register
21958 */
21959 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
21960 public final void emitMOVSX_Reg_Reg_Byte(GPR dstReg, GPR srcReg) {
21961 int miStart = mi;
21962 generateREXprefix(false, dstReg, null, srcReg);
21963 setMachineCodes(mi++, (byte) 0x0F);
21964 setMachineCodes(mi++, (byte) 0xBE);
21965 emitRegRegOperands(srcReg, dstReg);
21966 if (lister != null) lister.RR(miStart, "MOVSX", dstReg, srcReg);
21967 }
21968
21969 /**
21970 * Generate a move sign extended from register displacement. That is,
21971 * <PRE>
21972 * dstReg := (byte) [srcBase + srcDisp] (sign extended)
21973 * </PRE>
21974 *
21975 * @param dstReg the destination register
21976 * @param srcBase the source base register
21977 * @param srcDisp the source displacement
21978 */
21979 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
21980 public final void emitMOVSX_Reg_RegDisp_Byte(GPR dstReg, GPR srcBase, Offset srcDisp) {
21981 int miStart = mi;
21982 generateREXprefix(false, dstReg, null, srcBase);
21983 setMachineCodes(mi++, (byte) 0x0F);
21984 setMachineCodes(mi++, (byte) 0xBE);
21985 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
21986 if (lister != null) lister.RRD(miStart, "MOVSX", dstReg, srcBase, srcDisp);
21987 }
21988
21989 /**
21990 * Generate a move sign extended from register indirect. That is,
21991 * <PRE>
21992 * dstReg := (byte) [srcBase] (sign extended)
21993 * </PRE>
21994 *
21995 * @param dstReg the destination register
21996 * @param srcBase the source base register
21997 */
21998 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
21999 public final void emitMOVSX_Reg_RegInd_Byte(GPR dstReg, GPR srcBase) {
22000 int miStart = mi;
22001 generateREXprefix(false, dstReg, null, srcBase);
22002 setMachineCodes(mi++, (byte) 0x0F);
22003 setMachineCodes(mi++, (byte) 0xBE);
22004 emitRegIndirectRegOperands(srcBase, dstReg);
22005 if (lister != null) lister.RRN(miStart, "MOVSX", dstReg, srcBase);
22006 }
22007
22008 /**
22009 * Generate a move sign extended from register offset. That is,
22010 * <PRE>
22011 * dstReg := (byte) [srcIndex<<srcScale + srcDisp] (sign extended)
22012 * </PRE>
22013 *
22014 * @param dstReg the destination register
22015 * @param srcIndex the source index register
22016 * @param srcScale the source scale of the index
22017 * @param srcDisp the source displacement
22018 */
22019 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
22020 public final void emitMOVSX_Reg_RegOff_Byte(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
22021 int miStart = mi;
22022 generateREXprefix(false, dstReg, srcIndex, null);
22023 setMachineCodes(mi++, (byte) 0x0F);
22024 setMachineCodes(mi++, (byte) 0xBE);
22025 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
22026 if (lister != null) lister.RRFD(miStart, "MOVSX", dstReg, srcIndex, srcScale, srcDisp);
22027 }
22028
22029 /**
22030 * Generate a move sign extended from an absolute address. That is,
22031 * <PRE>
22032 * dstReg := (byte) [srcDisp] (sign extended)
22033 * </PRE>
22034 *
22035 * @param dstReg the destination register
22036 * @param srcDisp the source displacement
22037 */
22038 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
22039 public final void emitMOVSX_Reg_Abs_Byte(GPR dstReg, Address srcDisp) {
22040 int miStart = mi;
22041 generateREXprefix(false, dstReg, null, null);
22042 setMachineCodes(mi++, (byte) 0x0F);
22043 setMachineCodes(mi++, (byte) 0xBE);
22044 emitAbsRegOperands(srcDisp, dstReg);
22045 if (lister != null) lister.RRA(miStart, "MOVSX", dstReg, srcDisp);
22046 }
22047
22048 /**
22049 * Generate a move sign extended by register indexed. That is,
22050 * <PRE>
22051 * dstReg := (byte) [srcBase + srcIndex<<srcScale + srcDisp] (sign extended)
22052 * </PRE>
22053 *
22054 * @param dstReg the destination register
22055 * @param srcBase the source base register
22056 * @param srcIndex the source index register
22057 * @param srcScale the source scale of the index
22058 * @param srcDisp the source displacement
22059 */
22060 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
22061 public final void emitMOVSX_Reg_RegIdx_Byte(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
22062 int miStart = mi;
22063 generateREXprefix(false, dstReg, srcIndex, srcBase);
22064 setMachineCodes(mi++, (byte) 0x0F);
22065 setMachineCodes(mi++, (byte) 0xBE);
22066 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
22067 if (lister != null) lister.RRXD(miStart, "MOVSX", dstReg, srcBase, srcIndex, srcScale, srcDisp);
22068 }
22069
22070 /**
22071 * Generate a move sign extended from register. That is,
22072 * <PRE>
22073 * dstReg := (word) srcReg (sign extended)
22074 * </PRE>
22075 *
22076 * @param dstReg the destination register
22077 * @param srcReg the source register
22078 */
22079 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
22080 public final void emitMOVSX_Reg_Reg_Word(GPR dstReg, GPR srcReg) {
22081 int miStart = mi;
22082 generateREXprefix(false, dstReg, null, srcReg);
22083 setMachineCodes(mi++, (byte) 0x0F);
22084 setMachineCodes(mi++, (byte) 0xBF);
22085 emitRegRegOperands(srcReg, dstReg);
22086 if (lister != null) lister.RR(miStart, "MOVSX", dstReg, srcReg);
22087 }
22088
22089 /**
22090 * Generate a move sign extended from register displacement. That is,
22091 * <PRE>
22092 * dstReg := (word) [srcBase + srcDisp] (sign extended)
22093 * </PRE>
22094 *
22095 * @param dstReg the destination register
22096 * @param srcBase the source base register
22097 * @param srcDisp the source displacement
22098 */
22099 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
22100 public final void emitMOVSX_Reg_RegDisp_Word(GPR dstReg, GPR srcBase, Offset srcDisp) {
22101 int miStart = mi;
22102 generateREXprefix(false, dstReg, null, srcBase);
22103 setMachineCodes(mi++, (byte) 0x0F);
22104 setMachineCodes(mi++, (byte) 0xBF);
22105 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
22106 if (lister != null) lister.RRD(miStart, "MOVSX", dstReg, srcBase, srcDisp);
22107 }
22108
22109 /**
22110 * Generate a move sign extended from register indirect. That is,
22111 * <PRE>
22112 * dstReg := (word) [srcBase] (sign extended)
22113 * </PRE>
22114 *
22115 * @param dstReg the destination register
22116 * @param srcBase the source base register
22117 */
22118 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
22119 public final void emitMOVSX_Reg_RegInd_Word(GPR dstReg, GPR srcBase) {
22120 int miStart = mi;
22121 generateREXprefix(false, dstReg, null, srcBase);
22122 setMachineCodes(mi++, (byte) 0x0F);
22123 setMachineCodes(mi++, (byte) 0xBF);
22124 emitRegIndirectRegOperands(srcBase, dstReg);
22125 if (lister != null) lister.RRN(miStart, "MOVSX", dstReg, srcBase);
22126 }
22127
22128 /**
22129 * Generate a move sign extended from register offset. That is,
22130 * <PRE>
22131 * dstReg := (word) [srcIndex<<srcScale + srcDisp] (sign extended)
22132 * </PRE>
22133 *
22134 * @param dstReg the destination register
22135 * @param srcIndex the source index register
22136 * @param srcScale the source scale of the index
22137 * @param srcDisp the source displacement
22138 */
22139 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
22140 public final void emitMOVSX_Reg_RegOff_Word(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
22141 int miStart = mi;
22142 generateREXprefix(false, dstReg, srcIndex, null);
22143 setMachineCodes(mi++, (byte) 0x0F);
22144 setMachineCodes(mi++, (byte) 0xBF);
22145 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
22146 if (lister != null) lister.RRFD(miStart, "MOVSX", dstReg, srcIndex, srcScale, srcDisp);
22147 }
22148
22149 /**
22150 * Generate a move sign extended from an absolute address. That is,
22151 * <PRE>
22152 * dstReg := (word) [srcDisp] (sign extended)
22153 * </PRE>
22154 *
22155 * @param dstReg the destination register
22156 * @param srcDisp the source displacement
22157 */
22158 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
22159 public final void emitMOVSX_Reg_Abs_Word(GPR dstReg, Address srcDisp) {
22160 int miStart = mi;
22161 generateREXprefix(false, dstReg, null, null);
22162 setMachineCodes(mi++, (byte) 0x0F);
22163 setMachineCodes(mi++, (byte) 0xBF);
22164 emitAbsRegOperands(srcDisp, dstReg);
22165 if (lister != null) lister.RRA(miStart, "MOVSX", dstReg, srcDisp);
22166 }
22167
22168 /**
22169 * Generate a move sign extended by register indexed. That is,
22170 * <PRE>
22171 * dstReg := (word) [srcBase + srcIndex<<srcScale + srcDisp] (sign extended)
22172 * </PRE>
22173 *
22174 * @param dstReg the destination register
22175 * @param srcBase the source base register
22176 * @param srcIndex the source index register
22177 * @param srcScale the source scale of the index
22178 * @param srcDisp the source displacement
22179 */
22180 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
22181 public final void emitMOVSX_Reg_RegIdx_Word(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
22182 int miStart = mi;
22183 generateREXprefix(false, dstReg, srcIndex, srcBase);
22184 setMachineCodes(mi++, (byte) 0x0F);
22185 setMachineCodes(mi++, (byte) 0xBF);
22186 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
22187 if (lister != null) lister.RRXD(miStart, "MOVSX", dstReg, srcBase, srcIndex, srcScale, srcDisp);
22188 }
22189
22190 /**
22191 * Generate a move sign extended from register. That is,
22192 * <PRE>
22193 * dstReg := (byte) srcReg (sign extended)
22194 * </PRE>
22195 *
22196 * @param dstReg the destination register
22197 * @param srcReg the source register
22198 */
22199 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
22200 public final void emitMOVSXQ_Reg_Reg_Byte(GPR dstReg, GPR srcReg) {
22201 int miStart = mi;
22202 generateREXprefix(true, dstReg, null, srcReg);
22203 setMachineCodes(mi++, (byte) 0x0F);
22204 setMachineCodes(mi++, (byte) 0xBE);
22205 emitRegRegOperands(srcReg, dstReg);
22206 if (lister != null) lister.RR(miStart, "MOVSXQ", dstReg, srcReg);
22207 }
22208
22209 /**
22210 * Generate a move sign extended from register displacement. That is,
22211 * <PRE>
22212 * dstReg := (byte) [srcBase + srcDisp] (sign extended)
22213 * </PRE>
22214 *
22215 * @param dstReg the destination register
22216 * @param srcBase the source base register
22217 * @param srcDisp the source displacement
22218 */
22219 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
22220 public final void emitMOVSXQ_Reg_RegDisp_Byte(GPR dstReg, GPR srcBase, Offset srcDisp) {
22221 int miStart = mi;
22222 generateREXprefix(true, dstReg, null, srcBase);
22223 setMachineCodes(mi++, (byte) 0x0F);
22224 setMachineCodes(mi++, (byte) 0xBE);
22225 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
22226 if (lister != null) lister.RRD(miStart, "MOVSXQ", dstReg, srcBase, srcDisp);
22227 }
22228
22229 /**
22230 * Generate a move sign extended from register indirect. That is,
22231 * <PRE>
22232 * dstReg := (byte) [srcBase] (sign extended)
22233 * </PRE>
22234 *
22235 * @param dstReg the destination register
22236 * @param srcBase the source base register
22237 */
22238 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
22239 public final void emitMOVSXQ_Reg_RegInd_Byte(GPR dstReg, GPR srcBase) {
22240 int miStart = mi;
22241 generateREXprefix(true, dstReg, null, srcBase);
22242 setMachineCodes(mi++, (byte) 0x0F);
22243 setMachineCodes(mi++, (byte) 0xBE);
22244 emitRegIndirectRegOperands(srcBase, dstReg);
22245 if (lister != null) lister.RRN(miStart, "MOVSXQ", dstReg, srcBase);
22246 }
22247
22248 /**
22249 * Generate a move sign extended from register offset. That is,
22250 * <PRE>
22251 * dstReg := (byte) [srcIndex<<srcScale + srcDisp] (sign extended)
22252 * </PRE>
22253 *
22254 * @param dstReg the destination register
22255 * @param srcIndex the source index register
22256 * @param srcScale the source scale of the index
22257 * @param srcDisp the source displacement
22258 */
22259 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
22260 public final void emitMOVSXQ_Reg_RegOff_Byte(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
22261 int miStart = mi;
22262 generateREXprefix(true, dstReg, srcIndex, null);
22263 setMachineCodes(mi++, (byte) 0x0F);
22264 setMachineCodes(mi++, (byte) 0xBE);
22265 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
22266 if (lister != null) lister.RRFD(miStart, "MOVSXQ", dstReg, srcIndex, srcScale, srcDisp);
22267 }
22268
22269 /**
22270 * Generate a move sign extended from an absolute address. That is,
22271 * <PRE>
22272 * dstReg := (byte) [srcDisp] (sign extended)
22273 * </PRE>
22274 *
22275 * @param dstReg the destination register
22276 * @param srcDisp the source displacement
22277 */
22278 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
22279 public final void emitMOVSXQ_Reg_Abs_Byte(GPR dstReg, Address srcDisp) {
22280 int miStart = mi;
22281 generateREXprefix(true, dstReg, null, null);
22282 setMachineCodes(mi++, (byte) 0x0F);
22283 setMachineCodes(mi++, (byte) 0xBE);
22284 emitAbsRegOperands(srcDisp, dstReg);
22285 if (lister != null) lister.RRA(miStart, "MOVSXQ", dstReg, srcDisp);
22286 }
22287
22288 /**
22289 * Generate a move sign extended by register indexed. That is,
22290 * <PRE>
22291 * dstReg := (byte) [srcBase + srcIndex<<srcScale + srcDisp] (sign extended)
22292 * </PRE>
22293 *
22294 * @param dstReg the destination register
22295 * @param srcBase the source base register
22296 * @param srcIndex the source index register
22297 * @param srcScale the source scale of the index
22298 * @param srcDisp the source displacement
22299 */
22300 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
22301 public final void emitMOVSXQ_Reg_RegIdx_Byte(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
22302 int miStart = mi;
22303 generateREXprefix(true, dstReg, srcIndex, srcBase);
22304 setMachineCodes(mi++, (byte) 0x0F);
22305 setMachineCodes(mi++, (byte) 0xBE);
22306 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
22307 if (lister != null) lister.RRXD(miStart, "MOVSXQ", dstReg, srcBase, srcIndex, srcScale, srcDisp);
22308 }
22309
22310 /**
22311 * Generate a move sign extended from register. That is,
22312 * <PRE>
22313 * dstReg := (word) srcReg (sign extended)
22314 * </PRE>
22315 *
22316 * @param dstReg the destination register
22317 * @param srcReg the source register
22318 */
22319 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
22320 public final void emitMOVSXQ_Reg_Reg_Word(GPR dstReg, GPR srcReg) {
22321 int miStart = mi;
22322 generateREXprefix(true, dstReg, null, srcReg);
22323 setMachineCodes(mi++, (byte) 0x0F);
22324 setMachineCodes(mi++, (byte) 0xBF);
22325 emitRegRegOperands(srcReg, dstReg);
22326 if (lister != null) lister.RR(miStart, "MOVSXQ", dstReg, srcReg);
22327 }
22328
22329 /**
22330 * Generate a move sign extended from register displacement. That is,
22331 * <PRE>
22332 * dstReg := (word) [srcBase + srcDisp] (sign extended)
22333 * </PRE>
22334 *
22335 * @param dstReg the destination register
22336 * @param srcBase the source base register
22337 * @param srcDisp the source displacement
22338 */
22339 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
22340 public final void emitMOVSXQ_Reg_RegDisp_Word(GPR dstReg, GPR srcBase, Offset srcDisp) {
22341 int miStart = mi;
22342 generateREXprefix(true, dstReg, null, srcBase);
22343 setMachineCodes(mi++, (byte) 0x0F);
22344 setMachineCodes(mi++, (byte) 0xBF);
22345 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
22346 if (lister != null) lister.RRD(miStart, "MOVSXQ", dstReg, srcBase, srcDisp);
22347 }
22348
22349 /**
22350 * Generate a move sign extended from register indirect. That is,
22351 * <PRE>
22352 * dstReg := (word) [srcBase] (sign extended)
22353 * </PRE>
22354 *
22355 * @param dstReg the destination register
22356 * @param srcBase the source base register
22357 */
22358 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
22359 public final void emitMOVSXQ_Reg_RegInd_Word(GPR dstReg, GPR srcBase) {
22360 int miStart = mi;
22361 generateREXprefix(true, dstReg, null, srcBase);
22362 setMachineCodes(mi++, (byte) 0x0F);
22363 setMachineCodes(mi++, (byte) 0xBF);
22364 emitRegIndirectRegOperands(srcBase, dstReg);
22365 if (lister != null) lister.RRN(miStart, "MOVSXQ", dstReg, srcBase);
22366 }
22367
22368 /**
22369 * Generate a move sign extended from register offset. That is,
22370 * <PRE>
22371 * dstReg := (word) [srcIndex<<srcScale + srcDisp] (sign extended)
22372 * </PRE>
22373 *
22374 * @param dstReg the destination register
22375 * @param srcIndex the source index register
22376 * @param srcScale the source scale of the index
22377 * @param srcDisp the source displacement
22378 */
22379 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
22380 public final void emitMOVSXQ_Reg_RegOff_Word(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
22381 int miStart = mi;
22382 generateREXprefix(true, dstReg, srcIndex, null);
22383 setMachineCodes(mi++, (byte) 0x0F);
22384 setMachineCodes(mi++, (byte) 0xBF);
22385 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
22386 if (lister != null) lister.RRFD(miStart, "MOVSXQ", dstReg, srcIndex, srcScale, srcDisp);
22387 }
22388
22389 /**
22390 * Generate a move sign extended from an absolute address. That is,
22391 * <PRE>
22392 * dstReg := (word) [srcDisp] (sign extended)
22393 * </PRE>
22394 *
22395 * @param dstReg the destination register
22396 * @param srcDisp the source displacement
22397 */
22398 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
22399 public final void emitMOVSXQ_Reg_Abs_Word(GPR dstReg, Address srcDisp) {
22400 int miStart = mi;
22401 generateREXprefix(true, dstReg, null, null);
22402 setMachineCodes(mi++, (byte) 0x0F);
22403 setMachineCodes(mi++, (byte) 0xBF);
22404 emitAbsRegOperands(srcDisp, dstReg);
22405 if (lister != null) lister.RRA(miStart, "MOVSXQ", dstReg, srcDisp);
22406 }
22407
22408 /**
22409 * Generate a move sign extended by register indexed. That is,
22410 * <PRE>
22411 * dstReg := (word) [srcBase + srcIndex<<srcScale + srcDisp] (sign extended)
22412 * </PRE>
22413 *
22414 * @param dstReg the destination register
22415 * @param srcBase the source base register
22416 * @param srcIndex the source index register
22417 * @param srcScale the source scale of the index
22418 * @param srcDisp the source displacement
22419 */
22420 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
22421 public final void emitMOVSXQ_Reg_RegIdx_Word(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
22422 int miStart = mi;
22423 generateREXprefix(true, dstReg, srcIndex, srcBase);
22424 setMachineCodes(mi++, (byte) 0x0F);
22425 setMachineCodes(mi++, (byte) 0xBF);
22426 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
22427 if (lister != null) lister.RRXD(miStart, "MOVSXQ", dstReg, srcBase, srcIndex, srcScale, srcDisp);
22428 }
22429
22430 /**
22431 * Generate a move zero extended from register. That is,
22432 * <PRE>
22433 * dstReg := (byte) srcReg (zero extended)
22434 * </PRE>
22435 *
22436 * @param dstReg the destination register
22437 * @param srcReg the source register
22438 */
22439 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
22440 public final void emitMOVZX_Reg_Reg_Byte(GPR dstReg, GPR srcReg) {
22441 int miStart = mi;
22442 generateREXprefix(false, dstReg, null, srcReg);
22443 setMachineCodes(mi++, (byte) 0x0F);
22444 setMachineCodes(mi++, (byte) 0xB6);
22445 emitRegRegOperands(srcReg, dstReg);
22446 if (lister != null) lister.RR(miStart, "MOVZX", dstReg, srcReg);
22447 }
22448
22449 /**
22450 * Generate a move zero extended from register displacement. That is,
22451 * <PRE>
22452 * dstReg := (byte) [srcBase + srcDisp] (zero extended)
22453 * </PRE>
22454 *
22455 * @param dstReg the destination register
22456 * @param srcBase the source base register
22457 * @param srcDisp the source displacement
22458 */
22459 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
22460 public final void emitMOVZX_Reg_RegDisp_Byte(GPR dstReg, GPR srcBase, Offset srcDisp) {
22461 int miStart = mi;
22462 generateREXprefix(false, dstReg, null, srcBase);
22463 setMachineCodes(mi++, (byte) 0x0F);
22464 setMachineCodes(mi++, (byte) 0xB6);
22465 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
22466 if (lister != null) lister.RRD(miStart, "MOVZX", dstReg, srcBase, srcDisp);
22467 }
22468
22469 /**
22470 * Generate a move zero extended from register indirect. That is,
22471 * <PRE>
22472 * dstReg := (byte) [srcBase] (zero extended)
22473 * </PRE>
22474 *
22475 * @param dstReg the destination register
22476 * @param srcBase the source base register
22477 */
22478 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
22479 public final void emitMOVZX_Reg_RegInd_Byte(GPR dstReg, GPR srcBase) {
22480 int miStart = mi;
22481 generateREXprefix(false, dstReg, null, srcBase);
22482 setMachineCodes(mi++, (byte) 0x0F);
22483 setMachineCodes(mi++, (byte) 0xB6);
22484 emitRegIndirectRegOperands(srcBase, dstReg);
22485 if (lister != null) lister.RRN(miStart, "MOVZX", dstReg, srcBase);
22486 }
22487
22488 /**
22489 * Generate a move zero extended from register offset. That is,
22490 * <PRE>
22491 * dstReg := (byte) [srcIndex<<srcScale + srcDisp] (zero extended)
22492 * </PRE>
22493 *
22494 * @param dstReg the destination register
22495 * @param srcIndex the source index register
22496 * @param srcScale the source scale of the index
22497 * @param srcDisp the source displacement
22498 */
22499 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
22500 public final void emitMOVZX_Reg_RegOff_Byte(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
22501 int miStart = mi;
22502 generateREXprefix(false, dstReg, srcIndex, null);
22503 setMachineCodes(mi++, (byte) 0x0F);
22504 setMachineCodes(mi++, (byte) 0xB6);
22505 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
22506 if (lister != null) lister.RRFD(miStart, "MOVZX", dstReg, srcIndex, srcScale, srcDisp);
22507 }
22508
22509 /**
22510 * Generate a move zero extended from an absolute address. That is,
22511 * <PRE>
22512 * dstReg := (byte) [srcDisp] (zero extended)
22513 * </PRE>
22514 *
22515 * @param dstReg the destination register
22516 * @param srcDisp the source displacement
22517 */
22518 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
22519 public final void emitMOVZX_Reg_Abs_Byte(GPR dstReg, Address srcDisp) {
22520 int miStart = mi;
22521 generateREXprefix(false, dstReg, null, null);
22522 setMachineCodes(mi++, (byte) 0x0F);
22523 setMachineCodes(mi++, (byte) 0xB6);
22524 emitAbsRegOperands(srcDisp, dstReg);
22525 if (lister != null) lister.RRA(miStart, "MOVZX", dstReg, srcDisp);
22526 }
22527
22528 /**
22529 * Generate a move zero extended by register indexed. That is,
22530 * <PRE>
22531 * dstReg := (byte) [srcBase + srcIndex<<srcScale + srcDisp] (zero extended)
22532 * </PRE>
22533 *
22534 * @param dstReg the destination register
22535 * @param srcBase the source base register
22536 * @param srcIndex the source index register
22537 * @param srcScale the source scale of the index
22538 * @param srcDisp the source displacement
22539 */
22540 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
22541 public final void emitMOVZX_Reg_RegIdx_Byte(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
22542 int miStart = mi;
22543 generateREXprefix(false, dstReg, srcIndex, srcBase);
22544 setMachineCodes(mi++, (byte) 0x0F);
22545 setMachineCodes(mi++, (byte) 0xB6);
22546 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
22547 if (lister != null) lister.RRXD(miStart, "MOVZX", dstReg, srcBase, srcIndex, srcScale, srcDisp);
22548 }
22549
22550 /**
22551 * Generate a move zero extended from register. That is,
22552 * <PRE>
22553 * dstReg := (word) srcReg (zero extended)
22554 * </PRE>
22555 *
22556 * @param dstReg the destination register
22557 * @param srcReg the source register
22558 */
22559 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
22560 public final void emitMOVZX_Reg_Reg_Word(GPR dstReg, GPR srcReg) {
22561 int miStart = mi;
22562 generateREXprefix(false, dstReg, null, srcReg);
22563 setMachineCodes(mi++, (byte) 0x0F);
22564 setMachineCodes(mi++, (byte) 0xB7);
22565 emitRegRegOperands(srcReg, dstReg);
22566 if (lister != null) lister.RR(miStart, "MOVZX", dstReg, srcReg);
22567 }
22568
22569 /**
22570 * Generate a move zero extended from register displacement. That is,
22571 * <PRE>
22572 * dstReg := (word) [srcBase + srcDisp] (zero extended)
22573 * </PRE>
22574 *
22575 * @param dstReg the destination register
22576 * @param srcBase the source base register
22577 * @param srcDisp the source displacement
22578 */
22579 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
22580 public final void emitMOVZX_Reg_RegDisp_Word(GPR dstReg, GPR srcBase, Offset srcDisp) {
22581 int miStart = mi;
22582 generateREXprefix(false, dstReg, null, srcBase);
22583 setMachineCodes(mi++, (byte) 0x0F);
22584 setMachineCodes(mi++, (byte) 0xB7);
22585 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
22586 if (lister != null) lister.RRD(miStart, "MOVZX", dstReg, srcBase, srcDisp);
22587 }
22588
22589 /**
22590 * Generate a move zero extended from register indirect. That is,
22591 * <PRE>
22592 * dstReg := (word) [srcBase] (zero extended)
22593 * </PRE>
22594 *
22595 * @param dstReg the destination register
22596 * @param srcBase the source base register
22597 */
22598 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
22599 public final void emitMOVZX_Reg_RegInd_Word(GPR dstReg, GPR srcBase) {
22600 int miStart = mi;
22601 generateREXprefix(false, dstReg, null, srcBase);
22602 setMachineCodes(mi++, (byte) 0x0F);
22603 setMachineCodes(mi++, (byte) 0xB7);
22604 emitRegIndirectRegOperands(srcBase, dstReg);
22605 if (lister != null) lister.RRN(miStart, "MOVZX", dstReg, srcBase);
22606 }
22607
22608 /**
22609 * Generate a move zero extended from register offset. That is,
22610 * <PRE>
22611 * dstReg := (word) [srcIndex<<srcScale + srcDisp] (zero extended)
22612 * </PRE>
22613 *
22614 * @param dstReg the destination register
22615 * @param srcIndex the source index register
22616 * @param srcScale the source scale of the index
22617 * @param srcDisp the source displacement
22618 */
22619 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
22620 public final void emitMOVZX_Reg_RegOff_Word(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
22621 int miStart = mi;
22622 generateREXprefix(false, dstReg, srcIndex, null);
22623 setMachineCodes(mi++, (byte) 0x0F);
22624 setMachineCodes(mi++, (byte) 0xB7);
22625 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
22626 if (lister != null) lister.RRFD(miStart, "MOVZX", dstReg, srcIndex, srcScale, srcDisp);
22627 }
22628
22629 /**
22630 * Generate a move zero extended from an absolute address. That is,
22631 * <PRE>
22632 * dstReg := (word) [srcDisp] (zero extended)
22633 * </PRE>
22634 *
22635 * @param dstReg the destination register
22636 * @param srcDisp the source displacement
22637 */
22638 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
22639 public final void emitMOVZX_Reg_Abs_Word(GPR dstReg, Address srcDisp) {
22640 int miStart = mi;
22641 generateREXprefix(false, dstReg, null, null);
22642 setMachineCodes(mi++, (byte) 0x0F);
22643 setMachineCodes(mi++, (byte) 0xB7);
22644 emitAbsRegOperands(srcDisp, dstReg);
22645 if (lister != null) lister.RRA(miStart, "MOVZX", dstReg, srcDisp);
22646 }
22647
22648 /**
22649 * Generate a move zero extended by register indexed. That is,
22650 * <PRE>
22651 * dstReg := (word) [srcBase + srcIndex<<srcScale + srcDisp] (zero extended)
22652 * </PRE>
22653 *
22654 * @param dstReg the destination register
22655 * @param srcBase the source base register
22656 * @param srcIndex the source index register
22657 * @param srcScale the source scale of the index
22658 * @param srcDisp the source displacement
22659 */
22660 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
22661 public final void emitMOVZX_Reg_RegIdx_Word(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
22662 int miStart = mi;
22663 generateREXprefix(false, dstReg, srcIndex, srcBase);
22664 setMachineCodes(mi++, (byte) 0x0F);
22665 setMachineCodes(mi++, (byte) 0xB7);
22666 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
22667 if (lister != null) lister.RRXD(miStart, "MOVZX", dstReg, srcBase, srcIndex, srcScale, srcDisp);
22668 }
22669
22670 /**
22671 * Generate a move zero extended from register. That is,
22672 * <PRE>
22673 * dstReg := (byte) srcReg (zero extended)
22674 * </PRE>
22675 *
22676 * @param dstReg the destination register
22677 * @param srcReg the source register
22678 */
22679 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
22680 public final void emitMOVZXQ_Reg_Reg_Byte(GPR dstReg, GPR srcReg) {
22681 int miStart = mi;
22682 generateREXprefix(true, dstReg, null, srcReg);
22683 setMachineCodes(mi++, (byte) 0x0F);
22684 setMachineCodes(mi++, (byte) 0xB6);
22685 emitRegRegOperands(srcReg, dstReg);
22686 if (lister != null) lister.RR(miStart, "MOVZXQ", dstReg, srcReg);
22687 }
22688
22689 /**
22690 * Generate a move zero extended from register displacement. That is,
22691 * <PRE>
22692 * dstReg := (byte) [srcBase + srcDisp] (zero extended)
22693 * </PRE>
22694 *
22695 * @param dstReg the destination register
22696 * @param srcBase the source base register
22697 * @param srcDisp the source displacement
22698 */
22699 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
22700 public final void emitMOVZXQ_Reg_RegDisp_Byte(GPR dstReg, GPR srcBase, Offset srcDisp) {
22701 int miStart = mi;
22702 generateREXprefix(true, dstReg, null, srcBase);
22703 setMachineCodes(mi++, (byte) 0x0F);
22704 setMachineCodes(mi++, (byte) 0xB6);
22705 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
22706 if (lister != null) lister.RRD(miStart, "MOVZXQ", dstReg, srcBase, srcDisp);
22707 }
22708
22709 /**
22710 * Generate a move zero extended from register indirect. That is,
22711 * <PRE>
22712 * dstReg := (byte) [srcBase] (zero extended)
22713 * </PRE>
22714 *
22715 * @param dstReg the destination register
22716 * @param srcBase the source base register
22717 */
22718 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
22719 public final void emitMOVZXQ_Reg_RegInd_Byte(GPR dstReg, GPR srcBase) {
22720 int miStart = mi;
22721 generateREXprefix(true, dstReg, null, srcBase);
22722 setMachineCodes(mi++, (byte) 0x0F);
22723 setMachineCodes(mi++, (byte) 0xB6);
22724 emitRegIndirectRegOperands(srcBase, dstReg);
22725 if (lister != null) lister.RRN(miStart, "MOVZXQ", dstReg, srcBase);
22726 }
22727
22728 /**
22729 * Generate a move zero extended from register offset. That is,
22730 * <PRE>
22731 * dstReg := (byte) [srcIndex<<srcScale + srcDisp] (zero extended)
22732 * </PRE>
22733 *
22734 * @param dstReg the destination register
22735 * @param srcIndex the source index register
22736 * @param srcScale the source scale of the index
22737 * @param srcDisp the source displacement
22738 */
22739 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
22740 public final void emitMOVZXQ_Reg_RegOff_Byte(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
22741 int miStart = mi;
22742 generateREXprefix(true, dstReg, srcIndex, null);
22743 setMachineCodes(mi++, (byte) 0x0F);
22744 setMachineCodes(mi++, (byte) 0xB6);
22745 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
22746 if (lister != null) lister.RRFD(miStart, "MOVZXQ", dstReg, srcIndex, srcScale, srcDisp);
22747 }
22748
22749 /**
22750 * Generate a move zero extended from an absolute address. That is,
22751 * <PRE>
22752 * dstReg := (byte) [srcDisp] (zero extended)
22753 * </PRE>
22754 *
22755 * @param dstReg the destination register
22756 * @param srcDisp the source displacement
22757 */
22758 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
22759 public final void emitMOVZXQ_Reg_Abs_Byte(GPR dstReg, Address srcDisp) {
22760 int miStart = mi;
22761 generateREXprefix(true, dstReg, null, null);
22762 setMachineCodes(mi++, (byte) 0x0F);
22763 setMachineCodes(mi++, (byte) 0xB6);
22764 emitAbsRegOperands(srcDisp, dstReg);
22765 if (lister != null) lister.RRA(miStart, "MOVZXQ", dstReg, srcDisp);
22766 }
22767
22768 /**
22769 * Generate a move zero extended by register indexed. That is,
22770 * <PRE>
22771 * dstReg := (byte) [srcBase + srcIndex<<srcScale + srcDisp] (zero extended)
22772 * </PRE>
22773 *
22774 * @param dstReg the destination register
22775 * @param srcBase the source base register
22776 * @param srcIndex the source index register
22777 * @param srcScale the source scale of the index
22778 * @param srcDisp the source displacement
22779 */
22780 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
22781 public final void emitMOVZXQ_Reg_RegIdx_Byte(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
22782 int miStart = mi;
22783 generateREXprefix(true, dstReg, srcIndex, srcBase);
22784 setMachineCodes(mi++, (byte) 0x0F);
22785 setMachineCodes(mi++, (byte) 0xB6);
22786 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
22787 if (lister != null) lister.RRXD(miStart, "MOVZXQ", dstReg, srcBase, srcIndex, srcScale, srcDisp);
22788 }
22789
22790 /**
22791 * Generate a move zero extended from register. That is,
22792 * <PRE>
22793 * dstReg := (word) srcReg (zero extended)
22794 * </PRE>
22795 *
22796 * @param dstReg the destination register
22797 * @param srcReg the source register
22798 */
22799 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
22800 public final void emitMOVZXQ_Reg_Reg_Word(GPR dstReg, GPR srcReg) {
22801 int miStart = mi;
22802 generateREXprefix(true, dstReg, null, srcReg);
22803 setMachineCodes(mi++, (byte) 0x0F);
22804 setMachineCodes(mi++, (byte) 0xB7);
22805 emitRegRegOperands(srcReg, dstReg);
22806 if (lister != null) lister.RR(miStart, "MOVZXQ", dstReg, srcReg);
22807 }
22808
22809 /**
22810 * Generate a move zero extended from register displacement. That is,
22811 * <PRE>
22812 * dstReg := (word) [srcBase + srcDisp] (zero extended)
22813 * </PRE>
22814 *
22815 * @param dstReg the destination register
22816 * @param srcBase the source base register
22817 * @param srcDisp the source displacement
22818 */
22819 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
22820 public final void emitMOVZXQ_Reg_RegDisp_Word(GPR dstReg, GPR srcBase, Offset srcDisp) {
22821 int miStart = mi;
22822 generateREXprefix(true, dstReg, null, srcBase);
22823 setMachineCodes(mi++, (byte) 0x0F);
22824 setMachineCodes(mi++, (byte) 0xB7);
22825 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
22826 if (lister != null) lister.RRD(miStart, "MOVZXQ", dstReg, srcBase, srcDisp);
22827 }
22828
22829 /**
22830 * Generate a move zero extended from register indirect. That is,
22831 * <PRE>
22832 * dstReg := (word) [srcBase] (zero extended)
22833 * </PRE>
22834 *
22835 * @param dstReg the destination register
22836 * @param srcBase the source base register
22837 */
22838 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
22839 public final void emitMOVZXQ_Reg_RegInd_Word(GPR dstReg, GPR srcBase) {
22840 int miStart = mi;
22841 generateREXprefix(true, dstReg, null, srcBase);
22842 setMachineCodes(mi++, (byte) 0x0F);
22843 setMachineCodes(mi++, (byte) 0xB7);
22844 emitRegIndirectRegOperands(srcBase, dstReg);
22845 if (lister != null) lister.RRN(miStart, "MOVZXQ", dstReg, srcBase);
22846 }
22847
22848 /**
22849 * Generate a move zero extended from register offset. That is,
22850 * <PRE>
22851 * dstReg := (word) [srcIndex<<srcScale + srcDisp] (zero extended)
22852 * </PRE>
22853 *
22854 * @param dstReg the destination register
22855 * @param srcIndex the source index register
22856 * @param srcScale the source scale of the index
22857 * @param srcDisp the source displacement
22858 */
22859 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
22860 public final void emitMOVZXQ_Reg_RegOff_Word(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
22861 int miStart = mi;
22862 generateREXprefix(true, dstReg, srcIndex, null);
22863 setMachineCodes(mi++, (byte) 0x0F);
22864 setMachineCodes(mi++, (byte) 0xB7);
22865 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
22866 if (lister != null) lister.RRFD(miStart, "MOVZXQ", dstReg, srcIndex, srcScale, srcDisp);
22867 }
22868
22869 /**
22870 * Generate a move zero extended from an absolute address. That is,
22871 * <PRE>
22872 * dstReg := (word) [srcDisp] (zero extended)
22873 * </PRE>
22874 *
22875 * @param dstReg the destination register
22876 * @param srcDisp the source displacement
22877 */
22878 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
22879 public final void emitMOVZXQ_Reg_Abs_Word(GPR dstReg, Address srcDisp) {
22880 int miStart = mi;
22881 generateREXprefix(true, dstReg, null, null);
22882 setMachineCodes(mi++, (byte) 0x0F);
22883 setMachineCodes(mi++, (byte) 0xB7);
22884 emitAbsRegOperands(srcDisp, dstReg);
22885 if (lister != null) lister.RRA(miStart, "MOVZXQ", dstReg, srcDisp);
22886 }
22887
22888 /**
22889 * Generate a move zero extended by register indexed. That is,
22890 * <PRE>
22891 * dstReg := (word) [srcBase + srcIndex<<srcScale + srcDisp] (zero extended)
22892 * </PRE>
22893 *
22894 * @param dstReg the destination register
22895 * @param srcBase the source base register
22896 * @param srcIndex the source index register
22897 * @param srcScale the source scale of the index
22898 * @param srcDisp the source displacement
22899 */
22900 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
22901 public final void emitMOVZXQ_Reg_RegIdx_Word(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
22902 int miStart = mi;
22903 generateREXprefix(true, dstReg, srcIndex, srcBase);
22904 setMachineCodes(mi++, (byte) 0x0F);
22905 setMachineCodes(mi++, (byte) 0xB7);
22906 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
22907 if (lister != null) lister.RRXD(miStart, "MOVZXQ", dstReg, srcBase, srcIndex, srcScale, srcDisp);
22908 }
22909
22910 /**
22911 * Generate a register(indirect)--register CMPXCHG. That is,
22912 * <PRE>
22913 * [dstBase] <->= srcReg
22914 * </PRE>
22915 *
22916 * @param dstBase the destination base
22917 * @param srcReg the source register
22918 */
22919 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
22920 public final void emitCMPXCHG_RegInd_Reg(GPR dstBase, GPR srcReg) {
22921 int miStart = mi;
22922 // no group 1 to 4 prefix byte
22923 generateREXprefix(false, srcReg, null, dstBase);
22924 setMachineCodes(mi++, (byte) 0x0F);
22925 setMachineCodes(mi++, (byte) 0xB1);
22926 emitRegIndirectRegOperands(dstBase, srcReg);
22927 if (lister != null) lister.RNR(miStart, "CMPXCHG", dstBase, srcReg);
22928 }
22929
22930 /**
22931 * Generate a register-offset--register CMPXCHG. That is,
22932 * <PRE>
22933 * [dstReg<<dstScale + dstDisp] <->= srcReg
22934 * </PRE>
22935 *
22936 * @param dstIndex the destination index register
22937 * @param dstScale the destination shift amount
22938 * @param dstDisp the destination displacement
22939 * @param srcReg the source register
22940 */
22941 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
22942 public final void emitCMPXCHG_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
22943 int miStart = mi;
22944 // no group 1 to 4 prefix byte
22945 generateREXprefix(false, srcReg, dstIndex, null);
22946 setMachineCodes(mi++, (byte) 0x0F);
22947 setMachineCodes(mi++, (byte) 0xB1);
22948 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
22949 if (lister != null) lister.RFDR(miStart, "CMPXCHG", dstIndex, dstScale, dstDisp, srcReg);
22950 }
22951
22952 /**
22953 * Generate a absolute--register CMPXCHG. That is,
22954 * <PRE>
22955 * [dstDisp] <->= srcReg
22956 * </PRE>
22957 *
22958 * @param dstDisp the destination address
22959 * @param srcReg the source register
22960 */
22961 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
22962 public final void emitCMPXCHG_Abs_Reg(Address dstDisp, GPR srcReg) {
22963 int miStart = mi;
22964 // no group 1 to 4 prefix byte
22965 generateREXprefix(false, srcReg, null, null);
22966 setMachineCodes(mi++, (byte) 0x0F);
22967 setMachineCodes(mi++, (byte) 0xB1);
22968 emitAbsRegOperands(dstDisp, srcReg);
22969 if (lister != null) lister.RAR(miStart, "CMPXCHG", dstDisp, srcReg);
22970 }
22971
22972 /**
22973 * Generate a register-index--register CMPXCHG. That is,
22974 * <PRE>
22975 * [dstBase + dstIndex<<dstScale + dstDisp] <->= srcReg
22976 * </PRE>
22977 *
22978 * @param dstBase the base register
22979 * @param dstIndex the destination index register
22980 * @param dstScale the destination shift amount
22981 * @param dstDisp the destination displacement
22982 * @param srcReg the source register
22983 */
22984 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
22985 public final void emitCMPXCHG_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
22986 int miStart = mi;
22987 // no group 1 to 4 prefix byte
22988 generateREXprefix(false, srcReg, dstIndex, dstBase);
22989 setMachineCodes(mi++, (byte) 0x0F);
22990 setMachineCodes(mi++, (byte) 0xB1);
22991 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
22992 if (lister != null) lister.RXDR(miStart, "CMPXCHG", dstBase, dstIndex, dstScale, dstDisp, srcReg);
22993 }
22994
22995 /**
22996 * Generate a register-displacement--register CMPXCHG. That is,
22997 * <PRE>
22998 * [dstBase + dstDisp] <->= srcReg
22999 * </PRE>
23000 *
23001 * @param dstBase the base register
23002 * @param dstDisp the destination displacement
23003 * @param srcReg the source register
23004 */
23005 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
23006 public final void emitCMPXCHG_RegDisp_Reg(GPR dstBase, Offset dstDisp, GPR srcReg) {
23007 int miStart = mi;
23008 // no group 1 to 4 prefix byte
23009 generateREXprefix(false, srcReg, null, dstBase);
23010 setMachineCodes(mi++, (byte) 0x0F);
23011 setMachineCodes(mi++, (byte) 0xB1);
23012 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
23013 if (lister != null) lister.RDR(miStart, "CMPXCHG", dstBase, dstDisp, srcReg);
23014 }
23015
23016 /**
23017 * Generate a register--register CMPXCHG. That is,
23018 * <PRE>
23019 * dstReg <->= srcReg
23020 * </PRE>
23021 *
23022 * @param dstReg the destination register
23023 * @param srcReg the source register
23024 */
23025 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
23026 public final void emitCMPXCHG_Reg_Reg(GPR dstReg, GPR srcReg) {
23027 int miStart = mi;
23028 // no group 1 to 4 prefix byte
23029 generateREXprefix(false, srcReg, null, dstReg);
23030 setMachineCodes(mi++, (byte) 0x0F);
23031 setMachineCodes(mi++, (byte) 0xB1);
23032 emitRegRegOperands(dstReg, srcReg);
23033 if (lister != null) lister.RR(miStart, "CMPXCHG", dstReg, srcReg);
23034 }
23035
23036 /**
23037 * Generate a register(indirect)--register CMPXCHG. That is,
23038 * <PRE>
23039 * [dstBase] <->= (quad) srcReg
23040 * </PRE>
23041 *
23042 * @param dstBase the destination base
23043 * @param srcReg the source register
23044 */
23045 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
23046 public final void emitCMPXCHG_RegInd_Reg_Quad(GPR dstBase, GPR srcReg) {
23047 int miStart = mi;
23048 // no group 1 to 4 prefix byte
23049 generateREXprefix(true, srcReg, null, dstBase);
23050 setMachineCodes(mi++, (byte) 0x0F);
23051 setMachineCodes(mi++, (byte) 0xB1);
23052 emitRegIndirectRegOperands(dstBase, srcReg);
23053 if (lister != null) lister.RNR(miStart, "CMPXCHG", dstBase, srcReg);
23054 }
23055
23056 /**
23057 * Generate a register-offset--register CMPXCHG. That is,
23058 * <PRE>
23059 * [dstReg<<dstScale + dstDisp] <->= (quad) srcReg
23060 * </PRE>
23061 *
23062 * @param dstIndex the destination index register
23063 * @param dstScale the destination shift amount
23064 * @param dstDisp the destination displacement
23065 * @param srcReg the source register
23066 */
23067 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
23068 public final void emitCMPXCHG_RegOff_Reg_Quad(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
23069 int miStart = mi;
23070 // no group 1 to 4 prefix byte
23071 generateREXprefix(true, srcReg, dstIndex, null);
23072 setMachineCodes(mi++, (byte) 0x0F);
23073 setMachineCodes(mi++, (byte) 0xB1);
23074 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
23075 if (lister != null) lister.RFDR(miStart, "CMPXCHG", dstIndex, dstScale, dstDisp, srcReg);
23076 }
23077
23078 /**
23079 * Generate a absolute--register CMPXCHG. That is,
23080 * <PRE>
23081 * [dstDisp] <->= (quad) srcReg
23082 * </PRE>
23083 *
23084 * @param dstDisp the destination address
23085 * @param srcReg the source register
23086 */
23087 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
23088 public final void emitCMPXCHG_Abs_Reg_Quad(Address dstDisp, GPR srcReg) {
23089 int miStart = mi;
23090 // no group 1 to 4 prefix byte
23091 generateREXprefix(true, srcReg, null, null);
23092 setMachineCodes(mi++, (byte) 0x0F);
23093 setMachineCodes(mi++, (byte) 0xB1);
23094 emitAbsRegOperands(dstDisp, srcReg);
23095 if (lister != null) lister.RAR(miStart, "CMPXCHG", dstDisp, srcReg);
23096 }
23097
23098 /**
23099 * Generate a register-index--register CMPXCHG. That is,
23100 * <PRE>
23101 * [dstBase + dstIndex<<dstScale + dstDisp] <->= (quad) srcReg
23102 * </PRE>
23103 *
23104 * @param dstBase the base register
23105 * @param dstIndex the destination index register
23106 * @param dstScale the destination shift amount
23107 * @param dstDisp the destination displacement
23108 * @param srcReg the source register
23109 */
23110 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
23111 public final void emitCMPXCHG_RegIdx_Reg_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
23112 int miStart = mi;
23113 // no group 1 to 4 prefix byte
23114 generateREXprefix(true, srcReg, dstIndex, dstBase);
23115 setMachineCodes(mi++, (byte) 0x0F);
23116 setMachineCodes(mi++, (byte) 0xB1);
23117 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
23118 if (lister != null) lister.RXDR(miStart, "CMPXCHG", dstBase, dstIndex, dstScale, dstDisp, srcReg);
23119 }
23120
23121 /**
23122 * Generate a register-displacement--register CMPXCHG. That is,
23123 * <PRE>
23124 * [dstBase + dstDisp] <->= (quad) srcReg
23125 * </PRE>
23126 *
23127 * @param dstBase the base register
23128 * @param dstDisp the destination displacement
23129 * @param srcReg the source register
23130 */
23131 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
23132 public final void emitCMPXCHG_RegDisp_Reg_Quad(GPR dstBase, Offset dstDisp, GPR srcReg) {
23133 int miStart = mi;
23134 // no group 1 to 4 prefix byte
23135 generateREXprefix(true, srcReg, null, dstBase);
23136 setMachineCodes(mi++, (byte) 0x0F);
23137 setMachineCodes(mi++, (byte) 0xB1);
23138 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
23139 if (lister != null) lister.RDR(miStart, "CMPXCHG", dstBase, dstDisp, srcReg);
23140 }
23141
23142 /**
23143 * Generate a register--register CMPXCHG. That is,
23144 * <PRE>
23145 * dstReg <->= (quad) srcReg
23146 * </PRE>
23147 *
23148 * @param dstReg the destination register
23149 * @param srcReg the source register
23150 */
23151 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
23152 public final void emitCMPXCHG_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
23153 int miStart = mi;
23154 // no group 1 to 4 prefix byte
23155 generateREXprefix(true, srcReg, null, dstReg);
23156 setMachineCodes(mi++, (byte) 0x0F);
23157 setMachineCodes(mi++, (byte) 0xB1);
23158 emitRegRegOperands(dstReg, srcReg);
23159 if (lister != null) lister.RR(miStart, "CMPXCHG", dstReg, srcReg);
23160 }
23161
23162 /**
23163 * Generate a register--immediate ROL. That is,
23164 * <PRE>
23165 * rotate left of dstReg by imm
23166 * </PRE>
23167 *
23168 * @param dstReg the destination register
23169 * @param imm immediate
23170 */
23171 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
23172 public final void emitROL_Reg_Imm_Byte(GPR dstReg, int imm) {
23173 int miStart = mi;
23174 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
23175 // no size prefix
23176 generateREXprefix(false, null, null, dstReg);
23177 if (imm == 1) {
23178 setMachineCodes(mi++, (byte) 0xD0);
23179 emitRegRegOperands(dstReg, GPR.getForOpcode(0x0));
23180 } else {
23181 setMachineCodes(mi++, (byte) 0xC0);
23182 emitRegRegOperands(dstReg, GPR.getForOpcode(0x0));
23183 emitImm8((byte)imm);
23184 }
23185 if (lister != null) lister.RI(miStart, "ROL", dstReg, imm);
23186 }
23187
23188 /**
23189 * Generate a register-indirect--immediate ROL. That is,
23190 * <PRE>
23191 * rotate left of [dstBase] by imm
23192 * </PRE>
23193 *
23194 * @param dstBase the destination base register
23195 * @param imm immediate
23196 */
23197 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
23198 public final void emitROL_RegInd_Imm_Byte(GPR dstBase, int imm) {
23199 int miStart = mi;
23200 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
23201 // no size prefix
23202 generateREXprefix(false, null, null, dstBase);
23203 if (imm == 1) {
23204 setMachineCodes(mi++, (byte) 0xD0);
23205 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
23206 } else {
23207 setMachineCodes(mi++, (byte) 0xC0);
23208 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
23209 emitImm8((byte)imm);
23210 }
23211 if (lister != null) lister.RNI(miStart, "ROL", dstBase, imm);
23212 }
23213
23214 /**
23215 * Generate a register-displacement--immediate ROL. That is,
23216 * <PRE>
23217 * rotate left of [dstBase + dstDisp] by imm
23218 * </PRE>
23219 *
23220 * @param dstBase the destination base register
23221 * @param dstDisp the destination displacement
23222 * @param imm immediate
23223 */
23224 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
23225 public final void emitROL_RegDisp_Imm_Byte(GPR dstBase, Offset dstDisp, int imm) {
23226 int miStart = mi;
23227 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
23228 // no size prefix
23229 generateREXprefix(false, null, null, dstBase);
23230 if (imm == 1) {
23231 setMachineCodes(mi++, (byte) 0xD0);
23232 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
23233 } else {
23234 setMachineCodes(mi++, (byte) 0xC0);
23235 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
23236 emitImm8((byte)imm);
23237 }
23238 if (lister != null) lister.RDI(miStart, "ROL", dstBase, dstDisp, imm);
23239 }
23240
23241 /**
23242 * Generate a register-offset--immediate ROL. That is,
23243 * <PRE>
23244 * rotate left of [dstIndex<<dstScale + dstDisp] by imm
23245 * </PRE>
23246 *
23247 * @param dstIndex the destination index register
23248 * @param dstScale the destination shift amount
23249 * @param dstDisp the destination displacement
23250 * @param imm immediate
23251 */
23252 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
23253 public final void emitROL_RegOff_Imm_Byte(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
23254 int miStart = mi;
23255 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
23256 // no size prefix
23257 generateREXprefix(false, null, dstIndex, null);
23258 if (imm == 1) {
23259 setMachineCodes(mi++, (byte) 0xD0);
23260 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
23261 } else {
23262 setMachineCodes(mi++, (byte) 0xC0);
23263 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
23264 emitImm8((byte)imm);
23265 }
23266 if (lister != null) lister.RFDI(miStart, "ROL", dstIndex, dstScale, dstDisp, imm);
23267 }
23268
23269 /**
23270 * Generate a absolute--immediate ROL. That is,
23271 * <PRE>
23272 * rotate left of [dstDisp] by imm
23273 * </PRE>
23274 *
23275 * @param dstDisp the destination displacement
23276 * @param imm immediate
23277 */
23278 public final void emitROL_Abs_Imm_Byte(Address dstDisp, int imm) {
23279 int miStart = mi;
23280 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
23281 // no size prefix
23282 generateREXprefix(false, null, null, null);
23283 if (imm == 1) {
23284 setMachineCodes(mi++, (byte) 0xD0);
23285 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
23286 } else {
23287 setMachineCodes(mi++, (byte) 0xC0);
23288 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
23289 emitImm8((byte)imm);
23290 }
23291 if (lister != null) lister.RAI(miStart, "ROL", dstDisp, imm);
23292 }
23293
23294 /**
23295 * Generate a register-index--immediate ROL. That is,
23296 * <PRE>
23297 * rotate left of [dstBase + dstIndex<<dstScale + dstDisp] by imm
23298 * </PRE>
23299 *
23300 * @param dstBase the destination base register
23301 * @param dstIndex the destination index register
23302 * @param dstScale the destination shift amount
23303 * @param dstDisp the destination displacement
23304 * @param imm immediate
23305 */
23306 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
23307 public final void emitROL_RegIdx_Imm_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
23308 int miStart = mi;
23309 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
23310 // no size prefix
23311 generateREXprefix(false, null, dstIndex, dstBase);
23312 if (imm == 1) {
23313 setMachineCodes(mi++, (byte) 0xD0);
23314 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
23315 } else {
23316 setMachineCodes(mi++, (byte) 0xC0);
23317 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
23318 emitImm8((byte)imm);
23319 }
23320 if (lister != null) lister.RXDI(miStart, "ROL", dstBase, dstIndex, dstScale, dstDisp, imm);
23321 }
23322
23323 /**
23324 * Generate a register--register ROL. That is,
23325 * <PRE>
23326 * rotate left of dstReg by srcReg
23327 * </PRE>
23328 *
23329 * @param dstReg the destination register
23330 * @param srcReg must always be ECX
23331 */
23332 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
23333 public final void emitROL_Reg_Reg_Byte(GPR dstReg, GPR srcReg) {
23334 int miStart = mi;
23335 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
23336 // no size prefix
23337 generateREXprefix(false, null, null, dstReg);
23338 setMachineCodes(mi++, (byte) 0xD2);
23339 emitRegRegOperands(dstReg, GPR.getForOpcode(0x0));
23340 if (lister != null) lister.RR(miStart, "ROL", dstReg, srcReg);
23341 }
23342
23343 /**
23344 * Generate a register-indirect--register ROL. That is,
23345 * <PRE>
23346 * rotate left of [dstBase] by srcReg
23347 * </PRE>
23348 *
23349 * @param dstBase the destination register
23350 * @param srcReg must always be ECX
23351 */
23352 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
23353 public final void emitROL_RegInd_Reg_Byte(GPR dstBase, GPR srcReg) {
23354 int miStart = mi;
23355 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
23356 // no size prefix
23357 generateREXprefix(false, null, null, dstBase);
23358 setMachineCodes(mi++, (byte) 0xD2);
23359 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
23360 if (lister != null) lister.RNR(miStart, "ROL", dstBase, srcReg);
23361 }
23362
23363 /**
23364 * Generate a register-displacement--register ROL. That is,
23365 * <PRE>
23366 * rotate left of [dstBase + dstDisp] by srcReg
23367 * </PRE>
23368 *
23369 * @param dstBase the destination base register
23370 * @param dstDisp the destination displacement
23371 * @param srcReg must always be ECX
23372 */
23373 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
23374 public final void emitROL_RegDisp_Reg_Byte(GPR dstBase, Offset dstDisp, GPR srcReg) {
23375 int miStart = mi;
23376 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
23377 // no size prefix
23378 generateREXprefix(false, null, null, dstBase);
23379 setMachineCodes(mi++, (byte) 0xD2);
23380 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
23381 if (lister != null) lister.RDR(miStart, "ROL", dstBase, dstDisp, srcReg);
23382 }
23383
23384 /**
23385 * Generate a register-offset--register ROL. That is,
23386 * <PRE>
23387 * rotate left of [dstIndex<<dstScale + dstDisp] by srcReg
23388 * </PRE>
23389 *
23390 * @param dstIndex the destination index register
23391 * @param dstScale the destination shift amount
23392 * @param dstDisp the destination displacement
23393 * @param srcReg must always be ECX
23394 */
23395 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
23396 public final void emitROL_RegOff_Reg_Byte(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
23397 int miStart = mi;
23398 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
23399 // no size prefix
23400 generateREXprefix(false, null, dstIndex, null);
23401 setMachineCodes(mi++, (byte) 0xD2);
23402 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
23403 if (lister != null) lister.RFDR(miStart, "ROL", dstIndex, dstScale, dstDisp, srcReg);
23404 }
23405
23406 /**
23407 * Generate an absolute--register ROL. That is,
23408 * <PRE>
23409 * rotate left of [dstDisp] by srcReg
23410 * </PRE>
23411 *
23412 * @param dstDisp the destination displacement
23413 * @param srcReg must always be ECX
23414 */
23415 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
23416 public final void emitROL_Abs_Reg_Byte(Address dstDisp, GPR srcReg) {
23417 int miStart = mi;
23418 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
23419 // no size prefix
23420 generateREXprefix(false, null, null, null);
23421 setMachineCodes(mi++, (byte) 0xD2);
23422 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
23423 if (lister != null) lister.RAR(miStart, "ROL", dstDisp, srcReg);
23424 }
23425
23426 /**
23427 * Generate a register-displacement--register ROL. That is,
23428 * <PRE>
23429 * rotate left of [dstBase + dstIndex<<dstScale + dstDisp] by srcReg
23430 * </PRE>
23431 *
23432 * @param dstBase the destination base register
23433 * @param dstIndex the destination index register
23434 * @param dstScale the destination shift amount
23435 * @param dstDisp the destination displacement
23436 * @param srcReg must always be ECX
23437 */
23438 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
23439 public final void emitROL_RegIdx_Reg_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
23440 int miStart = mi;
23441 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
23442 // no size prefix
23443 generateREXprefix(false, null, dstIndex, dstBase);
23444 setMachineCodes(mi++, (byte) 0xD2);
23445 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
23446 if (lister != null) lister.RXDR(miStart, "ROL", dstBase, dstIndex, dstScale, dstDisp, srcReg);
23447 }
23448
23449 /**
23450 * Generate a register--immediate ROL. That is,
23451 * <PRE>
23452 * rotate left of dstReg by imm
23453 * </PRE>
23454 *
23455 * @param dstReg the destination register
23456 * @param imm immediate
23457 */
23458 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
23459 public final void emitROL_Reg_Imm_Word(GPR dstReg, int imm) {
23460 int miStart = mi;
23461 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
23462 setMachineCodes(mi++, (byte) 0x66);
23463 generateREXprefix(false, null, null, dstReg);
23464 if (imm == 1) {
23465 setMachineCodes(mi++, (byte) 0xD1);
23466 emitRegRegOperands(dstReg, GPR.getForOpcode(0x0));
23467 } else {
23468 setMachineCodes(mi++, (byte) 0xC1);
23469 emitRegRegOperands(dstReg, GPR.getForOpcode(0x0));
23470 emitImm8((byte)imm);
23471 }
23472 if (lister != null) lister.RI(miStart, "ROL", dstReg, imm);
23473 }
23474
23475 /**
23476 * Generate a register-indirect--immediate ROL. That is,
23477 * <PRE>
23478 * rotate left of [dstBase] by imm
23479 * </PRE>
23480 *
23481 * @param dstBase the destination base register
23482 * @param imm immediate
23483 */
23484 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
23485 public final void emitROL_RegInd_Imm_Word(GPR dstBase, int imm) {
23486 int miStart = mi;
23487 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
23488 setMachineCodes(mi++, (byte) 0x66);
23489 generateREXprefix(false, null, null, dstBase);
23490 if (imm == 1) {
23491 setMachineCodes(mi++, (byte) 0xD1);
23492 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
23493 } else {
23494 setMachineCodes(mi++, (byte) 0xC1);
23495 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
23496 emitImm8((byte)imm);
23497 }
23498 if (lister != null) lister.RNI(miStart, "ROL", dstBase, imm);
23499 }
23500
23501 /**
23502 * Generate a register-displacement--immediate ROL. That is,
23503 * <PRE>
23504 * rotate left of [dstBase + dstDisp] by imm
23505 * </PRE>
23506 *
23507 * @param dstBase the destination base register
23508 * @param dstDisp the destination displacement
23509 * @param imm immediate
23510 */
23511 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
23512 public final void emitROL_RegDisp_Imm_Word(GPR dstBase, Offset dstDisp, int imm) {
23513 int miStart = mi;
23514 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
23515 setMachineCodes(mi++, (byte) 0x66);
23516 generateREXprefix(false, null, null, dstBase);
23517 if (imm == 1) {
23518 setMachineCodes(mi++, (byte) 0xD1);
23519 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
23520 } else {
23521 setMachineCodes(mi++, (byte) 0xC1);
23522 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
23523 emitImm8((byte)imm);
23524 }
23525 if (lister != null) lister.RDI(miStart, "ROL", dstBase, dstDisp, imm);
23526 }
23527
23528 /**
23529 * Generate a register-offset--immediate ROL. That is,
23530 * <PRE>
23531 * rotate left of [dstIndex<<dstScale + dstDisp] by imm
23532 * </PRE>
23533 *
23534 * @param dstIndex the destination index register
23535 * @param dstScale the destination shift amount
23536 * @param dstDisp the destination displacement
23537 * @param imm immediate
23538 */
23539 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
23540 public final void emitROL_RegOff_Imm_Word(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
23541 int miStart = mi;
23542 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
23543 setMachineCodes(mi++, (byte) 0x66);
23544 generateREXprefix(false, null, dstIndex, null);
23545 if (imm == 1) {
23546 setMachineCodes(mi++, (byte) 0xD1);
23547 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
23548 } else {
23549 setMachineCodes(mi++, (byte) 0xC1);
23550 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
23551 emitImm8((byte)imm);
23552 }
23553 if (lister != null) lister.RFDI(miStart, "ROL", dstIndex, dstScale, dstDisp, imm);
23554 }
23555
23556 /**
23557 * Generate a absolute--immediate ROL. That is,
23558 * <PRE>
23559 * rotate left of [dstDisp] by imm
23560 * </PRE>
23561 *
23562 * @param dstDisp the destination displacement
23563 * @param imm immediate
23564 */
23565 public final void emitROL_Abs_Imm_Word(Address dstDisp, int imm) {
23566 int miStart = mi;
23567 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
23568 setMachineCodes(mi++, (byte) 0x66);
23569 generateREXprefix(false, null, null, null);
23570 if (imm == 1) {
23571 setMachineCodes(mi++, (byte) 0xD1);
23572 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
23573 } else {
23574 setMachineCodes(mi++, (byte) 0xC1);
23575 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
23576 emitImm8((byte)imm);
23577 }
23578 if (lister != null) lister.RAI(miStart, "ROL", dstDisp, imm);
23579 }
23580
23581 /**
23582 * Generate a register-index--immediate ROL. That is,
23583 * <PRE>
23584 * rotate left of [dstBase + dstIndex<<dstScale + dstDisp] by imm
23585 * </PRE>
23586 *
23587 * @param dstBase the destination base register
23588 * @param dstIndex the destination index register
23589 * @param dstScale the destination shift amount
23590 * @param dstDisp the destination displacement
23591 * @param imm immediate
23592 */
23593 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
23594 public final void emitROL_RegIdx_Imm_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
23595 int miStart = mi;
23596 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
23597 setMachineCodes(mi++, (byte) 0x66);
23598 generateREXprefix(false, null, dstIndex, dstBase);
23599 if (imm == 1) {
23600 setMachineCodes(mi++, (byte) 0xD1);
23601 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
23602 } else {
23603 setMachineCodes(mi++, (byte) 0xC1);
23604 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
23605 emitImm8((byte)imm);
23606 }
23607 if (lister != null) lister.RXDI(miStart, "ROL", dstBase, dstIndex, dstScale, dstDisp, imm);
23608 }
23609
23610 /**
23611 * Generate a register--register ROL. That is,
23612 * <PRE>
23613 * rotate left of dstReg by srcReg
23614 * </PRE>
23615 *
23616 * @param dstReg the destination register
23617 * @param srcReg must always be ECX
23618 */
23619 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
23620 public final void emitROL_Reg_Reg_Word(GPR dstReg, GPR srcReg) {
23621 int miStart = mi;
23622 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
23623 setMachineCodes(mi++, (byte) 0x66);
23624 generateREXprefix(false, null, null, dstReg);
23625 setMachineCodes(mi++, (byte) 0xD3);
23626 emitRegRegOperands(dstReg, GPR.getForOpcode(0x0));
23627 if (lister != null) lister.RR(miStart, "ROL", dstReg, srcReg);
23628 }
23629
23630 /**
23631 * Generate a register-indirect--register ROL. That is,
23632 * <PRE>
23633 * rotate left of [dstBase] by srcReg
23634 * </PRE>
23635 *
23636 * @param dstBase the destination register
23637 * @param srcReg must always be ECX
23638 */
23639 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
23640 public final void emitROL_RegInd_Reg_Word(GPR dstBase, GPR srcReg) {
23641 int miStart = mi;
23642 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
23643 setMachineCodes(mi++, (byte) 0x66);
23644 generateREXprefix(false, null, null, dstBase);
23645 setMachineCodes(mi++, (byte) 0xD3);
23646 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
23647 if (lister != null) lister.RNR(miStart, "ROL", dstBase, srcReg);
23648 }
23649
23650 /**
23651 * Generate a register-displacement--register ROL. That is,
23652 * <PRE>
23653 * rotate left of [dstBase + dstDisp] by srcReg
23654 * </PRE>
23655 *
23656 * @param dstBase the destination base register
23657 * @param dstDisp the destination displacement
23658 * @param srcReg must always be ECX
23659 */
23660 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
23661 public final void emitROL_RegDisp_Reg_Word(GPR dstBase, Offset dstDisp, GPR srcReg) {
23662 int miStart = mi;
23663 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
23664 setMachineCodes(mi++, (byte) 0x66);
23665 generateREXprefix(false, null, null, dstBase);
23666 setMachineCodes(mi++, (byte) 0xD3);
23667 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
23668 if (lister != null) lister.RDR(miStart, "ROL", dstBase, dstDisp, srcReg);
23669 }
23670
23671 /**
23672 * Generate a register-offset--register ROL. That is,
23673 * <PRE>
23674 * rotate left of [dstIndex<<dstScale + dstDisp] by srcReg
23675 * </PRE>
23676 *
23677 * @param dstIndex the destination index register
23678 * @param dstScale the destination shift amount
23679 * @param dstDisp the destination displacement
23680 * @param srcReg must always be ECX
23681 */
23682 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
23683 public final void emitROL_RegOff_Reg_Word(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
23684 int miStart = mi;
23685 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
23686 setMachineCodes(mi++, (byte) 0x66);
23687 generateREXprefix(false, null, dstIndex, null);
23688 setMachineCodes(mi++, (byte) 0xD3);
23689 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
23690 if (lister != null) lister.RFDR(miStart, "ROL", dstIndex, dstScale, dstDisp, srcReg);
23691 }
23692
23693 /**
23694 * Generate an absolute--register ROL. That is,
23695 * <PRE>
23696 * rotate left of [dstDisp] by srcReg
23697 * </PRE>
23698 *
23699 * @param dstDisp the destination displacement
23700 * @param srcReg must always be ECX
23701 */
23702 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
23703 public final void emitROL_Abs_Reg_Word(Address dstDisp, GPR srcReg) {
23704 int miStart = mi;
23705 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
23706 setMachineCodes(mi++, (byte) 0x66);
23707 generateREXprefix(false, null, null, null);
23708 setMachineCodes(mi++, (byte) 0xD3);
23709 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
23710 if (lister != null) lister.RAR(miStart, "ROL", dstDisp, srcReg);
23711 }
23712
23713 /**
23714 * Generate a register-displacement--register ROL. That is,
23715 * <PRE>
23716 * rotate left of [dstBase + dstIndex<<dstScale + dstDisp] by srcReg
23717 * </PRE>
23718 *
23719 * @param dstBase the destination base register
23720 * @param dstIndex the destination index register
23721 * @param dstScale the destination shift amount
23722 * @param dstDisp the destination displacement
23723 * @param srcReg must always be ECX
23724 */
23725 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
23726 public final void emitROL_RegIdx_Reg_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
23727 int miStart = mi;
23728 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
23729 setMachineCodes(mi++, (byte) 0x66);
23730 generateREXprefix(false, null, dstIndex, dstBase);
23731 setMachineCodes(mi++, (byte) 0xD3);
23732 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
23733 if (lister != null) lister.RXDR(miStart, "ROL", dstBase, dstIndex, dstScale, dstDisp, srcReg);
23734 }
23735
23736 /**
23737 * Generate a register--immediate ROL. That is,
23738 * <PRE>
23739 * rotate left of dstReg by imm
23740 * </PRE>
23741 *
23742 * @param dstReg the destination register
23743 * @param imm immediate
23744 */
23745 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
23746 public final void emitROL_Reg_Imm(GPR dstReg, int imm) {
23747 int miStart = mi;
23748 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
23749 // no size prefix
23750 generateREXprefix(false, null, null, dstReg);
23751 if (imm == 1) {
23752 setMachineCodes(mi++, (byte) 0xD1);
23753 emitRegRegOperands(dstReg, GPR.getForOpcode(0x0));
23754 } else {
23755 setMachineCodes(mi++, (byte) 0xC1);
23756 emitRegRegOperands(dstReg, GPR.getForOpcode(0x0));
23757 emitImm8((byte)imm);
23758 }
23759 if (lister != null) lister.RI(miStart, "ROL", dstReg, imm);
23760 }
23761
23762 /**
23763 * Generate a register-indirect--immediate ROL. That is,
23764 * <PRE>
23765 * rotate left of [dstBase] by imm
23766 * </PRE>
23767 *
23768 * @param dstBase the destination base register
23769 * @param imm immediate
23770 */
23771 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
23772 public final void emitROL_RegInd_Imm(GPR dstBase, int imm) {
23773 int miStart = mi;
23774 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
23775 // no size prefix
23776 generateREXprefix(false, null, null, dstBase);
23777 if (imm == 1) {
23778 setMachineCodes(mi++, (byte) 0xD1);
23779 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
23780 } else {
23781 setMachineCodes(mi++, (byte) 0xC1);
23782 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
23783 emitImm8((byte)imm);
23784 }
23785 if (lister != null) lister.RNI(miStart, "ROL", dstBase, imm);
23786 }
23787
23788 /**
23789 * Generate a register-displacement--immediate ROL. That is,
23790 * <PRE>
23791 * rotate left of [dstBase + dstDisp] by imm
23792 * </PRE>
23793 *
23794 * @param dstBase the destination base register
23795 * @param dstDisp the destination displacement
23796 * @param imm immediate
23797 */
23798 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
23799 public final void emitROL_RegDisp_Imm(GPR dstBase, Offset dstDisp, int imm) {
23800 int miStart = mi;
23801 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
23802 // no size prefix
23803 generateREXprefix(false, null, null, dstBase);
23804 if (imm == 1) {
23805 setMachineCodes(mi++, (byte) 0xD1);
23806 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
23807 } else {
23808 setMachineCodes(mi++, (byte) 0xC1);
23809 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
23810 emitImm8((byte)imm);
23811 }
23812 if (lister != null) lister.RDI(miStart, "ROL", dstBase, dstDisp, imm);
23813 }
23814
23815 /**
23816 * Generate a register-offset--immediate ROL. That is,
23817 * <PRE>
23818 * rotate left of [dstIndex<<dstScale + dstDisp] by imm
23819 * </PRE>
23820 *
23821 * @param dstIndex the destination index register
23822 * @param dstScale the destination shift amount
23823 * @param dstDisp the destination displacement
23824 * @param imm immediate
23825 */
23826 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
23827 public final void emitROL_RegOff_Imm(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
23828 int miStart = mi;
23829 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
23830 // no size prefix
23831 generateREXprefix(false, null, dstIndex, null);
23832 if (imm == 1) {
23833 setMachineCodes(mi++, (byte) 0xD1);
23834 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
23835 } else {
23836 setMachineCodes(mi++, (byte) 0xC1);
23837 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
23838 emitImm8((byte)imm);
23839 }
23840 if (lister != null) lister.RFDI(miStart, "ROL", dstIndex, dstScale, dstDisp, imm);
23841 }
23842
23843 /**
23844 * Generate a absolute--immediate ROL. That is,
23845 * <PRE>
23846 * rotate left of [dstDisp] by imm
23847 * </PRE>
23848 *
23849 * @param dstDisp the destination displacement
23850 * @param imm immediate
23851 */
23852 public final void emitROL_Abs_Imm(Address dstDisp, int imm) {
23853 int miStart = mi;
23854 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
23855 // no size prefix
23856 generateREXprefix(false, null, null, null);
23857 if (imm == 1) {
23858 setMachineCodes(mi++, (byte) 0xD1);
23859 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
23860 } else {
23861 setMachineCodes(mi++, (byte) 0xC1);
23862 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
23863 emitImm8((byte)imm);
23864 }
23865 if (lister != null) lister.RAI(miStart, "ROL", dstDisp, imm);
23866 }
23867
23868 /**
23869 * Generate a register-index--immediate ROL. That is,
23870 * <PRE>
23871 * rotate left of [dstBase + dstIndex<<dstScale + dstDisp] by imm
23872 * </PRE>
23873 *
23874 * @param dstBase the destination base register
23875 * @param dstIndex the destination index register
23876 * @param dstScale the destination shift amount
23877 * @param dstDisp the destination displacement
23878 * @param imm immediate
23879 */
23880 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
23881 public final void emitROL_RegIdx_Imm(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
23882 int miStart = mi;
23883 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
23884 // no size prefix
23885 generateREXprefix(false, null, dstIndex, dstBase);
23886 if (imm == 1) {
23887 setMachineCodes(mi++, (byte) 0xD1);
23888 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
23889 } else {
23890 setMachineCodes(mi++, (byte) 0xC1);
23891 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
23892 emitImm8((byte)imm);
23893 }
23894 if (lister != null) lister.RXDI(miStart, "ROL", dstBase, dstIndex, dstScale, dstDisp, imm);
23895 }
23896
23897 /**
23898 * Generate a register--register ROL. That is,
23899 * <PRE>
23900 * rotate left of dstReg by srcReg
23901 * </PRE>
23902 *
23903 * @param dstReg the destination register
23904 * @param srcReg must always be ECX
23905 */
23906 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
23907 public final void emitROL_Reg_Reg(GPR dstReg, GPR srcReg) {
23908 int miStart = mi;
23909 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
23910 // no size prefix
23911 generateREXprefix(false, null, null, dstReg);
23912 setMachineCodes(mi++, (byte) 0xD3);
23913 emitRegRegOperands(dstReg, GPR.getForOpcode(0x0));
23914 if (lister != null) lister.RR(miStart, "ROL", dstReg, srcReg);
23915 }
23916
23917 /**
23918 * Generate a register-indirect--register ROL. That is,
23919 * <PRE>
23920 * rotate left of [dstBase] by srcReg
23921 * </PRE>
23922 *
23923 * @param dstBase the destination register
23924 * @param srcReg must always be ECX
23925 */
23926 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
23927 public final void emitROL_RegInd_Reg(GPR dstBase, GPR srcReg) {
23928 int miStart = mi;
23929 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
23930 // no size prefix
23931 generateREXprefix(false, null, null, dstBase);
23932 setMachineCodes(mi++, (byte) 0xD3);
23933 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
23934 if (lister != null) lister.RNR(miStart, "ROL", dstBase, srcReg);
23935 }
23936
23937 /**
23938 * Generate a register-displacement--register ROL. That is,
23939 * <PRE>
23940 * rotate left of [dstBase + dstDisp] by srcReg
23941 * </PRE>
23942 *
23943 * @param dstBase the destination base register
23944 * @param dstDisp the destination displacement
23945 * @param srcReg must always be ECX
23946 */
23947 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
23948 public final void emitROL_RegDisp_Reg(GPR dstBase, Offset dstDisp, GPR srcReg) {
23949 int miStart = mi;
23950 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
23951 // no size prefix
23952 generateREXprefix(false, null, null, dstBase);
23953 setMachineCodes(mi++, (byte) 0xD3);
23954 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
23955 if (lister != null) lister.RDR(miStart, "ROL", dstBase, dstDisp, srcReg);
23956 }
23957
23958 /**
23959 * Generate a register-offset--register ROL. That is,
23960 * <PRE>
23961 * rotate left of [dstIndex<<dstScale + dstDisp] by srcReg
23962 * </PRE>
23963 *
23964 * @param dstIndex the destination index register
23965 * @param dstScale the destination shift amount
23966 * @param dstDisp the destination displacement
23967 * @param srcReg must always be ECX
23968 */
23969 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
23970 public final void emitROL_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
23971 int miStart = mi;
23972 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
23973 // no size prefix
23974 generateREXprefix(false, null, dstIndex, null);
23975 setMachineCodes(mi++, (byte) 0xD3);
23976 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
23977 if (lister != null) lister.RFDR(miStart, "ROL", dstIndex, dstScale, dstDisp, srcReg);
23978 }
23979
23980 /**
23981 * Generate an absolute--register ROL. That is,
23982 * <PRE>
23983 * rotate left of [dstDisp] by srcReg
23984 * </PRE>
23985 *
23986 * @param dstDisp the destination displacement
23987 * @param srcReg must always be ECX
23988 */
23989 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
23990 public final void emitROL_Abs_Reg(Address dstDisp, GPR srcReg) {
23991 int miStart = mi;
23992 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
23993 // no size prefix
23994 generateREXprefix(false, null, null, null);
23995 setMachineCodes(mi++, (byte) 0xD3);
23996 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
23997 if (lister != null) lister.RAR(miStart, "ROL", dstDisp, srcReg);
23998 }
23999
24000 /**
24001 * Generate a register-displacement--register ROL. That is,
24002 * <PRE>
24003 * rotate left of [dstBase + dstIndex<<dstScale + dstDisp] by srcReg
24004 * </PRE>
24005 *
24006 * @param dstBase the destination base register
24007 * @param dstIndex the destination index register
24008 * @param dstScale the destination shift amount
24009 * @param dstDisp the destination displacement
24010 * @param srcReg must always be ECX
24011 */
24012 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
24013 public final void emitROL_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
24014 int miStart = mi;
24015 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
24016 // no size prefix
24017 generateREXprefix(false, null, dstIndex, dstBase);
24018 setMachineCodes(mi++, (byte) 0xD3);
24019 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
24020 if (lister != null) lister.RXDR(miStart, "ROL", dstBase, dstIndex, dstScale, dstDisp, srcReg);
24021 }
24022
24023 /**
24024 * Generate a register--immediate ROL. That is,
24025 * <PRE>
24026 * rotate left of dstReg by imm
24027 * </PRE>
24028 *
24029 * @param dstReg the destination register
24030 * @param imm immediate
24031 */
24032 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
24033 public final void emitROL_Reg_Imm_Quad(GPR dstReg, int imm) {
24034 int miStart = mi;
24035 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
24036 // no size prefix
24037 generateREXprefix(true, null, null, dstReg);
24038 if (imm == 1) {
24039 setMachineCodes(mi++, (byte) 0xD1);
24040 emitRegRegOperands(dstReg, GPR.getForOpcode(0x0));
24041 } else {
24042 setMachineCodes(mi++, (byte) 0xC1);
24043 emitRegRegOperands(dstReg, GPR.getForOpcode(0x0));
24044 emitImm8((byte)imm);
24045 }
24046 if (lister != null) lister.RI(miStart, "ROL", dstReg, imm);
24047 }
24048
24049 /**
24050 * Generate a register-indirect--immediate ROL. That is,
24051 * <PRE>
24052 * rotate left of [dstBase] by imm
24053 * </PRE>
24054 *
24055 * @param dstBase the destination base register
24056 * @param imm immediate
24057 */
24058 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
24059 public final void emitROL_RegInd_Imm_Quad(GPR dstBase, int imm) {
24060 int miStart = mi;
24061 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
24062 // no size prefix
24063 generateREXprefix(true, null, null, dstBase);
24064 if (imm == 1) {
24065 setMachineCodes(mi++, (byte) 0xD1);
24066 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
24067 } else {
24068 setMachineCodes(mi++, (byte) 0xC1);
24069 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
24070 emitImm8((byte)imm);
24071 }
24072 if (lister != null) lister.RNI(miStart, "ROL", dstBase, imm);
24073 }
24074
24075 /**
24076 * Generate a register-displacement--immediate ROL. That is,
24077 * <PRE>
24078 * rotate left of [dstBase + dstDisp] by imm
24079 * </PRE>
24080 *
24081 * @param dstBase the destination base register
24082 * @param dstDisp the destination displacement
24083 * @param imm immediate
24084 */
24085 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
24086 public final void emitROL_RegDisp_Imm_Quad(GPR dstBase, Offset dstDisp, int imm) {
24087 int miStart = mi;
24088 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
24089 // no size prefix
24090 generateREXprefix(true, null, null, dstBase);
24091 if (imm == 1) {
24092 setMachineCodes(mi++, (byte) 0xD1);
24093 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
24094 } else {
24095 setMachineCodes(mi++, (byte) 0xC1);
24096 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
24097 emitImm8((byte)imm);
24098 }
24099 if (lister != null) lister.RDI(miStart, "ROL", dstBase, dstDisp, imm);
24100 }
24101
24102 /**
24103 * Generate a register-offset--immediate ROL. That is,
24104 * <PRE>
24105 * rotate left of [dstIndex<<dstScale + dstDisp] by imm
24106 * </PRE>
24107 *
24108 * @param dstIndex the destination index register
24109 * @param dstScale the destination shift amount
24110 * @param dstDisp the destination displacement
24111 * @param imm immediate
24112 */
24113 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
24114 public final void emitROL_RegOff_Imm_Quad(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
24115 int miStart = mi;
24116 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
24117 // no size prefix
24118 generateREXprefix(true, null, dstIndex, null);
24119 if (imm == 1) {
24120 setMachineCodes(mi++, (byte) 0xD1);
24121 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
24122 } else {
24123 setMachineCodes(mi++, (byte) 0xC1);
24124 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
24125 emitImm8((byte)imm);
24126 }
24127 if (lister != null) lister.RFDI(miStart, "ROL", dstIndex, dstScale, dstDisp, imm);
24128 }
24129
24130 /**
24131 * Generate a absolute--immediate ROL. That is,
24132 * <PRE>
24133 * rotate left of [dstDisp] by imm
24134 * </PRE>
24135 *
24136 * @param dstDisp the destination displacement
24137 * @param imm immediate
24138 */
24139 public final void emitROL_Abs_Imm_Quad(Address dstDisp, int imm) {
24140 int miStart = mi;
24141 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
24142 // no size prefix
24143 generateREXprefix(true, null, null, null);
24144 if (imm == 1) {
24145 setMachineCodes(mi++, (byte) 0xD1);
24146 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
24147 } else {
24148 setMachineCodes(mi++, (byte) 0xC1);
24149 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
24150 emitImm8((byte)imm);
24151 }
24152 if (lister != null) lister.RAI(miStart, "ROL", dstDisp, imm);
24153 }
24154
24155 /**
24156 * Generate a register-index--immediate ROL. That is,
24157 * <PRE>
24158 * rotate left of [dstBase + dstIndex<<dstScale + dstDisp] by imm
24159 * </PRE>
24160 *
24161 * @param dstBase the destination base register
24162 * @param dstIndex the destination index register
24163 * @param dstScale the destination shift amount
24164 * @param dstDisp the destination displacement
24165 * @param imm immediate
24166 */
24167 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
24168 public final void emitROL_RegIdx_Imm_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
24169 int miStart = mi;
24170 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
24171 // no size prefix
24172 generateREXprefix(true, null, dstIndex, dstBase);
24173 if (imm == 1) {
24174 setMachineCodes(mi++, (byte) 0xD1);
24175 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
24176 } else {
24177 setMachineCodes(mi++, (byte) 0xC1);
24178 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
24179 emitImm8((byte)imm);
24180 }
24181 if (lister != null) lister.RXDI(miStart, "ROL", dstBase, dstIndex, dstScale, dstDisp, imm);
24182 }
24183
24184 /**
24185 * Generate a register--register ROL. That is,
24186 * <PRE>
24187 * rotate left of dstReg by srcReg
24188 * </PRE>
24189 *
24190 * @param dstReg the destination register
24191 * @param srcReg must always be ECX
24192 */
24193 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
24194 public final void emitROL_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
24195 int miStart = mi;
24196 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
24197 // no size prefix
24198 generateREXprefix(true, null, null, dstReg);
24199 setMachineCodes(mi++, (byte) 0xD3);
24200 emitRegRegOperands(dstReg, GPR.getForOpcode(0x0));
24201 if (lister != null) lister.RR(miStart, "ROL", dstReg, srcReg);
24202 }
24203
24204 /**
24205 * Generate a register-indirect--register ROL. That is,
24206 * <PRE>
24207 * rotate left of [dstBase] by srcReg
24208 * </PRE>
24209 *
24210 * @param dstBase the destination register
24211 * @param srcReg must always be ECX
24212 */
24213 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
24214 public final void emitROL_RegInd_Reg_Quad(GPR dstBase, GPR srcReg) {
24215 int miStart = mi;
24216 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
24217 // no size prefix
24218 generateREXprefix(true, null, null, dstBase);
24219 setMachineCodes(mi++, (byte) 0xD3);
24220 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x0));
24221 if (lister != null) lister.RNR(miStart, "ROL", dstBase, srcReg);
24222 }
24223
24224 /**
24225 * Generate a register-displacement--register ROL. That is,
24226 * <PRE>
24227 * rotate left of [dstBase + dstDisp] by srcReg
24228 * </PRE>
24229 *
24230 * @param dstBase the destination base register
24231 * @param dstDisp the destination displacement
24232 * @param srcReg must always be ECX
24233 */
24234 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
24235 public final void emitROL_RegDisp_Reg_Quad(GPR dstBase, Offset dstDisp, GPR srcReg) {
24236 int miStart = mi;
24237 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
24238 // no size prefix
24239 generateREXprefix(true, null, null, dstBase);
24240 setMachineCodes(mi++, (byte) 0xD3);
24241 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x0));
24242 if (lister != null) lister.RDR(miStart, "ROL", dstBase, dstDisp, srcReg);
24243 }
24244
24245 /**
24246 * Generate a register-offset--register ROL. That is,
24247 * <PRE>
24248 * rotate left of [dstIndex<<dstScale + dstDisp] by srcReg
24249 * </PRE>
24250 *
24251 * @param dstIndex the destination index register
24252 * @param dstScale the destination shift amount
24253 * @param dstDisp the destination displacement
24254 * @param srcReg must always be ECX
24255 */
24256 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
24257 public final void emitROL_RegOff_Reg_Quad(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
24258 int miStart = mi;
24259 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
24260 // no size prefix
24261 generateREXprefix(true, null, dstIndex, null);
24262 setMachineCodes(mi++, (byte) 0xD3);
24263 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
24264 if (lister != null) lister.RFDR(miStart, "ROL", dstIndex, dstScale, dstDisp, srcReg);
24265 }
24266
24267 /**
24268 * Generate an absolute--register ROL. That is,
24269 * <PRE>
24270 * rotate left of [dstDisp] by srcReg
24271 * </PRE>
24272 *
24273 * @param dstDisp the destination displacement
24274 * @param srcReg must always be ECX
24275 */
24276 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
24277 public final void emitROL_Abs_Reg_Quad(Address dstDisp, GPR srcReg) {
24278 int miStart = mi;
24279 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
24280 // no size prefix
24281 generateREXprefix(true, null, null, null);
24282 setMachineCodes(mi++, (byte) 0xD3);
24283 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x0));
24284 if (lister != null) lister.RAR(miStart, "ROL", dstDisp, srcReg);
24285 }
24286
24287 /**
24288 * Generate a register-displacement--register ROL. That is,
24289 * <PRE>
24290 * rotate left of [dstBase + dstIndex<<dstScale + dstDisp] by srcReg
24291 * </PRE>
24292 *
24293 * @param dstBase the destination base register
24294 * @param dstIndex the destination index register
24295 * @param dstScale the destination shift amount
24296 * @param dstDisp the destination displacement
24297 * @param srcReg must always be ECX
24298 */
24299 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
24300 public final void emitROL_RegIdx_Reg_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
24301 int miStart = mi;
24302 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
24303 // no size prefix
24304 generateREXprefix(true, null, dstIndex, dstBase);
24305 setMachineCodes(mi++, (byte) 0xD3);
24306 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x0));
24307 if (lister != null) lister.RXDR(miStart, "ROL", dstBase, dstIndex, dstScale, dstDisp, srcReg);
24308 }
24309
24310 /**
24311 * Generate a register--immediate ROR. That is,
24312 * <PRE>
24313 * rotate right of dstReg by imm
24314 * </PRE>
24315 *
24316 * @param dstReg the destination register
24317 * @param imm immediate
24318 */
24319 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
24320 public final void emitROR_Reg_Imm_Byte(GPR dstReg, int imm) {
24321 int miStart = mi;
24322 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
24323 // no size prefix
24324 generateREXprefix(false, null, null, dstReg);
24325 if (imm == 1) {
24326 setMachineCodes(mi++, (byte) 0xD0);
24327 emitRegRegOperands(dstReg, GPR.getForOpcode(0x1));
24328 } else {
24329 setMachineCodes(mi++, (byte) 0xC0);
24330 emitRegRegOperands(dstReg, GPR.getForOpcode(0x1));
24331 emitImm8((byte)imm);
24332 }
24333 if (lister != null) lister.RI(miStart, "ROR", dstReg, imm);
24334 }
24335
24336 /**
24337 * Generate a register-indirect--immediate ROR. That is,
24338 * <PRE>
24339 * rotate right of [dstBase] by imm
24340 * </PRE>
24341 *
24342 * @param dstBase the destination base register
24343 * @param imm immediate
24344 */
24345 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
24346 public final void emitROR_RegInd_Imm_Byte(GPR dstBase, int imm) {
24347 int miStart = mi;
24348 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
24349 // no size prefix
24350 generateREXprefix(false, null, null, dstBase);
24351 if (imm == 1) {
24352 setMachineCodes(mi++, (byte) 0xD0);
24353 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x1));
24354 } else {
24355 setMachineCodes(mi++, (byte) 0xC0);
24356 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x1));
24357 emitImm8((byte)imm);
24358 }
24359 if (lister != null) lister.RNI(miStart, "ROR", dstBase, imm);
24360 }
24361
24362 /**
24363 * Generate a register-displacement--immediate ROR. That is,
24364 * <PRE>
24365 * rotate right of [dstBase + dstDisp] by imm
24366 * </PRE>
24367 *
24368 * @param dstBase the destination base register
24369 * @param dstDisp the destination displacement
24370 * @param imm immediate
24371 */
24372 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
24373 public final void emitROR_RegDisp_Imm_Byte(GPR dstBase, Offset dstDisp, int imm) {
24374 int miStart = mi;
24375 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
24376 // no size prefix
24377 generateREXprefix(false, null, null, dstBase);
24378 if (imm == 1) {
24379 setMachineCodes(mi++, (byte) 0xD0);
24380 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x1));
24381 } else {
24382 setMachineCodes(mi++, (byte) 0xC0);
24383 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x1));
24384 emitImm8((byte)imm);
24385 }
24386 if (lister != null) lister.RDI(miStart, "ROR", dstBase, dstDisp, imm);
24387 }
24388
24389 /**
24390 * Generate a register-offset--immediate ROR. That is,
24391 * <PRE>
24392 * rotate right of [dstIndex<<dstScale + dstDisp] by imm
24393 * </PRE>
24394 *
24395 * @param dstIndex the destination index register
24396 * @param dstScale the destination shift amount
24397 * @param dstDisp the destination displacement
24398 * @param imm immediate
24399 */
24400 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
24401 public final void emitROR_RegOff_Imm_Byte(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
24402 int miStart = mi;
24403 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
24404 // no size prefix
24405 generateREXprefix(false, null, dstIndex, null);
24406 if (imm == 1) {
24407 setMachineCodes(mi++, (byte) 0xD0);
24408 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
24409 } else {
24410 setMachineCodes(mi++, (byte) 0xC0);
24411 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
24412 emitImm8((byte)imm);
24413 }
24414 if (lister != null) lister.RFDI(miStart, "ROR", dstIndex, dstScale, dstDisp, imm);
24415 }
24416
24417 /**
24418 * Generate a absolute--immediate ROR. That is,
24419 * <PRE>
24420 * rotate right of [dstDisp] by imm
24421 * </PRE>
24422 *
24423 * @param dstDisp the destination displacement
24424 * @param imm immediate
24425 */
24426 public final void emitROR_Abs_Imm_Byte(Address dstDisp, int imm) {
24427 int miStart = mi;
24428 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
24429 // no size prefix
24430 generateREXprefix(false, null, null, null);
24431 if (imm == 1) {
24432 setMachineCodes(mi++, (byte) 0xD0);
24433 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x1));
24434 } else {
24435 setMachineCodes(mi++, (byte) 0xC0);
24436 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x1));
24437 emitImm8((byte)imm);
24438 }
24439 if (lister != null) lister.RAI(miStart, "ROR", dstDisp, imm);
24440 }
24441
24442 /**
24443 * Generate a register-index--immediate ROR. That is,
24444 * <PRE>
24445 * rotate right of [dstBase + dstIndex<<dstScale + dstDisp] by imm
24446 * </PRE>
24447 *
24448 * @param dstBase the destination base register
24449 * @param dstIndex the destination index register
24450 * @param dstScale the destination shift amount
24451 * @param dstDisp the destination displacement
24452 * @param imm immediate
24453 */
24454 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
24455 public final void emitROR_RegIdx_Imm_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
24456 int miStart = mi;
24457 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
24458 // no size prefix
24459 generateREXprefix(false, null, dstIndex, dstBase);
24460 if (imm == 1) {
24461 setMachineCodes(mi++, (byte) 0xD0);
24462 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
24463 } else {
24464 setMachineCodes(mi++, (byte) 0xC0);
24465 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
24466 emitImm8((byte)imm);
24467 }
24468 if (lister != null) lister.RXDI(miStart, "ROR", dstBase, dstIndex, dstScale, dstDisp, imm);
24469 }
24470
24471 /**
24472 * Generate a register--register ROR. That is,
24473 * <PRE>
24474 * rotate right of dstReg by srcReg
24475 * </PRE>
24476 *
24477 * @param dstReg the destination register
24478 * @param srcReg must always be ECX
24479 */
24480 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
24481 public final void emitROR_Reg_Reg_Byte(GPR dstReg, GPR srcReg) {
24482 int miStart = mi;
24483 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
24484 // no size prefix
24485 generateREXprefix(false, null, null, dstReg);
24486 setMachineCodes(mi++, (byte) 0xD2);
24487 emitRegRegOperands(dstReg, GPR.getForOpcode(0x1));
24488 if (lister != null) lister.RR(miStart, "ROR", dstReg, srcReg);
24489 }
24490
24491 /**
24492 * Generate a register-indirect--register ROR. That is,
24493 * <PRE>
24494 * rotate right of [dstBase] by srcReg
24495 * </PRE>
24496 *
24497 * @param dstBase the destination register
24498 * @param srcReg must always be ECX
24499 */
24500 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
24501 public final void emitROR_RegInd_Reg_Byte(GPR dstBase, GPR srcReg) {
24502 int miStart = mi;
24503 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
24504 // no size prefix
24505 generateREXprefix(false, null, null, dstBase);
24506 setMachineCodes(mi++, (byte) 0xD2);
24507 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x1));
24508 if (lister != null) lister.RNR(miStart, "ROR", dstBase, srcReg);
24509 }
24510
24511 /**
24512 * Generate a register-displacement--register ROR. That is,
24513 * <PRE>
24514 * rotate right of [dstBase + dstDisp] by srcReg
24515 * </PRE>
24516 *
24517 * @param dstBase the destination base register
24518 * @param dstDisp the destination displacement
24519 * @param srcReg must always be ECX
24520 */
24521 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
24522 public final void emitROR_RegDisp_Reg_Byte(GPR dstBase, Offset dstDisp, GPR srcReg) {
24523 int miStart = mi;
24524 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
24525 // no size prefix
24526 generateREXprefix(false, null, null, dstBase);
24527 setMachineCodes(mi++, (byte) 0xD2);
24528 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x1));
24529 if (lister != null) lister.RDR(miStart, "ROR", dstBase, dstDisp, srcReg);
24530 }
24531
24532 /**
24533 * Generate a register-offset--register ROR. That is,
24534 * <PRE>
24535 * rotate right of [dstIndex<<dstScale + dstDisp] by srcReg
24536 * </PRE>
24537 *
24538 * @param dstIndex the destination index register
24539 * @param dstScale the destination shift amount
24540 * @param dstDisp the destination displacement
24541 * @param srcReg must always be ECX
24542 */
24543 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
24544 public final void emitROR_RegOff_Reg_Byte(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
24545 int miStart = mi;
24546 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
24547 // no size prefix
24548 generateREXprefix(false, null, dstIndex, null);
24549 setMachineCodes(mi++, (byte) 0xD2);
24550 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
24551 if (lister != null) lister.RFDR(miStart, "ROR", dstIndex, dstScale, dstDisp, srcReg);
24552 }
24553
24554 /**
24555 * Generate an absolute--register ROR. That is,
24556 * <PRE>
24557 * rotate right of [dstDisp] by srcReg
24558 * </PRE>
24559 *
24560 * @param dstDisp the destination displacement
24561 * @param srcReg must always be ECX
24562 */
24563 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
24564 public final void emitROR_Abs_Reg_Byte(Address dstDisp, GPR srcReg) {
24565 int miStart = mi;
24566 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
24567 // no size prefix
24568 generateREXprefix(false, null, null, null);
24569 setMachineCodes(mi++, (byte) 0xD2);
24570 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x1));
24571 if (lister != null) lister.RAR(miStart, "ROR", dstDisp, srcReg);
24572 }
24573
24574 /**
24575 * Generate a register-displacement--register ROR. That is,
24576 * <PRE>
24577 * rotate right of [dstBase + dstIndex<<dstScale + dstDisp] by srcReg
24578 * </PRE>
24579 *
24580 * @param dstBase the destination base register
24581 * @param dstIndex the destination index register
24582 * @param dstScale the destination shift amount
24583 * @param dstDisp the destination displacement
24584 * @param srcReg must always be ECX
24585 */
24586 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
24587 public final void emitROR_RegIdx_Reg_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
24588 int miStart = mi;
24589 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
24590 // no size prefix
24591 generateREXprefix(false, null, dstIndex, dstBase);
24592 setMachineCodes(mi++, (byte) 0xD2);
24593 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
24594 if (lister != null) lister.RXDR(miStart, "ROR", dstBase, dstIndex, dstScale, dstDisp, srcReg);
24595 }
24596
24597 /**
24598 * Generate a register--immediate ROR. That is,
24599 * <PRE>
24600 * rotate right of dstReg by imm
24601 * </PRE>
24602 *
24603 * @param dstReg the destination register
24604 * @param imm immediate
24605 */
24606 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
24607 public final void emitROR_Reg_Imm_Word(GPR dstReg, int imm) {
24608 int miStart = mi;
24609 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
24610 setMachineCodes(mi++, (byte) 0x66);
24611 generateREXprefix(false, null, null, dstReg);
24612 if (imm == 1) {
24613 setMachineCodes(mi++, (byte) 0xD1);
24614 emitRegRegOperands(dstReg, GPR.getForOpcode(0x1));
24615 } else {
24616 setMachineCodes(mi++, (byte) 0xC1);
24617 emitRegRegOperands(dstReg, GPR.getForOpcode(0x1));
24618 emitImm8((byte)imm);
24619 }
24620 if (lister != null) lister.RI(miStart, "ROR", dstReg, imm);
24621 }
24622
24623 /**
24624 * Generate a register-indirect--immediate ROR. That is,
24625 * <PRE>
24626 * rotate right of [dstBase] by imm
24627 * </PRE>
24628 *
24629 * @param dstBase the destination base register
24630 * @param imm immediate
24631 */
24632 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
24633 public final void emitROR_RegInd_Imm_Word(GPR dstBase, int imm) {
24634 int miStart = mi;
24635 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
24636 setMachineCodes(mi++, (byte) 0x66);
24637 generateREXprefix(false, null, null, dstBase);
24638 if (imm == 1) {
24639 setMachineCodes(mi++, (byte) 0xD1);
24640 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x1));
24641 } else {
24642 setMachineCodes(mi++, (byte) 0xC1);
24643 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x1));
24644 emitImm8((byte)imm);
24645 }
24646 if (lister != null) lister.RNI(miStart, "ROR", dstBase, imm);
24647 }
24648
24649 /**
24650 * Generate a register-displacement--immediate ROR. That is,
24651 * <PRE>
24652 * rotate right of [dstBase + dstDisp] by imm
24653 * </PRE>
24654 *
24655 * @param dstBase the destination base register
24656 * @param dstDisp the destination displacement
24657 * @param imm immediate
24658 */
24659 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
24660 public final void emitROR_RegDisp_Imm_Word(GPR dstBase, Offset dstDisp, int imm) {
24661 int miStart = mi;
24662 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
24663 setMachineCodes(mi++, (byte) 0x66);
24664 generateREXprefix(false, null, null, dstBase);
24665 if (imm == 1) {
24666 setMachineCodes(mi++, (byte) 0xD1);
24667 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x1));
24668 } else {
24669 setMachineCodes(mi++, (byte) 0xC1);
24670 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x1));
24671 emitImm8((byte)imm);
24672 }
24673 if (lister != null) lister.RDI(miStart, "ROR", dstBase, dstDisp, imm);
24674 }
24675
24676 /**
24677 * Generate a register-offset--immediate ROR. That is,
24678 * <PRE>
24679 * rotate right of [dstIndex<<dstScale + dstDisp] by imm
24680 * </PRE>
24681 *
24682 * @param dstIndex the destination index register
24683 * @param dstScale the destination shift amount
24684 * @param dstDisp the destination displacement
24685 * @param imm immediate
24686 */
24687 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
24688 public final void emitROR_RegOff_Imm_Word(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
24689 int miStart = mi;
24690 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
24691 setMachineCodes(mi++, (byte) 0x66);
24692 generateREXprefix(false, null, dstIndex, null);
24693 if (imm == 1) {
24694 setMachineCodes(mi++, (byte) 0xD1);
24695 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
24696 } else {
24697 setMachineCodes(mi++, (byte) 0xC1);
24698 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
24699 emitImm8((byte)imm);
24700 }
24701 if (lister != null) lister.RFDI(miStart, "ROR", dstIndex, dstScale, dstDisp, imm);
24702 }
24703
24704 /**
24705 * Generate a absolute--immediate ROR. That is,
24706 * <PRE>
24707 * rotate right of [dstDisp] by imm
24708 * </PRE>
24709 *
24710 * @param dstDisp the destination displacement
24711 * @param imm immediate
24712 */
24713 public final void emitROR_Abs_Imm_Word(Address dstDisp, int imm) {
24714 int miStart = mi;
24715 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
24716 setMachineCodes(mi++, (byte) 0x66);
24717 generateREXprefix(false, null, null, null);
24718 if (imm == 1) {
24719 setMachineCodes(mi++, (byte) 0xD1);
24720 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x1));
24721 } else {
24722 setMachineCodes(mi++, (byte) 0xC1);
24723 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x1));
24724 emitImm8((byte)imm);
24725 }
24726 if (lister != null) lister.RAI(miStart, "ROR", dstDisp, imm);
24727 }
24728
24729 /**
24730 * Generate a register-index--immediate ROR. That is,
24731 * <PRE>
24732 * rotate right of [dstBase + dstIndex<<dstScale + dstDisp] by imm
24733 * </PRE>
24734 *
24735 * @param dstBase the destination base register
24736 * @param dstIndex the destination index register
24737 * @param dstScale the destination shift amount
24738 * @param dstDisp the destination displacement
24739 * @param imm immediate
24740 */
24741 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
24742 public final void emitROR_RegIdx_Imm_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
24743 int miStart = mi;
24744 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
24745 setMachineCodes(mi++, (byte) 0x66);
24746 generateREXprefix(false, null, dstIndex, dstBase);
24747 if (imm == 1) {
24748 setMachineCodes(mi++, (byte) 0xD1);
24749 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
24750 } else {
24751 setMachineCodes(mi++, (byte) 0xC1);
24752 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
24753 emitImm8((byte)imm);
24754 }
24755 if (lister != null) lister.RXDI(miStart, "ROR", dstBase, dstIndex, dstScale, dstDisp, imm);
24756 }
24757
24758 /**
24759 * Generate a register--register ROR. That is,
24760 * <PRE>
24761 * rotate right of dstReg by srcReg
24762 * </PRE>
24763 *
24764 * @param dstReg the destination register
24765 * @param srcReg must always be ECX
24766 */
24767 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
24768 public final void emitROR_Reg_Reg_Word(GPR dstReg, GPR srcReg) {
24769 int miStart = mi;
24770 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
24771 setMachineCodes(mi++, (byte) 0x66);
24772 generateREXprefix(false, null, null, dstReg);
24773 setMachineCodes(mi++, (byte) 0xD3);
24774 emitRegRegOperands(dstReg, GPR.getForOpcode(0x1));
24775 if (lister != null) lister.RR(miStart, "ROR", dstReg, srcReg);
24776 }
24777
24778 /**
24779 * Generate a register-indirect--register ROR. That is,
24780 * <PRE>
24781 * rotate right of [dstBase] by srcReg
24782 * </PRE>
24783 *
24784 * @param dstBase the destination register
24785 * @param srcReg must always be ECX
24786 */
24787 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
24788 public final void emitROR_RegInd_Reg_Word(GPR dstBase, GPR srcReg) {
24789 int miStart = mi;
24790 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
24791 setMachineCodes(mi++, (byte) 0x66);
24792 generateREXprefix(false, null, null, dstBase);
24793 setMachineCodes(mi++, (byte) 0xD3);
24794 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x1));
24795 if (lister != null) lister.RNR(miStart, "ROR", dstBase, srcReg);
24796 }
24797
24798 /**
24799 * Generate a register-displacement--register ROR. That is,
24800 * <PRE>
24801 * rotate right of [dstBase + dstDisp] by srcReg
24802 * </PRE>
24803 *
24804 * @param dstBase the destination base register
24805 * @param dstDisp the destination displacement
24806 * @param srcReg must always be ECX
24807 */
24808 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
24809 public final void emitROR_RegDisp_Reg_Word(GPR dstBase, Offset dstDisp, GPR srcReg) {
24810 int miStart = mi;
24811 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
24812 setMachineCodes(mi++, (byte) 0x66);
24813 generateREXprefix(false, null, null, dstBase);
24814 setMachineCodes(mi++, (byte) 0xD3);
24815 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x1));
24816 if (lister != null) lister.RDR(miStart, "ROR", dstBase, dstDisp, srcReg);
24817 }
24818
24819 /**
24820 * Generate a register-offset--register ROR. That is,
24821 * <PRE>
24822 * rotate right of [dstIndex<<dstScale + dstDisp] by srcReg
24823 * </PRE>
24824 *
24825 * @param dstIndex the destination index register
24826 * @param dstScale the destination shift amount
24827 * @param dstDisp the destination displacement
24828 * @param srcReg must always be ECX
24829 */
24830 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
24831 public final void emitROR_RegOff_Reg_Word(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
24832 int miStart = mi;
24833 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
24834 setMachineCodes(mi++, (byte) 0x66);
24835 generateREXprefix(false, null, dstIndex, null);
24836 setMachineCodes(mi++, (byte) 0xD3);
24837 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
24838 if (lister != null) lister.RFDR(miStart, "ROR", dstIndex, dstScale, dstDisp, srcReg);
24839 }
24840
24841 /**
24842 * Generate an absolute--register ROR. That is,
24843 * <PRE>
24844 * rotate right of [dstDisp] by srcReg
24845 * </PRE>
24846 *
24847 * @param dstDisp the destination displacement
24848 * @param srcReg must always be ECX
24849 */
24850 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
24851 public final void emitROR_Abs_Reg_Word(Address dstDisp, GPR srcReg) {
24852 int miStart = mi;
24853 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
24854 setMachineCodes(mi++, (byte) 0x66);
24855 generateREXprefix(false, null, null, null);
24856 setMachineCodes(mi++, (byte) 0xD3);
24857 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x1));
24858 if (lister != null) lister.RAR(miStart, "ROR", dstDisp, srcReg);
24859 }
24860
24861 /**
24862 * Generate a register-displacement--register ROR. That is,
24863 * <PRE>
24864 * rotate right of [dstBase + dstIndex<<dstScale + dstDisp] by srcReg
24865 * </PRE>
24866 *
24867 * @param dstBase the destination base register
24868 * @param dstIndex the destination index register
24869 * @param dstScale the destination shift amount
24870 * @param dstDisp the destination displacement
24871 * @param srcReg must always be ECX
24872 */
24873 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
24874 public final void emitROR_RegIdx_Reg_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
24875 int miStart = mi;
24876 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
24877 setMachineCodes(mi++, (byte) 0x66);
24878 generateREXprefix(false, null, dstIndex, dstBase);
24879 setMachineCodes(mi++, (byte) 0xD3);
24880 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
24881 if (lister != null) lister.RXDR(miStart, "ROR", dstBase, dstIndex, dstScale, dstDisp, srcReg);
24882 }
24883
24884 /**
24885 * Generate a register--immediate ROR. That is,
24886 * <PRE>
24887 * rotate right of dstReg by imm
24888 * </PRE>
24889 *
24890 * @param dstReg the destination register
24891 * @param imm immediate
24892 */
24893 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
24894 public final void emitROR_Reg_Imm(GPR dstReg, int imm) {
24895 int miStart = mi;
24896 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
24897 // no size prefix
24898 generateREXprefix(false, null, null, dstReg);
24899 if (imm == 1) {
24900 setMachineCodes(mi++, (byte) 0xD1);
24901 emitRegRegOperands(dstReg, GPR.getForOpcode(0x1));
24902 } else {
24903 setMachineCodes(mi++, (byte) 0xC1);
24904 emitRegRegOperands(dstReg, GPR.getForOpcode(0x1));
24905 emitImm8((byte)imm);
24906 }
24907 if (lister != null) lister.RI(miStart, "ROR", dstReg, imm);
24908 }
24909
24910 /**
24911 * Generate a register-indirect--immediate ROR. That is,
24912 * <PRE>
24913 * rotate right of [dstBase] by imm
24914 * </PRE>
24915 *
24916 * @param dstBase the destination base register
24917 * @param imm immediate
24918 */
24919 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
24920 public final void emitROR_RegInd_Imm(GPR dstBase, int imm) {
24921 int miStart = mi;
24922 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
24923 // no size prefix
24924 generateREXprefix(false, null, null, dstBase);
24925 if (imm == 1) {
24926 setMachineCodes(mi++, (byte) 0xD1);
24927 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x1));
24928 } else {
24929 setMachineCodes(mi++, (byte) 0xC1);
24930 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x1));
24931 emitImm8((byte)imm);
24932 }
24933 if (lister != null) lister.RNI(miStart, "ROR", dstBase, imm);
24934 }
24935
24936 /**
24937 * Generate a register-displacement--immediate ROR. That is,
24938 * <PRE>
24939 * rotate right of [dstBase + dstDisp] by imm
24940 * </PRE>
24941 *
24942 * @param dstBase the destination base register
24943 * @param dstDisp the destination displacement
24944 * @param imm immediate
24945 */
24946 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
24947 public final void emitROR_RegDisp_Imm(GPR dstBase, Offset dstDisp, int imm) {
24948 int miStart = mi;
24949 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
24950 // no size prefix
24951 generateREXprefix(false, null, null, dstBase);
24952 if (imm == 1) {
24953 setMachineCodes(mi++, (byte) 0xD1);
24954 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x1));
24955 } else {
24956 setMachineCodes(mi++, (byte) 0xC1);
24957 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x1));
24958 emitImm8((byte)imm);
24959 }
24960 if (lister != null) lister.RDI(miStart, "ROR", dstBase, dstDisp, imm);
24961 }
24962
24963 /**
24964 * Generate a register-offset--immediate ROR. That is,
24965 * <PRE>
24966 * rotate right of [dstIndex<<dstScale + dstDisp] by imm
24967 * </PRE>
24968 *
24969 * @param dstIndex the destination index register
24970 * @param dstScale the destination shift amount
24971 * @param dstDisp the destination displacement
24972 * @param imm immediate
24973 */
24974 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
24975 public final void emitROR_RegOff_Imm(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
24976 int miStart = mi;
24977 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
24978 // no size prefix
24979 generateREXprefix(false, null, dstIndex, null);
24980 if (imm == 1) {
24981 setMachineCodes(mi++, (byte) 0xD1);
24982 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
24983 } else {
24984 setMachineCodes(mi++, (byte) 0xC1);
24985 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
24986 emitImm8((byte)imm);
24987 }
24988 if (lister != null) lister.RFDI(miStart, "ROR", dstIndex, dstScale, dstDisp, imm);
24989 }
24990
24991 /**
24992 * Generate a absolute--immediate ROR. That is,
24993 * <PRE>
24994 * rotate right of [dstDisp] by imm
24995 * </PRE>
24996 *
24997 * @param dstDisp the destination displacement
24998 * @param imm immediate
24999 */
25000 public final void emitROR_Abs_Imm(Address dstDisp, int imm) {
25001 int miStart = mi;
25002 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
25003 // no size prefix
25004 generateREXprefix(false, null, null, null);
25005 if (imm == 1) {
25006 setMachineCodes(mi++, (byte) 0xD1);
25007 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x1));
25008 } else {
25009 setMachineCodes(mi++, (byte) 0xC1);
25010 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x1));
25011 emitImm8((byte)imm);
25012 }
25013 if (lister != null) lister.RAI(miStart, "ROR", dstDisp, imm);
25014 }
25015
25016 /**
25017 * Generate a register-index--immediate ROR. That is,
25018 * <PRE>
25019 * rotate right of [dstBase + dstIndex<<dstScale + dstDisp] by imm
25020 * </PRE>
25021 *
25022 * @param dstBase the destination base register
25023 * @param dstIndex the destination index register
25024 * @param dstScale the destination shift amount
25025 * @param dstDisp the destination displacement
25026 * @param imm immediate
25027 */
25028 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
25029 public final void emitROR_RegIdx_Imm(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
25030 int miStart = mi;
25031 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
25032 // no size prefix
25033 generateREXprefix(false, null, dstIndex, dstBase);
25034 if (imm == 1) {
25035 setMachineCodes(mi++, (byte) 0xD1);
25036 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
25037 } else {
25038 setMachineCodes(mi++, (byte) 0xC1);
25039 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
25040 emitImm8((byte)imm);
25041 }
25042 if (lister != null) lister.RXDI(miStart, "ROR", dstBase, dstIndex, dstScale, dstDisp, imm);
25043 }
25044
25045 /**
25046 * Generate a register--register ROR. That is,
25047 * <PRE>
25048 * rotate right of dstReg by srcReg
25049 * </PRE>
25050 *
25051 * @param dstReg the destination register
25052 * @param srcReg must always be ECX
25053 */
25054 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
25055 public final void emitROR_Reg_Reg(GPR dstReg, GPR srcReg) {
25056 int miStart = mi;
25057 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
25058 // no size prefix
25059 generateREXprefix(false, null, null, dstReg);
25060 setMachineCodes(mi++, (byte) 0xD3);
25061 emitRegRegOperands(dstReg, GPR.getForOpcode(0x1));
25062 if (lister != null) lister.RR(miStart, "ROR", dstReg, srcReg);
25063 }
25064
25065 /**
25066 * Generate a register-indirect--register ROR. That is,
25067 * <PRE>
25068 * rotate right of [dstBase] by srcReg
25069 * </PRE>
25070 *
25071 * @param dstBase the destination register
25072 * @param srcReg must always be ECX
25073 */
25074 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
25075 public final void emitROR_RegInd_Reg(GPR dstBase, GPR srcReg) {
25076 int miStart = mi;
25077 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
25078 // no size prefix
25079 generateREXprefix(false, null, null, dstBase);
25080 setMachineCodes(mi++, (byte) 0xD3);
25081 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x1));
25082 if (lister != null) lister.RNR(miStart, "ROR", dstBase, srcReg);
25083 }
25084
25085 /**
25086 * Generate a register-displacement--register ROR. That is,
25087 * <PRE>
25088 * rotate right of [dstBase + dstDisp] by srcReg
25089 * </PRE>
25090 *
25091 * @param dstBase the destination base register
25092 * @param dstDisp the destination displacement
25093 * @param srcReg must always be ECX
25094 */
25095 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
25096 public final void emitROR_RegDisp_Reg(GPR dstBase, Offset dstDisp, GPR srcReg) {
25097 int miStart = mi;
25098 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
25099 // no size prefix
25100 generateREXprefix(false, null, null, dstBase);
25101 setMachineCodes(mi++, (byte) 0xD3);
25102 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x1));
25103 if (lister != null) lister.RDR(miStart, "ROR", dstBase, dstDisp, srcReg);
25104 }
25105
25106 /**
25107 * Generate a register-offset--register ROR. That is,
25108 * <PRE>
25109 * rotate right of [dstIndex<<dstScale + dstDisp] by srcReg
25110 * </PRE>
25111 *
25112 * @param dstIndex the destination index register
25113 * @param dstScale the destination shift amount
25114 * @param dstDisp the destination displacement
25115 * @param srcReg must always be ECX
25116 */
25117 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
25118 public final void emitROR_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
25119 int miStart = mi;
25120 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
25121 // no size prefix
25122 generateREXprefix(false, null, dstIndex, null);
25123 setMachineCodes(mi++, (byte) 0xD3);
25124 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
25125 if (lister != null) lister.RFDR(miStart, "ROR", dstIndex, dstScale, dstDisp, srcReg);
25126 }
25127
25128 /**
25129 * Generate an absolute--register ROR. That is,
25130 * <PRE>
25131 * rotate right of [dstDisp] by srcReg
25132 * </PRE>
25133 *
25134 * @param dstDisp the destination displacement
25135 * @param srcReg must always be ECX
25136 */
25137 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
25138 public final void emitROR_Abs_Reg(Address dstDisp, GPR srcReg) {
25139 int miStart = mi;
25140 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
25141 // no size prefix
25142 generateREXprefix(false, null, null, null);
25143 setMachineCodes(mi++, (byte) 0xD3);
25144 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x1));
25145 if (lister != null) lister.RAR(miStart, "ROR", dstDisp, srcReg);
25146 }
25147
25148 /**
25149 * Generate a register-displacement--register ROR. That is,
25150 * <PRE>
25151 * rotate right of [dstBase + dstIndex<<dstScale + dstDisp] by srcReg
25152 * </PRE>
25153 *
25154 * @param dstBase the destination base register
25155 * @param dstIndex the destination index register
25156 * @param dstScale the destination shift amount
25157 * @param dstDisp the destination displacement
25158 * @param srcReg must always be ECX
25159 */
25160 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
25161 public final void emitROR_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
25162 int miStart = mi;
25163 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
25164 // no size prefix
25165 generateREXprefix(false, null, dstIndex, dstBase);
25166 setMachineCodes(mi++, (byte) 0xD3);
25167 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
25168 if (lister != null) lister.RXDR(miStart, "ROR", dstBase, dstIndex, dstScale, dstDisp, srcReg);
25169 }
25170
25171 /**
25172 * Generate a register--immediate ROR. That is,
25173 * <PRE>
25174 * rotate right of dstReg by imm
25175 * </PRE>
25176 *
25177 * @param dstReg the destination register
25178 * @param imm immediate
25179 */
25180 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
25181 public final void emitROR_Reg_Imm_Quad(GPR dstReg, int imm) {
25182 int miStart = mi;
25183 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
25184 // no size prefix
25185 generateREXprefix(true, null, null, dstReg);
25186 if (imm == 1) {
25187 setMachineCodes(mi++, (byte) 0xD1);
25188 emitRegRegOperands(dstReg, GPR.getForOpcode(0x1));
25189 } else {
25190 setMachineCodes(mi++, (byte) 0xC1);
25191 emitRegRegOperands(dstReg, GPR.getForOpcode(0x1));
25192 emitImm8((byte)imm);
25193 }
25194 if (lister != null) lister.RI(miStart, "ROR", dstReg, imm);
25195 }
25196
25197 /**
25198 * Generate a register-indirect--immediate ROR. That is,
25199 * <PRE>
25200 * rotate right of [dstBase] by imm
25201 * </PRE>
25202 *
25203 * @param dstBase the destination base register
25204 * @param imm immediate
25205 */
25206 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
25207 public final void emitROR_RegInd_Imm_Quad(GPR dstBase, int imm) {
25208 int miStart = mi;
25209 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
25210 // no size prefix
25211 generateREXprefix(true, null, null, dstBase);
25212 if (imm == 1) {
25213 setMachineCodes(mi++, (byte) 0xD1);
25214 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x1));
25215 } else {
25216 setMachineCodes(mi++, (byte) 0xC1);
25217 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x1));
25218 emitImm8((byte)imm);
25219 }
25220 if (lister != null) lister.RNI(miStart, "ROR", dstBase, imm);
25221 }
25222
25223 /**
25224 * Generate a register-displacement--immediate ROR. That is,
25225 * <PRE>
25226 * rotate right of [dstBase + dstDisp] by imm
25227 * </PRE>
25228 *
25229 * @param dstBase the destination base register
25230 * @param dstDisp the destination displacement
25231 * @param imm immediate
25232 */
25233 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
25234 public final void emitROR_RegDisp_Imm_Quad(GPR dstBase, Offset dstDisp, int imm) {
25235 int miStart = mi;
25236 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
25237 // no size prefix
25238 generateREXprefix(true, null, null, dstBase);
25239 if (imm == 1) {
25240 setMachineCodes(mi++, (byte) 0xD1);
25241 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x1));
25242 } else {
25243 setMachineCodes(mi++, (byte) 0xC1);
25244 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x1));
25245 emitImm8((byte)imm);
25246 }
25247 if (lister != null) lister.RDI(miStart, "ROR", dstBase, dstDisp, imm);
25248 }
25249
25250 /**
25251 * Generate a register-offset--immediate ROR. That is,
25252 * <PRE>
25253 * rotate right of [dstIndex<<dstScale + dstDisp] by imm
25254 * </PRE>
25255 *
25256 * @param dstIndex the destination index register
25257 * @param dstScale the destination shift amount
25258 * @param dstDisp the destination displacement
25259 * @param imm immediate
25260 */
25261 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
25262 public final void emitROR_RegOff_Imm_Quad(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
25263 int miStart = mi;
25264 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
25265 // no size prefix
25266 generateREXprefix(true, null, dstIndex, null);
25267 if (imm == 1) {
25268 setMachineCodes(mi++, (byte) 0xD1);
25269 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
25270 } else {
25271 setMachineCodes(mi++, (byte) 0xC1);
25272 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
25273 emitImm8((byte)imm);
25274 }
25275 if (lister != null) lister.RFDI(miStart, "ROR", dstIndex, dstScale, dstDisp, imm);
25276 }
25277
25278 /**
25279 * Generate a absolute--immediate ROR. That is,
25280 * <PRE>
25281 * rotate right of [dstDisp] by imm
25282 * </PRE>
25283 *
25284 * @param dstDisp the destination displacement
25285 * @param imm immediate
25286 */
25287 public final void emitROR_Abs_Imm_Quad(Address dstDisp, int imm) {
25288 int miStart = mi;
25289 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
25290 // no size prefix
25291 generateREXprefix(true, null, null, null);
25292 if (imm == 1) {
25293 setMachineCodes(mi++, (byte) 0xD1);
25294 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x1));
25295 } else {
25296 setMachineCodes(mi++, (byte) 0xC1);
25297 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x1));
25298 emitImm8((byte)imm);
25299 }
25300 if (lister != null) lister.RAI(miStart, "ROR", dstDisp, imm);
25301 }
25302
25303 /**
25304 * Generate a register-index--immediate ROR. That is,
25305 * <PRE>
25306 * rotate right of [dstBase + dstIndex<<dstScale + dstDisp] by imm
25307 * </PRE>
25308 *
25309 * @param dstBase the destination base register
25310 * @param dstIndex the destination index register
25311 * @param dstScale the destination shift amount
25312 * @param dstDisp the destination displacement
25313 * @param imm immediate
25314 */
25315 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
25316 public final void emitROR_RegIdx_Imm_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
25317 int miStart = mi;
25318 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
25319 // no size prefix
25320 generateREXprefix(true, null, dstIndex, dstBase);
25321 if (imm == 1) {
25322 setMachineCodes(mi++, (byte) 0xD1);
25323 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
25324 } else {
25325 setMachineCodes(mi++, (byte) 0xC1);
25326 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
25327 emitImm8((byte)imm);
25328 }
25329 if (lister != null) lister.RXDI(miStart, "ROR", dstBase, dstIndex, dstScale, dstDisp, imm);
25330 }
25331
25332 /**
25333 * Generate a register--register ROR. That is,
25334 * <PRE>
25335 * rotate right of dstReg by srcReg
25336 * </PRE>
25337 *
25338 * @param dstReg the destination register
25339 * @param srcReg must always be ECX
25340 */
25341 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
25342 public final void emitROR_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
25343 int miStart = mi;
25344 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
25345 // no size prefix
25346 generateREXprefix(true, null, null, dstReg);
25347 setMachineCodes(mi++, (byte) 0xD3);
25348 emitRegRegOperands(dstReg, GPR.getForOpcode(0x1));
25349 if (lister != null) lister.RR(miStart, "ROR", dstReg, srcReg);
25350 }
25351
25352 /**
25353 * Generate a register-indirect--register ROR. That is,
25354 * <PRE>
25355 * rotate right of [dstBase] by srcReg
25356 * </PRE>
25357 *
25358 * @param dstBase the destination register
25359 * @param srcReg must always be ECX
25360 */
25361 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
25362 public final void emitROR_RegInd_Reg_Quad(GPR dstBase, GPR srcReg) {
25363 int miStart = mi;
25364 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
25365 // no size prefix
25366 generateREXprefix(true, null, null, dstBase);
25367 setMachineCodes(mi++, (byte) 0xD3);
25368 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x1));
25369 if (lister != null) lister.RNR(miStart, "ROR", dstBase, srcReg);
25370 }
25371
25372 /**
25373 * Generate a register-displacement--register ROR. That is,
25374 * <PRE>
25375 * rotate right of [dstBase + dstDisp] by srcReg
25376 * </PRE>
25377 *
25378 * @param dstBase the destination base register
25379 * @param dstDisp the destination displacement
25380 * @param srcReg must always be ECX
25381 */
25382 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
25383 public final void emitROR_RegDisp_Reg_Quad(GPR dstBase, Offset dstDisp, GPR srcReg) {
25384 int miStart = mi;
25385 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
25386 // no size prefix
25387 generateREXprefix(true, null, null, dstBase);
25388 setMachineCodes(mi++, (byte) 0xD3);
25389 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x1));
25390 if (lister != null) lister.RDR(miStart, "ROR", dstBase, dstDisp, srcReg);
25391 }
25392
25393 /**
25394 * Generate a register-offset--register ROR. That is,
25395 * <PRE>
25396 * rotate right of [dstIndex<<dstScale + dstDisp] by srcReg
25397 * </PRE>
25398 *
25399 * @param dstIndex the destination index register
25400 * @param dstScale the destination shift amount
25401 * @param dstDisp the destination displacement
25402 * @param srcReg must always be ECX
25403 */
25404 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
25405 public final void emitROR_RegOff_Reg_Quad(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
25406 int miStart = mi;
25407 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
25408 // no size prefix
25409 generateREXprefix(true, null, dstIndex, null);
25410 setMachineCodes(mi++, (byte) 0xD3);
25411 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
25412 if (lister != null) lister.RFDR(miStart, "ROR", dstIndex, dstScale, dstDisp, srcReg);
25413 }
25414
25415 /**
25416 * Generate an absolute--register ROR. That is,
25417 * <PRE>
25418 * rotate right of [dstDisp] by srcReg
25419 * </PRE>
25420 *
25421 * @param dstDisp the destination displacement
25422 * @param srcReg must always be ECX
25423 */
25424 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
25425 public final void emitROR_Abs_Reg_Quad(Address dstDisp, GPR srcReg) {
25426 int miStart = mi;
25427 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
25428 // no size prefix
25429 generateREXprefix(true, null, null, null);
25430 setMachineCodes(mi++, (byte) 0xD3);
25431 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x1));
25432 if (lister != null) lister.RAR(miStart, "ROR", dstDisp, srcReg);
25433 }
25434
25435 /**
25436 * Generate a register-displacement--register ROR. That is,
25437 * <PRE>
25438 * rotate right of [dstBase + dstIndex<<dstScale + dstDisp] by srcReg
25439 * </PRE>
25440 *
25441 * @param dstBase the destination base register
25442 * @param dstIndex the destination index register
25443 * @param dstScale the destination shift amount
25444 * @param dstDisp the destination displacement
25445 * @param srcReg must always be ECX
25446 */
25447 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
25448 public final void emitROR_RegIdx_Reg_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
25449 int miStart = mi;
25450 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
25451 // no size prefix
25452 generateREXprefix(true, null, dstIndex, dstBase);
25453 setMachineCodes(mi++, (byte) 0xD3);
25454 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x1));
25455 if (lister != null) lister.RXDR(miStart, "ROR", dstBase, dstIndex, dstScale, dstDisp, srcReg);
25456 }
25457
25458 /**
25459 * Generate a register--immediate RCL. That is,
25460 * <PRE>
25461 * rotate left with carry of dstReg by imm
25462 * </PRE>
25463 *
25464 * @param dstReg the destination register
25465 * @param imm immediate
25466 */
25467 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
25468 public final void emitRCL_Reg_Imm_Byte(GPR dstReg, int imm) {
25469 int miStart = mi;
25470 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
25471 // no size prefix
25472 generateREXprefix(false, null, null, dstReg);
25473 if (imm == 1) {
25474 setMachineCodes(mi++, (byte) 0xD0);
25475 emitRegRegOperands(dstReg, GPR.getForOpcode(0x2));
25476 } else {
25477 setMachineCodes(mi++, (byte) 0xC0);
25478 emitRegRegOperands(dstReg, GPR.getForOpcode(0x2));
25479 emitImm8((byte)imm);
25480 }
25481 if (lister != null) lister.RI(miStart, "RCL", dstReg, imm);
25482 }
25483
25484 /**
25485 * Generate a register-indirect--immediate RCL. That is,
25486 * <PRE>
25487 * rotate left with carry of [dstBase] by imm
25488 * </PRE>
25489 *
25490 * @param dstBase the destination base register
25491 * @param imm immediate
25492 */
25493 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
25494 public final void emitRCL_RegInd_Imm_Byte(GPR dstBase, int imm) {
25495 int miStart = mi;
25496 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
25497 // no size prefix
25498 generateREXprefix(false, null, null, dstBase);
25499 if (imm == 1) {
25500 setMachineCodes(mi++, (byte) 0xD0);
25501 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x2));
25502 } else {
25503 setMachineCodes(mi++, (byte) 0xC0);
25504 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x2));
25505 emitImm8((byte)imm);
25506 }
25507 if (lister != null) lister.RNI(miStart, "RCL", dstBase, imm);
25508 }
25509
25510 /**
25511 * Generate a register-displacement--immediate RCL. That is,
25512 * <PRE>
25513 * rotate left with carry of [dstBase + dstDisp] by imm
25514 * </PRE>
25515 *
25516 * @param dstBase the destination base register
25517 * @param dstDisp the destination displacement
25518 * @param imm immediate
25519 */
25520 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
25521 public final void emitRCL_RegDisp_Imm_Byte(GPR dstBase, Offset dstDisp, int imm) {
25522 int miStart = mi;
25523 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
25524 // no size prefix
25525 generateREXprefix(false, null, null, dstBase);
25526 if (imm == 1) {
25527 setMachineCodes(mi++, (byte) 0xD0);
25528 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x2));
25529 } else {
25530 setMachineCodes(mi++, (byte) 0xC0);
25531 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x2));
25532 emitImm8((byte)imm);
25533 }
25534 if (lister != null) lister.RDI(miStart, "RCL", dstBase, dstDisp, imm);
25535 }
25536
25537 /**
25538 * Generate a register-offset--immediate RCL. That is,
25539 * <PRE>
25540 * rotate left with carry of [dstIndex<<dstScale + dstDisp] by imm
25541 * </PRE>
25542 *
25543 * @param dstIndex the destination index register
25544 * @param dstScale the destination shift amount
25545 * @param dstDisp the destination displacement
25546 * @param imm immediate
25547 */
25548 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
25549 public final void emitRCL_RegOff_Imm_Byte(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
25550 int miStart = mi;
25551 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
25552 // no size prefix
25553 generateREXprefix(false, null, dstIndex, null);
25554 if (imm == 1) {
25555 setMachineCodes(mi++, (byte) 0xD0);
25556 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
25557 } else {
25558 setMachineCodes(mi++, (byte) 0xC0);
25559 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
25560 emitImm8((byte)imm);
25561 }
25562 if (lister != null) lister.RFDI(miStart, "RCL", dstIndex, dstScale, dstDisp, imm);
25563 }
25564
25565 /**
25566 * Generate a absolute--immediate RCL. That is,
25567 * <PRE>
25568 * rotate left with carry of [dstDisp] by imm
25569 * </PRE>
25570 *
25571 * @param dstDisp the destination displacement
25572 * @param imm immediate
25573 */
25574 public final void emitRCL_Abs_Imm_Byte(Address dstDisp, int imm) {
25575 int miStart = mi;
25576 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
25577 // no size prefix
25578 generateREXprefix(false, null, null, null);
25579 if (imm == 1) {
25580 setMachineCodes(mi++, (byte) 0xD0);
25581 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x2));
25582 } else {
25583 setMachineCodes(mi++, (byte) 0xC0);
25584 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x2));
25585 emitImm8((byte)imm);
25586 }
25587 if (lister != null) lister.RAI(miStart, "RCL", dstDisp, imm);
25588 }
25589
25590 /**
25591 * Generate a register-index--immediate RCL. That is,
25592 * <PRE>
25593 * rotate left with carry of [dstBase + dstIndex<<dstScale + dstDisp] by imm
25594 * </PRE>
25595 *
25596 * @param dstBase the destination base register
25597 * @param dstIndex the destination index register
25598 * @param dstScale the destination shift amount
25599 * @param dstDisp the destination displacement
25600 * @param imm immediate
25601 */
25602 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
25603 public final void emitRCL_RegIdx_Imm_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
25604 int miStart = mi;
25605 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
25606 // no size prefix
25607 generateREXprefix(false, null, dstIndex, dstBase);
25608 if (imm == 1) {
25609 setMachineCodes(mi++, (byte) 0xD0);
25610 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
25611 } else {
25612 setMachineCodes(mi++, (byte) 0xC0);
25613 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
25614 emitImm8((byte)imm);
25615 }
25616 if (lister != null) lister.RXDI(miStart, "RCL", dstBase, dstIndex, dstScale, dstDisp, imm);
25617 }
25618
25619 /**
25620 * Generate a register--register RCL. That is,
25621 * <PRE>
25622 * rotate left with carry of dstReg by srcReg
25623 * </PRE>
25624 *
25625 * @param dstReg the destination register
25626 * @param srcReg must always be ECX
25627 */
25628 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
25629 public final void emitRCL_Reg_Reg_Byte(GPR dstReg, GPR srcReg) {
25630 int miStart = mi;
25631 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
25632 // no size prefix
25633 generateREXprefix(false, null, null, dstReg);
25634 setMachineCodes(mi++, (byte) 0xD2);
25635 emitRegRegOperands(dstReg, GPR.getForOpcode(0x2));
25636 if (lister != null) lister.RR(miStart, "RCL", dstReg, srcReg);
25637 }
25638
25639 /**
25640 * Generate a register-indirect--register RCL. That is,
25641 * <PRE>
25642 * rotate left with carry of [dstBase] by srcReg
25643 * </PRE>
25644 *
25645 * @param dstBase the destination register
25646 * @param srcReg must always be ECX
25647 */
25648 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
25649 public final void emitRCL_RegInd_Reg_Byte(GPR dstBase, GPR srcReg) {
25650 int miStart = mi;
25651 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
25652 // no size prefix
25653 generateREXprefix(false, null, null, dstBase);
25654 setMachineCodes(mi++, (byte) 0xD2);
25655 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x2));
25656 if (lister != null) lister.RNR(miStart, "RCL", dstBase, srcReg);
25657 }
25658
25659 /**
25660 * Generate a register-displacement--register RCL. That is,
25661 * <PRE>
25662 * rotate left with carry of [dstBase + dstDisp] by srcReg
25663 * </PRE>
25664 *
25665 * @param dstBase the destination base register
25666 * @param dstDisp the destination displacement
25667 * @param srcReg must always be ECX
25668 */
25669 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
25670 public final void emitRCL_RegDisp_Reg_Byte(GPR dstBase, Offset dstDisp, GPR srcReg) {
25671 int miStart = mi;
25672 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
25673 // no size prefix
25674 generateREXprefix(false, null, null, dstBase);
25675 setMachineCodes(mi++, (byte) 0xD2);
25676 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x2));
25677 if (lister != null) lister.RDR(miStart, "RCL", dstBase, dstDisp, srcReg);
25678 }
25679
25680 /**
25681 * Generate a register-offset--register RCL. That is,
25682 * <PRE>
25683 * rotate left with carry of [dstIndex<<dstScale + dstDisp] by srcReg
25684 * </PRE>
25685 *
25686 * @param dstIndex the destination index register
25687 * @param dstScale the destination shift amount
25688 * @param dstDisp the destination displacement
25689 * @param srcReg must always be ECX
25690 */
25691 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
25692 public final void emitRCL_RegOff_Reg_Byte(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
25693 int miStart = mi;
25694 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
25695 // no size prefix
25696 generateREXprefix(false, null, dstIndex, null);
25697 setMachineCodes(mi++, (byte) 0xD2);
25698 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
25699 if (lister != null) lister.RFDR(miStart, "RCL", dstIndex, dstScale, dstDisp, srcReg);
25700 }
25701
25702 /**
25703 * Generate an absolute--register RCL. That is,
25704 * <PRE>
25705 * rotate left with carry of [dstDisp] by srcReg
25706 * </PRE>
25707 *
25708 * @param dstDisp the destination displacement
25709 * @param srcReg must always be ECX
25710 */
25711 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
25712 public final void emitRCL_Abs_Reg_Byte(Address dstDisp, GPR srcReg) {
25713 int miStart = mi;
25714 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
25715 // no size prefix
25716 generateREXprefix(false, null, null, null);
25717 setMachineCodes(mi++, (byte) 0xD2);
25718 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x2));
25719 if (lister != null) lister.RAR(miStart, "RCL", dstDisp, srcReg);
25720 }
25721
25722 /**
25723 * Generate a register-displacement--register RCL. That is,
25724 * <PRE>
25725 * rotate left with carry of [dstBase + dstIndex<<dstScale + dstDisp] by srcReg
25726 * </PRE>
25727 *
25728 * @param dstBase the destination base register
25729 * @param dstIndex the destination index register
25730 * @param dstScale the destination shift amount
25731 * @param dstDisp the destination displacement
25732 * @param srcReg must always be ECX
25733 */
25734 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
25735 public final void emitRCL_RegIdx_Reg_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
25736 int miStart = mi;
25737 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
25738 // no size prefix
25739 generateREXprefix(false, null, dstIndex, dstBase);
25740 setMachineCodes(mi++, (byte) 0xD2);
25741 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
25742 if (lister != null) lister.RXDR(miStart, "RCL", dstBase, dstIndex, dstScale, dstDisp, srcReg);
25743 }
25744
25745 /**
25746 * Generate a register--immediate RCL. That is,
25747 * <PRE>
25748 * rotate left with carry of dstReg by imm
25749 * </PRE>
25750 *
25751 * @param dstReg the destination register
25752 * @param imm immediate
25753 */
25754 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
25755 public final void emitRCL_Reg_Imm_Word(GPR dstReg, int imm) {
25756 int miStart = mi;
25757 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
25758 setMachineCodes(mi++, (byte) 0x66);
25759 generateREXprefix(false, null, null, dstReg);
25760 if (imm == 1) {
25761 setMachineCodes(mi++, (byte) 0xD1);
25762 emitRegRegOperands(dstReg, GPR.getForOpcode(0x2));
25763 } else {
25764 setMachineCodes(mi++, (byte) 0xC1);
25765 emitRegRegOperands(dstReg, GPR.getForOpcode(0x2));
25766 emitImm8((byte)imm);
25767 }
25768 if (lister != null) lister.RI(miStart, "RCL", dstReg, imm);
25769 }
25770
25771 /**
25772 * Generate a register-indirect--immediate RCL. That is,
25773 * <PRE>
25774 * rotate left with carry of [dstBase] by imm
25775 * </PRE>
25776 *
25777 * @param dstBase the destination base register
25778 * @param imm immediate
25779 */
25780 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
25781 public final void emitRCL_RegInd_Imm_Word(GPR dstBase, int imm) {
25782 int miStart = mi;
25783 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
25784 setMachineCodes(mi++, (byte) 0x66);
25785 generateREXprefix(false, null, null, dstBase);
25786 if (imm == 1) {
25787 setMachineCodes(mi++, (byte) 0xD1);
25788 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x2));
25789 } else {
25790 setMachineCodes(mi++, (byte) 0xC1);
25791 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x2));
25792 emitImm8((byte)imm);
25793 }
25794 if (lister != null) lister.RNI(miStart, "RCL", dstBase, imm);
25795 }
25796
25797 /**
25798 * Generate a register-displacement--immediate RCL. That is,
25799 * <PRE>
25800 * rotate left with carry of [dstBase + dstDisp] by imm
25801 * </PRE>
25802 *
25803 * @param dstBase the destination base register
25804 * @param dstDisp the destination displacement
25805 * @param imm immediate
25806 */
25807 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
25808 public final void emitRCL_RegDisp_Imm_Word(GPR dstBase, Offset dstDisp, int imm) {
25809 int miStart = mi;
25810 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
25811 setMachineCodes(mi++, (byte) 0x66);
25812 generateREXprefix(false, null, null, dstBase);
25813 if (imm == 1) {
25814 setMachineCodes(mi++, (byte) 0xD1);
25815 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x2));
25816 } else {
25817 setMachineCodes(mi++, (byte) 0xC1);
25818 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x2));
25819 emitImm8((byte)imm);
25820 }
25821 if (lister != null) lister.RDI(miStart, "RCL", dstBase, dstDisp, imm);
25822 }
25823
25824 /**
25825 * Generate a register-offset--immediate RCL. That is,
25826 * <PRE>
25827 * rotate left with carry of [dstIndex<<dstScale + dstDisp] by imm
25828 * </PRE>
25829 *
25830 * @param dstIndex the destination index register
25831 * @param dstScale the destination shift amount
25832 * @param dstDisp the destination displacement
25833 * @param imm immediate
25834 */
25835 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
25836 public final void emitRCL_RegOff_Imm_Word(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
25837 int miStart = mi;
25838 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
25839 setMachineCodes(mi++, (byte) 0x66);
25840 generateREXprefix(false, null, dstIndex, null);
25841 if (imm == 1) {
25842 setMachineCodes(mi++, (byte) 0xD1);
25843 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
25844 } else {
25845 setMachineCodes(mi++, (byte) 0xC1);
25846 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
25847 emitImm8((byte)imm);
25848 }
25849 if (lister != null) lister.RFDI(miStart, "RCL", dstIndex, dstScale, dstDisp, imm);
25850 }
25851
25852 /**
25853 * Generate a absolute--immediate RCL. That is,
25854 * <PRE>
25855 * rotate left with carry of [dstDisp] by imm
25856 * </PRE>
25857 *
25858 * @param dstDisp the destination displacement
25859 * @param imm immediate
25860 */
25861 public final void emitRCL_Abs_Imm_Word(Address dstDisp, int imm) {
25862 int miStart = mi;
25863 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
25864 setMachineCodes(mi++, (byte) 0x66);
25865 generateREXprefix(false, null, null, null);
25866 if (imm == 1) {
25867 setMachineCodes(mi++, (byte) 0xD1);
25868 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x2));
25869 } else {
25870 setMachineCodes(mi++, (byte) 0xC1);
25871 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x2));
25872 emitImm8((byte)imm);
25873 }
25874 if (lister != null) lister.RAI(miStart, "RCL", dstDisp, imm);
25875 }
25876
25877 /**
25878 * Generate a register-index--immediate RCL. That is,
25879 * <PRE>
25880 * rotate left with carry of [dstBase + dstIndex<<dstScale + dstDisp] by imm
25881 * </PRE>
25882 *
25883 * @param dstBase the destination base register
25884 * @param dstIndex the destination index register
25885 * @param dstScale the destination shift amount
25886 * @param dstDisp the destination displacement
25887 * @param imm immediate
25888 */
25889 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
25890 public final void emitRCL_RegIdx_Imm_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
25891 int miStart = mi;
25892 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
25893 setMachineCodes(mi++, (byte) 0x66);
25894 generateREXprefix(false, null, dstIndex, dstBase);
25895 if (imm == 1) {
25896 setMachineCodes(mi++, (byte) 0xD1);
25897 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
25898 } else {
25899 setMachineCodes(mi++, (byte) 0xC1);
25900 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
25901 emitImm8((byte)imm);
25902 }
25903 if (lister != null) lister.RXDI(miStart, "RCL", dstBase, dstIndex, dstScale, dstDisp, imm);
25904 }
25905
25906 /**
25907 * Generate a register--register RCL. That is,
25908 * <PRE>
25909 * rotate left with carry of dstReg by srcReg
25910 * </PRE>
25911 *
25912 * @param dstReg the destination register
25913 * @param srcReg must always be ECX
25914 */
25915 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
25916 public final void emitRCL_Reg_Reg_Word(GPR dstReg, GPR srcReg) {
25917 int miStart = mi;
25918 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
25919 setMachineCodes(mi++, (byte) 0x66);
25920 generateREXprefix(false, null, null, dstReg);
25921 setMachineCodes(mi++, (byte) 0xD3);
25922 emitRegRegOperands(dstReg, GPR.getForOpcode(0x2));
25923 if (lister != null) lister.RR(miStart, "RCL", dstReg, srcReg);
25924 }
25925
25926 /**
25927 * Generate a register-indirect--register RCL. That is,
25928 * <PRE>
25929 * rotate left with carry of [dstBase] by srcReg
25930 * </PRE>
25931 *
25932 * @param dstBase the destination register
25933 * @param srcReg must always be ECX
25934 */
25935 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
25936 public final void emitRCL_RegInd_Reg_Word(GPR dstBase, GPR srcReg) {
25937 int miStart = mi;
25938 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
25939 setMachineCodes(mi++, (byte) 0x66);
25940 generateREXprefix(false, null, null, dstBase);
25941 setMachineCodes(mi++, (byte) 0xD3);
25942 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x2));
25943 if (lister != null) lister.RNR(miStart, "RCL", dstBase, srcReg);
25944 }
25945
25946 /**
25947 * Generate a register-displacement--register RCL. That is,
25948 * <PRE>
25949 * rotate left with carry of [dstBase + dstDisp] by srcReg
25950 * </PRE>
25951 *
25952 * @param dstBase the destination base register
25953 * @param dstDisp the destination displacement
25954 * @param srcReg must always be ECX
25955 */
25956 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
25957 public final void emitRCL_RegDisp_Reg_Word(GPR dstBase, Offset dstDisp, GPR srcReg) {
25958 int miStart = mi;
25959 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
25960 setMachineCodes(mi++, (byte) 0x66);
25961 generateREXprefix(false, null, null, dstBase);
25962 setMachineCodes(mi++, (byte) 0xD3);
25963 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x2));
25964 if (lister != null) lister.RDR(miStart, "RCL", dstBase, dstDisp, srcReg);
25965 }
25966
25967 /**
25968 * Generate a register-offset--register RCL. That is,
25969 * <PRE>
25970 * rotate left with carry of [dstIndex<<dstScale + dstDisp] by srcReg
25971 * </PRE>
25972 *
25973 * @param dstIndex the destination index register
25974 * @param dstScale the destination shift amount
25975 * @param dstDisp the destination displacement
25976 * @param srcReg must always be ECX
25977 */
25978 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
25979 public final void emitRCL_RegOff_Reg_Word(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
25980 int miStart = mi;
25981 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
25982 setMachineCodes(mi++, (byte) 0x66);
25983 generateREXprefix(false, null, dstIndex, null);
25984 setMachineCodes(mi++, (byte) 0xD3);
25985 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
25986 if (lister != null) lister.RFDR(miStart, "RCL", dstIndex, dstScale, dstDisp, srcReg);
25987 }
25988
25989 /**
25990 * Generate an absolute--register RCL. That is,
25991 * <PRE>
25992 * rotate left with carry of [dstDisp] by srcReg
25993 * </PRE>
25994 *
25995 * @param dstDisp the destination displacement
25996 * @param srcReg must always be ECX
25997 */
25998 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
25999 public final void emitRCL_Abs_Reg_Word(Address dstDisp, GPR srcReg) {
26000 int miStart = mi;
26001 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
26002 setMachineCodes(mi++, (byte) 0x66);
26003 generateREXprefix(false, null, null, null);
26004 setMachineCodes(mi++, (byte) 0xD3);
26005 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x2));
26006 if (lister != null) lister.RAR(miStart, "RCL", dstDisp, srcReg);
26007 }
26008
26009 /**
26010 * Generate a register-displacement--register RCL. That is,
26011 * <PRE>
26012 * rotate left with carry of [dstBase + dstIndex<<dstScale + dstDisp] by srcReg
26013 * </PRE>
26014 *
26015 * @param dstBase the destination base register
26016 * @param dstIndex the destination index register
26017 * @param dstScale the destination shift amount
26018 * @param dstDisp the destination displacement
26019 * @param srcReg must always be ECX
26020 */
26021 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
26022 public final void emitRCL_RegIdx_Reg_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
26023 int miStart = mi;
26024 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
26025 setMachineCodes(mi++, (byte) 0x66);
26026 generateREXprefix(false, null, dstIndex, dstBase);
26027 setMachineCodes(mi++, (byte) 0xD3);
26028 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
26029 if (lister != null) lister.RXDR(miStart, "RCL", dstBase, dstIndex, dstScale, dstDisp, srcReg);
26030 }
26031
26032 /**
26033 * Generate a register--immediate RCL. That is,
26034 * <PRE>
26035 * rotate left with carry of dstReg by imm
26036 * </PRE>
26037 *
26038 * @param dstReg the destination register
26039 * @param imm immediate
26040 */
26041 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
26042 public final void emitRCL_Reg_Imm(GPR dstReg, int imm) {
26043 int miStart = mi;
26044 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
26045 // no size prefix
26046 generateREXprefix(false, null, null, dstReg);
26047 if (imm == 1) {
26048 setMachineCodes(mi++, (byte) 0xD1);
26049 emitRegRegOperands(dstReg, GPR.getForOpcode(0x2));
26050 } else {
26051 setMachineCodes(mi++, (byte) 0xC1);
26052 emitRegRegOperands(dstReg, GPR.getForOpcode(0x2));
26053 emitImm8((byte)imm);
26054 }
26055 if (lister != null) lister.RI(miStart, "RCL", dstReg, imm);
26056 }
26057
26058 /**
26059 * Generate a register-indirect--immediate RCL. That is,
26060 * <PRE>
26061 * rotate left with carry of [dstBase] by imm
26062 * </PRE>
26063 *
26064 * @param dstBase the destination base register
26065 * @param imm immediate
26066 */
26067 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
26068 public final void emitRCL_RegInd_Imm(GPR dstBase, int imm) {
26069 int miStart = mi;
26070 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
26071 // no size prefix
26072 generateREXprefix(false, null, null, dstBase);
26073 if (imm == 1) {
26074 setMachineCodes(mi++, (byte) 0xD1);
26075 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x2));
26076 } else {
26077 setMachineCodes(mi++, (byte) 0xC1);
26078 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x2));
26079 emitImm8((byte)imm);
26080 }
26081 if (lister != null) lister.RNI(miStart, "RCL", dstBase, imm);
26082 }
26083
26084 /**
26085 * Generate a register-displacement--immediate RCL. That is,
26086 * <PRE>
26087 * rotate left with carry of [dstBase + dstDisp] by imm
26088 * </PRE>
26089 *
26090 * @param dstBase the destination base register
26091 * @param dstDisp the destination displacement
26092 * @param imm immediate
26093 */
26094 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
26095 public final void emitRCL_RegDisp_Imm(GPR dstBase, Offset dstDisp, int imm) {
26096 int miStart = mi;
26097 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
26098 // no size prefix
26099 generateREXprefix(false, null, null, dstBase);
26100 if (imm == 1) {
26101 setMachineCodes(mi++, (byte) 0xD1);
26102 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x2));
26103 } else {
26104 setMachineCodes(mi++, (byte) 0xC1);
26105 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x2));
26106 emitImm8((byte)imm);
26107 }
26108 if (lister != null) lister.RDI(miStart, "RCL", dstBase, dstDisp, imm);
26109 }
26110
26111 /**
26112 * Generate a register-offset--immediate RCL. That is,
26113 * <PRE>
26114 * rotate left with carry of [dstIndex<<dstScale + dstDisp] by imm
26115 * </PRE>
26116 *
26117 * @param dstIndex the destination index register
26118 * @param dstScale the destination shift amount
26119 * @param dstDisp the destination displacement
26120 * @param imm immediate
26121 */
26122 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
26123 public final void emitRCL_RegOff_Imm(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
26124 int miStart = mi;
26125 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
26126 // no size prefix
26127 generateREXprefix(false, null, dstIndex, null);
26128 if (imm == 1) {
26129 setMachineCodes(mi++, (byte) 0xD1);
26130 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
26131 } else {
26132 setMachineCodes(mi++, (byte) 0xC1);
26133 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
26134 emitImm8((byte)imm);
26135 }
26136 if (lister != null) lister.RFDI(miStart, "RCL", dstIndex, dstScale, dstDisp, imm);
26137 }
26138
26139 /**
26140 * Generate a absolute--immediate RCL. That is,
26141 * <PRE>
26142 * rotate left with carry of [dstDisp] by imm
26143 * </PRE>
26144 *
26145 * @param dstDisp the destination displacement
26146 * @param imm immediate
26147 */
26148 public final void emitRCL_Abs_Imm(Address dstDisp, int imm) {
26149 int miStart = mi;
26150 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
26151 // no size prefix
26152 generateREXprefix(false, null, null, null);
26153 if (imm == 1) {
26154 setMachineCodes(mi++, (byte) 0xD1);
26155 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x2));
26156 } else {
26157 setMachineCodes(mi++, (byte) 0xC1);
26158 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x2));
26159 emitImm8((byte)imm);
26160 }
26161 if (lister != null) lister.RAI(miStart, "RCL", dstDisp, imm);
26162 }
26163
26164 /**
26165 * Generate a register-index--immediate RCL. That is,
26166 * <PRE>
26167 * rotate left with carry of [dstBase + dstIndex<<dstScale + dstDisp] by imm
26168 * </PRE>
26169 *
26170 * @param dstBase the destination base register
26171 * @param dstIndex the destination index register
26172 * @param dstScale the destination shift amount
26173 * @param dstDisp the destination displacement
26174 * @param imm immediate
26175 */
26176 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
26177 public final void emitRCL_RegIdx_Imm(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
26178 int miStart = mi;
26179 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
26180 // no size prefix
26181 generateREXprefix(false, null, dstIndex, dstBase);
26182 if (imm == 1) {
26183 setMachineCodes(mi++, (byte) 0xD1);
26184 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
26185 } else {
26186 setMachineCodes(mi++, (byte) 0xC1);
26187 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
26188 emitImm8((byte)imm);
26189 }
26190 if (lister != null) lister.RXDI(miStart, "RCL", dstBase, dstIndex, dstScale, dstDisp, imm);
26191 }
26192
26193 /**
26194 * Generate a register--register RCL. That is,
26195 * <PRE>
26196 * rotate left with carry of dstReg by srcReg
26197 * </PRE>
26198 *
26199 * @param dstReg the destination register
26200 * @param srcReg must always be ECX
26201 */
26202 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
26203 public final void emitRCL_Reg_Reg(GPR dstReg, GPR srcReg) {
26204 int miStart = mi;
26205 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
26206 // no size prefix
26207 generateREXprefix(false, null, null, dstReg);
26208 setMachineCodes(mi++, (byte) 0xD3);
26209 emitRegRegOperands(dstReg, GPR.getForOpcode(0x2));
26210 if (lister != null) lister.RR(miStart, "RCL", dstReg, srcReg);
26211 }
26212
26213 /**
26214 * Generate a register-indirect--register RCL. That is,
26215 * <PRE>
26216 * rotate left with carry of [dstBase] by srcReg
26217 * </PRE>
26218 *
26219 * @param dstBase the destination register
26220 * @param srcReg must always be ECX
26221 */
26222 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
26223 public final void emitRCL_RegInd_Reg(GPR dstBase, GPR srcReg) {
26224 int miStart = mi;
26225 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
26226 // no size prefix
26227 generateREXprefix(false, null, null, dstBase);
26228 setMachineCodes(mi++, (byte) 0xD3);
26229 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x2));
26230 if (lister != null) lister.RNR(miStart, "RCL", dstBase, srcReg);
26231 }
26232
26233 /**
26234 * Generate a register-displacement--register RCL. That is,
26235 * <PRE>
26236 * rotate left with carry of [dstBase + dstDisp] by srcReg
26237 * </PRE>
26238 *
26239 * @param dstBase the destination base register
26240 * @param dstDisp the destination displacement
26241 * @param srcReg must always be ECX
26242 */
26243 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
26244 public final void emitRCL_RegDisp_Reg(GPR dstBase, Offset dstDisp, GPR srcReg) {
26245 int miStart = mi;
26246 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
26247 // no size prefix
26248 generateREXprefix(false, null, null, dstBase);
26249 setMachineCodes(mi++, (byte) 0xD3);
26250 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x2));
26251 if (lister != null) lister.RDR(miStart, "RCL", dstBase, dstDisp, srcReg);
26252 }
26253
26254 /**
26255 * Generate a register-offset--register RCL. That is,
26256 * <PRE>
26257 * rotate left with carry of [dstIndex<<dstScale + dstDisp] by srcReg
26258 * </PRE>
26259 *
26260 * @param dstIndex the destination index register
26261 * @param dstScale the destination shift amount
26262 * @param dstDisp the destination displacement
26263 * @param srcReg must always be ECX
26264 */
26265 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
26266 public final void emitRCL_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
26267 int miStart = mi;
26268 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
26269 // no size prefix
26270 generateREXprefix(false, null, dstIndex, null);
26271 setMachineCodes(mi++, (byte) 0xD3);
26272 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
26273 if (lister != null) lister.RFDR(miStart, "RCL", dstIndex, dstScale, dstDisp, srcReg);
26274 }
26275
26276 /**
26277 * Generate an absolute--register RCL. That is,
26278 * <PRE>
26279 * rotate left with carry of [dstDisp] by srcReg
26280 * </PRE>
26281 *
26282 * @param dstDisp the destination displacement
26283 * @param srcReg must always be ECX
26284 */
26285 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
26286 public final void emitRCL_Abs_Reg(Address dstDisp, GPR srcReg) {
26287 int miStart = mi;
26288 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
26289 // no size prefix
26290 generateREXprefix(false, null, null, null);
26291 setMachineCodes(mi++, (byte) 0xD3);
26292 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x2));
26293 if (lister != null) lister.RAR(miStart, "RCL", dstDisp, srcReg);
26294 }
26295
26296 /**
26297 * Generate a register-displacement--register RCL. That is,
26298 * <PRE>
26299 * rotate left with carry of [dstBase + dstIndex<<dstScale + dstDisp] by srcReg
26300 * </PRE>
26301 *
26302 * @param dstBase the destination base register
26303 * @param dstIndex the destination index register
26304 * @param dstScale the destination shift amount
26305 * @param dstDisp the destination displacement
26306 * @param srcReg must always be ECX
26307 */
26308 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
26309 public final void emitRCL_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
26310 int miStart = mi;
26311 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
26312 // no size prefix
26313 generateREXprefix(false, null, dstIndex, dstBase);
26314 setMachineCodes(mi++, (byte) 0xD3);
26315 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
26316 if (lister != null) lister.RXDR(miStart, "RCL", dstBase, dstIndex, dstScale, dstDisp, srcReg);
26317 }
26318
26319 /**
26320 * Generate a register--immediate RCL. That is,
26321 * <PRE>
26322 * rotate left with carry of dstReg by imm
26323 * </PRE>
26324 *
26325 * @param dstReg the destination register
26326 * @param imm immediate
26327 */
26328 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
26329 public final void emitRCL_Reg_Imm_Quad(GPR dstReg, int imm) {
26330 int miStart = mi;
26331 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
26332 // no size prefix
26333 generateREXprefix(true, null, null, dstReg);
26334 if (imm == 1) {
26335 setMachineCodes(mi++, (byte) 0xD1);
26336 emitRegRegOperands(dstReg, GPR.getForOpcode(0x2));
26337 } else {
26338 setMachineCodes(mi++, (byte) 0xC1);
26339 emitRegRegOperands(dstReg, GPR.getForOpcode(0x2));
26340 emitImm8((byte)imm);
26341 }
26342 if (lister != null) lister.RI(miStart, "RCL", dstReg, imm);
26343 }
26344
26345 /**
26346 * Generate a register-indirect--immediate RCL. That is,
26347 * <PRE>
26348 * rotate left with carry of [dstBase] by imm
26349 * </PRE>
26350 *
26351 * @param dstBase the destination base register
26352 * @param imm immediate
26353 */
26354 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
26355 public final void emitRCL_RegInd_Imm_Quad(GPR dstBase, int imm) {
26356 int miStart = mi;
26357 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
26358 // no size prefix
26359 generateREXprefix(true, null, null, dstBase);
26360 if (imm == 1) {
26361 setMachineCodes(mi++, (byte) 0xD1);
26362 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x2));
26363 } else {
26364 setMachineCodes(mi++, (byte) 0xC1);
26365 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x2));
26366 emitImm8((byte)imm);
26367 }
26368 if (lister != null) lister.RNI(miStart, "RCL", dstBase, imm);
26369 }
26370
26371 /**
26372 * Generate a register-displacement--immediate RCL. That is,
26373 * <PRE>
26374 * rotate left with carry of [dstBase + dstDisp] by imm
26375 * </PRE>
26376 *
26377 * @param dstBase the destination base register
26378 * @param dstDisp the destination displacement
26379 * @param imm immediate
26380 */
26381 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
26382 public final void emitRCL_RegDisp_Imm_Quad(GPR dstBase, Offset dstDisp, int imm) {
26383 int miStart = mi;
26384 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
26385 // no size prefix
26386 generateREXprefix(true, null, null, dstBase);
26387 if (imm == 1) {
26388 setMachineCodes(mi++, (byte) 0xD1);
26389 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x2));
26390 } else {
26391 setMachineCodes(mi++, (byte) 0xC1);
26392 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x2));
26393 emitImm8((byte)imm);
26394 }
26395 if (lister != null) lister.RDI(miStart, "RCL", dstBase, dstDisp, imm);
26396 }
26397
26398 /**
26399 * Generate a register-offset--immediate RCL. That is,
26400 * <PRE>
26401 * rotate left with carry of [dstIndex<<dstScale + dstDisp] by imm
26402 * </PRE>
26403 *
26404 * @param dstIndex the destination index register
26405 * @param dstScale the destination shift amount
26406 * @param dstDisp the destination displacement
26407 * @param imm immediate
26408 */
26409 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
26410 public final void emitRCL_RegOff_Imm_Quad(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
26411 int miStart = mi;
26412 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
26413 // no size prefix
26414 generateREXprefix(true, null, dstIndex, null);
26415 if (imm == 1) {
26416 setMachineCodes(mi++, (byte) 0xD1);
26417 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
26418 } else {
26419 setMachineCodes(mi++, (byte) 0xC1);
26420 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
26421 emitImm8((byte)imm);
26422 }
26423 if (lister != null) lister.RFDI(miStart, "RCL", dstIndex, dstScale, dstDisp, imm);
26424 }
26425
26426 /**
26427 * Generate a absolute--immediate RCL. That is,
26428 * <PRE>
26429 * rotate left with carry of [dstDisp] by imm
26430 * </PRE>
26431 *
26432 * @param dstDisp the destination displacement
26433 * @param imm immediate
26434 */
26435 public final void emitRCL_Abs_Imm_Quad(Address dstDisp, int imm) {
26436 int miStart = mi;
26437 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
26438 // no size prefix
26439 generateREXprefix(true, null, null, null);
26440 if (imm == 1) {
26441 setMachineCodes(mi++, (byte) 0xD1);
26442 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x2));
26443 } else {
26444 setMachineCodes(mi++, (byte) 0xC1);
26445 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x2));
26446 emitImm8((byte)imm);
26447 }
26448 if (lister != null) lister.RAI(miStart, "RCL", dstDisp, imm);
26449 }
26450
26451 /**
26452 * Generate a register-index--immediate RCL. That is,
26453 * <PRE>
26454 * rotate left with carry of [dstBase + dstIndex<<dstScale + dstDisp] by imm
26455 * </PRE>
26456 *
26457 * @param dstBase the destination base register
26458 * @param dstIndex the destination index register
26459 * @param dstScale the destination shift amount
26460 * @param dstDisp the destination displacement
26461 * @param imm immediate
26462 */
26463 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
26464 public final void emitRCL_RegIdx_Imm_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
26465 int miStart = mi;
26466 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
26467 // no size prefix
26468 generateREXprefix(true, null, dstIndex, dstBase);
26469 if (imm == 1) {
26470 setMachineCodes(mi++, (byte) 0xD1);
26471 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
26472 } else {
26473 setMachineCodes(mi++, (byte) 0xC1);
26474 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
26475 emitImm8((byte)imm);
26476 }
26477 if (lister != null) lister.RXDI(miStart, "RCL", dstBase, dstIndex, dstScale, dstDisp, imm);
26478 }
26479
26480 /**
26481 * Generate a register--register RCL. That is,
26482 * <PRE>
26483 * rotate left with carry of dstReg by srcReg
26484 * </PRE>
26485 *
26486 * @param dstReg the destination register
26487 * @param srcReg must always be ECX
26488 */
26489 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
26490 public final void emitRCL_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
26491 int miStart = mi;
26492 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
26493 // no size prefix
26494 generateREXprefix(true, null, null, dstReg);
26495 setMachineCodes(mi++, (byte) 0xD3);
26496 emitRegRegOperands(dstReg, GPR.getForOpcode(0x2));
26497 if (lister != null) lister.RR(miStart, "RCL", dstReg, srcReg);
26498 }
26499
26500 /**
26501 * Generate a register-indirect--register RCL. That is,
26502 * <PRE>
26503 * rotate left with carry of [dstBase] by srcReg
26504 * </PRE>
26505 *
26506 * @param dstBase the destination register
26507 * @param srcReg must always be ECX
26508 */
26509 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
26510 public final void emitRCL_RegInd_Reg_Quad(GPR dstBase, GPR srcReg) {
26511 int miStart = mi;
26512 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
26513 // no size prefix
26514 generateREXprefix(true, null, null, dstBase);
26515 setMachineCodes(mi++, (byte) 0xD3);
26516 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x2));
26517 if (lister != null) lister.RNR(miStart, "RCL", dstBase, srcReg);
26518 }
26519
26520 /**
26521 * Generate a register-displacement--register RCL. That is,
26522 * <PRE>
26523 * rotate left with carry of [dstBase + dstDisp] by srcReg
26524 * </PRE>
26525 *
26526 * @param dstBase the destination base register
26527 * @param dstDisp the destination displacement
26528 * @param srcReg must always be ECX
26529 */
26530 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
26531 public final void emitRCL_RegDisp_Reg_Quad(GPR dstBase, Offset dstDisp, GPR srcReg) {
26532 int miStart = mi;
26533 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
26534 // no size prefix
26535 generateREXprefix(true, null, null, dstBase);
26536 setMachineCodes(mi++, (byte) 0xD3);
26537 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x2));
26538 if (lister != null) lister.RDR(miStart, "RCL", dstBase, dstDisp, srcReg);
26539 }
26540
26541 /**
26542 * Generate a register-offset--register RCL. That is,
26543 * <PRE>
26544 * rotate left with carry of [dstIndex<<dstScale + dstDisp] by srcReg
26545 * </PRE>
26546 *
26547 * @param dstIndex the destination index register
26548 * @param dstScale the destination shift amount
26549 * @param dstDisp the destination displacement
26550 * @param srcReg must always be ECX
26551 */
26552 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
26553 public final void emitRCL_RegOff_Reg_Quad(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
26554 int miStart = mi;
26555 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
26556 // no size prefix
26557 generateREXprefix(true, null, dstIndex, null);
26558 setMachineCodes(mi++, (byte) 0xD3);
26559 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
26560 if (lister != null) lister.RFDR(miStart, "RCL", dstIndex, dstScale, dstDisp, srcReg);
26561 }
26562
26563 /**
26564 * Generate an absolute--register RCL. That is,
26565 * <PRE>
26566 * rotate left with carry of [dstDisp] by srcReg
26567 * </PRE>
26568 *
26569 * @param dstDisp the destination displacement
26570 * @param srcReg must always be ECX
26571 */
26572 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
26573 public final void emitRCL_Abs_Reg_Quad(Address dstDisp, GPR srcReg) {
26574 int miStart = mi;
26575 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
26576 // no size prefix
26577 generateREXprefix(true, null, null, null);
26578 setMachineCodes(mi++, (byte) 0xD3);
26579 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x2));
26580 if (lister != null) lister.RAR(miStart, "RCL", dstDisp, srcReg);
26581 }
26582
26583 /**
26584 * Generate a register-displacement--register RCL. That is,
26585 * <PRE>
26586 * rotate left with carry of [dstBase + dstIndex<<dstScale + dstDisp] by srcReg
26587 * </PRE>
26588 *
26589 * @param dstBase the destination base register
26590 * @param dstIndex the destination index register
26591 * @param dstScale the destination shift amount
26592 * @param dstDisp the destination displacement
26593 * @param srcReg must always be ECX
26594 */
26595 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
26596 public final void emitRCL_RegIdx_Reg_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
26597 int miStart = mi;
26598 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
26599 // no size prefix
26600 generateREXprefix(true, null, dstIndex, dstBase);
26601 setMachineCodes(mi++, (byte) 0xD3);
26602 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x2));
26603 if (lister != null) lister.RXDR(miStart, "RCL", dstBase, dstIndex, dstScale, dstDisp, srcReg);
26604 }
26605
26606 /**
26607 * Generate a register--immediate RCR. That is,
26608 * <PRE>
26609 * rotate right with carry of dstReg by imm
26610 * </PRE>
26611 *
26612 * @param dstReg the destination register
26613 * @param imm immediate
26614 */
26615 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
26616 public final void emitRCR_Reg_Imm_Byte(GPR dstReg, int imm) {
26617 int miStart = mi;
26618 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
26619 // no size prefix
26620 generateREXprefix(false, null, null, dstReg);
26621 if (imm == 1) {
26622 setMachineCodes(mi++, (byte) 0xD0);
26623 emitRegRegOperands(dstReg, GPR.getForOpcode(0x3));
26624 } else {
26625 setMachineCodes(mi++, (byte) 0xC0);
26626 emitRegRegOperands(dstReg, GPR.getForOpcode(0x3));
26627 emitImm8((byte)imm);
26628 }
26629 if (lister != null) lister.RI(miStart, "RCR", dstReg, imm);
26630 }
26631
26632 /**
26633 * Generate a register-indirect--immediate RCR. That is,
26634 * <PRE>
26635 * rotate right with carry of [dstBase] by imm
26636 * </PRE>
26637 *
26638 * @param dstBase the destination base register
26639 * @param imm immediate
26640 */
26641 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
26642 public final void emitRCR_RegInd_Imm_Byte(GPR dstBase, int imm) {
26643 int miStart = mi;
26644 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
26645 // no size prefix
26646 generateREXprefix(false, null, null, dstBase);
26647 if (imm == 1) {
26648 setMachineCodes(mi++, (byte) 0xD0);
26649 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x3));
26650 } else {
26651 setMachineCodes(mi++, (byte) 0xC0);
26652 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x3));
26653 emitImm8((byte)imm);
26654 }
26655 if (lister != null) lister.RNI(miStart, "RCR", dstBase, imm);
26656 }
26657
26658 /**
26659 * Generate a register-displacement--immediate RCR. That is,
26660 * <PRE>
26661 * rotate right with carry of [dstBase + dstDisp] by imm
26662 * </PRE>
26663 *
26664 * @param dstBase the destination base register
26665 * @param dstDisp the destination displacement
26666 * @param imm immediate
26667 */
26668 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
26669 public final void emitRCR_RegDisp_Imm_Byte(GPR dstBase, Offset dstDisp, int imm) {
26670 int miStart = mi;
26671 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
26672 // no size prefix
26673 generateREXprefix(false, null, null, dstBase);
26674 if (imm == 1) {
26675 setMachineCodes(mi++, (byte) 0xD0);
26676 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x3));
26677 } else {
26678 setMachineCodes(mi++, (byte) 0xC0);
26679 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x3));
26680 emitImm8((byte)imm);
26681 }
26682 if (lister != null) lister.RDI(miStart, "RCR", dstBase, dstDisp, imm);
26683 }
26684
26685 /**
26686 * Generate a register-offset--immediate RCR. That is,
26687 * <PRE>
26688 * rotate right with carry of [dstIndex<<dstScale + dstDisp] by imm
26689 * </PRE>
26690 *
26691 * @param dstIndex the destination index register
26692 * @param dstScale the destination shift amount
26693 * @param dstDisp the destination displacement
26694 * @param imm immediate
26695 */
26696 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
26697 public final void emitRCR_RegOff_Imm_Byte(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
26698 int miStart = mi;
26699 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
26700 // no size prefix
26701 generateREXprefix(false, null, dstIndex, null);
26702 if (imm == 1) {
26703 setMachineCodes(mi++, (byte) 0xD0);
26704 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
26705 } else {
26706 setMachineCodes(mi++, (byte) 0xC0);
26707 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
26708 emitImm8((byte)imm);
26709 }
26710 if (lister != null) lister.RFDI(miStart, "RCR", dstIndex, dstScale, dstDisp, imm);
26711 }
26712
26713 /**
26714 * Generate a absolute--immediate RCR. That is,
26715 * <PRE>
26716 * rotate right with carry of [dstDisp] by imm
26717 * </PRE>
26718 *
26719 * @param dstDisp the destination displacement
26720 * @param imm immediate
26721 */
26722 public final void emitRCR_Abs_Imm_Byte(Address dstDisp, int imm) {
26723 int miStart = mi;
26724 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
26725 // no size prefix
26726 generateREXprefix(false, null, null, null);
26727 if (imm == 1) {
26728 setMachineCodes(mi++, (byte) 0xD0);
26729 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x3));
26730 } else {
26731 setMachineCodes(mi++, (byte) 0xC0);
26732 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x3));
26733 emitImm8((byte)imm);
26734 }
26735 if (lister != null) lister.RAI(miStart, "RCR", dstDisp, imm);
26736 }
26737
26738 /**
26739 * Generate a register-index--immediate RCR. That is,
26740 * <PRE>
26741 * rotate right with carry of [dstBase + dstIndex<<dstScale + dstDisp] by imm
26742 * </PRE>
26743 *
26744 * @param dstBase the destination base register
26745 * @param dstIndex the destination index register
26746 * @param dstScale the destination shift amount
26747 * @param dstDisp the destination displacement
26748 * @param imm immediate
26749 */
26750 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
26751 public final void emitRCR_RegIdx_Imm_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
26752 int miStart = mi;
26753 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
26754 // no size prefix
26755 generateREXprefix(false, null, dstIndex, dstBase);
26756 if (imm == 1) {
26757 setMachineCodes(mi++, (byte) 0xD0);
26758 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
26759 } else {
26760 setMachineCodes(mi++, (byte) 0xC0);
26761 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
26762 emitImm8((byte)imm);
26763 }
26764 if (lister != null) lister.RXDI(miStart, "RCR", dstBase, dstIndex, dstScale, dstDisp, imm);
26765 }
26766
26767 /**
26768 * Generate a register--register RCR. That is,
26769 * <PRE>
26770 * rotate right with carry of dstReg by srcReg
26771 * </PRE>
26772 *
26773 * @param dstReg the destination register
26774 * @param srcReg must always be ECX
26775 */
26776 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
26777 public final void emitRCR_Reg_Reg_Byte(GPR dstReg, GPR srcReg) {
26778 int miStart = mi;
26779 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
26780 // no size prefix
26781 generateREXprefix(false, null, null, dstReg);
26782 setMachineCodes(mi++, (byte) 0xD2);
26783 emitRegRegOperands(dstReg, GPR.getForOpcode(0x3));
26784 if (lister != null) lister.RR(miStart, "RCR", dstReg, srcReg);
26785 }
26786
26787 /**
26788 * Generate a register-indirect--register RCR. That is,
26789 * <PRE>
26790 * rotate right with carry of [dstBase] by srcReg
26791 * </PRE>
26792 *
26793 * @param dstBase the destination register
26794 * @param srcReg must always be ECX
26795 */
26796 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
26797 public final void emitRCR_RegInd_Reg_Byte(GPR dstBase, GPR srcReg) {
26798 int miStart = mi;
26799 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
26800 // no size prefix
26801 generateREXprefix(false, null, null, dstBase);
26802 setMachineCodes(mi++, (byte) 0xD2);
26803 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x3));
26804 if (lister != null) lister.RNR(miStart, "RCR", dstBase, srcReg);
26805 }
26806
26807 /**
26808 * Generate a register-displacement--register RCR. That is,
26809 * <PRE>
26810 * rotate right with carry of [dstBase + dstDisp] by srcReg
26811 * </PRE>
26812 *
26813 * @param dstBase the destination base register
26814 * @param dstDisp the destination displacement
26815 * @param srcReg must always be ECX
26816 */
26817 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
26818 public final void emitRCR_RegDisp_Reg_Byte(GPR dstBase, Offset dstDisp, GPR srcReg) {
26819 int miStart = mi;
26820 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
26821 // no size prefix
26822 generateREXprefix(false, null, null, dstBase);
26823 setMachineCodes(mi++, (byte) 0xD2);
26824 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x3));
26825 if (lister != null) lister.RDR(miStart, "RCR", dstBase, dstDisp, srcReg);
26826 }
26827
26828 /**
26829 * Generate a register-offset--register RCR. That is,
26830 * <PRE>
26831 * rotate right with carry of [dstIndex<<dstScale + dstDisp] by srcReg
26832 * </PRE>
26833 *
26834 * @param dstIndex the destination index register
26835 * @param dstScale the destination shift amount
26836 * @param dstDisp the destination displacement
26837 * @param srcReg must always be ECX
26838 */
26839 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
26840 public final void emitRCR_RegOff_Reg_Byte(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
26841 int miStart = mi;
26842 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
26843 // no size prefix
26844 generateREXprefix(false, null, dstIndex, null);
26845 setMachineCodes(mi++, (byte) 0xD2);
26846 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
26847 if (lister != null) lister.RFDR(miStart, "RCR", dstIndex, dstScale, dstDisp, srcReg);
26848 }
26849
26850 /**
26851 * Generate an absolute--register RCR. That is,
26852 * <PRE>
26853 * rotate right with carry of [dstDisp] by srcReg
26854 * </PRE>
26855 *
26856 * @param dstDisp the destination displacement
26857 * @param srcReg must always be ECX
26858 */
26859 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
26860 public final void emitRCR_Abs_Reg_Byte(Address dstDisp, GPR srcReg) {
26861 int miStart = mi;
26862 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
26863 // no size prefix
26864 generateREXprefix(false, null, null, null);
26865 setMachineCodes(mi++, (byte) 0xD2);
26866 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x3));
26867 if (lister != null) lister.RAR(miStart, "RCR", dstDisp, srcReg);
26868 }
26869
26870 /**
26871 * Generate a register-displacement--register RCR. That is,
26872 * <PRE>
26873 * rotate right with carry of [dstBase + dstIndex<<dstScale + dstDisp] by srcReg
26874 * </PRE>
26875 *
26876 * @param dstBase the destination base register
26877 * @param dstIndex the destination index register
26878 * @param dstScale the destination shift amount
26879 * @param dstDisp the destination displacement
26880 * @param srcReg must always be ECX
26881 */
26882 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
26883 public final void emitRCR_RegIdx_Reg_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
26884 int miStart = mi;
26885 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
26886 // no size prefix
26887 generateREXprefix(false, null, dstIndex, dstBase);
26888 setMachineCodes(mi++, (byte) 0xD2);
26889 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
26890 if (lister != null) lister.RXDR(miStart, "RCR", dstBase, dstIndex, dstScale, dstDisp, srcReg);
26891 }
26892
26893 /**
26894 * Generate a register--immediate RCR. That is,
26895 * <PRE>
26896 * rotate right with carry of dstReg by imm
26897 * </PRE>
26898 *
26899 * @param dstReg the destination register
26900 * @param imm immediate
26901 */
26902 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
26903 public final void emitRCR_Reg_Imm_Word(GPR dstReg, int imm) {
26904 int miStart = mi;
26905 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
26906 setMachineCodes(mi++, (byte) 0x66);
26907 generateREXprefix(false, null, null, dstReg);
26908 if (imm == 1) {
26909 setMachineCodes(mi++, (byte) 0xD1);
26910 emitRegRegOperands(dstReg, GPR.getForOpcode(0x3));
26911 } else {
26912 setMachineCodes(mi++, (byte) 0xC1);
26913 emitRegRegOperands(dstReg, GPR.getForOpcode(0x3));
26914 emitImm8((byte)imm);
26915 }
26916 if (lister != null) lister.RI(miStart, "RCR", dstReg, imm);
26917 }
26918
26919 /**
26920 * Generate a register-indirect--immediate RCR. That is,
26921 * <PRE>
26922 * rotate right with carry of [dstBase] by imm
26923 * </PRE>
26924 *
26925 * @param dstBase the destination base register
26926 * @param imm immediate
26927 */
26928 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
26929 public final void emitRCR_RegInd_Imm_Word(GPR dstBase, int imm) {
26930 int miStart = mi;
26931 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
26932 setMachineCodes(mi++, (byte) 0x66);
26933 generateREXprefix(false, null, null, dstBase);
26934 if (imm == 1) {
26935 setMachineCodes(mi++, (byte) 0xD1);
26936 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x3));
26937 } else {
26938 setMachineCodes(mi++, (byte) 0xC1);
26939 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x3));
26940 emitImm8((byte)imm);
26941 }
26942 if (lister != null) lister.RNI(miStart, "RCR", dstBase, imm);
26943 }
26944
26945 /**
26946 * Generate a register-displacement--immediate RCR. That is,
26947 * <PRE>
26948 * rotate right with carry of [dstBase + dstDisp] by imm
26949 * </PRE>
26950 *
26951 * @param dstBase the destination base register
26952 * @param dstDisp the destination displacement
26953 * @param imm immediate
26954 */
26955 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
26956 public final void emitRCR_RegDisp_Imm_Word(GPR dstBase, Offset dstDisp, int imm) {
26957 int miStart = mi;
26958 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
26959 setMachineCodes(mi++, (byte) 0x66);
26960 generateREXprefix(false, null, null, dstBase);
26961 if (imm == 1) {
26962 setMachineCodes(mi++, (byte) 0xD1);
26963 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x3));
26964 } else {
26965 setMachineCodes(mi++, (byte) 0xC1);
26966 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x3));
26967 emitImm8((byte)imm);
26968 }
26969 if (lister != null) lister.RDI(miStart, "RCR", dstBase, dstDisp, imm);
26970 }
26971
26972 /**
26973 * Generate a register-offset--immediate RCR. That is,
26974 * <PRE>
26975 * rotate right with carry of [dstIndex<<dstScale + dstDisp] by imm
26976 * </PRE>
26977 *
26978 * @param dstIndex the destination index register
26979 * @param dstScale the destination shift amount
26980 * @param dstDisp the destination displacement
26981 * @param imm immediate
26982 */
26983 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
26984 public final void emitRCR_RegOff_Imm_Word(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
26985 int miStart = mi;
26986 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
26987 setMachineCodes(mi++, (byte) 0x66);
26988 generateREXprefix(false, null, dstIndex, null);
26989 if (imm == 1) {
26990 setMachineCodes(mi++, (byte) 0xD1);
26991 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
26992 } else {
26993 setMachineCodes(mi++, (byte) 0xC1);
26994 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
26995 emitImm8((byte)imm);
26996 }
26997 if (lister != null) lister.RFDI(miStart, "RCR", dstIndex, dstScale, dstDisp, imm);
26998 }
26999
27000 /**
27001 * Generate a absolute--immediate RCR. That is,
27002 * <PRE>
27003 * rotate right with carry of [dstDisp] by imm
27004 * </PRE>
27005 *
27006 * @param dstDisp the destination displacement
27007 * @param imm immediate
27008 */
27009 public final void emitRCR_Abs_Imm_Word(Address dstDisp, int imm) {
27010 int miStart = mi;
27011 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
27012 setMachineCodes(mi++, (byte) 0x66);
27013 generateREXprefix(false, null, null, null);
27014 if (imm == 1) {
27015 setMachineCodes(mi++, (byte) 0xD1);
27016 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x3));
27017 } else {
27018 setMachineCodes(mi++, (byte) 0xC1);
27019 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x3));
27020 emitImm8((byte)imm);
27021 }
27022 if (lister != null) lister.RAI(miStart, "RCR", dstDisp, imm);
27023 }
27024
27025 /**
27026 * Generate a register-index--immediate RCR. That is,
27027 * <PRE>
27028 * rotate right with carry of [dstBase + dstIndex<<dstScale + dstDisp] by imm
27029 * </PRE>
27030 *
27031 * @param dstBase the destination base register
27032 * @param dstIndex the destination index register
27033 * @param dstScale the destination shift amount
27034 * @param dstDisp the destination displacement
27035 * @param imm immediate
27036 */
27037 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
27038 public final void emitRCR_RegIdx_Imm_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
27039 int miStart = mi;
27040 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
27041 setMachineCodes(mi++, (byte) 0x66);
27042 generateREXprefix(false, null, dstIndex, dstBase);
27043 if (imm == 1) {
27044 setMachineCodes(mi++, (byte) 0xD1);
27045 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
27046 } else {
27047 setMachineCodes(mi++, (byte) 0xC1);
27048 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
27049 emitImm8((byte)imm);
27050 }
27051 if (lister != null) lister.RXDI(miStart, "RCR", dstBase, dstIndex, dstScale, dstDisp, imm);
27052 }
27053
27054 /**
27055 * Generate a register--register RCR. That is,
27056 * <PRE>
27057 * rotate right with carry of dstReg by srcReg
27058 * </PRE>
27059 *
27060 * @param dstReg the destination register
27061 * @param srcReg must always be ECX
27062 */
27063 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
27064 public final void emitRCR_Reg_Reg_Word(GPR dstReg, GPR srcReg) {
27065 int miStart = mi;
27066 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
27067 setMachineCodes(mi++, (byte) 0x66);
27068 generateREXprefix(false, null, null, dstReg);
27069 setMachineCodes(mi++, (byte) 0xD3);
27070 emitRegRegOperands(dstReg, GPR.getForOpcode(0x3));
27071 if (lister != null) lister.RR(miStart, "RCR", dstReg, srcReg);
27072 }
27073
27074 /**
27075 * Generate a register-indirect--register RCR. That is,
27076 * <PRE>
27077 * rotate right with carry of [dstBase] by srcReg
27078 * </PRE>
27079 *
27080 * @param dstBase the destination register
27081 * @param srcReg must always be ECX
27082 */
27083 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
27084 public final void emitRCR_RegInd_Reg_Word(GPR dstBase, GPR srcReg) {
27085 int miStart = mi;
27086 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
27087 setMachineCodes(mi++, (byte) 0x66);
27088 generateREXprefix(false, null, null, dstBase);
27089 setMachineCodes(mi++, (byte) 0xD3);
27090 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x3));
27091 if (lister != null) lister.RNR(miStart, "RCR", dstBase, srcReg);
27092 }
27093
27094 /**
27095 * Generate a register-displacement--register RCR. That is,
27096 * <PRE>
27097 * rotate right with carry of [dstBase + dstDisp] by srcReg
27098 * </PRE>
27099 *
27100 * @param dstBase the destination base register
27101 * @param dstDisp the destination displacement
27102 * @param srcReg must always be ECX
27103 */
27104 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
27105 public final void emitRCR_RegDisp_Reg_Word(GPR dstBase, Offset dstDisp, GPR srcReg) {
27106 int miStart = mi;
27107 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
27108 setMachineCodes(mi++, (byte) 0x66);
27109 generateREXprefix(false, null, null, dstBase);
27110 setMachineCodes(mi++, (byte) 0xD3);
27111 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x3));
27112 if (lister != null) lister.RDR(miStart, "RCR", dstBase, dstDisp, srcReg);
27113 }
27114
27115 /**
27116 * Generate a register-offset--register RCR. That is,
27117 * <PRE>
27118 * rotate right with carry of [dstIndex<<dstScale + dstDisp] by srcReg
27119 * </PRE>
27120 *
27121 * @param dstIndex the destination index register
27122 * @param dstScale the destination shift amount
27123 * @param dstDisp the destination displacement
27124 * @param srcReg must always be ECX
27125 */
27126 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
27127 public final void emitRCR_RegOff_Reg_Word(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
27128 int miStart = mi;
27129 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
27130 setMachineCodes(mi++, (byte) 0x66);
27131 generateREXprefix(false, null, dstIndex, null);
27132 setMachineCodes(mi++, (byte) 0xD3);
27133 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
27134 if (lister != null) lister.RFDR(miStart, "RCR", dstIndex, dstScale, dstDisp, srcReg);
27135 }
27136
27137 /**
27138 * Generate an absolute--register RCR. That is,
27139 * <PRE>
27140 * rotate right with carry of [dstDisp] by srcReg
27141 * </PRE>
27142 *
27143 * @param dstDisp the destination displacement
27144 * @param srcReg must always be ECX
27145 */
27146 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
27147 public final void emitRCR_Abs_Reg_Word(Address dstDisp, GPR srcReg) {
27148 int miStart = mi;
27149 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
27150 setMachineCodes(mi++, (byte) 0x66);
27151 generateREXprefix(false, null, null, null);
27152 setMachineCodes(mi++, (byte) 0xD3);
27153 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x3));
27154 if (lister != null) lister.RAR(miStart, "RCR", dstDisp, srcReg);
27155 }
27156
27157 /**
27158 * Generate a register-displacement--register RCR. That is,
27159 * <PRE>
27160 * rotate right with carry of [dstBase + dstIndex<<dstScale + dstDisp] by srcReg
27161 * </PRE>
27162 *
27163 * @param dstBase the destination base register
27164 * @param dstIndex the destination index register
27165 * @param dstScale the destination shift amount
27166 * @param dstDisp the destination displacement
27167 * @param srcReg must always be ECX
27168 */
27169 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
27170 public final void emitRCR_RegIdx_Reg_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
27171 int miStart = mi;
27172 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
27173 setMachineCodes(mi++, (byte) 0x66);
27174 generateREXprefix(false, null, dstIndex, dstBase);
27175 setMachineCodes(mi++, (byte) 0xD3);
27176 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
27177 if (lister != null) lister.RXDR(miStart, "RCR", dstBase, dstIndex, dstScale, dstDisp, srcReg);
27178 }
27179
27180 /**
27181 * Generate a register--immediate RCR. That is,
27182 * <PRE>
27183 * rotate right with carry of dstReg by imm
27184 * </PRE>
27185 *
27186 * @param dstReg the destination register
27187 * @param imm immediate
27188 */
27189 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
27190 public final void emitRCR_Reg_Imm(GPR dstReg, int imm) {
27191 int miStart = mi;
27192 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
27193 // no size prefix
27194 generateREXprefix(false, null, null, dstReg);
27195 if (imm == 1) {
27196 setMachineCodes(mi++, (byte) 0xD1);
27197 emitRegRegOperands(dstReg, GPR.getForOpcode(0x3));
27198 } else {
27199 setMachineCodes(mi++, (byte) 0xC1);
27200 emitRegRegOperands(dstReg, GPR.getForOpcode(0x3));
27201 emitImm8((byte)imm);
27202 }
27203 if (lister != null) lister.RI(miStart, "RCR", dstReg, imm);
27204 }
27205
27206 /**
27207 * Generate a register-indirect--immediate RCR. That is,
27208 * <PRE>
27209 * rotate right with carry of [dstBase] by imm
27210 * </PRE>
27211 *
27212 * @param dstBase the destination base register
27213 * @param imm immediate
27214 */
27215 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
27216 public final void emitRCR_RegInd_Imm(GPR dstBase, int imm) {
27217 int miStart = mi;
27218 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
27219 // no size prefix
27220 generateREXprefix(false, null, null, dstBase);
27221 if (imm == 1) {
27222 setMachineCodes(mi++, (byte) 0xD1);
27223 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x3));
27224 } else {
27225 setMachineCodes(mi++, (byte) 0xC1);
27226 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x3));
27227 emitImm8((byte)imm);
27228 }
27229 if (lister != null) lister.RNI(miStart, "RCR", dstBase, imm);
27230 }
27231
27232 /**
27233 * Generate a register-displacement--immediate RCR. That is,
27234 * <PRE>
27235 * rotate right with carry of [dstBase + dstDisp] by imm
27236 * </PRE>
27237 *
27238 * @param dstBase the destination base register
27239 * @param dstDisp the destination displacement
27240 * @param imm immediate
27241 */
27242 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
27243 public final void emitRCR_RegDisp_Imm(GPR dstBase, Offset dstDisp, int imm) {
27244 int miStart = mi;
27245 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
27246 // no size prefix
27247 generateREXprefix(false, null, null, dstBase);
27248 if (imm == 1) {
27249 setMachineCodes(mi++, (byte) 0xD1);
27250 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x3));
27251 } else {
27252 setMachineCodes(mi++, (byte) 0xC1);
27253 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x3));
27254 emitImm8((byte)imm);
27255 }
27256 if (lister != null) lister.RDI(miStart, "RCR", dstBase, dstDisp, imm);
27257 }
27258
27259 /**
27260 * Generate a register-offset--immediate RCR. That is,
27261 * <PRE>
27262 * rotate right with carry of [dstIndex<<dstScale + dstDisp] by imm
27263 * </PRE>
27264 *
27265 * @param dstIndex the destination index register
27266 * @param dstScale the destination shift amount
27267 * @param dstDisp the destination displacement
27268 * @param imm immediate
27269 */
27270 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
27271 public final void emitRCR_RegOff_Imm(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
27272 int miStart = mi;
27273 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
27274 // no size prefix
27275 generateREXprefix(false, null, dstIndex, null);
27276 if (imm == 1) {
27277 setMachineCodes(mi++, (byte) 0xD1);
27278 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
27279 } else {
27280 setMachineCodes(mi++, (byte) 0xC1);
27281 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
27282 emitImm8((byte)imm);
27283 }
27284 if (lister != null) lister.RFDI(miStart, "RCR", dstIndex, dstScale, dstDisp, imm);
27285 }
27286
27287 /**
27288 * Generate a absolute--immediate RCR. That is,
27289 * <PRE>
27290 * rotate right with carry of [dstDisp] by imm
27291 * </PRE>
27292 *
27293 * @param dstDisp the destination displacement
27294 * @param imm immediate
27295 */
27296 public final void emitRCR_Abs_Imm(Address dstDisp, int imm) {
27297 int miStart = mi;
27298 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
27299 // no size prefix
27300 generateREXprefix(false, null, null, null);
27301 if (imm == 1) {
27302 setMachineCodes(mi++, (byte) 0xD1);
27303 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x3));
27304 } else {
27305 setMachineCodes(mi++, (byte) 0xC1);
27306 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x3));
27307 emitImm8((byte)imm);
27308 }
27309 if (lister != null) lister.RAI(miStart, "RCR", dstDisp, imm);
27310 }
27311
27312 /**
27313 * Generate a register-index--immediate RCR. That is,
27314 * <PRE>
27315 * rotate right with carry of [dstBase + dstIndex<<dstScale + dstDisp] by imm
27316 * </PRE>
27317 *
27318 * @param dstBase the destination base register
27319 * @param dstIndex the destination index register
27320 * @param dstScale the destination shift amount
27321 * @param dstDisp the destination displacement
27322 * @param imm immediate
27323 */
27324 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
27325 public final void emitRCR_RegIdx_Imm(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
27326 int miStart = mi;
27327 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
27328 // no size prefix
27329 generateREXprefix(false, null, dstIndex, dstBase);
27330 if (imm == 1) {
27331 setMachineCodes(mi++, (byte) 0xD1);
27332 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
27333 } else {
27334 setMachineCodes(mi++, (byte) 0xC1);
27335 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
27336 emitImm8((byte)imm);
27337 }
27338 if (lister != null) lister.RXDI(miStart, "RCR", dstBase, dstIndex, dstScale, dstDisp, imm);
27339 }
27340
27341 /**
27342 * Generate a register--register RCR. That is,
27343 * <PRE>
27344 * rotate right with carry of dstReg by srcReg
27345 * </PRE>
27346 *
27347 * @param dstReg the destination register
27348 * @param srcReg must always be ECX
27349 */
27350 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
27351 public final void emitRCR_Reg_Reg(GPR dstReg, GPR srcReg) {
27352 int miStart = mi;
27353 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
27354 // no size prefix
27355 generateREXprefix(false, null, null, dstReg);
27356 setMachineCodes(mi++, (byte) 0xD3);
27357 emitRegRegOperands(dstReg, GPR.getForOpcode(0x3));
27358 if (lister != null) lister.RR(miStart, "RCR", dstReg, srcReg);
27359 }
27360
27361 /**
27362 * Generate a register-indirect--register RCR. That is,
27363 * <PRE>
27364 * rotate right with carry of [dstBase] by srcReg
27365 * </PRE>
27366 *
27367 * @param dstBase the destination register
27368 * @param srcReg must always be ECX
27369 */
27370 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
27371 public final void emitRCR_RegInd_Reg(GPR dstBase, GPR srcReg) {
27372 int miStart = mi;
27373 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
27374 // no size prefix
27375 generateREXprefix(false, null, null, dstBase);
27376 setMachineCodes(mi++, (byte) 0xD3);
27377 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x3));
27378 if (lister != null) lister.RNR(miStart, "RCR", dstBase, srcReg);
27379 }
27380
27381 /**
27382 * Generate a register-displacement--register RCR. That is,
27383 * <PRE>
27384 * rotate right with carry of [dstBase + dstDisp] by srcReg
27385 * </PRE>
27386 *
27387 * @param dstBase the destination base register
27388 * @param dstDisp the destination displacement
27389 * @param srcReg must always be ECX
27390 */
27391 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
27392 public final void emitRCR_RegDisp_Reg(GPR dstBase, Offset dstDisp, GPR srcReg) {
27393 int miStart = mi;
27394 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
27395 // no size prefix
27396 generateREXprefix(false, null, null, dstBase);
27397 setMachineCodes(mi++, (byte) 0xD3);
27398 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x3));
27399 if (lister != null) lister.RDR(miStart, "RCR", dstBase, dstDisp, srcReg);
27400 }
27401
27402 /**
27403 * Generate a register-offset--register RCR. That is,
27404 * <PRE>
27405 * rotate right with carry of [dstIndex<<dstScale + dstDisp] by srcReg
27406 * </PRE>
27407 *
27408 * @param dstIndex the destination index register
27409 * @param dstScale the destination shift amount
27410 * @param dstDisp the destination displacement
27411 * @param srcReg must always be ECX
27412 */
27413 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
27414 public final void emitRCR_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
27415 int miStart = mi;
27416 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
27417 // no size prefix
27418 generateREXprefix(false, null, dstIndex, null);
27419 setMachineCodes(mi++, (byte) 0xD3);
27420 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
27421 if (lister != null) lister.RFDR(miStart, "RCR", dstIndex, dstScale, dstDisp, srcReg);
27422 }
27423
27424 /**
27425 * Generate an absolute--register RCR. That is,
27426 * <PRE>
27427 * rotate right with carry of [dstDisp] by srcReg
27428 * </PRE>
27429 *
27430 * @param dstDisp the destination displacement
27431 * @param srcReg must always be ECX
27432 */
27433 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
27434 public final void emitRCR_Abs_Reg(Address dstDisp, GPR srcReg) {
27435 int miStart = mi;
27436 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
27437 // no size prefix
27438 generateREXprefix(false, null, null, null);
27439 setMachineCodes(mi++, (byte) 0xD3);
27440 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x3));
27441 if (lister != null) lister.RAR(miStart, "RCR", dstDisp, srcReg);
27442 }
27443
27444 /**
27445 * Generate a register-displacement--register RCR. That is,
27446 * <PRE>
27447 * rotate right with carry of [dstBase + dstIndex<<dstScale + dstDisp] by srcReg
27448 * </PRE>
27449 *
27450 * @param dstBase the destination base register
27451 * @param dstIndex the destination index register
27452 * @param dstScale the destination shift amount
27453 * @param dstDisp the destination displacement
27454 * @param srcReg must always be ECX
27455 */
27456 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
27457 public final void emitRCR_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
27458 int miStart = mi;
27459 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
27460 // no size prefix
27461 generateREXprefix(false, null, dstIndex, dstBase);
27462 setMachineCodes(mi++, (byte) 0xD3);
27463 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
27464 if (lister != null) lister.RXDR(miStart, "RCR", dstBase, dstIndex, dstScale, dstDisp, srcReg);
27465 }
27466
27467 /**
27468 * Generate a register--immediate RCR. That is,
27469 * <PRE>
27470 * rotate right with carry of dstReg by imm
27471 * </PRE>
27472 *
27473 * @param dstReg the destination register
27474 * @param imm immediate
27475 */
27476 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
27477 public final void emitRCR_Reg_Imm_Quad(GPR dstReg, int imm) {
27478 int miStart = mi;
27479 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
27480 // no size prefix
27481 generateREXprefix(true, null, null, dstReg);
27482 if (imm == 1) {
27483 setMachineCodes(mi++, (byte) 0xD1);
27484 emitRegRegOperands(dstReg, GPR.getForOpcode(0x3));
27485 } else {
27486 setMachineCodes(mi++, (byte) 0xC1);
27487 emitRegRegOperands(dstReg, GPR.getForOpcode(0x3));
27488 emitImm8((byte)imm);
27489 }
27490 if (lister != null) lister.RI(miStart, "RCR", dstReg, imm);
27491 }
27492
27493 /**
27494 * Generate a register-indirect--immediate RCR. That is,
27495 * <PRE>
27496 * rotate right with carry of [dstBase] by imm
27497 * </PRE>
27498 *
27499 * @param dstBase the destination base register
27500 * @param imm immediate
27501 */
27502 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
27503 public final void emitRCR_RegInd_Imm_Quad(GPR dstBase, int imm) {
27504 int miStart = mi;
27505 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
27506 // no size prefix
27507 generateREXprefix(true, null, null, dstBase);
27508 if (imm == 1) {
27509 setMachineCodes(mi++, (byte) 0xD1);
27510 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x3));
27511 } else {
27512 setMachineCodes(mi++, (byte) 0xC1);
27513 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x3));
27514 emitImm8((byte)imm);
27515 }
27516 if (lister != null) lister.RNI(miStart, "RCR", dstBase, imm);
27517 }
27518
27519 /**
27520 * Generate a register-displacement--immediate RCR. That is,
27521 * <PRE>
27522 * rotate right with carry of [dstBase + dstDisp] by imm
27523 * </PRE>
27524 *
27525 * @param dstBase the destination base register
27526 * @param dstDisp the destination displacement
27527 * @param imm immediate
27528 */
27529 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
27530 public final void emitRCR_RegDisp_Imm_Quad(GPR dstBase, Offset dstDisp, int imm) {
27531 int miStart = mi;
27532 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
27533 // no size prefix
27534 generateREXprefix(true, null, null, dstBase);
27535 if (imm == 1) {
27536 setMachineCodes(mi++, (byte) 0xD1);
27537 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x3));
27538 } else {
27539 setMachineCodes(mi++, (byte) 0xC1);
27540 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x3));
27541 emitImm8((byte)imm);
27542 }
27543 if (lister != null) lister.RDI(miStart, "RCR", dstBase, dstDisp, imm);
27544 }
27545
27546 /**
27547 * Generate a register-offset--immediate RCR. That is,
27548 * <PRE>
27549 * rotate right with carry of [dstIndex<<dstScale + dstDisp] by imm
27550 * </PRE>
27551 *
27552 * @param dstIndex the destination index register
27553 * @param dstScale the destination shift amount
27554 * @param dstDisp the destination displacement
27555 * @param imm immediate
27556 */
27557 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
27558 public final void emitRCR_RegOff_Imm_Quad(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
27559 int miStart = mi;
27560 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
27561 // no size prefix
27562 generateREXprefix(true, null, dstIndex, null);
27563 if (imm == 1) {
27564 setMachineCodes(mi++, (byte) 0xD1);
27565 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
27566 } else {
27567 setMachineCodes(mi++, (byte) 0xC1);
27568 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
27569 emitImm8((byte)imm);
27570 }
27571 if (lister != null) lister.RFDI(miStart, "RCR", dstIndex, dstScale, dstDisp, imm);
27572 }
27573
27574 /**
27575 * Generate a absolute--immediate RCR. That is,
27576 * <PRE>
27577 * rotate right with carry of [dstDisp] by imm
27578 * </PRE>
27579 *
27580 * @param dstDisp the destination displacement
27581 * @param imm immediate
27582 */
27583 public final void emitRCR_Abs_Imm_Quad(Address dstDisp, int imm) {
27584 int miStart = mi;
27585 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
27586 // no size prefix
27587 generateREXprefix(true, null, null, null);
27588 if (imm == 1) {
27589 setMachineCodes(mi++, (byte) 0xD1);
27590 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x3));
27591 } else {
27592 setMachineCodes(mi++, (byte) 0xC1);
27593 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x3));
27594 emitImm8((byte)imm);
27595 }
27596 if (lister != null) lister.RAI(miStart, "RCR", dstDisp, imm);
27597 }
27598
27599 /**
27600 * Generate a register-index--immediate RCR. That is,
27601 * <PRE>
27602 * rotate right with carry of [dstBase + dstIndex<<dstScale + dstDisp] by imm
27603 * </PRE>
27604 *
27605 * @param dstBase the destination base register
27606 * @param dstIndex the destination index register
27607 * @param dstScale the destination shift amount
27608 * @param dstDisp the destination displacement
27609 * @param imm immediate
27610 */
27611 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
27612 public final void emitRCR_RegIdx_Imm_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
27613 int miStart = mi;
27614 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
27615 // no size prefix
27616 generateREXprefix(true, null, dstIndex, dstBase);
27617 if (imm == 1) {
27618 setMachineCodes(mi++, (byte) 0xD1);
27619 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
27620 } else {
27621 setMachineCodes(mi++, (byte) 0xC1);
27622 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
27623 emitImm8((byte)imm);
27624 }
27625 if (lister != null) lister.RXDI(miStart, "RCR", dstBase, dstIndex, dstScale, dstDisp, imm);
27626 }
27627
27628 /**
27629 * Generate a register--register RCR. That is,
27630 * <PRE>
27631 * rotate right with carry of dstReg by srcReg
27632 * </PRE>
27633 *
27634 * @param dstReg the destination register
27635 * @param srcReg must always be ECX
27636 */
27637 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
27638 public final void emitRCR_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
27639 int miStart = mi;
27640 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
27641 // no size prefix
27642 generateREXprefix(true, null, null, dstReg);
27643 setMachineCodes(mi++, (byte) 0xD3);
27644 emitRegRegOperands(dstReg, GPR.getForOpcode(0x3));
27645 if (lister != null) lister.RR(miStart, "RCR", dstReg, srcReg);
27646 }
27647
27648 /**
27649 * Generate a register-indirect--register RCR. That is,
27650 * <PRE>
27651 * rotate right with carry of [dstBase] by srcReg
27652 * </PRE>
27653 *
27654 * @param dstBase the destination register
27655 * @param srcReg must always be ECX
27656 */
27657 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
27658 public final void emitRCR_RegInd_Reg_Quad(GPR dstBase, GPR srcReg) {
27659 int miStart = mi;
27660 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
27661 // no size prefix
27662 generateREXprefix(true, null, null, dstBase);
27663 setMachineCodes(mi++, (byte) 0xD3);
27664 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x3));
27665 if (lister != null) lister.RNR(miStart, "RCR", dstBase, srcReg);
27666 }
27667
27668 /**
27669 * Generate a register-displacement--register RCR. That is,
27670 * <PRE>
27671 * rotate right with carry of [dstBase + dstDisp] by srcReg
27672 * </PRE>
27673 *
27674 * @param dstBase the destination base register
27675 * @param dstDisp the destination displacement
27676 * @param srcReg must always be ECX
27677 */
27678 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
27679 public final void emitRCR_RegDisp_Reg_Quad(GPR dstBase, Offset dstDisp, GPR srcReg) {
27680 int miStart = mi;
27681 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
27682 // no size prefix
27683 generateREXprefix(true, null, null, dstBase);
27684 setMachineCodes(mi++, (byte) 0xD3);
27685 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x3));
27686 if (lister != null) lister.RDR(miStart, "RCR", dstBase, dstDisp, srcReg);
27687 }
27688
27689 /**
27690 * Generate a register-offset--register RCR. That is,
27691 * <PRE>
27692 * rotate right with carry of [dstIndex<<dstScale + dstDisp] by srcReg
27693 * </PRE>
27694 *
27695 * @param dstIndex the destination index register
27696 * @param dstScale the destination shift amount
27697 * @param dstDisp the destination displacement
27698 * @param srcReg must always be ECX
27699 */
27700 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
27701 public final void emitRCR_RegOff_Reg_Quad(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
27702 int miStart = mi;
27703 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
27704 // no size prefix
27705 generateREXprefix(true, null, dstIndex, null);
27706 setMachineCodes(mi++, (byte) 0xD3);
27707 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
27708 if (lister != null) lister.RFDR(miStart, "RCR", dstIndex, dstScale, dstDisp, srcReg);
27709 }
27710
27711 /**
27712 * Generate an absolute--register RCR. That is,
27713 * <PRE>
27714 * rotate right with carry of [dstDisp] by srcReg
27715 * </PRE>
27716 *
27717 * @param dstDisp the destination displacement
27718 * @param srcReg must always be ECX
27719 */
27720 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
27721 public final void emitRCR_Abs_Reg_Quad(Address dstDisp, GPR srcReg) {
27722 int miStart = mi;
27723 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
27724 // no size prefix
27725 generateREXprefix(true, null, null, null);
27726 setMachineCodes(mi++, (byte) 0xD3);
27727 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x3));
27728 if (lister != null) lister.RAR(miStart, "RCR", dstDisp, srcReg);
27729 }
27730
27731 /**
27732 * Generate a register-displacement--register RCR. That is,
27733 * <PRE>
27734 * rotate right with carry of [dstBase + dstIndex<<dstScale + dstDisp] by srcReg
27735 * </PRE>
27736 *
27737 * @param dstBase the destination base register
27738 * @param dstIndex the destination index register
27739 * @param dstScale the destination shift amount
27740 * @param dstDisp the destination displacement
27741 * @param srcReg must always be ECX
27742 */
27743 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
27744 public final void emitRCR_RegIdx_Reg_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
27745 int miStart = mi;
27746 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
27747 // no size prefix
27748 generateREXprefix(true, null, dstIndex, dstBase);
27749 setMachineCodes(mi++, (byte) 0xD3);
27750 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x3));
27751 if (lister != null) lister.RXDR(miStart, "RCR", dstBase, dstIndex, dstScale, dstDisp, srcReg);
27752 }
27753
27754 /**
27755 * Generate a register--immediate SAL. That is,
27756 * <PRE>
27757 * arithemetic shift left of dstReg by imm
27758 * </PRE>
27759 *
27760 * @param dstReg the destination register
27761 * @param imm immediate
27762 */
27763 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
27764 public final void emitSAL_Reg_Imm_Byte(GPR dstReg, int imm) {
27765 int miStart = mi;
27766 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
27767 // no size prefix
27768 generateREXprefix(false, null, null, dstReg);
27769 if (imm == 1) {
27770 setMachineCodes(mi++, (byte) 0xD0);
27771 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
27772 } else {
27773 setMachineCodes(mi++, (byte) 0xC0);
27774 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
27775 emitImm8((byte)imm);
27776 }
27777 if (lister != null) lister.RI(miStart, "SAL", dstReg, imm);
27778 }
27779
27780 /**
27781 * Generate a register-indirect--immediate SAL. That is,
27782 * <PRE>
27783 * arithemetic shift left of [dstBase] by imm
27784 * </PRE>
27785 *
27786 * @param dstBase the destination base register
27787 * @param imm immediate
27788 */
27789 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
27790 public final void emitSAL_RegInd_Imm_Byte(GPR dstBase, int imm) {
27791 int miStart = mi;
27792 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
27793 // no size prefix
27794 generateREXprefix(false, null, null, dstBase);
27795 if (imm == 1) {
27796 setMachineCodes(mi++, (byte) 0xD0);
27797 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
27798 } else {
27799 setMachineCodes(mi++, (byte) 0xC0);
27800 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
27801 emitImm8((byte)imm);
27802 }
27803 if (lister != null) lister.RNI(miStart, "SAL", dstBase, imm);
27804 }
27805
27806 /**
27807 * Generate a register-displacement--immediate SAL. That is,
27808 * <PRE>
27809 * arithemetic shift left of [dstBase + dstDisp] by imm
27810 * </PRE>
27811 *
27812 * @param dstBase the destination base register
27813 * @param dstDisp the destination displacement
27814 * @param imm immediate
27815 */
27816 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
27817 public final void emitSAL_RegDisp_Imm_Byte(GPR dstBase, Offset dstDisp, int imm) {
27818 int miStart = mi;
27819 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
27820 // no size prefix
27821 generateREXprefix(false, null, null, dstBase);
27822 if (imm == 1) {
27823 setMachineCodes(mi++, (byte) 0xD0);
27824 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
27825 } else {
27826 setMachineCodes(mi++, (byte) 0xC0);
27827 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
27828 emitImm8((byte)imm);
27829 }
27830 if (lister != null) lister.RDI(miStart, "SAL", dstBase, dstDisp, imm);
27831 }
27832
27833 /**
27834 * Generate a register-offset--immediate SAL. That is,
27835 * <PRE>
27836 * arithemetic shift left of [dstIndex<<dstScale + dstDisp] by imm
27837 * </PRE>
27838 *
27839 * @param dstIndex the destination index register
27840 * @param dstScale the destination shift amount
27841 * @param dstDisp the destination displacement
27842 * @param imm immediate
27843 */
27844 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
27845 public final void emitSAL_RegOff_Imm_Byte(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
27846 int miStart = mi;
27847 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
27848 // no size prefix
27849 generateREXprefix(false, null, dstIndex, null);
27850 if (imm == 1) {
27851 setMachineCodes(mi++, (byte) 0xD0);
27852 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
27853 } else {
27854 setMachineCodes(mi++, (byte) 0xC0);
27855 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
27856 emitImm8((byte)imm);
27857 }
27858 if (lister != null) lister.RFDI(miStart, "SAL", dstIndex, dstScale, dstDisp, imm);
27859 }
27860
27861 /**
27862 * Generate a absolute--immediate SAL. That is,
27863 * <PRE>
27864 * arithemetic shift left of [dstDisp] by imm
27865 * </PRE>
27866 *
27867 * @param dstDisp the destination displacement
27868 * @param imm immediate
27869 */
27870 public final void emitSAL_Abs_Imm_Byte(Address dstDisp, int imm) {
27871 int miStart = mi;
27872 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
27873 // no size prefix
27874 generateREXprefix(false, null, null, null);
27875 if (imm == 1) {
27876 setMachineCodes(mi++, (byte) 0xD0);
27877 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
27878 } else {
27879 setMachineCodes(mi++, (byte) 0xC0);
27880 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
27881 emitImm8((byte)imm);
27882 }
27883 if (lister != null) lister.RAI(miStart, "SAL", dstDisp, imm);
27884 }
27885
27886 /**
27887 * Generate a register-index--immediate SAL. That is,
27888 * <PRE>
27889 * arithemetic shift left of [dstBase + dstIndex<<dstScale + dstDisp] by imm
27890 * </PRE>
27891 *
27892 * @param dstBase the destination base register
27893 * @param dstIndex the destination index register
27894 * @param dstScale the destination shift amount
27895 * @param dstDisp the destination displacement
27896 * @param imm immediate
27897 */
27898 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
27899 public final void emitSAL_RegIdx_Imm_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
27900 int miStart = mi;
27901 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
27902 // no size prefix
27903 generateREXprefix(false, null, dstIndex, dstBase);
27904 if (imm == 1) {
27905 setMachineCodes(mi++, (byte) 0xD0);
27906 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
27907 } else {
27908 setMachineCodes(mi++, (byte) 0xC0);
27909 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
27910 emitImm8((byte)imm);
27911 }
27912 if (lister != null) lister.RXDI(miStart, "SAL", dstBase, dstIndex, dstScale, dstDisp, imm);
27913 }
27914
27915 /**
27916 * Generate a register--register SAL. That is,
27917 * <PRE>
27918 * arithemetic shift left of dstReg by srcReg
27919 * </PRE>
27920 *
27921 * @param dstReg the destination register
27922 * @param srcReg must always be ECX
27923 */
27924 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
27925 public final void emitSAL_Reg_Reg_Byte(GPR dstReg, GPR srcReg) {
27926 int miStart = mi;
27927 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
27928 // no size prefix
27929 generateREXprefix(false, null, null, dstReg);
27930 setMachineCodes(mi++, (byte) 0xD2);
27931 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
27932 if (lister != null) lister.RR(miStart, "SAL", dstReg, srcReg);
27933 }
27934
27935 /**
27936 * Generate a register-indirect--register SAL. That is,
27937 * <PRE>
27938 * arithemetic shift left of [dstBase] by srcReg
27939 * </PRE>
27940 *
27941 * @param dstBase the destination register
27942 * @param srcReg must always be ECX
27943 */
27944 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
27945 public final void emitSAL_RegInd_Reg_Byte(GPR dstBase, GPR srcReg) {
27946 int miStart = mi;
27947 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
27948 // no size prefix
27949 generateREXprefix(false, null, null, dstBase);
27950 setMachineCodes(mi++, (byte) 0xD2);
27951 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
27952 if (lister != null) lister.RNR(miStart, "SAL", dstBase, srcReg);
27953 }
27954
27955 /**
27956 * Generate a register-displacement--register SAL. That is,
27957 * <PRE>
27958 * arithemetic shift left of [dstBase + dstDisp] by srcReg
27959 * </PRE>
27960 *
27961 * @param dstBase the destination base register
27962 * @param dstDisp the destination displacement
27963 * @param srcReg must always be ECX
27964 */
27965 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
27966 public final void emitSAL_RegDisp_Reg_Byte(GPR dstBase, Offset dstDisp, GPR srcReg) {
27967 int miStart = mi;
27968 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
27969 // no size prefix
27970 generateREXprefix(false, null, null, dstBase);
27971 setMachineCodes(mi++, (byte) 0xD2);
27972 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
27973 if (lister != null) lister.RDR(miStart, "SAL", dstBase, dstDisp, srcReg);
27974 }
27975
27976 /**
27977 * Generate a register-offset--register SAL. That is,
27978 * <PRE>
27979 * arithemetic shift left of [dstIndex<<dstScale + dstDisp] by srcReg
27980 * </PRE>
27981 *
27982 * @param dstIndex the destination index register
27983 * @param dstScale the destination shift amount
27984 * @param dstDisp the destination displacement
27985 * @param srcReg must always be ECX
27986 */
27987 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
27988 public final void emitSAL_RegOff_Reg_Byte(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
27989 int miStart = mi;
27990 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
27991 // no size prefix
27992 generateREXprefix(false, null, dstIndex, null);
27993 setMachineCodes(mi++, (byte) 0xD2);
27994 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
27995 if (lister != null) lister.RFDR(miStart, "SAL", dstIndex, dstScale, dstDisp, srcReg);
27996 }
27997
27998 /**
27999 * Generate an absolute--register SAL. That is,
28000 * <PRE>
28001 * arithemetic shift left of [dstDisp] by srcReg
28002 * </PRE>
28003 *
28004 * @param dstDisp the destination displacement
28005 * @param srcReg must always be ECX
28006 */
28007 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
28008 public final void emitSAL_Abs_Reg_Byte(Address dstDisp, GPR srcReg) {
28009 int miStart = mi;
28010 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
28011 // no size prefix
28012 generateREXprefix(false, null, null, null);
28013 setMachineCodes(mi++, (byte) 0xD2);
28014 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
28015 if (lister != null) lister.RAR(miStart, "SAL", dstDisp, srcReg);
28016 }
28017
28018 /**
28019 * Generate a register-displacement--register SAL. That is,
28020 * <PRE>
28021 * arithemetic shift left of [dstBase + dstIndex<<dstScale + dstDisp] by srcReg
28022 * </PRE>
28023 *
28024 * @param dstBase the destination base register
28025 * @param dstIndex the destination index register
28026 * @param dstScale the destination shift amount
28027 * @param dstDisp the destination displacement
28028 * @param srcReg must always be ECX
28029 */
28030 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
28031 public final void emitSAL_RegIdx_Reg_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
28032 int miStart = mi;
28033 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
28034 // no size prefix
28035 generateREXprefix(false, null, dstIndex, dstBase);
28036 setMachineCodes(mi++, (byte) 0xD2);
28037 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
28038 if (lister != null) lister.RXDR(miStart, "SAL", dstBase, dstIndex, dstScale, dstDisp, srcReg);
28039 }
28040
28041 /**
28042 * Generate a register--immediate SAL. That is,
28043 * <PRE>
28044 * arithemetic shift left of dstReg by imm
28045 * </PRE>
28046 *
28047 * @param dstReg the destination register
28048 * @param imm immediate
28049 */
28050 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
28051 public final void emitSAL_Reg_Imm_Word(GPR dstReg, int imm) {
28052 int miStart = mi;
28053 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
28054 setMachineCodes(mi++, (byte) 0x66);
28055 generateREXprefix(false, null, null, dstReg);
28056 if (imm == 1) {
28057 setMachineCodes(mi++, (byte) 0xD1);
28058 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
28059 } else {
28060 setMachineCodes(mi++, (byte) 0xC1);
28061 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
28062 emitImm8((byte)imm);
28063 }
28064 if (lister != null) lister.RI(miStart, "SAL", dstReg, imm);
28065 }
28066
28067 /**
28068 * Generate a register-indirect--immediate SAL. That is,
28069 * <PRE>
28070 * arithemetic shift left of [dstBase] by imm
28071 * </PRE>
28072 *
28073 * @param dstBase the destination base register
28074 * @param imm immediate
28075 */
28076 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
28077 public final void emitSAL_RegInd_Imm_Word(GPR dstBase, int imm) {
28078 int miStart = mi;
28079 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
28080 setMachineCodes(mi++, (byte) 0x66);
28081 generateREXprefix(false, null, null, dstBase);
28082 if (imm == 1) {
28083 setMachineCodes(mi++, (byte) 0xD1);
28084 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
28085 } else {
28086 setMachineCodes(mi++, (byte) 0xC1);
28087 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
28088 emitImm8((byte)imm);
28089 }
28090 if (lister != null) lister.RNI(miStart, "SAL", dstBase, imm);
28091 }
28092
28093 /**
28094 * Generate a register-displacement--immediate SAL. That is,
28095 * <PRE>
28096 * arithemetic shift left of [dstBase + dstDisp] by imm
28097 * </PRE>
28098 *
28099 * @param dstBase the destination base register
28100 * @param dstDisp the destination displacement
28101 * @param imm immediate
28102 */
28103 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
28104 public final void emitSAL_RegDisp_Imm_Word(GPR dstBase, Offset dstDisp, int imm) {
28105 int miStart = mi;
28106 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
28107 setMachineCodes(mi++, (byte) 0x66);
28108 generateREXprefix(false, null, null, dstBase);
28109 if (imm == 1) {
28110 setMachineCodes(mi++, (byte) 0xD1);
28111 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
28112 } else {
28113 setMachineCodes(mi++, (byte) 0xC1);
28114 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
28115 emitImm8((byte)imm);
28116 }
28117 if (lister != null) lister.RDI(miStart, "SAL", dstBase, dstDisp, imm);
28118 }
28119
28120 /**
28121 * Generate a register-offset--immediate SAL. That is,
28122 * <PRE>
28123 * arithemetic shift left of [dstIndex<<dstScale + dstDisp] by imm
28124 * </PRE>
28125 *
28126 * @param dstIndex the destination index register
28127 * @param dstScale the destination shift amount
28128 * @param dstDisp the destination displacement
28129 * @param imm immediate
28130 */
28131 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
28132 public final void emitSAL_RegOff_Imm_Word(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
28133 int miStart = mi;
28134 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
28135 setMachineCodes(mi++, (byte) 0x66);
28136 generateREXprefix(false, null, dstIndex, null);
28137 if (imm == 1) {
28138 setMachineCodes(mi++, (byte) 0xD1);
28139 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
28140 } else {
28141 setMachineCodes(mi++, (byte) 0xC1);
28142 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
28143 emitImm8((byte)imm);
28144 }
28145 if (lister != null) lister.RFDI(miStart, "SAL", dstIndex, dstScale, dstDisp, imm);
28146 }
28147
28148 /**
28149 * Generate a absolute--immediate SAL. That is,
28150 * <PRE>
28151 * arithemetic shift left of [dstDisp] by imm
28152 * </PRE>
28153 *
28154 * @param dstDisp the destination displacement
28155 * @param imm immediate
28156 */
28157 public final void emitSAL_Abs_Imm_Word(Address dstDisp, int imm) {
28158 int miStart = mi;
28159 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
28160 setMachineCodes(mi++, (byte) 0x66);
28161 generateREXprefix(false, null, null, null);
28162 if (imm == 1) {
28163 setMachineCodes(mi++, (byte) 0xD1);
28164 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
28165 } else {
28166 setMachineCodes(mi++, (byte) 0xC1);
28167 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
28168 emitImm8((byte)imm);
28169 }
28170 if (lister != null) lister.RAI(miStart, "SAL", dstDisp, imm);
28171 }
28172
28173 /**
28174 * Generate a register-index--immediate SAL. That is,
28175 * <PRE>
28176 * arithemetic shift left of [dstBase + dstIndex<<dstScale + dstDisp] by imm
28177 * </PRE>
28178 *
28179 * @param dstBase the destination base register
28180 * @param dstIndex the destination index register
28181 * @param dstScale the destination shift amount
28182 * @param dstDisp the destination displacement
28183 * @param imm immediate
28184 */
28185 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
28186 public final void emitSAL_RegIdx_Imm_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
28187 int miStart = mi;
28188 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
28189 setMachineCodes(mi++, (byte) 0x66);
28190 generateREXprefix(false, null, dstIndex, dstBase);
28191 if (imm == 1) {
28192 setMachineCodes(mi++, (byte) 0xD1);
28193 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
28194 } else {
28195 setMachineCodes(mi++, (byte) 0xC1);
28196 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
28197 emitImm8((byte)imm);
28198 }
28199 if (lister != null) lister.RXDI(miStart, "SAL", dstBase, dstIndex, dstScale, dstDisp, imm);
28200 }
28201
28202 /**
28203 * Generate a register--register SAL. That is,
28204 * <PRE>
28205 * arithemetic shift left of dstReg by srcReg
28206 * </PRE>
28207 *
28208 * @param dstReg the destination register
28209 * @param srcReg must always be ECX
28210 */
28211 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
28212 public final void emitSAL_Reg_Reg_Word(GPR dstReg, GPR srcReg) {
28213 int miStart = mi;
28214 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
28215 setMachineCodes(mi++, (byte) 0x66);
28216 generateREXprefix(false, null, null, dstReg);
28217 setMachineCodes(mi++, (byte) 0xD3);
28218 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
28219 if (lister != null) lister.RR(miStart, "SAL", dstReg, srcReg);
28220 }
28221
28222 /**
28223 * Generate a register-indirect--register SAL. That is,
28224 * <PRE>
28225 * arithemetic shift left of [dstBase] by srcReg
28226 * </PRE>
28227 *
28228 * @param dstBase the destination register
28229 * @param srcReg must always be ECX
28230 */
28231 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
28232 public final void emitSAL_RegInd_Reg_Word(GPR dstBase, GPR srcReg) {
28233 int miStart = mi;
28234 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
28235 setMachineCodes(mi++, (byte) 0x66);
28236 generateREXprefix(false, null, null, dstBase);
28237 setMachineCodes(mi++, (byte) 0xD3);
28238 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
28239 if (lister != null) lister.RNR(miStart, "SAL", dstBase, srcReg);
28240 }
28241
28242 /**
28243 * Generate a register-displacement--register SAL. That is,
28244 * <PRE>
28245 * arithemetic shift left of [dstBase + dstDisp] by srcReg
28246 * </PRE>
28247 *
28248 * @param dstBase the destination base register
28249 * @param dstDisp the destination displacement
28250 * @param srcReg must always be ECX
28251 */
28252 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
28253 public final void emitSAL_RegDisp_Reg_Word(GPR dstBase, Offset dstDisp, GPR srcReg) {
28254 int miStart = mi;
28255 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
28256 setMachineCodes(mi++, (byte) 0x66);
28257 generateREXprefix(false, null, null, dstBase);
28258 setMachineCodes(mi++, (byte) 0xD3);
28259 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
28260 if (lister != null) lister.RDR(miStart, "SAL", dstBase, dstDisp, srcReg);
28261 }
28262
28263 /**
28264 * Generate a register-offset--register SAL. That is,
28265 * <PRE>
28266 * arithemetic shift left of [dstIndex<<dstScale + dstDisp] by srcReg
28267 * </PRE>
28268 *
28269 * @param dstIndex the destination index register
28270 * @param dstScale the destination shift amount
28271 * @param dstDisp the destination displacement
28272 * @param srcReg must always be ECX
28273 */
28274 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
28275 public final void emitSAL_RegOff_Reg_Word(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
28276 int miStart = mi;
28277 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
28278 setMachineCodes(mi++, (byte) 0x66);
28279 generateREXprefix(false, null, dstIndex, null);
28280 setMachineCodes(mi++, (byte) 0xD3);
28281 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
28282 if (lister != null) lister.RFDR(miStart, "SAL", dstIndex, dstScale, dstDisp, srcReg);
28283 }
28284
28285 /**
28286 * Generate an absolute--register SAL. That is,
28287 * <PRE>
28288 * arithemetic shift left of [dstDisp] by srcReg
28289 * </PRE>
28290 *
28291 * @param dstDisp the destination displacement
28292 * @param srcReg must always be ECX
28293 */
28294 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
28295 public final void emitSAL_Abs_Reg_Word(Address dstDisp, GPR srcReg) {
28296 int miStart = mi;
28297 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
28298 setMachineCodes(mi++, (byte) 0x66);
28299 generateREXprefix(false, null, null, null);
28300 setMachineCodes(mi++, (byte) 0xD3);
28301 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
28302 if (lister != null) lister.RAR(miStart, "SAL", dstDisp, srcReg);
28303 }
28304
28305 /**
28306 * Generate a register-displacement--register SAL. That is,
28307 * <PRE>
28308 * arithemetic shift left of [dstBase + dstIndex<<dstScale + dstDisp] by srcReg
28309 * </PRE>
28310 *
28311 * @param dstBase the destination base register
28312 * @param dstIndex the destination index register
28313 * @param dstScale the destination shift amount
28314 * @param dstDisp the destination displacement
28315 * @param srcReg must always be ECX
28316 */
28317 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
28318 public final void emitSAL_RegIdx_Reg_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
28319 int miStart = mi;
28320 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
28321 setMachineCodes(mi++, (byte) 0x66);
28322 generateREXprefix(false, null, dstIndex, dstBase);
28323 setMachineCodes(mi++, (byte) 0xD3);
28324 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
28325 if (lister != null) lister.RXDR(miStart, "SAL", dstBase, dstIndex, dstScale, dstDisp, srcReg);
28326 }
28327
28328 /**
28329 * Generate a register--immediate SAL. That is,
28330 * <PRE>
28331 * arithemetic shift left of dstReg by imm
28332 * </PRE>
28333 *
28334 * @param dstReg the destination register
28335 * @param imm immediate
28336 */
28337 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
28338 public final void emitSAL_Reg_Imm(GPR dstReg, int imm) {
28339 int miStart = mi;
28340 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
28341 // no size prefix
28342 generateREXprefix(false, null, null, dstReg);
28343 if (imm == 1) {
28344 setMachineCodes(mi++, (byte) 0xD1);
28345 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
28346 } else {
28347 setMachineCodes(mi++, (byte) 0xC1);
28348 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
28349 emitImm8((byte)imm);
28350 }
28351 if (lister != null) lister.RI(miStart, "SAL", dstReg, imm);
28352 }
28353
28354 /**
28355 * Generate a register-indirect--immediate SAL. That is,
28356 * <PRE>
28357 * arithemetic shift left of [dstBase] by imm
28358 * </PRE>
28359 *
28360 * @param dstBase the destination base register
28361 * @param imm immediate
28362 */
28363 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
28364 public final void emitSAL_RegInd_Imm(GPR dstBase, int imm) {
28365 int miStart = mi;
28366 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
28367 // no size prefix
28368 generateREXprefix(false, null, null, dstBase);
28369 if (imm == 1) {
28370 setMachineCodes(mi++, (byte) 0xD1);
28371 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
28372 } else {
28373 setMachineCodes(mi++, (byte) 0xC1);
28374 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
28375 emitImm8((byte)imm);
28376 }
28377 if (lister != null) lister.RNI(miStart, "SAL", dstBase, imm);
28378 }
28379
28380 /**
28381 * Generate a register-displacement--immediate SAL. That is,
28382 * <PRE>
28383 * arithemetic shift left of [dstBase + dstDisp] by imm
28384 * </PRE>
28385 *
28386 * @param dstBase the destination base register
28387 * @param dstDisp the destination displacement
28388 * @param imm immediate
28389 */
28390 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
28391 public final void emitSAL_RegDisp_Imm(GPR dstBase, Offset dstDisp, int imm) {
28392 int miStart = mi;
28393 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
28394 // no size prefix
28395 generateREXprefix(false, null, null, dstBase);
28396 if (imm == 1) {
28397 setMachineCodes(mi++, (byte) 0xD1);
28398 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
28399 } else {
28400 setMachineCodes(mi++, (byte) 0xC1);
28401 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
28402 emitImm8((byte)imm);
28403 }
28404 if (lister != null) lister.RDI(miStart, "SAL", dstBase, dstDisp, imm);
28405 }
28406
28407 /**
28408 * Generate a register-offset--immediate SAL. That is,
28409 * <PRE>
28410 * arithemetic shift left of [dstIndex<<dstScale + dstDisp] by imm
28411 * </PRE>
28412 *
28413 * @param dstIndex the destination index register
28414 * @param dstScale the destination shift amount
28415 * @param dstDisp the destination displacement
28416 * @param imm immediate
28417 */
28418 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
28419 public final void emitSAL_RegOff_Imm(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
28420 int miStart = mi;
28421 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
28422 // no size prefix
28423 generateREXprefix(false, null, dstIndex, null);
28424 if (imm == 1) {
28425 setMachineCodes(mi++, (byte) 0xD1);
28426 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
28427 } else {
28428 setMachineCodes(mi++, (byte) 0xC1);
28429 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
28430 emitImm8((byte)imm);
28431 }
28432 if (lister != null) lister.RFDI(miStart, "SAL", dstIndex, dstScale, dstDisp, imm);
28433 }
28434
28435 /**
28436 * Generate a absolute--immediate SAL. That is,
28437 * <PRE>
28438 * arithemetic shift left of [dstDisp] by imm
28439 * </PRE>
28440 *
28441 * @param dstDisp the destination displacement
28442 * @param imm immediate
28443 */
28444 public final void emitSAL_Abs_Imm(Address dstDisp, int imm) {
28445 int miStart = mi;
28446 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
28447 // no size prefix
28448 generateREXprefix(false, null, null, null);
28449 if (imm == 1) {
28450 setMachineCodes(mi++, (byte) 0xD1);
28451 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
28452 } else {
28453 setMachineCodes(mi++, (byte) 0xC1);
28454 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
28455 emitImm8((byte)imm);
28456 }
28457 if (lister != null) lister.RAI(miStart, "SAL", dstDisp, imm);
28458 }
28459
28460 /**
28461 * Generate a register-index--immediate SAL. That is,
28462 * <PRE>
28463 * arithemetic shift left of [dstBase + dstIndex<<dstScale + dstDisp] by imm
28464 * </PRE>
28465 *
28466 * @param dstBase the destination base register
28467 * @param dstIndex the destination index register
28468 * @param dstScale the destination shift amount
28469 * @param dstDisp the destination displacement
28470 * @param imm immediate
28471 */
28472 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
28473 public final void emitSAL_RegIdx_Imm(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
28474 int miStart = mi;
28475 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
28476 // no size prefix
28477 generateREXprefix(false, null, dstIndex, dstBase);
28478 if (imm == 1) {
28479 setMachineCodes(mi++, (byte) 0xD1);
28480 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
28481 } else {
28482 setMachineCodes(mi++, (byte) 0xC1);
28483 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
28484 emitImm8((byte)imm);
28485 }
28486 if (lister != null) lister.RXDI(miStart, "SAL", dstBase, dstIndex, dstScale, dstDisp, imm);
28487 }
28488
28489 /**
28490 * Generate a register--register SAL. That is,
28491 * <PRE>
28492 * arithemetic shift left of dstReg by srcReg
28493 * </PRE>
28494 *
28495 * @param dstReg the destination register
28496 * @param srcReg must always be ECX
28497 */
28498 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
28499 public final void emitSAL_Reg_Reg(GPR dstReg, GPR srcReg) {
28500 int miStart = mi;
28501 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
28502 // no size prefix
28503 generateREXprefix(false, null, null, dstReg);
28504 setMachineCodes(mi++, (byte) 0xD3);
28505 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
28506 if (lister != null) lister.RR(miStart, "SAL", dstReg, srcReg);
28507 }
28508
28509 /**
28510 * Generate a register-indirect--register SAL. That is,
28511 * <PRE>
28512 * arithemetic shift left of [dstBase] by srcReg
28513 * </PRE>
28514 *
28515 * @param dstBase the destination register
28516 * @param srcReg must always be ECX
28517 */
28518 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
28519 public final void emitSAL_RegInd_Reg(GPR dstBase, GPR srcReg) {
28520 int miStart = mi;
28521 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
28522 // no size prefix
28523 generateREXprefix(false, null, null, dstBase);
28524 setMachineCodes(mi++, (byte) 0xD3);
28525 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
28526 if (lister != null) lister.RNR(miStart, "SAL", dstBase, srcReg);
28527 }
28528
28529 /**
28530 * Generate a register-displacement--register SAL. That is,
28531 * <PRE>
28532 * arithemetic shift left of [dstBase + dstDisp] by srcReg
28533 * </PRE>
28534 *
28535 * @param dstBase the destination base register
28536 * @param dstDisp the destination displacement
28537 * @param srcReg must always be ECX
28538 */
28539 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
28540 public final void emitSAL_RegDisp_Reg(GPR dstBase, Offset dstDisp, GPR srcReg) {
28541 int miStart = mi;
28542 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
28543 // no size prefix
28544 generateREXprefix(false, null, null, dstBase);
28545 setMachineCodes(mi++, (byte) 0xD3);
28546 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
28547 if (lister != null) lister.RDR(miStart, "SAL", dstBase, dstDisp, srcReg);
28548 }
28549
28550 /**
28551 * Generate a register-offset--register SAL. That is,
28552 * <PRE>
28553 * arithemetic shift left of [dstIndex<<dstScale + dstDisp] by srcReg
28554 * </PRE>
28555 *
28556 * @param dstIndex the destination index register
28557 * @param dstScale the destination shift amount
28558 * @param dstDisp the destination displacement
28559 * @param srcReg must always be ECX
28560 */
28561 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
28562 public final void emitSAL_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
28563 int miStart = mi;
28564 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
28565 // no size prefix
28566 generateREXprefix(false, null, dstIndex, null);
28567 setMachineCodes(mi++, (byte) 0xD3);
28568 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
28569 if (lister != null) lister.RFDR(miStart, "SAL", dstIndex, dstScale, dstDisp, srcReg);
28570 }
28571
28572 /**
28573 * Generate an absolute--register SAL. That is,
28574 * <PRE>
28575 * arithemetic shift left of [dstDisp] by srcReg
28576 * </PRE>
28577 *
28578 * @param dstDisp the destination displacement
28579 * @param srcReg must always be ECX
28580 */
28581 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
28582 public final void emitSAL_Abs_Reg(Address dstDisp, GPR srcReg) {
28583 int miStart = mi;
28584 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
28585 // no size prefix
28586 generateREXprefix(false, null, null, null);
28587 setMachineCodes(mi++, (byte) 0xD3);
28588 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
28589 if (lister != null) lister.RAR(miStart, "SAL", dstDisp, srcReg);
28590 }
28591
28592 /**
28593 * Generate a register-displacement--register SAL. That is,
28594 * <PRE>
28595 * arithemetic shift left of [dstBase + dstIndex<<dstScale + dstDisp] by srcReg
28596 * </PRE>
28597 *
28598 * @param dstBase the destination base register
28599 * @param dstIndex the destination index register
28600 * @param dstScale the destination shift amount
28601 * @param dstDisp the destination displacement
28602 * @param srcReg must always be ECX
28603 */
28604 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
28605 public final void emitSAL_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
28606 int miStart = mi;
28607 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
28608 // no size prefix
28609 generateREXprefix(false, null, dstIndex, dstBase);
28610 setMachineCodes(mi++, (byte) 0xD3);
28611 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
28612 if (lister != null) lister.RXDR(miStart, "SAL", dstBase, dstIndex, dstScale, dstDisp, srcReg);
28613 }
28614
28615 /**
28616 * Generate a register--immediate SAL. That is,
28617 * <PRE>
28618 * arithemetic shift left of dstReg by imm
28619 * </PRE>
28620 *
28621 * @param dstReg the destination register
28622 * @param imm immediate
28623 */
28624 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
28625 public final void emitSAL_Reg_Imm_Quad(GPR dstReg, int imm) {
28626 int miStart = mi;
28627 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
28628 // no size prefix
28629 generateREXprefix(true, null, null, dstReg);
28630 if (imm == 1) {
28631 setMachineCodes(mi++, (byte) 0xD1);
28632 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
28633 } else {
28634 setMachineCodes(mi++, (byte) 0xC1);
28635 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
28636 emitImm8((byte)imm);
28637 }
28638 if (lister != null) lister.RI(miStart, "SAL", dstReg, imm);
28639 }
28640
28641 /**
28642 * Generate a register-indirect--immediate SAL. That is,
28643 * <PRE>
28644 * arithemetic shift left of [dstBase] by imm
28645 * </PRE>
28646 *
28647 * @param dstBase the destination base register
28648 * @param imm immediate
28649 */
28650 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
28651 public final void emitSAL_RegInd_Imm_Quad(GPR dstBase, int imm) {
28652 int miStart = mi;
28653 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
28654 // no size prefix
28655 generateREXprefix(true, null, null, dstBase);
28656 if (imm == 1) {
28657 setMachineCodes(mi++, (byte) 0xD1);
28658 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
28659 } else {
28660 setMachineCodes(mi++, (byte) 0xC1);
28661 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
28662 emitImm8((byte)imm);
28663 }
28664 if (lister != null) lister.RNI(miStart, "SAL", dstBase, imm);
28665 }
28666
28667 /**
28668 * Generate a register-displacement--immediate SAL. That is,
28669 * <PRE>
28670 * arithemetic shift left of [dstBase + dstDisp] by imm
28671 * </PRE>
28672 *
28673 * @param dstBase the destination base register
28674 * @param dstDisp the destination displacement
28675 * @param imm immediate
28676 */
28677 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
28678 public final void emitSAL_RegDisp_Imm_Quad(GPR dstBase, Offset dstDisp, int imm) {
28679 int miStart = mi;
28680 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
28681 // no size prefix
28682 generateREXprefix(true, null, null, dstBase);
28683 if (imm == 1) {
28684 setMachineCodes(mi++, (byte) 0xD1);
28685 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
28686 } else {
28687 setMachineCodes(mi++, (byte) 0xC1);
28688 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
28689 emitImm8((byte)imm);
28690 }
28691 if (lister != null) lister.RDI(miStart, "SAL", dstBase, dstDisp, imm);
28692 }
28693
28694 /**
28695 * Generate a register-offset--immediate SAL. That is,
28696 * <PRE>
28697 * arithemetic shift left of [dstIndex<<dstScale + dstDisp] by imm
28698 * </PRE>
28699 *
28700 * @param dstIndex the destination index register
28701 * @param dstScale the destination shift amount
28702 * @param dstDisp the destination displacement
28703 * @param imm immediate
28704 */
28705 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
28706 public final void emitSAL_RegOff_Imm_Quad(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
28707 int miStart = mi;
28708 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
28709 // no size prefix
28710 generateREXprefix(true, null, dstIndex, null);
28711 if (imm == 1) {
28712 setMachineCodes(mi++, (byte) 0xD1);
28713 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
28714 } else {
28715 setMachineCodes(mi++, (byte) 0xC1);
28716 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
28717 emitImm8((byte)imm);
28718 }
28719 if (lister != null) lister.RFDI(miStart, "SAL", dstIndex, dstScale, dstDisp, imm);
28720 }
28721
28722 /**
28723 * Generate a absolute--immediate SAL. That is,
28724 * <PRE>
28725 * arithemetic shift left of [dstDisp] by imm
28726 * </PRE>
28727 *
28728 * @param dstDisp the destination displacement
28729 * @param imm immediate
28730 */
28731 public final void emitSAL_Abs_Imm_Quad(Address dstDisp, int imm) {
28732 int miStart = mi;
28733 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
28734 // no size prefix
28735 generateREXprefix(true, null, null, null);
28736 if (imm == 1) {
28737 setMachineCodes(mi++, (byte) 0xD1);
28738 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
28739 } else {
28740 setMachineCodes(mi++, (byte) 0xC1);
28741 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
28742 emitImm8((byte)imm);
28743 }
28744 if (lister != null) lister.RAI(miStart, "SAL", dstDisp, imm);
28745 }
28746
28747 /**
28748 * Generate a register-index--immediate SAL. That is,
28749 * <PRE>
28750 * arithemetic shift left of [dstBase + dstIndex<<dstScale + dstDisp] by imm
28751 * </PRE>
28752 *
28753 * @param dstBase the destination base register
28754 * @param dstIndex the destination index register
28755 * @param dstScale the destination shift amount
28756 * @param dstDisp the destination displacement
28757 * @param imm immediate
28758 */
28759 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
28760 public final void emitSAL_RegIdx_Imm_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
28761 int miStart = mi;
28762 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
28763 // no size prefix
28764 generateREXprefix(true, null, dstIndex, dstBase);
28765 if (imm == 1) {
28766 setMachineCodes(mi++, (byte) 0xD1);
28767 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
28768 } else {
28769 setMachineCodes(mi++, (byte) 0xC1);
28770 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
28771 emitImm8((byte)imm);
28772 }
28773 if (lister != null) lister.RXDI(miStart, "SAL", dstBase, dstIndex, dstScale, dstDisp, imm);
28774 }
28775
28776 /**
28777 * Generate a register--register SAL. That is,
28778 * <PRE>
28779 * arithemetic shift left of dstReg by srcReg
28780 * </PRE>
28781 *
28782 * @param dstReg the destination register
28783 * @param srcReg must always be ECX
28784 */
28785 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
28786 public final void emitSAL_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
28787 int miStart = mi;
28788 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
28789 // no size prefix
28790 generateREXprefix(true, null, null, dstReg);
28791 setMachineCodes(mi++, (byte) 0xD3);
28792 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
28793 if (lister != null) lister.RR(miStart, "SAL", dstReg, srcReg);
28794 }
28795
28796 /**
28797 * Generate a register-indirect--register SAL. That is,
28798 * <PRE>
28799 * arithemetic shift left of [dstBase] by srcReg
28800 * </PRE>
28801 *
28802 * @param dstBase the destination register
28803 * @param srcReg must always be ECX
28804 */
28805 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
28806 public final void emitSAL_RegInd_Reg_Quad(GPR dstBase, GPR srcReg) {
28807 int miStart = mi;
28808 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
28809 // no size prefix
28810 generateREXprefix(true, null, null, dstBase);
28811 setMachineCodes(mi++, (byte) 0xD3);
28812 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
28813 if (lister != null) lister.RNR(miStart, "SAL", dstBase, srcReg);
28814 }
28815
28816 /**
28817 * Generate a register-displacement--register SAL. That is,
28818 * <PRE>
28819 * arithemetic shift left of [dstBase + dstDisp] by srcReg
28820 * </PRE>
28821 *
28822 * @param dstBase the destination base register
28823 * @param dstDisp the destination displacement
28824 * @param srcReg must always be ECX
28825 */
28826 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
28827 public final void emitSAL_RegDisp_Reg_Quad(GPR dstBase, Offset dstDisp, GPR srcReg) {
28828 int miStart = mi;
28829 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
28830 // no size prefix
28831 generateREXprefix(true, null, null, dstBase);
28832 setMachineCodes(mi++, (byte) 0xD3);
28833 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
28834 if (lister != null) lister.RDR(miStart, "SAL", dstBase, dstDisp, srcReg);
28835 }
28836
28837 /**
28838 * Generate a register-offset--register SAL. That is,
28839 * <PRE>
28840 * arithemetic shift left of [dstIndex<<dstScale + dstDisp] by srcReg
28841 * </PRE>
28842 *
28843 * @param dstIndex the destination index register
28844 * @param dstScale the destination shift amount
28845 * @param dstDisp the destination displacement
28846 * @param srcReg must always be ECX
28847 */
28848 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
28849 public final void emitSAL_RegOff_Reg_Quad(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
28850 int miStart = mi;
28851 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
28852 // no size prefix
28853 generateREXprefix(true, null, dstIndex, null);
28854 setMachineCodes(mi++, (byte) 0xD3);
28855 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
28856 if (lister != null) lister.RFDR(miStart, "SAL", dstIndex, dstScale, dstDisp, srcReg);
28857 }
28858
28859 /**
28860 * Generate an absolute--register SAL. That is,
28861 * <PRE>
28862 * arithemetic shift left of [dstDisp] by srcReg
28863 * </PRE>
28864 *
28865 * @param dstDisp the destination displacement
28866 * @param srcReg must always be ECX
28867 */
28868 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
28869 public final void emitSAL_Abs_Reg_Quad(Address dstDisp, GPR srcReg) {
28870 int miStart = mi;
28871 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
28872 // no size prefix
28873 generateREXprefix(true, null, null, null);
28874 setMachineCodes(mi++, (byte) 0xD3);
28875 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
28876 if (lister != null) lister.RAR(miStart, "SAL", dstDisp, srcReg);
28877 }
28878
28879 /**
28880 * Generate a register-displacement--register SAL. That is,
28881 * <PRE>
28882 * arithemetic shift left of [dstBase + dstIndex<<dstScale + dstDisp] by srcReg
28883 * </PRE>
28884 *
28885 * @param dstBase the destination base register
28886 * @param dstIndex the destination index register
28887 * @param dstScale the destination shift amount
28888 * @param dstDisp the destination displacement
28889 * @param srcReg must always be ECX
28890 */
28891 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
28892 public final void emitSAL_RegIdx_Reg_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
28893 int miStart = mi;
28894 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
28895 // no size prefix
28896 generateREXprefix(true, null, dstIndex, dstBase);
28897 setMachineCodes(mi++, (byte) 0xD3);
28898 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
28899 if (lister != null) lister.RXDR(miStart, "SAL", dstBase, dstIndex, dstScale, dstDisp, srcReg);
28900 }
28901
28902 /**
28903 * Generate a register--immediate SHL. That is,
28904 * <PRE>
28905 * logical shift left of dstReg by imm
28906 * </PRE>
28907 *
28908 * @param dstReg the destination register
28909 * @param imm immediate
28910 */
28911 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
28912 public final void emitSHL_Reg_Imm_Byte(GPR dstReg, int imm) {
28913 int miStart = mi;
28914 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
28915 // no size prefix
28916 generateREXprefix(false, null, null, dstReg);
28917 if (imm == 1) {
28918 setMachineCodes(mi++, (byte) 0xD0);
28919 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
28920 } else {
28921 setMachineCodes(mi++, (byte) 0xC0);
28922 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
28923 emitImm8((byte)imm);
28924 }
28925 if (lister != null) lister.RI(miStart, "SHL", dstReg, imm);
28926 }
28927
28928 /**
28929 * Generate a register-indirect--immediate SHL. That is,
28930 * <PRE>
28931 * logical shift left of [dstBase] by imm
28932 * </PRE>
28933 *
28934 * @param dstBase the destination base register
28935 * @param imm immediate
28936 */
28937 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
28938 public final void emitSHL_RegInd_Imm_Byte(GPR dstBase, int imm) {
28939 int miStart = mi;
28940 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
28941 // no size prefix
28942 generateREXprefix(false, null, null, dstBase);
28943 if (imm == 1) {
28944 setMachineCodes(mi++, (byte) 0xD0);
28945 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
28946 } else {
28947 setMachineCodes(mi++, (byte) 0xC0);
28948 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
28949 emitImm8((byte)imm);
28950 }
28951 if (lister != null) lister.RNI(miStart, "SHL", dstBase, imm);
28952 }
28953
28954 /**
28955 * Generate a register-displacement--immediate SHL. That is,
28956 * <PRE>
28957 * logical shift left of [dstBase + dstDisp] by imm
28958 * </PRE>
28959 *
28960 * @param dstBase the destination base register
28961 * @param dstDisp the destination displacement
28962 * @param imm immediate
28963 */
28964 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
28965 public final void emitSHL_RegDisp_Imm_Byte(GPR dstBase, Offset dstDisp, int imm) {
28966 int miStart = mi;
28967 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
28968 // no size prefix
28969 generateREXprefix(false, null, null, dstBase);
28970 if (imm == 1) {
28971 setMachineCodes(mi++, (byte) 0xD0);
28972 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
28973 } else {
28974 setMachineCodes(mi++, (byte) 0xC0);
28975 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
28976 emitImm8((byte)imm);
28977 }
28978 if (lister != null) lister.RDI(miStart, "SHL", dstBase, dstDisp, imm);
28979 }
28980
28981 /**
28982 * Generate a register-offset--immediate SHL. That is,
28983 * <PRE>
28984 * logical shift left of [dstIndex<<dstScale + dstDisp] by imm
28985 * </PRE>
28986 *
28987 * @param dstIndex the destination index register
28988 * @param dstScale the destination shift amount
28989 * @param dstDisp the destination displacement
28990 * @param imm immediate
28991 */
28992 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
28993 public final void emitSHL_RegOff_Imm_Byte(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
28994 int miStart = mi;
28995 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
28996 // no size prefix
28997 generateREXprefix(false, null, dstIndex, null);
28998 if (imm == 1) {
28999 setMachineCodes(mi++, (byte) 0xD0);
29000 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
29001 } else {
29002 setMachineCodes(mi++, (byte) 0xC0);
29003 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
29004 emitImm8((byte)imm);
29005 }
29006 if (lister != null) lister.RFDI(miStart, "SHL", dstIndex, dstScale, dstDisp, imm);
29007 }
29008
29009 /**
29010 * Generate a absolute--immediate SHL. That is,
29011 * <PRE>
29012 * logical shift left of [dstDisp] by imm
29013 * </PRE>
29014 *
29015 * @param dstDisp the destination displacement
29016 * @param imm immediate
29017 */
29018 public final void emitSHL_Abs_Imm_Byte(Address dstDisp, int imm) {
29019 int miStart = mi;
29020 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
29021 // no size prefix
29022 generateREXprefix(false, null, null, null);
29023 if (imm == 1) {
29024 setMachineCodes(mi++, (byte) 0xD0);
29025 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
29026 } else {
29027 setMachineCodes(mi++, (byte) 0xC0);
29028 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
29029 emitImm8((byte)imm);
29030 }
29031 if (lister != null) lister.RAI(miStart, "SHL", dstDisp, imm);
29032 }
29033
29034 /**
29035 * Generate a register-index--immediate SHL. That is,
29036 * <PRE>
29037 * logical shift left of [dstBase + dstIndex<<dstScale + dstDisp] by imm
29038 * </PRE>
29039 *
29040 * @param dstBase the destination base register
29041 * @param dstIndex the destination index register
29042 * @param dstScale the destination shift amount
29043 * @param dstDisp the destination displacement
29044 * @param imm immediate
29045 */
29046 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
29047 public final void emitSHL_RegIdx_Imm_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
29048 int miStart = mi;
29049 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
29050 // no size prefix
29051 generateREXprefix(false, null, dstIndex, dstBase);
29052 if (imm == 1) {
29053 setMachineCodes(mi++, (byte) 0xD0);
29054 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
29055 } else {
29056 setMachineCodes(mi++, (byte) 0xC0);
29057 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
29058 emitImm8((byte)imm);
29059 }
29060 if (lister != null) lister.RXDI(miStart, "SHL", dstBase, dstIndex, dstScale, dstDisp, imm);
29061 }
29062
29063 /**
29064 * Generate a register--register SHL. That is,
29065 * <PRE>
29066 * logical shift left of dstReg by srcReg
29067 * </PRE>
29068 *
29069 * @param dstReg the destination register
29070 * @param srcReg must always be ECX
29071 */
29072 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
29073 public final void emitSHL_Reg_Reg_Byte(GPR dstReg, GPR srcReg) {
29074 int miStart = mi;
29075 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
29076 // no size prefix
29077 generateREXprefix(false, null, null, dstReg);
29078 setMachineCodes(mi++, (byte) 0xD2);
29079 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
29080 if (lister != null) lister.RR(miStart, "SHL", dstReg, srcReg);
29081 }
29082
29083 /**
29084 * Generate a register-indirect--register SHL. That is,
29085 * <PRE>
29086 * logical shift left of [dstBase] by srcReg
29087 * </PRE>
29088 *
29089 * @param dstBase the destination register
29090 * @param srcReg must always be ECX
29091 */
29092 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
29093 public final void emitSHL_RegInd_Reg_Byte(GPR dstBase, GPR srcReg) {
29094 int miStart = mi;
29095 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
29096 // no size prefix
29097 generateREXprefix(false, null, null, dstBase);
29098 setMachineCodes(mi++, (byte) 0xD2);
29099 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
29100 if (lister != null) lister.RNR(miStart, "SHL", dstBase, srcReg);
29101 }
29102
29103 /**
29104 * Generate a register-displacement--register SHL. That is,
29105 * <PRE>
29106 * logical shift left of [dstBase + dstDisp] by srcReg
29107 * </PRE>
29108 *
29109 * @param dstBase the destination base register
29110 * @param dstDisp the destination displacement
29111 * @param srcReg must always be ECX
29112 */
29113 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
29114 public final void emitSHL_RegDisp_Reg_Byte(GPR dstBase, Offset dstDisp, GPR srcReg) {
29115 int miStart = mi;
29116 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
29117 // no size prefix
29118 generateREXprefix(false, null, null, dstBase);
29119 setMachineCodes(mi++, (byte) 0xD2);
29120 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
29121 if (lister != null) lister.RDR(miStart, "SHL", dstBase, dstDisp, srcReg);
29122 }
29123
29124 /**
29125 * Generate a register-offset--register SHL. That is,
29126 * <PRE>
29127 * logical shift left of [dstIndex<<dstScale + dstDisp] by srcReg
29128 * </PRE>
29129 *
29130 * @param dstIndex the destination index register
29131 * @param dstScale the destination shift amount
29132 * @param dstDisp the destination displacement
29133 * @param srcReg must always be ECX
29134 */
29135 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
29136 public final void emitSHL_RegOff_Reg_Byte(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
29137 int miStart = mi;
29138 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
29139 // no size prefix
29140 generateREXprefix(false, null, dstIndex, null);
29141 setMachineCodes(mi++, (byte) 0xD2);
29142 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
29143 if (lister != null) lister.RFDR(miStart, "SHL", dstIndex, dstScale, dstDisp, srcReg);
29144 }
29145
29146 /**
29147 * Generate an absolute--register SHL. That is,
29148 * <PRE>
29149 * logical shift left of [dstDisp] by srcReg
29150 * </PRE>
29151 *
29152 * @param dstDisp the destination displacement
29153 * @param srcReg must always be ECX
29154 */
29155 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
29156 public final void emitSHL_Abs_Reg_Byte(Address dstDisp, GPR srcReg) {
29157 int miStart = mi;
29158 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
29159 // no size prefix
29160 generateREXprefix(false, null, null, null);
29161 setMachineCodes(mi++, (byte) 0xD2);
29162 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
29163 if (lister != null) lister.RAR(miStart, "SHL", dstDisp, srcReg);
29164 }
29165
29166 /**
29167 * Generate a register-displacement--register SHL. That is,
29168 * <PRE>
29169 * logical shift left of [dstBase + dstIndex<<dstScale + dstDisp] by srcReg
29170 * </PRE>
29171 *
29172 * @param dstBase the destination base register
29173 * @param dstIndex the destination index register
29174 * @param dstScale the destination shift amount
29175 * @param dstDisp the destination displacement
29176 * @param srcReg must always be ECX
29177 */
29178 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
29179 public final void emitSHL_RegIdx_Reg_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
29180 int miStart = mi;
29181 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
29182 // no size prefix
29183 generateREXprefix(false, null, dstIndex, dstBase);
29184 setMachineCodes(mi++, (byte) 0xD2);
29185 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
29186 if (lister != null) lister.RXDR(miStart, "SHL", dstBase, dstIndex, dstScale, dstDisp, srcReg);
29187 }
29188
29189 /**
29190 * Generate a register--immediate SHL. That is,
29191 * <PRE>
29192 * logical shift left of dstReg by imm
29193 * </PRE>
29194 *
29195 * @param dstReg the destination register
29196 * @param imm immediate
29197 */
29198 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
29199 public final void emitSHL_Reg_Imm_Word(GPR dstReg, int imm) {
29200 int miStart = mi;
29201 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
29202 setMachineCodes(mi++, (byte) 0x66);
29203 generateREXprefix(false, null, null, dstReg);
29204 if (imm == 1) {
29205 setMachineCodes(mi++, (byte) 0xD1);
29206 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
29207 } else {
29208 setMachineCodes(mi++, (byte) 0xC1);
29209 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
29210 emitImm8((byte)imm);
29211 }
29212 if (lister != null) lister.RI(miStart, "SHL", dstReg, imm);
29213 }
29214
29215 /**
29216 * Generate a register-indirect--immediate SHL. That is,
29217 * <PRE>
29218 * logical shift left of [dstBase] by imm
29219 * </PRE>
29220 *
29221 * @param dstBase the destination base register
29222 * @param imm immediate
29223 */
29224 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
29225 public final void emitSHL_RegInd_Imm_Word(GPR dstBase, int imm) {
29226 int miStart = mi;
29227 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
29228 setMachineCodes(mi++, (byte) 0x66);
29229 generateREXprefix(false, null, null, dstBase);
29230 if (imm == 1) {
29231 setMachineCodes(mi++, (byte) 0xD1);
29232 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
29233 } else {
29234 setMachineCodes(mi++, (byte) 0xC1);
29235 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
29236 emitImm8((byte)imm);
29237 }
29238 if (lister != null) lister.RNI(miStart, "SHL", dstBase, imm);
29239 }
29240
29241 /**
29242 * Generate a register-displacement--immediate SHL. That is,
29243 * <PRE>
29244 * logical shift left of [dstBase + dstDisp] by imm
29245 * </PRE>
29246 *
29247 * @param dstBase the destination base register
29248 * @param dstDisp the destination displacement
29249 * @param imm immediate
29250 */
29251 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
29252 public final void emitSHL_RegDisp_Imm_Word(GPR dstBase, Offset dstDisp, int imm) {
29253 int miStart = mi;
29254 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
29255 setMachineCodes(mi++, (byte) 0x66);
29256 generateREXprefix(false, null, null, dstBase);
29257 if (imm == 1) {
29258 setMachineCodes(mi++, (byte) 0xD1);
29259 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
29260 } else {
29261 setMachineCodes(mi++, (byte) 0xC1);
29262 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
29263 emitImm8((byte)imm);
29264 }
29265 if (lister != null) lister.RDI(miStart, "SHL", dstBase, dstDisp, imm);
29266 }
29267
29268 /**
29269 * Generate a register-offset--immediate SHL. That is,
29270 * <PRE>
29271 * logical shift left of [dstIndex<<dstScale + dstDisp] by imm
29272 * </PRE>
29273 *
29274 * @param dstIndex the destination index register
29275 * @param dstScale the destination shift amount
29276 * @param dstDisp the destination displacement
29277 * @param imm immediate
29278 */
29279 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
29280 public final void emitSHL_RegOff_Imm_Word(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
29281 int miStart = mi;
29282 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
29283 setMachineCodes(mi++, (byte) 0x66);
29284 generateREXprefix(false, null, dstIndex, null);
29285 if (imm == 1) {
29286 setMachineCodes(mi++, (byte) 0xD1);
29287 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
29288 } else {
29289 setMachineCodes(mi++, (byte) 0xC1);
29290 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
29291 emitImm8((byte)imm);
29292 }
29293 if (lister != null) lister.RFDI(miStart, "SHL", dstIndex, dstScale, dstDisp, imm);
29294 }
29295
29296 /**
29297 * Generate a absolute--immediate SHL. That is,
29298 * <PRE>
29299 * logical shift left of [dstDisp] by imm
29300 * </PRE>
29301 *
29302 * @param dstDisp the destination displacement
29303 * @param imm immediate
29304 */
29305 public final void emitSHL_Abs_Imm_Word(Address dstDisp, int imm) {
29306 int miStart = mi;
29307 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
29308 setMachineCodes(mi++, (byte) 0x66);
29309 generateREXprefix(false, null, null, null);
29310 if (imm == 1) {
29311 setMachineCodes(mi++, (byte) 0xD1);
29312 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
29313 } else {
29314 setMachineCodes(mi++, (byte) 0xC1);
29315 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
29316 emitImm8((byte)imm);
29317 }
29318 if (lister != null) lister.RAI(miStart, "SHL", dstDisp, imm);
29319 }
29320
29321 /**
29322 * Generate a register-index--immediate SHL. That is,
29323 * <PRE>
29324 * logical shift left of [dstBase + dstIndex<<dstScale + dstDisp] by imm
29325 * </PRE>
29326 *
29327 * @param dstBase the destination base register
29328 * @param dstIndex the destination index register
29329 * @param dstScale the destination shift amount
29330 * @param dstDisp the destination displacement
29331 * @param imm immediate
29332 */
29333 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
29334 public final void emitSHL_RegIdx_Imm_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
29335 int miStart = mi;
29336 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
29337 setMachineCodes(mi++, (byte) 0x66);
29338 generateREXprefix(false, null, dstIndex, dstBase);
29339 if (imm == 1) {
29340 setMachineCodes(mi++, (byte) 0xD1);
29341 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
29342 } else {
29343 setMachineCodes(mi++, (byte) 0xC1);
29344 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
29345 emitImm8((byte)imm);
29346 }
29347 if (lister != null) lister.RXDI(miStart, "SHL", dstBase, dstIndex, dstScale, dstDisp, imm);
29348 }
29349
29350 /**
29351 * Generate a register--register SHL. That is,
29352 * <PRE>
29353 * logical shift left of dstReg by srcReg
29354 * </PRE>
29355 *
29356 * @param dstReg the destination register
29357 * @param srcReg must always be ECX
29358 */
29359 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
29360 public final void emitSHL_Reg_Reg_Word(GPR dstReg, GPR srcReg) {
29361 int miStart = mi;
29362 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
29363 setMachineCodes(mi++, (byte) 0x66);
29364 generateREXprefix(false, null, null, dstReg);
29365 setMachineCodes(mi++, (byte) 0xD3);
29366 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
29367 if (lister != null) lister.RR(miStart, "SHL", dstReg, srcReg);
29368 }
29369
29370 /**
29371 * Generate a register-indirect--register SHL. That is,
29372 * <PRE>
29373 * logical shift left of [dstBase] by srcReg
29374 * </PRE>
29375 *
29376 * @param dstBase the destination register
29377 * @param srcReg must always be ECX
29378 */
29379 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
29380 public final void emitSHL_RegInd_Reg_Word(GPR dstBase, GPR srcReg) {
29381 int miStart = mi;
29382 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
29383 setMachineCodes(mi++, (byte) 0x66);
29384 generateREXprefix(false, null, null, dstBase);
29385 setMachineCodes(mi++, (byte) 0xD3);
29386 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
29387 if (lister != null) lister.RNR(miStart, "SHL", dstBase, srcReg);
29388 }
29389
29390 /**
29391 * Generate a register-displacement--register SHL. That is,
29392 * <PRE>
29393 * logical shift left of [dstBase + dstDisp] by srcReg
29394 * </PRE>
29395 *
29396 * @param dstBase the destination base register
29397 * @param dstDisp the destination displacement
29398 * @param srcReg must always be ECX
29399 */
29400 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
29401 public final void emitSHL_RegDisp_Reg_Word(GPR dstBase, Offset dstDisp, GPR srcReg) {
29402 int miStart = mi;
29403 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
29404 setMachineCodes(mi++, (byte) 0x66);
29405 generateREXprefix(false, null, null, dstBase);
29406 setMachineCodes(mi++, (byte) 0xD3);
29407 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
29408 if (lister != null) lister.RDR(miStart, "SHL", dstBase, dstDisp, srcReg);
29409 }
29410
29411 /**
29412 * Generate a register-offset--register SHL. That is,
29413 * <PRE>
29414 * logical shift left of [dstIndex<<dstScale + dstDisp] by srcReg
29415 * </PRE>
29416 *
29417 * @param dstIndex the destination index register
29418 * @param dstScale the destination shift amount
29419 * @param dstDisp the destination displacement
29420 * @param srcReg must always be ECX
29421 */
29422 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
29423 public final void emitSHL_RegOff_Reg_Word(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
29424 int miStart = mi;
29425 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
29426 setMachineCodes(mi++, (byte) 0x66);
29427 generateREXprefix(false, null, dstIndex, null);
29428 setMachineCodes(mi++, (byte) 0xD3);
29429 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
29430 if (lister != null) lister.RFDR(miStart, "SHL", dstIndex, dstScale, dstDisp, srcReg);
29431 }
29432
29433 /**
29434 * Generate an absolute--register SHL. That is,
29435 * <PRE>
29436 * logical shift left of [dstDisp] by srcReg
29437 * </PRE>
29438 *
29439 * @param dstDisp the destination displacement
29440 * @param srcReg must always be ECX
29441 */
29442 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
29443 public final void emitSHL_Abs_Reg_Word(Address dstDisp, GPR srcReg) {
29444 int miStart = mi;
29445 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
29446 setMachineCodes(mi++, (byte) 0x66);
29447 generateREXprefix(false, null, null, null);
29448 setMachineCodes(mi++, (byte) 0xD3);
29449 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
29450 if (lister != null) lister.RAR(miStart, "SHL", dstDisp, srcReg);
29451 }
29452
29453 /**
29454 * Generate a register-displacement--register SHL. That is,
29455 * <PRE>
29456 * logical shift left of [dstBase + dstIndex<<dstScale + dstDisp] by srcReg
29457 * </PRE>
29458 *
29459 * @param dstBase the destination base register
29460 * @param dstIndex the destination index register
29461 * @param dstScale the destination shift amount
29462 * @param dstDisp the destination displacement
29463 * @param srcReg must always be ECX
29464 */
29465 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
29466 public final void emitSHL_RegIdx_Reg_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
29467 int miStart = mi;
29468 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
29469 setMachineCodes(mi++, (byte) 0x66);
29470 generateREXprefix(false, null, dstIndex, dstBase);
29471 setMachineCodes(mi++, (byte) 0xD3);
29472 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
29473 if (lister != null) lister.RXDR(miStart, "SHL", dstBase, dstIndex, dstScale, dstDisp, srcReg);
29474 }
29475
29476 /**
29477 * Generate a register--immediate SHL. That is,
29478 * <PRE>
29479 * logical shift left of dstReg by imm
29480 * </PRE>
29481 *
29482 * @param dstReg the destination register
29483 * @param imm immediate
29484 */
29485 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
29486 public final void emitSHL_Reg_Imm(GPR dstReg, int imm) {
29487 int miStart = mi;
29488 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
29489 // no size prefix
29490 generateREXprefix(false, null, null, dstReg);
29491 if (imm == 1) {
29492 setMachineCodes(mi++, (byte) 0xD1);
29493 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
29494 } else {
29495 setMachineCodes(mi++, (byte) 0xC1);
29496 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
29497 emitImm8((byte)imm);
29498 }
29499 if (lister != null) lister.RI(miStart, "SHL", dstReg, imm);
29500 }
29501
29502 /**
29503 * Generate a register-indirect--immediate SHL. That is,
29504 * <PRE>
29505 * logical shift left of [dstBase] by imm
29506 * </PRE>
29507 *
29508 * @param dstBase the destination base register
29509 * @param imm immediate
29510 */
29511 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
29512 public final void emitSHL_RegInd_Imm(GPR dstBase, int imm) {
29513 int miStart = mi;
29514 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
29515 // no size prefix
29516 generateREXprefix(false, null, null, dstBase);
29517 if (imm == 1) {
29518 setMachineCodes(mi++, (byte) 0xD1);
29519 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
29520 } else {
29521 setMachineCodes(mi++, (byte) 0xC1);
29522 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
29523 emitImm8((byte)imm);
29524 }
29525 if (lister != null) lister.RNI(miStart, "SHL", dstBase, imm);
29526 }
29527
29528 /**
29529 * Generate a register-displacement--immediate SHL. That is,
29530 * <PRE>
29531 * logical shift left of [dstBase + dstDisp] by imm
29532 * </PRE>
29533 *
29534 * @param dstBase the destination base register
29535 * @param dstDisp the destination displacement
29536 * @param imm immediate
29537 */
29538 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
29539 public final void emitSHL_RegDisp_Imm(GPR dstBase, Offset dstDisp, int imm) {
29540 int miStart = mi;
29541 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
29542 // no size prefix
29543 generateREXprefix(false, null, null, dstBase);
29544 if (imm == 1) {
29545 setMachineCodes(mi++, (byte) 0xD1);
29546 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
29547 } else {
29548 setMachineCodes(mi++, (byte) 0xC1);
29549 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
29550 emitImm8((byte)imm);
29551 }
29552 if (lister != null) lister.RDI(miStart, "SHL", dstBase, dstDisp, imm);
29553 }
29554
29555 /**
29556 * Generate a register-offset--immediate SHL. That is,
29557 * <PRE>
29558 * logical shift left of [dstIndex<<dstScale + dstDisp] by imm
29559 * </PRE>
29560 *
29561 * @param dstIndex the destination index register
29562 * @param dstScale the destination shift amount
29563 * @param dstDisp the destination displacement
29564 * @param imm immediate
29565 */
29566 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
29567 public final void emitSHL_RegOff_Imm(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
29568 int miStart = mi;
29569 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
29570 // no size prefix
29571 generateREXprefix(false, null, dstIndex, null);
29572 if (imm == 1) {
29573 setMachineCodes(mi++, (byte) 0xD1);
29574 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
29575 } else {
29576 setMachineCodes(mi++, (byte) 0xC1);
29577 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
29578 emitImm8((byte)imm);
29579 }
29580 if (lister != null) lister.RFDI(miStart, "SHL", dstIndex, dstScale, dstDisp, imm);
29581 }
29582
29583 /**
29584 * Generate a absolute--immediate SHL. That is,
29585 * <PRE>
29586 * logical shift left of [dstDisp] by imm
29587 * </PRE>
29588 *
29589 * @param dstDisp the destination displacement
29590 * @param imm immediate
29591 */
29592 public final void emitSHL_Abs_Imm(Address dstDisp, int imm) {
29593 int miStart = mi;
29594 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
29595 // no size prefix
29596 generateREXprefix(false, null, null, null);
29597 if (imm == 1) {
29598 setMachineCodes(mi++, (byte) 0xD1);
29599 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
29600 } else {
29601 setMachineCodes(mi++, (byte) 0xC1);
29602 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
29603 emitImm8((byte)imm);
29604 }
29605 if (lister != null) lister.RAI(miStart, "SHL", dstDisp, imm);
29606 }
29607
29608 /**
29609 * Generate a register-index--immediate SHL. That is,
29610 * <PRE>
29611 * logical shift left of [dstBase + dstIndex<<dstScale + dstDisp] by imm
29612 * </PRE>
29613 *
29614 * @param dstBase the destination base register
29615 * @param dstIndex the destination index register
29616 * @param dstScale the destination shift amount
29617 * @param dstDisp the destination displacement
29618 * @param imm immediate
29619 */
29620 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
29621 public final void emitSHL_RegIdx_Imm(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
29622 int miStart = mi;
29623 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
29624 // no size prefix
29625 generateREXprefix(false, null, dstIndex, dstBase);
29626 if (imm == 1) {
29627 setMachineCodes(mi++, (byte) 0xD1);
29628 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
29629 } else {
29630 setMachineCodes(mi++, (byte) 0xC1);
29631 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
29632 emitImm8((byte)imm);
29633 }
29634 if (lister != null) lister.RXDI(miStart, "SHL", dstBase, dstIndex, dstScale, dstDisp, imm);
29635 }
29636
29637 /**
29638 * Generate a register--register SHL. That is,
29639 * <PRE>
29640 * logical shift left of dstReg by srcReg
29641 * </PRE>
29642 *
29643 * @param dstReg the destination register
29644 * @param srcReg must always be ECX
29645 */
29646 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
29647 public final void emitSHL_Reg_Reg(GPR dstReg, GPR srcReg) {
29648 int miStart = mi;
29649 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
29650 // no size prefix
29651 generateREXprefix(false, null, null, dstReg);
29652 setMachineCodes(mi++, (byte) 0xD3);
29653 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
29654 if (lister != null) lister.RR(miStart, "SHL", dstReg, srcReg);
29655 }
29656
29657 /**
29658 * Generate a register-indirect--register SHL. That is,
29659 * <PRE>
29660 * logical shift left of [dstBase] by srcReg
29661 * </PRE>
29662 *
29663 * @param dstBase the destination register
29664 * @param srcReg must always be ECX
29665 */
29666 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
29667 public final void emitSHL_RegInd_Reg(GPR dstBase, GPR srcReg) {
29668 int miStart = mi;
29669 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
29670 // no size prefix
29671 generateREXprefix(false, null, null, dstBase);
29672 setMachineCodes(mi++, (byte) 0xD3);
29673 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
29674 if (lister != null) lister.RNR(miStart, "SHL", dstBase, srcReg);
29675 }
29676
29677 /**
29678 * Generate a register-displacement--register SHL. That is,
29679 * <PRE>
29680 * logical shift left of [dstBase + dstDisp] by srcReg
29681 * </PRE>
29682 *
29683 * @param dstBase the destination base register
29684 * @param dstDisp the destination displacement
29685 * @param srcReg must always be ECX
29686 */
29687 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
29688 public final void emitSHL_RegDisp_Reg(GPR dstBase, Offset dstDisp, GPR srcReg) {
29689 int miStart = mi;
29690 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
29691 // no size prefix
29692 generateREXprefix(false, null, null, dstBase);
29693 setMachineCodes(mi++, (byte) 0xD3);
29694 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
29695 if (lister != null) lister.RDR(miStart, "SHL", dstBase, dstDisp, srcReg);
29696 }
29697
29698 /**
29699 * Generate a register-offset--register SHL. That is,
29700 * <PRE>
29701 * logical shift left of [dstIndex<<dstScale + dstDisp] by srcReg
29702 * </PRE>
29703 *
29704 * @param dstIndex the destination index register
29705 * @param dstScale the destination shift amount
29706 * @param dstDisp the destination displacement
29707 * @param srcReg must always be ECX
29708 */
29709 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
29710 public final void emitSHL_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
29711 int miStart = mi;
29712 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
29713 // no size prefix
29714 generateREXprefix(false, null, dstIndex, null);
29715 setMachineCodes(mi++, (byte) 0xD3);
29716 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
29717 if (lister != null) lister.RFDR(miStart, "SHL", dstIndex, dstScale, dstDisp, srcReg);
29718 }
29719
29720 /**
29721 * Generate an absolute--register SHL. That is,
29722 * <PRE>
29723 * logical shift left of [dstDisp] by srcReg
29724 * </PRE>
29725 *
29726 * @param dstDisp the destination displacement
29727 * @param srcReg must always be ECX
29728 */
29729 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
29730 public final void emitSHL_Abs_Reg(Address dstDisp, GPR srcReg) {
29731 int miStart = mi;
29732 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
29733 // no size prefix
29734 generateREXprefix(false, null, null, null);
29735 setMachineCodes(mi++, (byte) 0xD3);
29736 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
29737 if (lister != null) lister.RAR(miStart, "SHL", dstDisp, srcReg);
29738 }
29739
29740 /**
29741 * Generate a register-displacement--register SHL. That is,
29742 * <PRE>
29743 * logical shift left of [dstBase + dstIndex<<dstScale + dstDisp] by srcReg
29744 * </PRE>
29745 *
29746 * @param dstBase the destination base register
29747 * @param dstIndex the destination index register
29748 * @param dstScale the destination shift amount
29749 * @param dstDisp the destination displacement
29750 * @param srcReg must always be ECX
29751 */
29752 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
29753 public final void emitSHL_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
29754 int miStart = mi;
29755 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
29756 // no size prefix
29757 generateREXprefix(false, null, dstIndex, dstBase);
29758 setMachineCodes(mi++, (byte) 0xD3);
29759 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
29760 if (lister != null) lister.RXDR(miStart, "SHL", dstBase, dstIndex, dstScale, dstDisp, srcReg);
29761 }
29762
29763 /**
29764 * Generate a register--immediate SHL. That is,
29765 * <PRE>
29766 * logical shift left of dstReg by imm
29767 * </PRE>
29768 *
29769 * @param dstReg the destination register
29770 * @param imm immediate
29771 */
29772 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
29773 public final void emitSHL_Reg_Imm_Quad(GPR dstReg, int imm) {
29774 int miStart = mi;
29775 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
29776 // no size prefix
29777 generateREXprefix(true, null, null, dstReg);
29778 if (imm == 1) {
29779 setMachineCodes(mi++, (byte) 0xD1);
29780 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
29781 } else {
29782 setMachineCodes(mi++, (byte) 0xC1);
29783 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
29784 emitImm8((byte)imm);
29785 }
29786 if (lister != null) lister.RI(miStart, "SHL", dstReg, imm);
29787 }
29788
29789 /**
29790 * Generate a register-indirect--immediate SHL. That is,
29791 * <PRE>
29792 * logical shift left of [dstBase] by imm
29793 * </PRE>
29794 *
29795 * @param dstBase the destination base register
29796 * @param imm immediate
29797 */
29798 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
29799 public final void emitSHL_RegInd_Imm_Quad(GPR dstBase, int imm) {
29800 int miStart = mi;
29801 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
29802 // no size prefix
29803 generateREXprefix(true, null, null, dstBase);
29804 if (imm == 1) {
29805 setMachineCodes(mi++, (byte) 0xD1);
29806 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
29807 } else {
29808 setMachineCodes(mi++, (byte) 0xC1);
29809 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
29810 emitImm8((byte)imm);
29811 }
29812 if (lister != null) lister.RNI(miStart, "SHL", dstBase, imm);
29813 }
29814
29815 /**
29816 * Generate a register-displacement--immediate SHL. That is,
29817 * <PRE>
29818 * logical shift left of [dstBase + dstDisp] by imm
29819 * </PRE>
29820 *
29821 * @param dstBase the destination base register
29822 * @param dstDisp the destination displacement
29823 * @param imm immediate
29824 */
29825 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
29826 public final void emitSHL_RegDisp_Imm_Quad(GPR dstBase, Offset dstDisp, int imm) {
29827 int miStart = mi;
29828 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
29829 // no size prefix
29830 generateREXprefix(true, null, null, dstBase);
29831 if (imm == 1) {
29832 setMachineCodes(mi++, (byte) 0xD1);
29833 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
29834 } else {
29835 setMachineCodes(mi++, (byte) 0xC1);
29836 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
29837 emitImm8((byte)imm);
29838 }
29839 if (lister != null) lister.RDI(miStart, "SHL", dstBase, dstDisp, imm);
29840 }
29841
29842 /**
29843 * Generate a register-offset--immediate SHL. That is,
29844 * <PRE>
29845 * logical shift left of [dstIndex<<dstScale + dstDisp] by imm
29846 * </PRE>
29847 *
29848 * @param dstIndex the destination index register
29849 * @param dstScale the destination shift amount
29850 * @param dstDisp the destination displacement
29851 * @param imm immediate
29852 */
29853 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
29854 public final void emitSHL_RegOff_Imm_Quad(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
29855 int miStart = mi;
29856 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
29857 // no size prefix
29858 generateREXprefix(true, null, dstIndex, null);
29859 if (imm == 1) {
29860 setMachineCodes(mi++, (byte) 0xD1);
29861 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
29862 } else {
29863 setMachineCodes(mi++, (byte) 0xC1);
29864 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
29865 emitImm8((byte)imm);
29866 }
29867 if (lister != null) lister.RFDI(miStart, "SHL", dstIndex, dstScale, dstDisp, imm);
29868 }
29869
29870 /**
29871 * Generate a absolute--immediate SHL. That is,
29872 * <PRE>
29873 * logical shift left of [dstDisp] by imm
29874 * </PRE>
29875 *
29876 * @param dstDisp the destination displacement
29877 * @param imm immediate
29878 */
29879 public final void emitSHL_Abs_Imm_Quad(Address dstDisp, int imm) {
29880 int miStart = mi;
29881 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
29882 // no size prefix
29883 generateREXprefix(true, null, null, null);
29884 if (imm == 1) {
29885 setMachineCodes(mi++, (byte) 0xD1);
29886 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
29887 } else {
29888 setMachineCodes(mi++, (byte) 0xC1);
29889 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
29890 emitImm8((byte)imm);
29891 }
29892 if (lister != null) lister.RAI(miStart, "SHL", dstDisp, imm);
29893 }
29894
29895 /**
29896 * Generate a register-index--immediate SHL. That is,
29897 * <PRE>
29898 * logical shift left of [dstBase + dstIndex<<dstScale + dstDisp] by imm
29899 * </PRE>
29900 *
29901 * @param dstBase the destination base register
29902 * @param dstIndex the destination index register
29903 * @param dstScale the destination shift amount
29904 * @param dstDisp the destination displacement
29905 * @param imm immediate
29906 */
29907 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
29908 public final void emitSHL_RegIdx_Imm_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
29909 int miStart = mi;
29910 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
29911 // no size prefix
29912 generateREXprefix(true, null, dstIndex, dstBase);
29913 if (imm == 1) {
29914 setMachineCodes(mi++, (byte) 0xD1);
29915 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
29916 } else {
29917 setMachineCodes(mi++, (byte) 0xC1);
29918 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
29919 emitImm8((byte)imm);
29920 }
29921 if (lister != null) lister.RXDI(miStart, "SHL", dstBase, dstIndex, dstScale, dstDisp, imm);
29922 }
29923
29924 /**
29925 * Generate a register--register SHL. That is,
29926 * <PRE>
29927 * logical shift left of dstReg by srcReg
29928 * </PRE>
29929 *
29930 * @param dstReg the destination register
29931 * @param srcReg must always be ECX
29932 */
29933 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
29934 public final void emitSHL_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
29935 int miStart = mi;
29936 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
29937 // no size prefix
29938 generateREXprefix(true, null, null, dstReg);
29939 setMachineCodes(mi++, (byte) 0xD3);
29940 emitRegRegOperands(dstReg, GPR.getForOpcode(0x4));
29941 if (lister != null) lister.RR(miStart, "SHL", dstReg, srcReg);
29942 }
29943
29944 /**
29945 * Generate a register-indirect--register SHL. That is,
29946 * <PRE>
29947 * logical shift left of [dstBase] by srcReg
29948 * </PRE>
29949 *
29950 * @param dstBase the destination register
29951 * @param srcReg must always be ECX
29952 */
29953 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
29954 public final void emitSHL_RegInd_Reg_Quad(GPR dstBase, GPR srcReg) {
29955 int miStart = mi;
29956 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
29957 // no size prefix
29958 generateREXprefix(true, null, null, dstBase);
29959 setMachineCodes(mi++, (byte) 0xD3);
29960 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x4));
29961 if (lister != null) lister.RNR(miStart, "SHL", dstBase, srcReg);
29962 }
29963
29964 /**
29965 * Generate a register-displacement--register SHL. That is,
29966 * <PRE>
29967 * logical shift left of [dstBase + dstDisp] by srcReg
29968 * </PRE>
29969 *
29970 * @param dstBase the destination base register
29971 * @param dstDisp the destination displacement
29972 * @param srcReg must always be ECX
29973 */
29974 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
29975 public final void emitSHL_RegDisp_Reg_Quad(GPR dstBase, Offset dstDisp, GPR srcReg) {
29976 int miStart = mi;
29977 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
29978 // no size prefix
29979 generateREXprefix(true, null, null, dstBase);
29980 setMachineCodes(mi++, (byte) 0xD3);
29981 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x4));
29982 if (lister != null) lister.RDR(miStart, "SHL", dstBase, dstDisp, srcReg);
29983 }
29984
29985 /**
29986 * Generate a register-offset--register SHL. That is,
29987 * <PRE>
29988 * logical shift left of [dstIndex<<dstScale + dstDisp] by srcReg
29989 * </PRE>
29990 *
29991 * @param dstIndex the destination index register
29992 * @param dstScale the destination shift amount
29993 * @param dstDisp the destination displacement
29994 * @param srcReg must always be ECX
29995 */
29996 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
29997 public final void emitSHL_RegOff_Reg_Quad(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
29998 int miStart = mi;
29999 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
30000 // no size prefix
30001 generateREXprefix(true, null, dstIndex, null);
30002 setMachineCodes(mi++, (byte) 0xD3);
30003 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
30004 if (lister != null) lister.RFDR(miStart, "SHL", dstIndex, dstScale, dstDisp, srcReg);
30005 }
30006
30007 /**
30008 * Generate an absolute--register SHL. That is,
30009 * <PRE>
30010 * logical shift left of [dstDisp] by srcReg
30011 * </PRE>
30012 *
30013 * @param dstDisp the destination displacement
30014 * @param srcReg must always be ECX
30015 */
30016 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
30017 public final void emitSHL_Abs_Reg_Quad(Address dstDisp, GPR srcReg) {
30018 int miStart = mi;
30019 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
30020 // no size prefix
30021 generateREXprefix(true, null, null, null);
30022 setMachineCodes(mi++, (byte) 0xD3);
30023 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x4));
30024 if (lister != null) lister.RAR(miStart, "SHL", dstDisp, srcReg);
30025 }
30026
30027 /**
30028 * Generate a register-displacement--register SHL. That is,
30029 * <PRE>
30030 * logical shift left of [dstBase + dstIndex<<dstScale + dstDisp] by srcReg
30031 * </PRE>
30032 *
30033 * @param dstBase the destination base register
30034 * @param dstIndex the destination index register
30035 * @param dstScale the destination shift amount
30036 * @param dstDisp the destination displacement
30037 * @param srcReg must always be ECX
30038 */
30039 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
30040 public final void emitSHL_RegIdx_Reg_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
30041 int miStart = mi;
30042 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
30043 // no size prefix
30044 generateREXprefix(true, null, dstIndex, dstBase);
30045 setMachineCodes(mi++, (byte) 0xD3);
30046 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x4));
30047 if (lister != null) lister.RXDR(miStart, "SHL", dstBase, dstIndex, dstScale, dstDisp, srcReg);
30048 }
30049
30050 /**
30051 * Generate a register--immediate SHR. That is,
30052 * <PRE>
30053 * logical shift right of dstReg by imm
30054 * </PRE>
30055 *
30056 * @param dstReg the destination register
30057 * @param imm immediate
30058 */
30059 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
30060 public final void emitSHR_Reg_Imm_Byte(GPR dstReg, int imm) {
30061 int miStart = mi;
30062 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
30063 // no size prefix
30064 generateREXprefix(false, null, null, dstReg);
30065 if (imm == 1) {
30066 setMachineCodes(mi++, (byte) 0xD0);
30067 emitRegRegOperands(dstReg, GPR.getForOpcode(0x5));
30068 } else {
30069 setMachineCodes(mi++, (byte) 0xC0);
30070 emitRegRegOperands(dstReg, GPR.getForOpcode(0x5));
30071 emitImm8((byte)imm);
30072 }
30073 if (lister != null) lister.RI(miStart, "SHR", dstReg, imm);
30074 }
30075
30076 /**
30077 * Generate a register-indirect--immediate SHR. That is,
30078 * <PRE>
30079 * logical shift right of [dstBase] by imm
30080 * </PRE>
30081 *
30082 * @param dstBase the destination base register
30083 * @param imm immediate
30084 */
30085 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
30086 public final void emitSHR_RegInd_Imm_Byte(GPR dstBase, int imm) {
30087 int miStart = mi;
30088 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
30089 // no size prefix
30090 generateREXprefix(false, null, null, dstBase);
30091 if (imm == 1) {
30092 setMachineCodes(mi++, (byte) 0xD0);
30093 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x5));
30094 } else {
30095 setMachineCodes(mi++, (byte) 0xC0);
30096 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x5));
30097 emitImm8((byte)imm);
30098 }
30099 if (lister != null) lister.RNI(miStart, "SHR", dstBase, imm);
30100 }
30101
30102 /**
30103 * Generate a register-displacement--immediate SHR. That is,
30104 * <PRE>
30105 * logical shift right of [dstBase + dstDisp] by imm
30106 * </PRE>
30107 *
30108 * @param dstBase the destination base register
30109 * @param dstDisp the destination displacement
30110 * @param imm immediate
30111 */
30112 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
30113 public final void emitSHR_RegDisp_Imm_Byte(GPR dstBase, Offset dstDisp, int imm) {
30114 int miStart = mi;
30115 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
30116 // no size prefix
30117 generateREXprefix(false, null, null, dstBase);
30118 if (imm == 1) {
30119 setMachineCodes(mi++, (byte) 0xD0);
30120 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x5));
30121 } else {
30122 setMachineCodes(mi++, (byte) 0xC0);
30123 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x5));
30124 emitImm8((byte)imm);
30125 }
30126 if (lister != null) lister.RDI(miStart, "SHR", dstBase, dstDisp, imm);
30127 }
30128
30129 /**
30130 * Generate a register-offset--immediate SHR. That is,
30131 * <PRE>
30132 * logical shift right of [dstIndex<<dstScale + dstDisp] by imm
30133 * </PRE>
30134 *
30135 * @param dstIndex the destination index register
30136 * @param dstScale the destination shift amount
30137 * @param dstDisp the destination displacement
30138 * @param imm immediate
30139 */
30140 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
30141 public final void emitSHR_RegOff_Imm_Byte(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
30142 int miStart = mi;
30143 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
30144 // no size prefix
30145 generateREXprefix(false, null, dstIndex, null);
30146 if (imm == 1) {
30147 setMachineCodes(mi++, (byte) 0xD0);
30148 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
30149 } else {
30150 setMachineCodes(mi++, (byte) 0xC0);
30151 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
30152 emitImm8((byte)imm);
30153 }
30154 if (lister != null) lister.RFDI(miStart, "SHR", dstIndex, dstScale, dstDisp, imm);
30155 }
30156
30157 /**
30158 * Generate a absolute--immediate SHR. That is,
30159 * <PRE>
30160 * logical shift right of [dstDisp] by imm
30161 * </PRE>
30162 *
30163 * @param dstDisp the destination displacement
30164 * @param imm immediate
30165 */
30166 public final void emitSHR_Abs_Imm_Byte(Address dstDisp, int imm) {
30167 int miStart = mi;
30168 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
30169 // no size prefix
30170 generateREXprefix(false, null, null, null);
30171 if (imm == 1) {
30172 setMachineCodes(mi++, (byte) 0xD0);
30173 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x5));
30174 } else {
30175 setMachineCodes(mi++, (byte) 0xC0);
30176 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x5));
30177 emitImm8((byte)imm);
30178 }
30179 if (lister != null) lister.RAI(miStart, "SHR", dstDisp, imm);
30180 }
30181
30182 /**
30183 * Generate a register-index--immediate SHR. That is,
30184 * <PRE>
30185 * logical shift right of [dstBase + dstIndex<<dstScale + dstDisp] by imm
30186 * </PRE>
30187 *
30188 * @param dstBase the destination base register
30189 * @param dstIndex the destination index register
30190 * @param dstScale the destination shift amount
30191 * @param dstDisp the destination displacement
30192 * @param imm immediate
30193 */
30194 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
30195 public final void emitSHR_RegIdx_Imm_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
30196 int miStart = mi;
30197 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
30198 // no size prefix
30199 generateREXprefix(false, null, dstIndex, dstBase);
30200 if (imm == 1) {
30201 setMachineCodes(mi++, (byte) 0xD0);
30202 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
30203 } else {
30204 setMachineCodes(mi++, (byte) 0xC0);
30205 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
30206 emitImm8((byte)imm);
30207 }
30208 if (lister != null) lister.RXDI(miStart, "SHR", dstBase, dstIndex, dstScale, dstDisp, imm);
30209 }
30210
30211 /**
30212 * Generate a register--register SHR. That is,
30213 * <PRE>
30214 * logical shift right of dstReg by srcReg
30215 * </PRE>
30216 *
30217 * @param dstReg the destination register
30218 * @param srcReg must always be ECX
30219 */
30220 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
30221 public final void emitSHR_Reg_Reg_Byte(GPR dstReg, GPR srcReg) {
30222 int miStart = mi;
30223 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
30224 // no size prefix
30225 generateREXprefix(false, null, null, dstReg);
30226 setMachineCodes(mi++, (byte) 0xD2);
30227 emitRegRegOperands(dstReg, GPR.getForOpcode(0x5));
30228 if (lister != null) lister.RR(miStart, "SHR", dstReg, srcReg);
30229 }
30230
30231 /**
30232 * Generate a register-indirect--register SHR. That is,
30233 * <PRE>
30234 * logical shift right of [dstBase] by srcReg
30235 * </PRE>
30236 *
30237 * @param dstBase the destination register
30238 * @param srcReg must always be ECX
30239 */
30240 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
30241 public final void emitSHR_RegInd_Reg_Byte(GPR dstBase, GPR srcReg) {
30242 int miStart = mi;
30243 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
30244 // no size prefix
30245 generateREXprefix(false, null, null, dstBase);
30246 setMachineCodes(mi++, (byte) 0xD2);
30247 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x5));
30248 if (lister != null) lister.RNR(miStart, "SHR", dstBase, srcReg);
30249 }
30250
30251 /**
30252 * Generate a register-displacement--register SHR. That is,
30253 * <PRE>
30254 * logical shift right of [dstBase + dstDisp] by srcReg
30255 * </PRE>
30256 *
30257 * @param dstBase the destination base register
30258 * @param dstDisp the destination displacement
30259 * @param srcReg must always be ECX
30260 */
30261 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
30262 public final void emitSHR_RegDisp_Reg_Byte(GPR dstBase, Offset dstDisp, GPR srcReg) {
30263 int miStart = mi;
30264 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
30265 // no size prefix
30266 generateREXprefix(false, null, null, dstBase);
30267 setMachineCodes(mi++, (byte) 0xD2);
30268 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x5));
30269 if (lister != null) lister.RDR(miStart, "SHR", dstBase, dstDisp, srcReg);
30270 }
30271
30272 /**
30273 * Generate a register-offset--register SHR. That is,
30274 * <PRE>
30275 * logical shift right of [dstIndex<<dstScale + dstDisp] by srcReg
30276 * </PRE>
30277 *
30278 * @param dstIndex the destination index register
30279 * @param dstScale the destination shift amount
30280 * @param dstDisp the destination displacement
30281 * @param srcReg must always be ECX
30282 */
30283 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
30284 public final void emitSHR_RegOff_Reg_Byte(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
30285 int miStart = mi;
30286 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
30287 // no size prefix
30288 generateREXprefix(false, null, dstIndex, null);
30289 setMachineCodes(mi++, (byte) 0xD2);
30290 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
30291 if (lister != null) lister.RFDR(miStart, "SHR", dstIndex, dstScale, dstDisp, srcReg);
30292 }
30293
30294 /**
30295 * Generate an absolute--register SHR. That is,
30296 * <PRE>
30297 * logical shift right of [dstDisp] by srcReg
30298 * </PRE>
30299 *
30300 * @param dstDisp the destination displacement
30301 * @param srcReg must always be ECX
30302 */
30303 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
30304 public final void emitSHR_Abs_Reg_Byte(Address dstDisp, GPR srcReg) {
30305 int miStart = mi;
30306 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
30307 // no size prefix
30308 generateREXprefix(false, null, null, null);
30309 setMachineCodes(mi++, (byte) 0xD2);
30310 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x5));
30311 if (lister != null) lister.RAR(miStart, "SHR", dstDisp, srcReg);
30312 }
30313
30314 /**
30315 * Generate a register-displacement--register SHR. That is,
30316 * <PRE>
30317 * logical shift right of [dstBase + dstIndex<<dstScale + dstDisp] by srcReg
30318 * </PRE>
30319 *
30320 * @param dstBase the destination base register
30321 * @param dstIndex the destination index register
30322 * @param dstScale the destination shift amount
30323 * @param dstDisp the destination displacement
30324 * @param srcReg must always be ECX
30325 */
30326 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
30327 public final void emitSHR_RegIdx_Reg_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
30328 int miStart = mi;
30329 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
30330 // no size prefix
30331 generateREXprefix(false, null, dstIndex, dstBase);
30332 setMachineCodes(mi++, (byte) 0xD2);
30333 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
30334 if (lister != null) lister.RXDR(miStart, "SHR", dstBase, dstIndex, dstScale, dstDisp, srcReg);
30335 }
30336
30337 /**
30338 * Generate a register--immediate SHR. That is,
30339 * <PRE>
30340 * logical shift right of dstReg by imm
30341 * </PRE>
30342 *
30343 * @param dstReg the destination register
30344 * @param imm immediate
30345 */
30346 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
30347 public final void emitSHR_Reg_Imm_Word(GPR dstReg, int imm) {
30348 int miStart = mi;
30349 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
30350 setMachineCodes(mi++, (byte) 0x66);
30351 generateREXprefix(false, null, null, dstReg);
30352 if (imm == 1) {
30353 setMachineCodes(mi++, (byte) 0xD1);
30354 emitRegRegOperands(dstReg, GPR.getForOpcode(0x5));
30355 } else {
30356 setMachineCodes(mi++, (byte) 0xC1);
30357 emitRegRegOperands(dstReg, GPR.getForOpcode(0x5));
30358 emitImm8((byte)imm);
30359 }
30360 if (lister != null) lister.RI(miStart, "SHR", dstReg, imm);
30361 }
30362
30363 /**
30364 * Generate a register-indirect--immediate SHR. That is,
30365 * <PRE>
30366 * logical shift right of [dstBase] by imm
30367 * </PRE>
30368 *
30369 * @param dstBase the destination base register
30370 * @param imm immediate
30371 */
30372 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
30373 public final void emitSHR_RegInd_Imm_Word(GPR dstBase, int imm) {
30374 int miStart = mi;
30375 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
30376 setMachineCodes(mi++, (byte) 0x66);
30377 generateREXprefix(false, null, null, dstBase);
30378 if (imm == 1) {
30379 setMachineCodes(mi++, (byte) 0xD1);
30380 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x5));
30381 } else {
30382 setMachineCodes(mi++, (byte) 0xC1);
30383 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x5));
30384 emitImm8((byte)imm);
30385 }
30386 if (lister != null) lister.RNI(miStart, "SHR", dstBase, imm);
30387 }
30388
30389 /**
30390 * Generate a register-displacement--immediate SHR. That is,
30391 * <PRE>
30392 * logical shift right of [dstBase + dstDisp] by imm
30393 * </PRE>
30394 *
30395 * @param dstBase the destination base register
30396 * @param dstDisp the destination displacement
30397 * @param imm immediate
30398 */
30399 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
30400 public final void emitSHR_RegDisp_Imm_Word(GPR dstBase, Offset dstDisp, int imm) {
30401 int miStart = mi;
30402 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
30403 setMachineCodes(mi++, (byte) 0x66);
30404 generateREXprefix(false, null, null, dstBase);
30405 if (imm == 1) {
30406 setMachineCodes(mi++, (byte) 0xD1);
30407 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x5));
30408 } else {
30409 setMachineCodes(mi++, (byte) 0xC1);
30410 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x5));
30411 emitImm8((byte)imm);
30412 }
30413 if (lister != null) lister.RDI(miStart, "SHR", dstBase, dstDisp, imm);
30414 }
30415
30416 /**
30417 * Generate a register-offset--immediate SHR. That is,
30418 * <PRE>
30419 * logical shift right of [dstIndex<<dstScale + dstDisp] by imm
30420 * </PRE>
30421 *
30422 * @param dstIndex the destination index register
30423 * @param dstScale the destination shift amount
30424 * @param dstDisp the destination displacement
30425 * @param imm immediate
30426 */
30427 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
30428 public final void emitSHR_RegOff_Imm_Word(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
30429 int miStart = mi;
30430 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
30431 setMachineCodes(mi++, (byte) 0x66);
30432 generateREXprefix(false, null, dstIndex, null);
30433 if (imm == 1) {
30434 setMachineCodes(mi++, (byte) 0xD1);
30435 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
30436 } else {
30437 setMachineCodes(mi++, (byte) 0xC1);
30438 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
30439 emitImm8((byte)imm);
30440 }
30441 if (lister != null) lister.RFDI(miStart, "SHR", dstIndex, dstScale, dstDisp, imm);
30442 }
30443
30444 /**
30445 * Generate a absolute--immediate SHR. That is,
30446 * <PRE>
30447 * logical shift right of [dstDisp] by imm
30448 * </PRE>
30449 *
30450 * @param dstDisp the destination displacement
30451 * @param imm immediate
30452 */
30453 public final void emitSHR_Abs_Imm_Word(Address dstDisp, int imm) {
30454 int miStart = mi;
30455 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
30456 setMachineCodes(mi++, (byte) 0x66);
30457 generateREXprefix(false, null, null, null);
30458 if (imm == 1) {
30459 setMachineCodes(mi++, (byte) 0xD1);
30460 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x5));
30461 } else {
30462 setMachineCodes(mi++, (byte) 0xC1);
30463 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x5));
30464 emitImm8((byte)imm);
30465 }
30466 if (lister != null) lister.RAI(miStart, "SHR", dstDisp, imm);
30467 }
30468
30469 /**
30470 * Generate a register-index--immediate SHR. That is,
30471 * <PRE>
30472 * logical shift right of [dstBase + dstIndex<<dstScale + dstDisp] by imm
30473 * </PRE>
30474 *
30475 * @param dstBase the destination base register
30476 * @param dstIndex the destination index register
30477 * @param dstScale the destination shift amount
30478 * @param dstDisp the destination displacement
30479 * @param imm immediate
30480 */
30481 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
30482 public final void emitSHR_RegIdx_Imm_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
30483 int miStart = mi;
30484 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
30485 setMachineCodes(mi++, (byte) 0x66);
30486 generateREXprefix(false, null, dstIndex, dstBase);
30487 if (imm == 1) {
30488 setMachineCodes(mi++, (byte) 0xD1);
30489 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
30490 } else {
30491 setMachineCodes(mi++, (byte) 0xC1);
30492 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
30493 emitImm8((byte)imm);
30494 }
30495 if (lister != null) lister.RXDI(miStart, "SHR", dstBase, dstIndex, dstScale, dstDisp, imm);
30496 }
30497
30498 /**
30499 * Generate a register--register SHR. That is,
30500 * <PRE>
30501 * logical shift right of dstReg by srcReg
30502 * </PRE>
30503 *
30504 * @param dstReg the destination register
30505 * @param srcReg must always be ECX
30506 */
30507 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
30508 public final void emitSHR_Reg_Reg_Word(GPR dstReg, GPR srcReg) {
30509 int miStart = mi;
30510 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
30511 setMachineCodes(mi++, (byte) 0x66);
30512 generateREXprefix(false, null, null, dstReg);
30513 setMachineCodes(mi++, (byte) 0xD3);
30514 emitRegRegOperands(dstReg, GPR.getForOpcode(0x5));
30515 if (lister != null) lister.RR(miStart, "SHR", dstReg, srcReg);
30516 }
30517
30518 /**
30519 * Generate a register-indirect--register SHR. That is,
30520 * <PRE>
30521 * logical shift right of [dstBase] by srcReg
30522 * </PRE>
30523 *
30524 * @param dstBase the destination register
30525 * @param srcReg must always be ECX
30526 */
30527 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
30528 public final void emitSHR_RegInd_Reg_Word(GPR dstBase, GPR srcReg) {
30529 int miStart = mi;
30530 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
30531 setMachineCodes(mi++, (byte) 0x66);
30532 generateREXprefix(false, null, null, dstBase);
30533 setMachineCodes(mi++, (byte) 0xD3);
30534 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x5));
30535 if (lister != null) lister.RNR(miStart, "SHR", dstBase, srcReg);
30536 }
30537
30538 /**
30539 * Generate a register-displacement--register SHR. That is,
30540 * <PRE>
30541 * logical shift right of [dstBase + dstDisp] by srcReg
30542 * </PRE>
30543 *
30544 * @param dstBase the destination base register
30545 * @param dstDisp the destination displacement
30546 * @param srcReg must always be ECX
30547 */
30548 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
30549 public final void emitSHR_RegDisp_Reg_Word(GPR dstBase, Offset dstDisp, GPR srcReg) {
30550 int miStart = mi;
30551 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
30552 setMachineCodes(mi++, (byte) 0x66);
30553 generateREXprefix(false, null, null, dstBase);
30554 setMachineCodes(mi++, (byte) 0xD3);
30555 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x5));
30556 if (lister != null) lister.RDR(miStart, "SHR", dstBase, dstDisp, srcReg);
30557 }
30558
30559 /**
30560 * Generate a register-offset--register SHR. That is,
30561 * <PRE>
30562 * logical shift right of [dstIndex<<dstScale + dstDisp] by srcReg
30563 * </PRE>
30564 *
30565 * @param dstIndex the destination index register
30566 * @param dstScale the destination shift amount
30567 * @param dstDisp the destination displacement
30568 * @param srcReg must always be ECX
30569 */
30570 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
30571 public final void emitSHR_RegOff_Reg_Word(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
30572 int miStart = mi;
30573 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
30574 setMachineCodes(mi++, (byte) 0x66);
30575 generateREXprefix(false, null, dstIndex, null);
30576 setMachineCodes(mi++, (byte) 0xD3);
30577 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
30578 if (lister != null) lister.RFDR(miStart, "SHR", dstIndex, dstScale, dstDisp, srcReg);
30579 }
30580
30581 /**
30582 * Generate an absolute--register SHR. That is,
30583 * <PRE>
30584 * logical shift right of [dstDisp] by srcReg
30585 * </PRE>
30586 *
30587 * @param dstDisp the destination displacement
30588 * @param srcReg must always be ECX
30589 */
30590 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
30591 public final void emitSHR_Abs_Reg_Word(Address dstDisp, GPR srcReg) {
30592 int miStart = mi;
30593 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
30594 setMachineCodes(mi++, (byte) 0x66);
30595 generateREXprefix(false, null, null, null);
30596 setMachineCodes(mi++, (byte) 0xD3);
30597 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x5));
30598 if (lister != null) lister.RAR(miStart, "SHR", dstDisp, srcReg);
30599 }
30600
30601 /**
30602 * Generate a register-displacement--register SHR. That is,
30603 * <PRE>
30604 * logical shift right of [dstBase + dstIndex<<dstScale + dstDisp] by srcReg
30605 * </PRE>
30606 *
30607 * @param dstBase the destination base register
30608 * @param dstIndex the destination index register
30609 * @param dstScale the destination shift amount
30610 * @param dstDisp the destination displacement
30611 * @param srcReg must always be ECX
30612 */
30613 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
30614 public final void emitSHR_RegIdx_Reg_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
30615 int miStart = mi;
30616 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
30617 setMachineCodes(mi++, (byte) 0x66);
30618 generateREXprefix(false, null, dstIndex, dstBase);
30619 setMachineCodes(mi++, (byte) 0xD3);
30620 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
30621 if (lister != null) lister.RXDR(miStart, "SHR", dstBase, dstIndex, dstScale, dstDisp, srcReg);
30622 }
30623
30624 /**
30625 * Generate a register--immediate SHR. That is,
30626 * <PRE>
30627 * logical shift right of dstReg by imm
30628 * </PRE>
30629 *
30630 * @param dstReg the destination register
30631 * @param imm immediate
30632 */
30633 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
30634 public final void emitSHR_Reg_Imm(GPR dstReg, int imm) {
30635 int miStart = mi;
30636 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
30637 // no size prefix
30638 generateREXprefix(false, null, null, dstReg);
30639 if (imm == 1) {
30640 setMachineCodes(mi++, (byte) 0xD1);
30641 emitRegRegOperands(dstReg, GPR.getForOpcode(0x5));
30642 } else {
30643 setMachineCodes(mi++, (byte) 0xC1);
30644 emitRegRegOperands(dstReg, GPR.getForOpcode(0x5));
30645 emitImm8((byte)imm);
30646 }
30647 if (lister != null) lister.RI(miStart, "SHR", dstReg, imm);
30648 }
30649
30650 /**
30651 * Generate a register-indirect--immediate SHR. That is,
30652 * <PRE>
30653 * logical shift right of [dstBase] by imm
30654 * </PRE>
30655 *
30656 * @param dstBase the destination base register
30657 * @param imm immediate
30658 */
30659 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
30660 public final void emitSHR_RegInd_Imm(GPR dstBase, int imm) {
30661 int miStart = mi;
30662 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
30663 // no size prefix
30664 generateREXprefix(false, null, null, dstBase);
30665 if (imm == 1) {
30666 setMachineCodes(mi++, (byte) 0xD1);
30667 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x5));
30668 } else {
30669 setMachineCodes(mi++, (byte) 0xC1);
30670 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x5));
30671 emitImm8((byte)imm);
30672 }
30673 if (lister != null) lister.RNI(miStart, "SHR", dstBase, imm);
30674 }
30675
30676 /**
30677 * Generate a register-displacement--immediate SHR. That is,
30678 * <PRE>
30679 * logical shift right of [dstBase + dstDisp] by imm
30680 * </PRE>
30681 *
30682 * @param dstBase the destination base register
30683 * @param dstDisp the destination displacement
30684 * @param imm immediate
30685 */
30686 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
30687 public final void emitSHR_RegDisp_Imm(GPR dstBase, Offset dstDisp, int imm) {
30688 int miStart = mi;
30689 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
30690 // no size prefix
30691 generateREXprefix(false, null, null, dstBase);
30692 if (imm == 1) {
30693 setMachineCodes(mi++, (byte) 0xD1);
30694 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x5));
30695 } else {
30696 setMachineCodes(mi++, (byte) 0xC1);
30697 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x5));
30698 emitImm8((byte)imm);
30699 }
30700 if (lister != null) lister.RDI(miStart, "SHR", dstBase, dstDisp, imm);
30701 }
30702
30703 /**
30704 * Generate a register-offset--immediate SHR. That is,
30705 * <PRE>
30706 * logical shift right of [dstIndex<<dstScale + dstDisp] by imm
30707 * </PRE>
30708 *
30709 * @param dstIndex the destination index register
30710 * @param dstScale the destination shift amount
30711 * @param dstDisp the destination displacement
30712 * @param imm immediate
30713 */
30714 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
30715 public final void emitSHR_RegOff_Imm(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
30716 int miStart = mi;
30717 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
30718 // no size prefix
30719 generateREXprefix(false, null, dstIndex, null);
30720 if (imm == 1) {
30721 setMachineCodes(mi++, (byte) 0xD1);
30722 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
30723 } else {
30724 setMachineCodes(mi++, (byte) 0xC1);
30725 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
30726 emitImm8((byte)imm);
30727 }
30728 if (lister != null) lister.RFDI(miStart, "SHR", dstIndex, dstScale, dstDisp, imm);
30729 }
30730
30731 /**
30732 * Generate a absolute--immediate SHR. That is,
30733 * <PRE>
30734 * logical shift right of [dstDisp] by imm
30735 * </PRE>
30736 *
30737 * @param dstDisp the destination displacement
30738 * @param imm immediate
30739 */
30740 public final void emitSHR_Abs_Imm(Address dstDisp, int imm) {
30741 int miStart = mi;
30742 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
30743 // no size prefix
30744 generateREXprefix(false, null, null, null);
30745 if (imm == 1) {
30746 setMachineCodes(mi++, (byte) 0xD1);
30747 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x5));
30748 } else {
30749 setMachineCodes(mi++, (byte) 0xC1);
30750 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x5));
30751 emitImm8((byte)imm);
30752 }
30753 if (lister != null) lister.RAI(miStart, "SHR", dstDisp, imm);
30754 }
30755
30756 /**
30757 * Generate a register-index--immediate SHR. That is,
30758 * <PRE>
30759 * logical shift right of [dstBase + dstIndex<<dstScale + dstDisp] by imm
30760 * </PRE>
30761 *
30762 * @param dstBase the destination base register
30763 * @param dstIndex the destination index register
30764 * @param dstScale the destination shift amount
30765 * @param dstDisp the destination displacement
30766 * @param imm immediate
30767 */
30768 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
30769 public final void emitSHR_RegIdx_Imm(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
30770 int miStart = mi;
30771 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
30772 // no size prefix
30773 generateREXprefix(false, null, dstIndex, dstBase);
30774 if (imm == 1) {
30775 setMachineCodes(mi++, (byte) 0xD1);
30776 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
30777 } else {
30778 setMachineCodes(mi++, (byte) 0xC1);
30779 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
30780 emitImm8((byte)imm);
30781 }
30782 if (lister != null) lister.RXDI(miStart, "SHR", dstBase, dstIndex, dstScale, dstDisp, imm);
30783 }
30784
30785 /**
30786 * Generate a register--register SHR. That is,
30787 * <PRE>
30788 * logical shift right of dstReg by srcReg
30789 * </PRE>
30790 *
30791 * @param dstReg the destination register
30792 * @param srcReg must always be ECX
30793 */
30794 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
30795 public final void emitSHR_Reg_Reg(GPR dstReg, GPR srcReg) {
30796 int miStart = mi;
30797 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
30798 // no size prefix
30799 generateREXprefix(false, null, null, dstReg);
30800 setMachineCodes(mi++, (byte) 0xD3);
30801 emitRegRegOperands(dstReg, GPR.getForOpcode(0x5));
30802 if (lister != null) lister.RR(miStart, "SHR", dstReg, srcReg);
30803 }
30804
30805 /**
30806 * Generate a register-indirect--register SHR. That is,
30807 * <PRE>
30808 * logical shift right of [dstBase] by srcReg
30809 * </PRE>
30810 *
30811 * @param dstBase the destination register
30812 * @param srcReg must always be ECX
30813 */
30814 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
30815 public final void emitSHR_RegInd_Reg(GPR dstBase, GPR srcReg) {
30816 int miStart = mi;
30817 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
30818 // no size prefix
30819 generateREXprefix(false, null, null, dstBase);
30820 setMachineCodes(mi++, (byte) 0xD3);
30821 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x5));
30822 if (lister != null) lister.RNR(miStart, "SHR", dstBase, srcReg);
30823 }
30824
30825 /**
30826 * Generate a register-displacement--register SHR. That is,
30827 * <PRE>
30828 * logical shift right of [dstBase + dstDisp] by srcReg
30829 * </PRE>
30830 *
30831 * @param dstBase the destination base register
30832 * @param dstDisp the destination displacement
30833 * @param srcReg must always be ECX
30834 */
30835 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
30836 public final void emitSHR_RegDisp_Reg(GPR dstBase, Offset dstDisp, GPR srcReg) {
30837 int miStart = mi;
30838 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
30839 // no size prefix
30840 generateREXprefix(false, null, null, dstBase);
30841 setMachineCodes(mi++, (byte) 0xD3);
30842 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x5));
30843 if (lister != null) lister.RDR(miStart, "SHR", dstBase, dstDisp, srcReg);
30844 }
30845
30846 /**
30847 * Generate a register-offset--register SHR. That is,
30848 * <PRE>
30849 * logical shift right of [dstIndex<<dstScale + dstDisp] by srcReg
30850 * </PRE>
30851 *
30852 * @param dstIndex the destination index register
30853 * @param dstScale the destination shift amount
30854 * @param dstDisp the destination displacement
30855 * @param srcReg must always be ECX
30856 */
30857 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
30858 public final void emitSHR_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
30859 int miStart = mi;
30860 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
30861 // no size prefix
30862 generateREXprefix(false, null, dstIndex, null);
30863 setMachineCodes(mi++, (byte) 0xD3);
30864 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
30865 if (lister != null) lister.RFDR(miStart, "SHR", dstIndex, dstScale, dstDisp, srcReg);
30866 }
30867
30868 /**
30869 * Generate an absolute--register SHR. That is,
30870 * <PRE>
30871 * logical shift right of [dstDisp] by srcReg
30872 * </PRE>
30873 *
30874 * @param dstDisp the destination displacement
30875 * @param srcReg must always be ECX
30876 */
30877 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
30878 public final void emitSHR_Abs_Reg(Address dstDisp, GPR srcReg) {
30879 int miStart = mi;
30880 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
30881 // no size prefix
30882 generateREXprefix(false, null, null, null);
30883 setMachineCodes(mi++, (byte) 0xD3);
30884 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x5));
30885 if (lister != null) lister.RAR(miStart, "SHR", dstDisp, srcReg);
30886 }
30887
30888 /**
30889 * Generate a register-displacement--register SHR. That is,
30890 * <PRE>
30891 * logical shift right of [dstBase + dstIndex<<dstScale + dstDisp] by srcReg
30892 * </PRE>
30893 *
30894 * @param dstBase the destination base register
30895 * @param dstIndex the destination index register
30896 * @param dstScale the destination shift amount
30897 * @param dstDisp the destination displacement
30898 * @param srcReg must always be ECX
30899 */
30900 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
30901 public final void emitSHR_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
30902 int miStart = mi;
30903 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
30904 // no size prefix
30905 generateREXprefix(false, null, dstIndex, dstBase);
30906 setMachineCodes(mi++, (byte) 0xD3);
30907 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
30908 if (lister != null) lister.RXDR(miStart, "SHR", dstBase, dstIndex, dstScale, dstDisp, srcReg);
30909 }
30910
30911 /**
30912 * Generate a register--immediate SHR. That is,
30913 * <PRE>
30914 * logical shift right of dstReg by imm
30915 * </PRE>
30916 *
30917 * @param dstReg the destination register
30918 * @param imm immediate
30919 */
30920 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
30921 public final void emitSHR_Reg_Imm_Quad(GPR dstReg, int imm) {
30922 int miStart = mi;
30923 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
30924 // no size prefix
30925 generateREXprefix(true, null, null, dstReg);
30926 if (imm == 1) {
30927 setMachineCodes(mi++, (byte) 0xD1);
30928 emitRegRegOperands(dstReg, GPR.getForOpcode(0x5));
30929 } else {
30930 setMachineCodes(mi++, (byte) 0xC1);
30931 emitRegRegOperands(dstReg, GPR.getForOpcode(0x5));
30932 emitImm8((byte)imm);
30933 }
30934 if (lister != null) lister.RI(miStart, "SHR", dstReg, imm);
30935 }
30936
30937 /**
30938 * Generate a register-indirect--immediate SHR. That is,
30939 * <PRE>
30940 * logical shift right of [dstBase] by imm
30941 * </PRE>
30942 *
30943 * @param dstBase the destination base register
30944 * @param imm immediate
30945 */
30946 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
30947 public final void emitSHR_RegInd_Imm_Quad(GPR dstBase, int imm) {
30948 int miStart = mi;
30949 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
30950 // no size prefix
30951 generateREXprefix(true, null, null, dstBase);
30952 if (imm == 1) {
30953 setMachineCodes(mi++, (byte) 0xD1);
30954 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x5));
30955 } else {
30956 setMachineCodes(mi++, (byte) 0xC1);
30957 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x5));
30958 emitImm8((byte)imm);
30959 }
30960 if (lister != null) lister.RNI(miStart, "SHR", dstBase, imm);
30961 }
30962
30963 /**
30964 * Generate a register-displacement--immediate SHR. That is,
30965 * <PRE>
30966 * logical shift right of [dstBase + dstDisp] by imm
30967 * </PRE>
30968 *
30969 * @param dstBase the destination base register
30970 * @param dstDisp the destination displacement
30971 * @param imm immediate
30972 */
30973 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
30974 public final void emitSHR_RegDisp_Imm_Quad(GPR dstBase, Offset dstDisp, int imm) {
30975 int miStart = mi;
30976 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
30977 // no size prefix
30978 generateREXprefix(true, null, null, dstBase);
30979 if (imm == 1) {
30980 setMachineCodes(mi++, (byte) 0xD1);
30981 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x5));
30982 } else {
30983 setMachineCodes(mi++, (byte) 0xC1);
30984 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x5));
30985 emitImm8((byte)imm);
30986 }
30987 if (lister != null) lister.RDI(miStart, "SHR", dstBase, dstDisp, imm);
30988 }
30989
30990 /**
30991 * Generate a register-offset--immediate SHR. That is,
30992 * <PRE>
30993 * logical shift right of [dstIndex<<dstScale + dstDisp] by imm
30994 * </PRE>
30995 *
30996 * @param dstIndex the destination index register
30997 * @param dstScale the destination shift amount
30998 * @param dstDisp the destination displacement
30999 * @param imm immediate
31000 */
31001 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
31002 public final void emitSHR_RegOff_Imm_Quad(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
31003 int miStart = mi;
31004 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
31005 // no size prefix
31006 generateREXprefix(true, null, dstIndex, null);
31007 if (imm == 1) {
31008 setMachineCodes(mi++, (byte) 0xD1);
31009 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
31010 } else {
31011 setMachineCodes(mi++, (byte) 0xC1);
31012 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
31013 emitImm8((byte)imm);
31014 }
31015 if (lister != null) lister.RFDI(miStart, "SHR", dstIndex, dstScale, dstDisp, imm);
31016 }
31017
31018 /**
31019 * Generate a absolute--immediate SHR. That is,
31020 * <PRE>
31021 * logical shift right of [dstDisp] by imm
31022 * </PRE>
31023 *
31024 * @param dstDisp the destination displacement
31025 * @param imm immediate
31026 */
31027 public final void emitSHR_Abs_Imm_Quad(Address dstDisp, int imm) {
31028 int miStart = mi;
31029 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
31030 // no size prefix
31031 generateREXprefix(true, null, null, null);
31032 if (imm == 1) {
31033 setMachineCodes(mi++, (byte) 0xD1);
31034 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x5));
31035 } else {
31036 setMachineCodes(mi++, (byte) 0xC1);
31037 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x5));
31038 emitImm8((byte)imm);
31039 }
31040 if (lister != null) lister.RAI(miStart, "SHR", dstDisp, imm);
31041 }
31042
31043 /**
31044 * Generate a register-index--immediate SHR. That is,
31045 * <PRE>
31046 * logical shift right of [dstBase + dstIndex<<dstScale + dstDisp] by imm
31047 * </PRE>
31048 *
31049 * @param dstBase the destination base register
31050 * @param dstIndex the destination index register
31051 * @param dstScale the destination shift amount
31052 * @param dstDisp the destination displacement
31053 * @param imm immediate
31054 */
31055 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
31056 public final void emitSHR_RegIdx_Imm_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
31057 int miStart = mi;
31058 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
31059 // no size prefix
31060 generateREXprefix(true, null, dstIndex, dstBase);
31061 if (imm == 1) {
31062 setMachineCodes(mi++, (byte) 0xD1);
31063 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
31064 } else {
31065 setMachineCodes(mi++, (byte) 0xC1);
31066 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
31067 emitImm8((byte)imm);
31068 }
31069 if (lister != null) lister.RXDI(miStart, "SHR", dstBase, dstIndex, dstScale, dstDisp, imm);
31070 }
31071
31072 /**
31073 * Generate a register--register SHR. That is,
31074 * <PRE>
31075 * logical shift right of dstReg by srcReg
31076 * </PRE>
31077 *
31078 * @param dstReg the destination register
31079 * @param srcReg must always be ECX
31080 */
31081 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
31082 public final void emitSHR_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
31083 int miStart = mi;
31084 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
31085 // no size prefix
31086 generateREXprefix(true, null, null, dstReg);
31087 setMachineCodes(mi++, (byte) 0xD3);
31088 emitRegRegOperands(dstReg, GPR.getForOpcode(0x5));
31089 if (lister != null) lister.RR(miStart, "SHR", dstReg, srcReg);
31090 }
31091
31092 /**
31093 * Generate a register-indirect--register SHR. That is,
31094 * <PRE>
31095 * logical shift right of [dstBase] by srcReg
31096 * </PRE>
31097 *
31098 * @param dstBase the destination register
31099 * @param srcReg must always be ECX
31100 */
31101 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
31102 public final void emitSHR_RegInd_Reg_Quad(GPR dstBase, GPR srcReg) {
31103 int miStart = mi;
31104 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
31105 // no size prefix
31106 generateREXprefix(true, null, null, dstBase);
31107 setMachineCodes(mi++, (byte) 0xD3);
31108 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x5));
31109 if (lister != null) lister.RNR(miStart, "SHR", dstBase, srcReg);
31110 }
31111
31112 /**
31113 * Generate a register-displacement--register SHR. That is,
31114 * <PRE>
31115 * logical shift right of [dstBase + dstDisp] by srcReg
31116 * </PRE>
31117 *
31118 * @param dstBase the destination base register
31119 * @param dstDisp the destination displacement
31120 * @param srcReg must always be ECX
31121 */
31122 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
31123 public final void emitSHR_RegDisp_Reg_Quad(GPR dstBase, Offset dstDisp, GPR srcReg) {
31124 int miStart = mi;
31125 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
31126 // no size prefix
31127 generateREXprefix(true, null, null, dstBase);
31128 setMachineCodes(mi++, (byte) 0xD3);
31129 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x5));
31130 if (lister != null) lister.RDR(miStart, "SHR", dstBase, dstDisp, srcReg);
31131 }
31132
31133 /**
31134 * Generate a register-offset--register SHR. That is,
31135 * <PRE>
31136 * logical shift right of [dstIndex<<dstScale + dstDisp] by srcReg
31137 * </PRE>
31138 *
31139 * @param dstIndex the destination index register
31140 * @param dstScale the destination shift amount
31141 * @param dstDisp the destination displacement
31142 * @param srcReg must always be ECX
31143 */
31144 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
31145 public final void emitSHR_RegOff_Reg_Quad(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
31146 int miStart = mi;
31147 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
31148 // no size prefix
31149 generateREXprefix(true, null, dstIndex, null);
31150 setMachineCodes(mi++, (byte) 0xD3);
31151 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
31152 if (lister != null) lister.RFDR(miStart, "SHR", dstIndex, dstScale, dstDisp, srcReg);
31153 }
31154
31155 /**
31156 * Generate an absolute--register SHR. That is,
31157 * <PRE>
31158 * logical shift right of [dstDisp] by srcReg
31159 * </PRE>
31160 *
31161 * @param dstDisp the destination displacement
31162 * @param srcReg must always be ECX
31163 */
31164 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
31165 public final void emitSHR_Abs_Reg_Quad(Address dstDisp, GPR srcReg) {
31166 int miStart = mi;
31167 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
31168 // no size prefix
31169 generateREXprefix(true, null, null, null);
31170 setMachineCodes(mi++, (byte) 0xD3);
31171 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x5));
31172 if (lister != null) lister.RAR(miStart, "SHR", dstDisp, srcReg);
31173 }
31174
31175 /**
31176 * Generate a register-displacement--register SHR. That is,
31177 * <PRE>
31178 * logical shift right of [dstBase + dstIndex<<dstScale + dstDisp] by srcReg
31179 * </PRE>
31180 *
31181 * @param dstBase the destination base register
31182 * @param dstIndex the destination index register
31183 * @param dstScale the destination shift amount
31184 * @param dstDisp the destination displacement
31185 * @param srcReg must always be ECX
31186 */
31187 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
31188 public final void emitSHR_RegIdx_Reg_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
31189 int miStart = mi;
31190 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
31191 // no size prefix
31192 generateREXprefix(true, null, dstIndex, dstBase);
31193 setMachineCodes(mi++, (byte) 0xD3);
31194 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x5));
31195 if (lister != null) lister.RXDR(miStart, "SHR", dstBase, dstIndex, dstScale, dstDisp, srcReg);
31196 }
31197
31198 /**
31199 * Generate a register--immediate SAR. That is,
31200 * <PRE>
31201 * arithemetic shift right of dstReg by imm
31202 * </PRE>
31203 *
31204 * @param dstReg the destination register
31205 * @param imm immediate
31206 */
31207 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
31208 public final void emitSAR_Reg_Imm_Byte(GPR dstReg, int imm) {
31209 int miStart = mi;
31210 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
31211 // no size prefix
31212 generateREXprefix(false, null, null, dstReg);
31213 if (imm == 1) {
31214 setMachineCodes(mi++, (byte) 0xD0);
31215 emitRegRegOperands(dstReg, GPR.getForOpcode(0x7));
31216 } else {
31217 setMachineCodes(mi++, (byte) 0xC0);
31218 emitRegRegOperands(dstReg, GPR.getForOpcode(0x7));
31219 emitImm8((byte)imm);
31220 }
31221 if (lister != null) lister.RI(miStart, "SAR", dstReg, imm);
31222 }
31223
31224 /**
31225 * Generate a register-indirect--immediate SAR. That is,
31226 * <PRE>
31227 * arithemetic shift right of [dstBase] by imm
31228 * </PRE>
31229 *
31230 * @param dstBase the destination base register
31231 * @param imm immediate
31232 */
31233 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
31234 public final void emitSAR_RegInd_Imm_Byte(GPR dstBase, int imm) {
31235 int miStart = mi;
31236 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
31237 // no size prefix
31238 generateREXprefix(false, null, null, dstBase);
31239 if (imm == 1) {
31240 setMachineCodes(mi++, (byte) 0xD0);
31241 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x7));
31242 } else {
31243 setMachineCodes(mi++, (byte) 0xC0);
31244 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x7));
31245 emitImm8((byte)imm);
31246 }
31247 if (lister != null) lister.RNI(miStart, "SAR", dstBase, imm);
31248 }
31249
31250 /**
31251 * Generate a register-displacement--immediate SAR. That is,
31252 * <PRE>
31253 * arithemetic shift right of [dstBase + dstDisp] by imm
31254 * </PRE>
31255 *
31256 * @param dstBase the destination base register
31257 * @param dstDisp the destination displacement
31258 * @param imm immediate
31259 */
31260 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
31261 public final void emitSAR_RegDisp_Imm_Byte(GPR dstBase, Offset dstDisp, int imm) {
31262 int miStart = mi;
31263 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
31264 // no size prefix
31265 generateREXprefix(false, null, null, dstBase);
31266 if (imm == 1) {
31267 setMachineCodes(mi++, (byte) 0xD0);
31268 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x7));
31269 } else {
31270 setMachineCodes(mi++, (byte) 0xC0);
31271 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x7));
31272 emitImm8((byte)imm);
31273 }
31274 if (lister != null) lister.RDI(miStart, "SAR", dstBase, dstDisp, imm);
31275 }
31276
31277 /**
31278 * Generate a register-offset--immediate SAR. That is,
31279 * <PRE>
31280 * arithemetic shift right of [dstIndex<<dstScale + dstDisp] by imm
31281 * </PRE>
31282 *
31283 * @param dstIndex the destination index register
31284 * @param dstScale the destination shift amount
31285 * @param dstDisp the destination displacement
31286 * @param imm immediate
31287 */
31288 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
31289 public final void emitSAR_RegOff_Imm_Byte(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
31290 int miStart = mi;
31291 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
31292 // no size prefix
31293 generateREXprefix(false, null, dstIndex, null);
31294 if (imm == 1) {
31295 setMachineCodes(mi++, (byte) 0xD0);
31296 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
31297 } else {
31298 setMachineCodes(mi++, (byte) 0xC0);
31299 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
31300 emitImm8((byte)imm);
31301 }
31302 if (lister != null) lister.RFDI(miStart, "SAR", dstIndex, dstScale, dstDisp, imm);
31303 }
31304
31305 /**
31306 * Generate a absolute--immediate SAR. That is,
31307 * <PRE>
31308 * arithemetic shift right of [dstDisp] by imm
31309 * </PRE>
31310 *
31311 * @param dstDisp the destination displacement
31312 * @param imm immediate
31313 */
31314 public final void emitSAR_Abs_Imm_Byte(Address dstDisp, int imm) {
31315 int miStart = mi;
31316 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
31317 // no size prefix
31318 generateREXprefix(false, null, null, null);
31319 if (imm == 1) {
31320 setMachineCodes(mi++, (byte) 0xD0);
31321 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x7));
31322 } else {
31323 setMachineCodes(mi++, (byte) 0xC0);
31324 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x7));
31325 emitImm8((byte)imm);
31326 }
31327 if (lister != null) lister.RAI(miStart, "SAR", dstDisp, imm);
31328 }
31329
31330 /**
31331 * Generate a register-index--immediate SAR. That is,
31332 * <PRE>
31333 * arithemetic shift right of [dstBase + dstIndex<<dstScale + dstDisp] by imm
31334 * </PRE>
31335 *
31336 * @param dstBase the destination base register
31337 * @param dstIndex the destination index register
31338 * @param dstScale the destination shift amount
31339 * @param dstDisp the destination displacement
31340 * @param imm immediate
31341 */
31342 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
31343 public final void emitSAR_RegIdx_Imm_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
31344 int miStart = mi;
31345 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
31346 // no size prefix
31347 generateREXprefix(false, null, dstIndex, dstBase);
31348 if (imm == 1) {
31349 setMachineCodes(mi++, (byte) 0xD0);
31350 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
31351 } else {
31352 setMachineCodes(mi++, (byte) 0xC0);
31353 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
31354 emitImm8((byte)imm);
31355 }
31356 if (lister != null) lister.RXDI(miStart, "SAR", dstBase, dstIndex, dstScale, dstDisp, imm);
31357 }
31358
31359 /**
31360 * Generate a register--register SAR. That is,
31361 * <PRE>
31362 * arithemetic shift right of dstReg by srcReg
31363 * </PRE>
31364 *
31365 * @param dstReg the destination register
31366 * @param srcReg must always be ECX
31367 */
31368 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
31369 public final void emitSAR_Reg_Reg_Byte(GPR dstReg, GPR srcReg) {
31370 int miStart = mi;
31371 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
31372 // no size prefix
31373 generateREXprefix(false, null, null, dstReg);
31374 setMachineCodes(mi++, (byte) 0xD2);
31375 emitRegRegOperands(dstReg, GPR.getForOpcode(0x7));
31376 if (lister != null) lister.RR(miStart, "SAR", dstReg, srcReg);
31377 }
31378
31379 /**
31380 * Generate a register-indirect--register SAR. That is,
31381 * <PRE>
31382 * arithemetic shift right of [dstBase] by srcReg
31383 * </PRE>
31384 *
31385 * @param dstBase the destination register
31386 * @param srcReg must always be ECX
31387 */
31388 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
31389 public final void emitSAR_RegInd_Reg_Byte(GPR dstBase, GPR srcReg) {
31390 int miStart = mi;
31391 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
31392 // no size prefix
31393 generateREXprefix(false, null, null, dstBase);
31394 setMachineCodes(mi++, (byte) 0xD2);
31395 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x7));
31396 if (lister != null) lister.RNR(miStart, "SAR", dstBase, srcReg);
31397 }
31398
31399 /**
31400 * Generate a register-displacement--register SAR. That is,
31401 * <PRE>
31402 * arithemetic shift right of [dstBase + dstDisp] by srcReg
31403 * </PRE>
31404 *
31405 * @param dstBase the destination base register
31406 * @param dstDisp the destination displacement
31407 * @param srcReg must always be ECX
31408 */
31409 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
31410 public final void emitSAR_RegDisp_Reg_Byte(GPR dstBase, Offset dstDisp, GPR srcReg) {
31411 int miStart = mi;
31412 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
31413 // no size prefix
31414 generateREXprefix(false, null, null, dstBase);
31415 setMachineCodes(mi++, (byte) 0xD2);
31416 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x7));
31417 if (lister != null) lister.RDR(miStart, "SAR", dstBase, dstDisp, srcReg);
31418 }
31419
31420 /**
31421 * Generate a register-offset--register SAR. That is,
31422 * <PRE>
31423 * arithemetic shift right of [dstIndex<<dstScale + dstDisp] by srcReg
31424 * </PRE>
31425 *
31426 * @param dstIndex the destination index register
31427 * @param dstScale the destination shift amount
31428 * @param dstDisp the destination displacement
31429 * @param srcReg must always be ECX
31430 */
31431 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
31432 public final void emitSAR_RegOff_Reg_Byte(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
31433 int miStart = mi;
31434 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
31435 // no size prefix
31436 generateREXprefix(false, null, dstIndex, null);
31437 setMachineCodes(mi++, (byte) 0xD2);
31438 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
31439 if (lister != null) lister.RFDR(miStart, "SAR", dstIndex, dstScale, dstDisp, srcReg);
31440 }
31441
31442 /**
31443 * Generate an absolute--register SAR. That is,
31444 * <PRE>
31445 * arithemetic shift right of [dstDisp] by srcReg
31446 * </PRE>
31447 *
31448 * @param dstDisp the destination displacement
31449 * @param srcReg must always be ECX
31450 */
31451 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
31452 public final void emitSAR_Abs_Reg_Byte(Address dstDisp, GPR srcReg) {
31453 int miStart = mi;
31454 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
31455 // no size prefix
31456 generateREXprefix(false, null, null, null);
31457 setMachineCodes(mi++, (byte) 0xD2);
31458 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x7));
31459 if (lister != null) lister.RAR(miStart, "SAR", dstDisp, srcReg);
31460 }
31461
31462 /**
31463 * Generate a register-displacement--register SAR. That is,
31464 * <PRE>
31465 * arithemetic shift right of [dstBase + dstIndex<<dstScale + dstDisp] by srcReg
31466 * </PRE>
31467 *
31468 * @param dstBase the destination base register
31469 * @param dstIndex the destination index register
31470 * @param dstScale the destination shift amount
31471 * @param dstDisp the destination displacement
31472 * @param srcReg must always be ECX
31473 */
31474 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
31475 public final void emitSAR_RegIdx_Reg_Byte(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
31476 int miStart = mi;
31477 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
31478 // no size prefix
31479 generateREXprefix(false, null, dstIndex, dstBase);
31480 setMachineCodes(mi++, (byte) 0xD2);
31481 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
31482 if (lister != null) lister.RXDR(miStart, "SAR", dstBase, dstIndex, dstScale, dstDisp, srcReg);
31483 }
31484
31485 /**
31486 * Generate a register--immediate SAR. That is,
31487 * <PRE>
31488 * arithemetic shift right of dstReg by imm
31489 * </PRE>
31490 *
31491 * @param dstReg the destination register
31492 * @param imm immediate
31493 */
31494 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
31495 public final void emitSAR_Reg_Imm_Word(GPR dstReg, int imm) {
31496 int miStart = mi;
31497 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
31498 setMachineCodes(mi++, (byte) 0x66);
31499 generateREXprefix(false, null, null, dstReg);
31500 if (imm == 1) {
31501 setMachineCodes(mi++, (byte) 0xD1);
31502 emitRegRegOperands(dstReg, GPR.getForOpcode(0x7));
31503 } else {
31504 setMachineCodes(mi++, (byte) 0xC1);
31505 emitRegRegOperands(dstReg, GPR.getForOpcode(0x7));
31506 emitImm8((byte)imm);
31507 }
31508 if (lister != null) lister.RI(miStart, "SAR", dstReg, imm);
31509 }
31510
31511 /**
31512 * Generate a register-indirect--immediate SAR. That is,
31513 * <PRE>
31514 * arithemetic shift right of [dstBase] by imm
31515 * </PRE>
31516 *
31517 * @param dstBase the destination base register
31518 * @param imm immediate
31519 */
31520 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
31521 public final void emitSAR_RegInd_Imm_Word(GPR dstBase, int imm) {
31522 int miStart = mi;
31523 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
31524 setMachineCodes(mi++, (byte) 0x66);
31525 generateREXprefix(false, null, null, dstBase);
31526 if (imm == 1) {
31527 setMachineCodes(mi++, (byte) 0xD1);
31528 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x7));
31529 } else {
31530 setMachineCodes(mi++, (byte) 0xC1);
31531 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x7));
31532 emitImm8((byte)imm);
31533 }
31534 if (lister != null) lister.RNI(miStart, "SAR", dstBase, imm);
31535 }
31536
31537 /**
31538 * Generate a register-displacement--immediate SAR. That is,
31539 * <PRE>
31540 * arithemetic shift right of [dstBase + dstDisp] by imm
31541 * </PRE>
31542 *
31543 * @param dstBase the destination base register
31544 * @param dstDisp the destination displacement
31545 * @param imm immediate
31546 */
31547 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
31548 public final void emitSAR_RegDisp_Imm_Word(GPR dstBase, Offset dstDisp, int imm) {
31549 int miStart = mi;
31550 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
31551 setMachineCodes(mi++, (byte) 0x66);
31552 generateREXprefix(false, null, null, dstBase);
31553 if (imm == 1) {
31554 setMachineCodes(mi++, (byte) 0xD1);
31555 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x7));
31556 } else {
31557 setMachineCodes(mi++, (byte) 0xC1);
31558 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x7));
31559 emitImm8((byte)imm);
31560 }
31561 if (lister != null) lister.RDI(miStart, "SAR", dstBase, dstDisp, imm);
31562 }
31563
31564 /**
31565 * Generate a register-offset--immediate SAR. That is,
31566 * <PRE>
31567 * arithemetic shift right of [dstIndex<<dstScale + dstDisp] by imm
31568 * </PRE>
31569 *
31570 * @param dstIndex the destination index register
31571 * @param dstScale the destination shift amount
31572 * @param dstDisp the destination displacement
31573 * @param imm immediate
31574 */
31575 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
31576 public final void emitSAR_RegOff_Imm_Word(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
31577 int miStart = mi;
31578 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
31579 setMachineCodes(mi++, (byte) 0x66);
31580 generateREXprefix(false, null, dstIndex, null);
31581 if (imm == 1) {
31582 setMachineCodes(mi++, (byte) 0xD1);
31583 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
31584 } else {
31585 setMachineCodes(mi++, (byte) 0xC1);
31586 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
31587 emitImm8((byte)imm);
31588 }
31589 if (lister != null) lister.RFDI(miStart, "SAR", dstIndex, dstScale, dstDisp, imm);
31590 }
31591
31592 /**
31593 * Generate a absolute--immediate SAR. That is,
31594 * <PRE>
31595 * arithemetic shift right of [dstDisp] by imm
31596 * </PRE>
31597 *
31598 * @param dstDisp the destination displacement
31599 * @param imm immediate
31600 */
31601 public final void emitSAR_Abs_Imm_Word(Address dstDisp, int imm) {
31602 int miStart = mi;
31603 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
31604 setMachineCodes(mi++, (byte) 0x66);
31605 generateREXprefix(false, null, null, null);
31606 if (imm == 1) {
31607 setMachineCodes(mi++, (byte) 0xD1);
31608 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x7));
31609 } else {
31610 setMachineCodes(mi++, (byte) 0xC1);
31611 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x7));
31612 emitImm8((byte)imm);
31613 }
31614 if (lister != null) lister.RAI(miStart, "SAR", dstDisp, imm);
31615 }
31616
31617 /**
31618 * Generate a register-index--immediate SAR. That is,
31619 * <PRE>
31620 * arithemetic shift right of [dstBase + dstIndex<<dstScale + dstDisp] by imm
31621 * </PRE>
31622 *
31623 * @param dstBase the destination base register
31624 * @param dstIndex the destination index register
31625 * @param dstScale the destination shift amount
31626 * @param dstDisp the destination displacement
31627 * @param imm immediate
31628 */
31629 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
31630 public final void emitSAR_RegIdx_Imm_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
31631 int miStart = mi;
31632 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
31633 setMachineCodes(mi++, (byte) 0x66);
31634 generateREXprefix(false, null, dstIndex, dstBase);
31635 if (imm == 1) {
31636 setMachineCodes(mi++, (byte) 0xD1);
31637 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
31638 } else {
31639 setMachineCodes(mi++, (byte) 0xC1);
31640 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
31641 emitImm8((byte)imm);
31642 }
31643 if (lister != null) lister.RXDI(miStart, "SAR", dstBase, dstIndex, dstScale, dstDisp, imm);
31644 }
31645
31646 /**
31647 * Generate a register--register SAR. That is,
31648 * <PRE>
31649 * arithemetic shift right of dstReg by srcReg
31650 * </PRE>
31651 *
31652 * @param dstReg the destination register
31653 * @param srcReg must always be ECX
31654 */
31655 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
31656 public final void emitSAR_Reg_Reg_Word(GPR dstReg, GPR srcReg) {
31657 int miStart = mi;
31658 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
31659 setMachineCodes(mi++, (byte) 0x66);
31660 generateREXprefix(false, null, null, dstReg);
31661 setMachineCodes(mi++, (byte) 0xD3);
31662 emitRegRegOperands(dstReg, GPR.getForOpcode(0x7));
31663 if (lister != null) lister.RR(miStart, "SAR", dstReg, srcReg);
31664 }
31665
31666 /**
31667 * Generate a register-indirect--register SAR. That is,
31668 * <PRE>
31669 * arithemetic shift right of [dstBase] by srcReg
31670 * </PRE>
31671 *
31672 * @param dstBase the destination register
31673 * @param srcReg must always be ECX
31674 */
31675 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
31676 public final void emitSAR_RegInd_Reg_Word(GPR dstBase, GPR srcReg) {
31677 int miStart = mi;
31678 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
31679 setMachineCodes(mi++, (byte) 0x66);
31680 generateREXprefix(false, null, null, dstBase);
31681 setMachineCodes(mi++, (byte) 0xD3);
31682 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x7));
31683 if (lister != null) lister.RNR(miStart, "SAR", dstBase, srcReg);
31684 }
31685
31686 /**
31687 * Generate a register-displacement--register SAR. That is,
31688 * <PRE>
31689 * arithemetic shift right of [dstBase + dstDisp] by srcReg
31690 * </PRE>
31691 *
31692 * @param dstBase the destination base register
31693 * @param dstDisp the destination displacement
31694 * @param srcReg must always be ECX
31695 */
31696 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
31697 public final void emitSAR_RegDisp_Reg_Word(GPR dstBase, Offset dstDisp, GPR srcReg) {
31698 int miStart = mi;
31699 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
31700 setMachineCodes(mi++, (byte) 0x66);
31701 generateREXprefix(false, null, null, dstBase);
31702 setMachineCodes(mi++, (byte) 0xD3);
31703 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x7));
31704 if (lister != null) lister.RDR(miStart, "SAR", dstBase, dstDisp, srcReg);
31705 }
31706
31707 /**
31708 * Generate a register-offset--register SAR. That is,
31709 * <PRE>
31710 * arithemetic shift right of [dstIndex<<dstScale + dstDisp] by srcReg
31711 * </PRE>
31712 *
31713 * @param dstIndex the destination index register
31714 * @param dstScale the destination shift amount
31715 * @param dstDisp the destination displacement
31716 * @param srcReg must always be ECX
31717 */
31718 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
31719 public final void emitSAR_RegOff_Reg_Word(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
31720 int miStart = mi;
31721 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
31722 setMachineCodes(mi++, (byte) 0x66);
31723 generateREXprefix(false, null, dstIndex, null);
31724 setMachineCodes(mi++, (byte) 0xD3);
31725 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
31726 if (lister != null) lister.RFDR(miStart, "SAR", dstIndex, dstScale, dstDisp, srcReg);
31727 }
31728
31729 /**
31730 * Generate an absolute--register SAR. That is,
31731 * <PRE>
31732 * arithemetic shift right of [dstDisp] by srcReg
31733 * </PRE>
31734 *
31735 * @param dstDisp the destination displacement
31736 * @param srcReg must always be ECX
31737 */
31738 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
31739 public final void emitSAR_Abs_Reg_Word(Address dstDisp, GPR srcReg) {
31740 int miStart = mi;
31741 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
31742 setMachineCodes(mi++, (byte) 0x66);
31743 generateREXprefix(false, null, null, null);
31744 setMachineCodes(mi++, (byte) 0xD3);
31745 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x7));
31746 if (lister != null) lister.RAR(miStart, "SAR", dstDisp, srcReg);
31747 }
31748
31749 /**
31750 * Generate a register-displacement--register SAR. That is,
31751 * <PRE>
31752 * arithemetic shift right of [dstBase + dstIndex<<dstScale + dstDisp] by srcReg
31753 * </PRE>
31754 *
31755 * @param dstBase the destination base register
31756 * @param dstIndex the destination index register
31757 * @param dstScale the destination shift amount
31758 * @param dstDisp the destination displacement
31759 * @param srcReg must always be ECX
31760 */
31761 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
31762 public final void emitSAR_RegIdx_Reg_Word(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
31763 int miStart = mi;
31764 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
31765 setMachineCodes(mi++, (byte) 0x66);
31766 generateREXprefix(false, null, dstIndex, dstBase);
31767 setMachineCodes(mi++, (byte) 0xD3);
31768 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
31769 if (lister != null) lister.RXDR(miStart, "SAR", dstBase, dstIndex, dstScale, dstDisp, srcReg);
31770 }
31771
31772 /**
31773 * Generate a register--immediate SAR. That is,
31774 * <PRE>
31775 * arithemetic shift right of dstReg by imm
31776 * </PRE>
31777 *
31778 * @param dstReg the destination register
31779 * @param imm immediate
31780 */
31781 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
31782 public final void emitSAR_Reg_Imm(GPR dstReg, int imm) {
31783 int miStart = mi;
31784 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
31785 // no size prefix
31786 generateREXprefix(false, null, null, dstReg);
31787 if (imm == 1) {
31788 setMachineCodes(mi++, (byte) 0xD1);
31789 emitRegRegOperands(dstReg, GPR.getForOpcode(0x7));
31790 } else {
31791 setMachineCodes(mi++, (byte) 0xC1);
31792 emitRegRegOperands(dstReg, GPR.getForOpcode(0x7));
31793 emitImm8((byte)imm);
31794 }
31795 if (lister != null) lister.RI(miStart, "SAR", dstReg, imm);
31796 }
31797
31798 /**
31799 * Generate a register-indirect--immediate SAR. That is,
31800 * <PRE>
31801 * arithemetic shift right of [dstBase] by imm
31802 * </PRE>
31803 *
31804 * @param dstBase the destination base register
31805 * @param imm immediate
31806 */
31807 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
31808 public final void emitSAR_RegInd_Imm(GPR dstBase, int imm) {
31809 int miStart = mi;
31810 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
31811 // no size prefix
31812 generateREXprefix(false, null, null, dstBase);
31813 if (imm == 1) {
31814 setMachineCodes(mi++, (byte) 0xD1);
31815 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x7));
31816 } else {
31817 setMachineCodes(mi++, (byte) 0xC1);
31818 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x7));
31819 emitImm8((byte)imm);
31820 }
31821 if (lister != null) lister.RNI(miStart, "SAR", dstBase, imm);
31822 }
31823
31824 /**
31825 * Generate a register-displacement--immediate SAR. That is,
31826 * <PRE>
31827 * arithemetic shift right of [dstBase + dstDisp] by imm
31828 * </PRE>
31829 *
31830 * @param dstBase the destination base register
31831 * @param dstDisp the destination displacement
31832 * @param imm immediate
31833 */
31834 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
31835 public final void emitSAR_RegDisp_Imm(GPR dstBase, Offset dstDisp, int imm) {
31836 int miStart = mi;
31837 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
31838 // no size prefix
31839 generateREXprefix(false, null, null, dstBase);
31840 if (imm == 1) {
31841 setMachineCodes(mi++, (byte) 0xD1);
31842 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x7));
31843 } else {
31844 setMachineCodes(mi++, (byte) 0xC1);
31845 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x7));
31846 emitImm8((byte)imm);
31847 }
31848 if (lister != null) lister.RDI(miStart, "SAR", dstBase, dstDisp, imm);
31849 }
31850
31851 /**
31852 * Generate a register-offset--immediate SAR. That is,
31853 * <PRE>
31854 * arithemetic shift right of [dstIndex<<dstScale + dstDisp] by imm
31855 * </PRE>
31856 *
31857 * @param dstIndex the destination index register
31858 * @param dstScale the destination shift amount
31859 * @param dstDisp the destination displacement
31860 * @param imm immediate
31861 */
31862 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
31863 public final void emitSAR_RegOff_Imm(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
31864 int miStart = mi;
31865 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
31866 // no size prefix
31867 generateREXprefix(false, null, dstIndex, null);
31868 if (imm == 1) {
31869 setMachineCodes(mi++, (byte) 0xD1);
31870 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
31871 } else {
31872 setMachineCodes(mi++, (byte) 0xC1);
31873 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
31874 emitImm8((byte)imm);
31875 }
31876 if (lister != null) lister.RFDI(miStart, "SAR", dstIndex, dstScale, dstDisp, imm);
31877 }
31878
31879 /**
31880 * Generate a absolute--immediate SAR. That is,
31881 * <PRE>
31882 * arithemetic shift right of [dstDisp] by imm
31883 * </PRE>
31884 *
31885 * @param dstDisp the destination displacement
31886 * @param imm immediate
31887 */
31888 public final void emitSAR_Abs_Imm(Address dstDisp, int imm) {
31889 int miStart = mi;
31890 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
31891 // no size prefix
31892 generateREXprefix(false, null, null, null);
31893 if (imm == 1) {
31894 setMachineCodes(mi++, (byte) 0xD1);
31895 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x7));
31896 } else {
31897 setMachineCodes(mi++, (byte) 0xC1);
31898 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x7));
31899 emitImm8((byte)imm);
31900 }
31901 if (lister != null) lister.RAI(miStart, "SAR", dstDisp, imm);
31902 }
31903
31904 /**
31905 * Generate a register-index--immediate SAR. That is,
31906 * <PRE>
31907 * arithemetic shift right of [dstBase + dstIndex<<dstScale + dstDisp] by imm
31908 * </PRE>
31909 *
31910 * @param dstBase the destination base register
31911 * @param dstIndex the destination index register
31912 * @param dstScale the destination shift amount
31913 * @param dstDisp the destination displacement
31914 * @param imm immediate
31915 */
31916 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
31917 public final void emitSAR_RegIdx_Imm(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
31918 int miStart = mi;
31919 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
31920 // no size prefix
31921 generateREXprefix(false, null, dstIndex, dstBase);
31922 if (imm == 1) {
31923 setMachineCodes(mi++, (byte) 0xD1);
31924 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
31925 } else {
31926 setMachineCodes(mi++, (byte) 0xC1);
31927 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
31928 emitImm8((byte)imm);
31929 }
31930 if (lister != null) lister.RXDI(miStart, "SAR", dstBase, dstIndex, dstScale, dstDisp, imm);
31931 }
31932
31933 /**
31934 * Generate a register--register SAR. That is,
31935 * <PRE>
31936 * arithemetic shift right of dstReg by srcReg
31937 * </PRE>
31938 *
31939 * @param dstReg the destination register
31940 * @param srcReg must always be ECX
31941 */
31942 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
31943 public final void emitSAR_Reg_Reg(GPR dstReg, GPR srcReg) {
31944 int miStart = mi;
31945 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
31946 // no size prefix
31947 generateREXprefix(false, null, null, dstReg);
31948 setMachineCodes(mi++, (byte) 0xD3);
31949 emitRegRegOperands(dstReg, GPR.getForOpcode(0x7));
31950 if (lister != null) lister.RR(miStart, "SAR", dstReg, srcReg);
31951 }
31952
31953 /**
31954 * Generate a register-indirect--register SAR. That is,
31955 * <PRE>
31956 * arithemetic shift right of [dstBase] by srcReg
31957 * </PRE>
31958 *
31959 * @param dstBase the destination register
31960 * @param srcReg must always be ECX
31961 */
31962 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
31963 public final void emitSAR_RegInd_Reg(GPR dstBase, GPR srcReg) {
31964 int miStart = mi;
31965 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
31966 // no size prefix
31967 generateREXprefix(false, null, null, dstBase);
31968 setMachineCodes(mi++, (byte) 0xD3);
31969 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x7));
31970 if (lister != null) lister.RNR(miStart, "SAR", dstBase, srcReg);
31971 }
31972
31973 /**
31974 * Generate a register-displacement--register SAR. That is,
31975 * <PRE>
31976 * arithemetic shift right of [dstBase + dstDisp] by srcReg
31977 * </PRE>
31978 *
31979 * @param dstBase the destination base register
31980 * @param dstDisp the destination displacement
31981 * @param srcReg must always be ECX
31982 */
31983 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
31984 public final void emitSAR_RegDisp_Reg(GPR dstBase, Offset dstDisp, GPR srcReg) {
31985 int miStart = mi;
31986 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
31987 // no size prefix
31988 generateREXprefix(false, null, null, dstBase);
31989 setMachineCodes(mi++, (byte) 0xD3);
31990 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x7));
31991 if (lister != null) lister.RDR(miStart, "SAR", dstBase, dstDisp, srcReg);
31992 }
31993
31994 /**
31995 * Generate a register-offset--register SAR. That is,
31996 * <PRE>
31997 * arithemetic shift right of [dstIndex<<dstScale + dstDisp] by srcReg
31998 * </PRE>
31999 *
32000 * @param dstIndex the destination index register
32001 * @param dstScale the destination shift amount
32002 * @param dstDisp the destination displacement
32003 * @param srcReg must always be ECX
32004 */
32005 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
32006 public final void emitSAR_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
32007 int miStart = mi;
32008 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
32009 // no size prefix
32010 generateREXprefix(false, null, dstIndex, null);
32011 setMachineCodes(mi++, (byte) 0xD3);
32012 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
32013 if (lister != null) lister.RFDR(miStart, "SAR", dstIndex, dstScale, dstDisp, srcReg);
32014 }
32015
32016 /**
32017 * Generate an absolute--register SAR. That is,
32018 * <PRE>
32019 * arithemetic shift right of [dstDisp] by srcReg
32020 * </PRE>
32021 *
32022 * @param dstDisp the destination displacement
32023 * @param srcReg must always be ECX
32024 */
32025 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
32026 public final void emitSAR_Abs_Reg(Address dstDisp, GPR srcReg) {
32027 int miStart = mi;
32028 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
32029 // no size prefix
32030 generateREXprefix(false, null, null, null);
32031 setMachineCodes(mi++, (byte) 0xD3);
32032 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x7));
32033 if (lister != null) lister.RAR(miStart, "SAR", dstDisp, srcReg);
32034 }
32035
32036 /**
32037 * Generate a register-displacement--register SAR. That is,
32038 * <PRE>
32039 * arithemetic shift right of [dstBase + dstIndex<<dstScale + dstDisp] by srcReg
32040 * </PRE>
32041 *
32042 * @param dstBase the destination base register
32043 * @param dstIndex the destination index register
32044 * @param dstScale the destination shift amount
32045 * @param dstDisp the destination displacement
32046 * @param srcReg must always be ECX
32047 */
32048 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
32049 public final void emitSAR_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
32050 int miStart = mi;
32051 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
32052 // no size prefix
32053 generateREXprefix(false, null, dstIndex, dstBase);
32054 setMachineCodes(mi++, (byte) 0xD3);
32055 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
32056 if (lister != null) lister.RXDR(miStart, "SAR", dstBase, dstIndex, dstScale, dstDisp, srcReg);
32057 }
32058
32059 /**
32060 * Generate a register--immediate SAR. That is,
32061 * <PRE>
32062 * arithemetic shift right of dstReg by imm
32063 * </PRE>
32064 *
32065 * @param dstReg the destination register
32066 * @param imm immediate
32067 */
32068 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
32069 public final void emitSAR_Reg_Imm_Quad(GPR dstReg, int imm) {
32070 int miStart = mi;
32071 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
32072 // no size prefix
32073 generateREXprefix(true, null, null, dstReg);
32074 if (imm == 1) {
32075 setMachineCodes(mi++, (byte) 0xD1);
32076 emitRegRegOperands(dstReg, GPR.getForOpcode(0x7));
32077 } else {
32078 setMachineCodes(mi++, (byte) 0xC1);
32079 emitRegRegOperands(dstReg, GPR.getForOpcode(0x7));
32080 emitImm8((byte)imm);
32081 }
32082 if (lister != null) lister.RI(miStart, "SAR", dstReg, imm);
32083 }
32084
32085 /**
32086 * Generate a register-indirect--immediate SAR. That is,
32087 * <PRE>
32088 * arithemetic shift right of [dstBase] by imm
32089 * </PRE>
32090 *
32091 * @param dstBase the destination base register
32092 * @param imm immediate
32093 */
32094 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
32095 public final void emitSAR_RegInd_Imm_Quad(GPR dstBase, int imm) {
32096 int miStart = mi;
32097 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
32098 // no size prefix
32099 generateREXprefix(true, null, null, dstBase);
32100 if (imm == 1) {
32101 setMachineCodes(mi++, (byte) 0xD1);
32102 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x7));
32103 } else {
32104 setMachineCodes(mi++, (byte) 0xC1);
32105 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x7));
32106 emitImm8((byte)imm);
32107 }
32108 if (lister != null) lister.RNI(miStart, "SAR", dstBase, imm);
32109 }
32110
32111 /**
32112 * Generate a register-displacement--immediate SAR. That is,
32113 * <PRE>
32114 * arithemetic shift right of [dstBase + dstDisp] by imm
32115 * </PRE>
32116 *
32117 * @param dstBase the destination base register
32118 * @param dstDisp the destination displacement
32119 * @param imm immediate
32120 */
32121 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
32122 public final void emitSAR_RegDisp_Imm_Quad(GPR dstBase, Offset dstDisp, int imm) {
32123 int miStart = mi;
32124 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
32125 // no size prefix
32126 generateREXprefix(true, null, null, dstBase);
32127 if (imm == 1) {
32128 setMachineCodes(mi++, (byte) 0xD1);
32129 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x7));
32130 } else {
32131 setMachineCodes(mi++, (byte) 0xC1);
32132 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x7));
32133 emitImm8((byte)imm);
32134 }
32135 if (lister != null) lister.RDI(miStart, "SAR", dstBase, dstDisp, imm);
32136 }
32137
32138 /**
32139 * Generate a register-offset--immediate SAR. That is,
32140 * <PRE>
32141 * arithemetic shift right of [dstIndex<<dstScale + dstDisp] by imm
32142 * </PRE>
32143 *
32144 * @param dstIndex the destination index register
32145 * @param dstScale the destination shift amount
32146 * @param dstDisp the destination displacement
32147 * @param imm immediate
32148 */
32149 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
32150 public final void emitSAR_RegOff_Imm_Quad(GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
32151 int miStart = mi;
32152 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
32153 // no size prefix
32154 generateREXprefix(true, null, dstIndex, null);
32155 if (imm == 1) {
32156 setMachineCodes(mi++, (byte) 0xD1);
32157 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
32158 } else {
32159 setMachineCodes(mi++, (byte) 0xC1);
32160 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
32161 emitImm8((byte)imm);
32162 }
32163 if (lister != null) lister.RFDI(miStart, "SAR", dstIndex, dstScale, dstDisp, imm);
32164 }
32165
32166 /**
32167 * Generate a absolute--immediate SAR. That is,
32168 * <PRE>
32169 * arithemetic shift right of [dstDisp] by imm
32170 * </PRE>
32171 *
32172 * @param dstDisp the destination displacement
32173 * @param imm immediate
32174 */
32175 public final void emitSAR_Abs_Imm_Quad(Address dstDisp, int imm) {
32176 int miStart = mi;
32177 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
32178 // no size prefix
32179 generateREXprefix(true, null, null, null);
32180 if (imm == 1) {
32181 setMachineCodes(mi++, (byte) 0xD1);
32182 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x7));
32183 } else {
32184 setMachineCodes(mi++, (byte) 0xC1);
32185 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x7));
32186 emitImm8((byte)imm);
32187 }
32188 if (lister != null) lister.RAI(miStart, "SAR", dstDisp, imm);
32189 }
32190
32191 /**
32192 * Generate a register-index--immediate SAR. That is,
32193 * <PRE>
32194 * arithemetic shift right of [dstBase + dstIndex<<dstScale + dstDisp] by imm
32195 * </PRE>
32196 *
32197 * @param dstBase the destination base register
32198 * @param dstIndex the destination index register
32199 * @param dstScale the destination shift amount
32200 * @param dstDisp the destination displacement
32201 * @param imm immediate
32202 */
32203 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
32204 public final void emitSAR_RegIdx_Imm_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, int imm) {
32205 int miStart = mi;
32206 if (VM.VerifyAssertions) VM._assert(fits(imm,8));
32207 // no size prefix
32208 generateREXprefix(true, null, dstIndex, dstBase);
32209 if (imm == 1) {
32210 setMachineCodes(mi++, (byte) 0xD1);
32211 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
32212 } else {
32213 setMachineCodes(mi++, (byte) 0xC1);
32214 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
32215 emitImm8((byte)imm);
32216 }
32217 if (lister != null) lister.RXDI(miStart, "SAR", dstBase, dstIndex, dstScale, dstDisp, imm);
32218 }
32219
32220 /**
32221 * Generate a register--register SAR. That is,
32222 * <PRE>
32223 * arithemetic shift right of dstReg by srcReg
32224 * </PRE>
32225 *
32226 * @param dstReg the destination register
32227 * @param srcReg must always be ECX
32228 */
32229 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
32230 public final void emitSAR_Reg_Reg_Quad(GPR dstReg, GPR srcReg) {
32231 int miStart = mi;
32232 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
32233 // no size prefix
32234 generateREXprefix(true, null, null, dstReg);
32235 setMachineCodes(mi++, (byte) 0xD3);
32236 emitRegRegOperands(dstReg, GPR.getForOpcode(0x7));
32237 if (lister != null) lister.RR(miStart, "SAR", dstReg, srcReg);
32238 }
32239
32240 /**
32241 * Generate a register-indirect--register SAR. That is,
32242 * <PRE>
32243 * arithemetic shift right of [dstBase] by srcReg
32244 * </PRE>
32245 *
32246 * @param dstBase the destination register
32247 * @param srcReg must always be ECX
32248 */
32249 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
32250 public final void emitSAR_RegInd_Reg_Quad(GPR dstBase, GPR srcReg) {
32251 int miStart = mi;
32252 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
32253 // no size prefix
32254 generateREXprefix(true, null, null, dstBase);
32255 setMachineCodes(mi++, (byte) 0xD3);
32256 emitRegIndirectRegOperands(dstBase, GPR.getForOpcode(0x7));
32257 if (lister != null) lister.RNR(miStart, "SAR", dstBase, srcReg);
32258 }
32259
32260 /**
32261 * Generate a register-displacement--register SAR. That is,
32262 * <PRE>
32263 * arithemetic shift right of [dstBase + dstDisp] by srcReg
32264 * </PRE>
32265 *
32266 * @param dstBase the destination base register
32267 * @param dstDisp the destination displacement
32268 * @param srcReg must always be ECX
32269 */
32270 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
32271 public final void emitSAR_RegDisp_Reg_Quad(GPR dstBase, Offset dstDisp, GPR srcReg) {
32272 int miStart = mi;
32273 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
32274 // no size prefix
32275 generateREXprefix(true, null, null, dstBase);
32276 setMachineCodes(mi++, (byte) 0xD3);
32277 emitRegDispRegOperands(dstBase, dstDisp, GPR.getForOpcode(0x7));
32278 if (lister != null) lister.RDR(miStart, "SAR", dstBase, dstDisp, srcReg);
32279 }
32280
32281 /**
32282 * Generate a register-offset--register SAR. That is,
32283 * <PRE>
32284 * arithemetic shift right of [dstIndex<<dstScale + dstDisp] by srcReg
32285 * </PRE>
32286 *
32287 * @param dstIndex the destination index register
32288 * @param dstScale the destination shift amount
32289 * @param dstDisp the destination displacement
32290 * @param srcReg must always be ECX
32291 */
32292 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
32293 public final void emitSAR_RegOff_Reg_Quad(GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
32294 int miStart = mi;
32295 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
32296 // no size prefix
32297 generateREXprefix(true, null, dstIndex, null);
32298 setMachineCodes(mi++, (byte) 0xD3);
32299 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
32300 if (lister != null) lister.RFDR(miStart, "SAR", dstIndex, dstScale, dstDisp, srcReg);
32301 }
32302
32303 /**
32304 * Generate an absolute--register SAR. That is,
32305 * <PRE>
32306 * arithemetic shift right of [dstDisp] by srcReg
32307 * </PRE>
32308 *
32309 * @param dstDisp the destination displacement
32310 * @param srcReg must always be ECX
32311 */
32312 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
32313 public final void emitSAR_Abs_Reg_Quad(Address dstDisp, GPR srcReg) {
32314 int miStart = mi;
32315 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
32316 // no size prefix
32317 generateREXprefix(true, null, null, null);
32318 setMachineCodes(mi++, (byte) 0xD3);
32319 emitAbsRegOperands(dstDisp, GPR.getForOpcode(0x7));
32320 if (lister != null) lister.RAR(miStart, "SAR", dstDisp, srcReg);
32321 }
32322
32323 /**
32324 * Generate a register-displacement--register SAR. That is,
32325 * <PRE>
32326 * arithemetic shift right of [dstBase + dstIndex<<dstScale + dstDisp] by srcReg
32327 * </PRE>
32328 *
32329 * @param dstBase the destination base register
32330 * @param dstIndex the destination index register
32331 * @param dstScale the destination shift amount
32332 * @param dstDisp the destination displacement
32333 * @param srcReg must always be ECX
32334 */
32335 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
32336 public final void emitSAR_RegIdx_Reg_Quad(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, GPR srcReg) {
32337 int miStart = mi;
32338 if (VM.VerifyAssertions) VM._assert(srcReg == ECX);
32339 // no size prefix
32340 generateREXprefix(true, null, dstIndex, dstBase);
32341 setMachineCodes(mi++, (byte) 0xD3);
32342 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, GPR.getForOpcode(0x7));
32343 if (lister != null) lister.RXDR(miStart, "SAR", dstBase, dstIndex, dstScale, dstDisp, srcReg);
32344 }
32345
32346 /**
32347 * Generate a register--register--immediate SHLD. That is,
32348 * <PRE>
32349 * left <<= shiftBy (with bits from right shifted in)
32350 * </PRE>
32351 *
32352 * @param left the destination register
32353 * @param right the register containing bits that are shifted in
32354 * @param shiftBy the amount to shift by
32355 */
32356 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
32357 public final void emitSHLD_Reg_Reg_Imm(GPR left, GPR right, int shiftBy) {
32358 int miStart = mi;
32359 generateREXprefix(false, right, null, left);
32360 setMachineCodes(mi++, (byte) 0x0F);
32361 setMachineCodes(mi++, (byte) 0xA4);
32362 emitRegRegOperands(left, right);
32363 emitImm8((byte)shiftBy);
32364 if (lister != null) lister.RRI(miStart, "SHLD", left, right, shiftBy);
32365 }
32366
32367 /**
32368 * Generate a register-indirect--register--immediate SHLD. That is,
32369 * <PRE>
32370 * [left] <<= shiftBy (with bits from right shifted in)
32371 * </PRE>
32372 *
32373 * @param left the destination base register
32374 * @param right the register containing bits that are shifted in
32375 * @param shiftBy the amount to shift by
32376 */
32377 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
32378 public final void emitSHLD_RegInd_Reg_Imm(GPR left, GPR right, int shiftBy) {
32379 int miStart = mi;
32380 generateREXprefix(false, right, null, left);
32381 setMachineCodes(mi++, (byte) 0x0F);
32382 setMachineCodes(mi++, (byte) 0xA4);
32383 emitRegIndirectRegOperands(left, right);
32384 emitImm8((byte)shiftBy);
32385 if (lister != null) lister.RNRI(miStart, "SHLD", left, right, shiftBy);
32386 }
32387
32388 /**
32389 * Generate a register-displacement--register--immediate SHLD. That is,
32390 * <PRE>
32391 * [left + disp] <<= shiftBy (with bits from right shifted in)
32392 * </PRE>
32393 *
32394 * @param left the destination base register
32395 * @param disp the destination displacement
32396 * @param right the register containing bits that are shifted in
32397 * @param shiftBy the amount to shift by
32398 */
32399 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
32400 public final void emitSHLD_RegDisp_Reg_Imm(GPR left, Offset disp, GPR right, int shiftBy) {
32401 int miStart = mi;
32402 generateREXprefix(false, right, null, left);
32403 setMachineCodes(mi++, (byte) 0x0F);
32404 setMachineCodes(mi++, (byte) 0xA4);
32405 emitRegDispRegOperands(left, disp, right);
32406 emitImm8((byte)shiftBy);
32407 if (lister != null) lister.RDRI(miStart, "SHLD", left, disp, right, shiftBy);
32408 }
32409
32410 /**
32411 * Generate a register-index--register--immediate SHLD. That is,
32412 * <PRE>
32413 * [leftBase + leftIndex<<scale + disp] <<= shiftBy (with bits from right shifted in)
32414 * </PRE>
32415 *
32416 * @param leftBase the destination base register
32417 * @param leftIndex the destination index register
32418 * @param scale the destination scale
32419 * @param disp the destination displacement
32420 * @param right the register containing bits that are shifted in
32421 * @param shiftBy the amount to shift by
32422 */
32423 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
32424 public final void emitSHLD_RegIdx_Reg_Imm(GPR leftBase, GPR leftIndex, short scale, Offset disp, GPR right, int shiftBy) {
32425 int miStart = mi;
32426 generateREXprefix(false, right, leftIndex, leftBase);
32427 setMachineCodes(mi++, (byte) 0x0F);
32428 setMachineCodes(mi++, (byte) 0xA4);
32429 emitSIBRegOperands(leftBase, leftIndex, scale, disp, right);
32430 emitImm8((byte)shiftBy);
32431 if (lister != null) lister.RXDRI(miStart, "SHLD", leftBase, leftIndex, scale, disp, right, shiftBy);
32432 }
32433
32434 /**
32435 * Generate a register-offset--register--immediate SHLD. That is,
32436 * <PRE>
32437 * [leftIndex<<scale + disp] <<= shiftBy (with bits from right shifted in)
32438 * </PRE>
32439 *
32440 * @param leftIndex the destination index register
32441 * @param scale the destination scale
32442 * @param disp the destination displacement
32443 * @param right the register containing bits that are shifted in
32444 * @param shiftBy the amount to shift by
32445 */
32446 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
32447 public final void emitSHLD_RegOff_Reg_Imm(GPR leftIndex, short scale, Offset disp, GPR right, int shiftBy) {
32448 int miStart = mi;
32449 generateREXprefix(false, right, leftIndex, null);
32450 setMachineCodes(mi++, (byte) 0x0F);
32451 setMachineCodes(mi++, (byte) 0xA4);
32452 emitRegOffRegOperands(leftIndex, scale, disp, right);
32453 emitImm8((byte)shiftBy);
32454 if (lister != null) lister.RFDRI(miStart, "SHLD", leftIndex, scale, disp, right, shiftBy);
32455 }
32456
32457 /**
32458 * Generate an absolute--register--immediate SHLD. That is,
32459 * <PRE>
32460 * [disp] <<= shiftBy (with bits from right shifted in)
32461 * </PRE>
32462 *
32463 * @param disp the destination displacement
32464 * @param right the register containing bits that are shifted in
32465 * @param shiftBy the amount to shift by
32466 */
32467 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
32468 public final void emitSHLD_Abs_Reg_Imm(Address disp, GPR right, int shiftBy) {
32469 int miStart = mi;
32470 generateREXprefix(false, right, null, null);
32471 setMachineCodes(mi++, (byte) 0x0F);
32472 setMachineCodes(mi++, (byte) 0xA4);
32473 emitAbsRegOperands(disp, right);
32474 emitImm8((byte)shiftBy);
32475 if (lister != null) lister.RARI(miStart, "SHLD", disp, right, shiftBy);
32476 }
32477
32478 /**
32479 * Generate a register--register--register SHLD. That is,
32480 * <PRE>
32481 * left <<= shiftBy (with bits from right shifted in)
32482 * </PRE>
32483 *
32484 * @param left the destination register
32485 * @param right the register containing bits that are shifted in
32486 * @param shiftBy must be ECX
32487 */
32488 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
32489 public final void emitSHLD_Reg_Reg_Reg(GPR left, GPR right, GPR shiftBy) {
32490 if (VM.VerifyAssertions) VM._assert(shiftBy == ECX);
32491 int miStart = mi;
32492 generateREXprefix(false, right, null, left);
32493 setMachineCodes(mi++, (byte) 0x0F);
32494 setMachineCodes(mi++, (byte) 0xA5);
32495 emitRegRegOperands(left, right);
32496 if (lister != null) lister.RRR(miStart, "SHLD", left, right, shiftBy);
32497 }
32498
32499 /**
32500 * Generate a register-indirect--register--register SHLD. That is,
32501 * <PRE>
32502 * [left] <<= shiftBy (with bits from right shifted in)
32503 * </PRE>
32504 *
32505 * @param left the destination base register
32506 * @param right the register containing bits that are shifted in
32507 * @param shiftBy must be ECX
32508 */
32509 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
32510 public final void emitSHLD_RegInd_Reg_Reg(GPR left, GPR right, GPR shiftBy) {
32511 if (VM.VerifyAssertions) VM._assert(shiftBy == ECX);
32512 int miStart = mi;
32513 generateREXprefix(false, right, null, left);
32514 setMachineCodes(mi++, (byte) 0x0F);
32515 setMachineCodes(mi++, (byte) 0xA5);
32516 emitRegIndirectRegOperands(left, right);
32517 if (lister != null) lister.RNRR(miStart, "SHLD", left, right, shiftBy);
32518 }
32519
32520 /**
32521 * Generate a register-displacement--register--register SHLD. That is,
32522 * <PRE>
32523 * [left + disp] <<= shiftBy (with bits from right shifted in)
32524 * </PRE>
32525 *
32526 * @param left the destination base register
32527 * @param disp the destination displacement
32528 * @param right the register containing bits that are shifted in
32529 * @param shiftBy must be ECX
32530 */
32531 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3,4})
32532 public final void emitSHLD_RegDisp_Reg_Reg(GPR left, Offset disp, GPR right, GPR shiftBy) {
32533 if (VM.VerifyAssertions) VM._assert(shiftBy == ECX);
32534 int miStart = mi;
32535 generateREXprefix(false, right, null, left);
32536 setMachineCodes(mi++, (byte) 0x0F);
32537 setMachineCodes(mi++, (byte) 0xA5);
32538 emitRegDispRegOperands(left, disp, right);
32539 if (lister != null) lister.RDRR(miStart, "SHLD", left, disp, right, shiftBy);
32540 }
32541
32542 /**
32543 * Generate a register-index--register--register SHLD. That is,
32544 * <PRE>
32545 * [leftBase + leftIndex<<scale + disp] <<= shiftBy (with bits from right shifted in)
32546 * </PRE>
32547 *
32548 * @param leftBase the destination base register
32549 * @param leftIndex the destination index register
32550 * @param scale the destination scale
32551 * @param disp the destination displacement
32552 * @param right the register containing bits that are shifted in
32553 * @param shiftBy must be ECX
32554 */
32555 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5,6})
32556 public final void emitSHLD_RegIdx_Reg_Reg(GPR leftBase, GPR leftIndex, short scale, Offset disp, GPR right, GPR shiftBy) {
32557 if (VM.VerifyAssertions) VM._assert(shiftBy == ECX);
32558 int miStart = mi;
32559 generateREXprefix(false, right, leftIndex, leftBase);
32560 setMachineCodes(mi++, (byte) 0x0F);
32561 setMachineCodes(mi++, (byte) 0xA5);
32562 emitSIBRegOperands(leftBase, leftIndex, scale, disp, right);
32563 if (lister != null) lister.RXDRR(miStart, "SHLD", leftBase, leftIndex, scale, disp, right, shiftBy);
32564 }
32565
32566 /**
32567 * Generate a register-index--register--register SHLD. That is,
32568 * <PRE>
32569 * [leftIndex<<scale + disp] <<= shiftBy (with bits from right shifted in)
32570 * </PRE>
32571 *
32572 * @param leftIndex the destination index register
32573 * @param scale the destination scale
32574 * @param disp the destination displacement
32575 * @param right the register containing bits that are shifted in
32576 * @param shiftBy must be ECX
32577 */
32578 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4,5})
32579 public final void emitSHLD_RegOff_Reg_Reg(GPR leftIndex, short scale, Offset disp, GPR right, GPR shiftBy) {
32580 if (VM.VerifyAssertions) VM._assert(shiftBy == ECX);
32581 int miStart = mi;
32582 generateREXprefix(false, right, leftIndex, null);
32583 setMachineCodes(mi++, (byte) 0x0F);
32584 setMachineCodes(mi++, (byte) 0xA5);
32585 emitRegOffRegOperands(leftIndex, scale, disp, right);
32586 if (lister != null) lister.RFDRR(miStart, "SHLD", leftIndex, scale, disp, right, shiftBy);
32587 }
32588
32589 /**
32590 * Generate a register-index--register--register SHLD. That is,
32591 * <PRE>
32592 * [disp] <<= shiftBy (with bits from right shifted in)
32593 * </PRE>
32594 *
32595 * @param disp the destination displacement
32596 * @param right the register containing bits that are shifted in
32597 * @param shiftBy must be ECX
32598 */
32599 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2,3})
32600 public final void emitSHLD_Abs_Reg_Reg(Address disp, GPR right, GPR shiftBy) {
32601 if (VM.VerifyAssertions) VM._assert(shiftBy == ECX);
32602 int miStart = mi;
32603 generateREXprefix(false, right, null, null);
32604 setMachineCodes(mi++, (byte) 0x0F);
32605 setMachineCodes(mi++, (byte) 0xA5);
32606 emitAbsRegOperands(disp, right);
32607 if (lister != null) lister.RARR(miStart, "SHLD", disp, right, shiftBy);
32608 }
32609
32610 /**
32611 * Generate a register--register--immediate SHLD. That is,
32612 * <PRE>
32613 * left <<= shiftBy (with bits from right shifted in)
32614 * </PRE>
32615 *
32616 * @param left the destination register
32617 * @param right the register containing bits that are shifted in
32618 * @param shiftBy the amount to shift by
32619 */
32620 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
32621 public final void emitSHLD_Reg_Reg_Imm_Quad(GPR left, GPR right, int shiftBy) {
32622 int miStart = mi;
32623 generateREXprefix(true, right, null, left);
32624 setMachineCodes(mi++, (byte) 0x0F);
32625 setMachineCodes(mi++, (byte) 0xA4);
32626 emitRegRegOperands(left, right);
32627 emitImm8((byte)shiftBy);
32628 if (lister != null) lister.RRI(miStart, "SHLD", left, right, shiftBy);
32629 }
32630
32631 /**
32632 * Generate a register-indirect--register--immediate SHLD. That is,
32633 * <PRE>
32634 * [left] <<= shiftBy (with bits from right shifted in)
32635 * </PRE>
32636 *
32637 * @param left the destination base register
32638 * @param right the register containing bits that are shifted in
32639 * @param shiftBy the amount to shift by
32640 */
32641 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
32642 public final void emitSHLD_RegInd_Reg_Imm_Quad(GPR left, GPR right, int shiftBy) {
32643 int miStart = mi;
32644 generateREXprefix(true, right, null, left);
32645 setMachineCodes(mi++, (byte) 0x0F);
32646 setMachineCodes(mi++, (byte) 0xA4);
32647 emitRegIndirectRegOperands(left, right);
32648 emitImm8((byte)shiftBy);
32649 if (lister != null) lister.RNRI(miStart, "SHLD", left, right, shiftBy);
32650 }
32651
32652 /**
32653 * Generate a register-displacement--register--immediate SHLD. That is,
32654 * <PRE>
32655 * [left + disp] <<= shiftBy (with bits from right shifted in)
32656 * </PRE>
32657 *
32658 * @param left the destination base register
32659 * @param disp the destination displacement
32660 * @param right the register containing bits that are shifted in
32661 * @param shiftBy the amount to shift by
32662 */
32663 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
32664 public final void emitSHLD_RegDisp_Reg_Imm_Quad(GPR left, Offset disp, GPR right, int shiftBy) {
32665 int miStart = mi;
32666 generateREXprefix(true, right, null, left);
32667 setMachineCodes(mi++, (byte) 0x0F);
32668 setMachineCodes(mi++, (byte) 0xA4);
32669 emitRegDispRegOperands(left, disp, right);
32670 emitImm8((byte)shiftBy);
32671 if (lister != null) lister.RDRI(miStart, "SHLD", left, disp, right, shiftBy);
32672 }
32673
32674 /**
32675 * Generate a register-index--register--immediate SHLD. That is,
32676 * <PRE>
32677 * [leftBase + leftIndex<<scale + disp] <<= shiftBy (with bits from right shifted in)
32678 * </PRE>
32679 *
32680 * @param leftBase the destination base register
32681 * @param leftIndex the destination index register
32682 * @param scale the destination scale
32683 * @param disp the destination displacement
32684 * @param right the register containing bits that are shifted in
32685 * @param shiftBy the amount to shift by
32686 */
32687 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
32688 public final void emitSHLD_RegIdx_Reg_Imm_Quad(GPR leftBase, GPR leftIndex, short scale, Offset disp, GPR right, int shiftBy) {
32689 int miStart = mi;
32690 generateREXprefix(true, right, leftIndex, leftBase);
32691 setMachineCodes(mi++, (byte) 0x0F);
32692 setMachineCodes(mi++, (byte) 0xA4);
32693 emitSIBRegOperands(leftBase, leftIndex, scale, disp, right);
32694 emitImm8((byte)shiftBy);
32695 if (lister != null) lister.RXDRI(miStart, "SHLD", leftBase, leftIndex, scale, disp, right, shiftBy);
32696 }
32697
32698 /**
32699 * Generate a register-offset--register--immediate SHLD. That is,
32700 * <PRE>
32701 * [leftIndex<<scale + disp] <<= shiftBy (with bits from right shifted in)
32702 * </PRE>
32703 *
32704 * @param leftIndex the destination index register
32705 * @param scale the destination scale
32706 * @param disp the destination displacement
32707 * @param right the register containing bits that are shifted in
32708 * @param shiftBy the amount to shift by
32709 */
32710 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
32711 public final void emitSHLD_RegOff_Reg_Imm_Quad(GPR leftIndex, short scale, Offset disp, GPR right, int shiftBy) {
32712 int miStart = mi;
32713 generateREXprefix(true, right, leftIndex, null);
32714 setMachineCodes(mi++, (byte) 0x0F);
32715 setMachineCodes(mi++, (byte) 0xA4);
32716 emitRegOffRegOperands(leftIndex, scale, disp, right);
32717 emitImm8((byte)shiftBy);
32718 if (lister != null) lister.RFDRI(miStart, "SHLD", leftIndex, scale, disp, right, shiftBy);
32719 }
32720
32721 /**
32722 * Generate an absolute--register--immediate SHLD. That is,
32723 * <PRE>
32724 * [disp] <<= shiftBy (with bits from right shifted in)
32725 * </PRE>
32726 *
32727 * @param disp the destination displacement
32728 * @param right the register containing bits that are shifted in
32729 * @param shiftBy the amount to shift by
32730 */
32731 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
32732 public final void emitSHLD_Abs_Reg_Imm_Quad(Address disp, GPR right, int shiftBy) {
32733 int miStart = mi;
32734 generateREXprefix(true, right, null, null);
32735 setMachineCodes(mi++, (byte) 0x0F);
32736 setMachineCodes(mi++, (byte) 0xA4);
32737 emitAbsRegOperands(disp, right);
32738 emitImm8((byte)shiftBy);
32739 if (lister != null) lister.RARI(miStart, "SHLD", disp, right, shiftBy);
32740 }
32741
32742 /**
32743 * Generate a register--register--register SHLD. That is,
32744 * <PRE>
32745 * left <<= shiftBy (with bits from right shifted in)
32746 * </PRE>
32747 *
32748 * @param left the destination register
32749 * @param right the register containing bits that are shifted in
32750 * @param shiftBy must be ECX
32751 */
32752 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
32753 public final void emitSHLD_Reg_Reg_Reg_Quad(GPR left, GPR right, GPR shiftBy) {
32754 if (VM.VerifyAssertions) VM._assert(shiftBy == ECX);
32755 int miStart = mi;
32756 generateREXprefix(true, right, null, left);
32757 setMachineCodes(mi++, (byte) 0x0F);
32758 setMachineCodes(mi++, (byte) 0xA5);
32759 emitRegRegOperands(left, right);
32760 if (lister != null) lister.RRR(miStart, "SHLD", left, right, shiftBy);
32761 }
32762
32763 /**
32764 * Generate a register-indirect--register--register SHLD. That is,
32765 * <PRE>
32766 * [left] <<= shiftBy (with bits from right shifted in)
32767 * </PRE>
32768 *
32769 * @param left the destination base register
32770 * @param right the register containing bits that are shifted in
32771 * @param shiftBy must be ECX
32772 */
32773 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
32774 public final void emitSHLD_RegInd_Reg_Reg_Quad(GPR left, GPR right, GPR shiftBy) {
32775 if (VM.VerifyAssertions) VM._assert(shiftBy == ECX);
32776 int miStart = mi;
32777 generateREXprefix(true, right, null, left);
32778 setMachineCodes(mi++, (byte) 0x0F);
32779 setMachineCodes(mi++, (byte) 0xA5);
32780 emitRegIndirectRegOperands(left, right);
32781 if (lister != null) lister.RNRR(miStart, "SHLD", left, right, shiftBy);
32782 }
32783
32784 /**
32785 * Generate a register-displacement--register--register SHLD. That is,
32786 * <PRE>
32787 * [left + disp] <<= shiftBy (with bits from right shifted in)
32788 * </PRE>
32789 *
32790 * @param left the destination base register
32791 * @param disp the destination displacement
32792 * @param right the register containing bits that are shifted in
32793 * @param shiftBy must be ECX
32794 */
32795 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3,4})
32796 public final void emitSHLD_RegDisp_Reg_Reg_Quad(GPR left, Offset disp, GPR right, GPR shiftBy) {
32797 if (VM.VerifyAssertions) VM._assert(shiftBy == ECX);
32798 int miStart = mi;
32799 generateREXprefix(true, right, null, left);
32800 setMachineCodes(mi++, (byte) 0x0F);
32801 setMachineCodes(mi++, (byte) 0xA5);
32802 emitRegDispRegOperands(left, disp, right);
32803 if (lister != null) lister.RDRR(miStart, "SHLD", left, disp, right, shiftBy);
32804 }
32805
32806 /**
32807 * Generate a register-index--register--register SHLD. That is,
32808 * <PRE>
32809 * [leftBase + leftIndex<<scale + disp] <<= shiftBy (with bits from right shifted in)
32810 * </PRE>
32811 *
32812 * @param leftBase the destination base register
32813 * @param leftIndex the destination index register
32814 * @param scale the destination scale
32815 * @param disp the destination displacement
32816 * @param right the register containing bits that are shifted in
32817 * @param shiftBy must be ECX
32818 */
32819 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5,6})
32820 public final void emitSHLD_RegIdx_Reg_Reg_Quad(GPR leftBase, GPR leftIndex, short scale, Offset disp, GPR right, GPR shiftBy) {
32821 if (VM.VerifyAssertions) VM._assert(shiftBy == ECX);
32822 int miStart = mi;
32823 generateREXprefix(true, right, leftIndex, leftBase);
32824 setMachineCodes(mi++, (byte) 0x0F);
32825 setMachineCodes(mi++, (byte) 0xA5);
32826 emitSIBRegOperands(leftBase, leftIndex, scale, disp, right);
32827 if (lister != null) lister.RXDRR(miStart, "SHLD", leftBase, leftIndex, scale, disp, right, shiftBy);
32828 }
32829
32830 /**
32831 * Generate a register-index--register--register SHLD. That is,
32832 * <PRE>
32833 * [leftIndex<<scale + disp] <<= shiftBy (with bits from right shifted in)
32834 * </PRE>
32835 *
32836 * @param leftIndex the destination index register
32837 * @param scale the destination scale
32838 * @param disp the destination displacement
32839 * @param right the register containing bits that are shifted in
32840 * @param shiftBy must be ECX
32841 */
32842 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4,5})
32843 public final void emitSHLD_RegOff_Reg_Reg_Quad(GPR leftIndex, short scale, Offset disp, GPR right, GPR shiftBy) {
32844 if (VM.VerifyAssertions) VM._assert(shiftBy == ECX);
32845 int miStart = mi;
32846 generateREXprefix(true, right, leftIndex, null);
32847 setMachineCodes(mi++, (byte) 0x0F);
32848 setMachineCodes(mi++, (byte) 0xA5);
32849 emitRegOffRegOperands(leftIndex, scale, disp, right);
32850 if (lister != null) lister.RFDRR(miStart, "SHLD", leftIndex, scale, disp, right, shiftBy);
32851 }
32852
32853 /**
32854 * Generate a register-index--register--register SHLD. That is,
32855 * <PRE>
32856 * [disp] <<= shiftBy (with bits from right shifted in)
32857 * </PRE>
32858 *
32859 * @param disp the destination displacement
32860 * @param right the register containing bits that are shifted in
32861 * @param shiftBy must be ECX
32862 */
32863 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2,3})
32864 public final void emitSHLD_Abs_Reg_Reg_Quad(Address disp, GPR right, GPR shiftBy) {
32865 if (VM.VerifyAssertions) VM._assert(shiftBy == ECX);
32866 int miStart = mi;
32867 generateREXprefix(true, right, null, null);
32868 setMachineCodes(mi++, (byte) 0x0F);
32869 setMachineCodes(mi++, (byte) 0xA5);
32870 emitAbsRegOperands(disp, right);
32871 if (lister != null) lister.RARR(miStart, "SHLD", disp, right, shiftBy);
32872 }
32873
32874 /**
32875 * Generate a register--register--immediate SHRD. That is,
32876 * <PRE>
32877 * left <<= shiftBy (with bits from right shifted in)
32878 * </PRE>
32879 *
32880 * @param left the destination register
32881 * @param right the register containing bits that are shifted in
32882 * @param shiftBy the amount to shift by
32883 */
32884 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
32885 public final void emitSHRD_Reg_Reg_Imm(GPR left, GPR right, int shiftBy) {
32886 int miStart = mi;
32887 generateREXprefix(false, right, null, left);
32888 setMachineCodes(mi++, (byte) 0x0F);
32889 setMachineCodes(mi++, (byte) 0xAC);
32890 emitRegRegOperands(left, right);
32891 emitImm8((byte)shiftBy);
32892 if (lister != null) lister.RRI(miStart, "SHRD", left, right, shiftBy);
32893 }
32894
32895 /**
32896 * Generate a register-indirect--register--immediate SHRD. That is,
32897 * <PRE>
32898 * [left] <<= shiftBy (with bits from right shifted in)
32899 * </PRE>
32900 *
32901 * @param left the destination base register
32902 * @param right the register containing bits that are shifted in
32903 * @param shiftBy the amount to shift by
32904 */
32905 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
32906 public final void emitSHRD_RegInd_Reg_Imm(GPR left, GPR right, int shiftBy) {
32907 int miStart = mi;
32908 generateREXprefix(false, right, null, left);
32909 setMachineCodes(mi++, (byte) 0x0F);
32910 setMachineCodes(mi++, (byte) 0xAC);
32911 emitRegIndirectRegOperands(left, right);
32912 emitImm8((byte)shiftBy);
32913 if (lister != null) lister.RNRI(miStart, "SHRD", left, right, shiftBy);
32914 }
32915
32916 /**
32917 * Generate a register-displacement--register--immediate SHRD. That is,
32918 * <PRE>
32919 * [left + disp] <<= shiftBy (with bits from right shifted in)
32920 * </PRE>
32921 *
32922 * @param left the destination base register
32923 * @param disp the destination displacement
32924 * @param right the register containing bits that are shifted in
32925 * @param shiftBy the amount to shift by
32926 */
32927 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
32928 public final void emitSHRD_RegDisp_Reg_Imm(GPR left, Offset disp, GPR right, int shiftBy) {
32929 int miStart = mi;
32930 generateREXprefix(false, right, null, left);
32931 setMachineCodes(mi++, (byte) 0x0F);
32932 setMachineCodes(mi++, (byte) 0xAC);
32933 emitRegDispRegOperands(left, disp, right);
32934 emitImm8((byte)shiftBy);
32935 if (lister != null) lister.RDRI(miStart, "SHRD", left, disp, right, shiftBy);
32936 }
32937
32938 /**
32939 * Generate a register-index--register--immediate SHRD. That is,
32940 * <PRE>
32941 * [leftBase + leftIndex<<scale + disp] <<= shiftBy (with bits from right shifted in)
32942 * </PRE>
32943 *
32944 * @param leftBase the destination base register
32945 * @param leftIndex the destination index register
32946 * @param scale the destination scale
32947 * @param disp the destination displacement
32948 * @param right the register containing bits that are shifted in
32949 * @param shiftBy the amount to shift by
32950 */
32951 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
32952 public final void emitSHRD_RegIdx_Reg_Imm(GPR leftBase, GPR leftIndex, short scale, Offset disp, GPR right, int shiftBy) {
32953 int miStart = mi;
32954 generateREXprefix(false, right, leftIndex, leftBase);
32955 setMachineCodes(mi++, (byte) 0x0F);
32956 setMachineCodes(mi++, (byte) 0xAC);
32957 emitSIBRegOperands(leftBase, leftIndex, scale, disp, right);
32958 emitImm8((byte)shiftBy);
32959 if (lister != null) lister.RXDRI(miStart, "SHRD", leftBase, leftIndex, scale, disp, right, shiftBy);
32960 }
32961
32962 /**
32963 * Generate a register-offset--register--immediate SHRD. That is,
32964 * <PRE>
32965 * [leftIndex<<scale + disp] <<= shiftBy (with bits from right shifted in)
32966 * </PRE>
32967 *
32968 * @param leftIndex the destination index register
32969 * @param scale the destination scale
32970 * @param disp the destination displacement
32971 * @param right the register containing bits that are shifted in
32972 * @param shiftBy the amount to shift by
32973 */
32974 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
32975 public final void emitSHRD_RegOff_Reg_Imm(GPR leftIndex, short scale, Offset disp, GPR right, int shiftBy) {
32976 int miStart = mi;
32977 generateREXprefix(false, right, leftIndex, null);
32978 setMachineCodes(mi++, (byte) 0x0F);
32979 setMachineCodes(mi++, (byte) 0xAC);
32980 emitRegOffRegOperands(leftIndex, scale, disp, right);
32981 emitImm8((byte)shiftBy);
32982 if (lister != null) lister.RFDRI(miStart, "SHRD", leftIndex, scale, disp, right, shiftBy);
32983 }
32984
32985 /**
32986 * Generate an absolute--register--immediate SHRD. That is,
32987 * <PRE>
32988 * [disp] <<= shiftBy (with bits from right shifted in)
32989 * </PRE>
32990 *
32991 * @param disp the destination displacement
32992 * @param right the register containing bits that are shifted in
32993 * @param shiftBy the amount to shift by
32994 */
32995 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
32996 public final void emitSHRD_Abs_Reg_Imm(Address disp, GPR right, int shiftBy) {
32997 int miStart = mi;
32998 generateREXprefix(false, right, null, null);
32999 setMachineCodes(mi++, (byte) 0x0F);
33000 setMachineCodes(mi++, (byte) 0xAC);
33001 emitAbsRegOperands(disp, right);
33002 emitImm8((byte)shiftBy);
33003 if (lister != null) lister.RARI(miStart, "SHRD", disp, right, shiftBy);
33004 }
33005
33006 /**
33007 * Generate a register--register--register SHRD. That is,
33008 * <PRE>
33009 * left <<= shiftBy (with bits from right shifted in)
33010 * </PRE>
33011 *
33012 * @param left the destination register
33013 * @param right the register containing bits that are shifted in
33014 * @param shiftBy must be ECX
33015 */
33016 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
33017 public final void emitSHRD_Reg_Reg_Reg(GPR left, GPR right, GPR shiftBy) {
33018 if (VM.VerifyAssertions) VM._assert(shiftBy == ECX);
33019 int miStart = mi;
33020 generateREXprefix(false, right, null, left);
33021 setMachineCodes(mi++, (byte) 0x0F);
33022 setMachineCodes(mi++, (byte) 0xAD);
33023 emitRegRegOperands(left, right);
33024 if (lister != null) lister.RRR(miStart, "SHRD", left, right, shiftBy);
33025 }
33026
33027 /**
33028 * Generate a register-indirect--register--register SHRD. That is,
33029 * <PRE>
33030 * [left] <<= shiftBy (with bits from right shifted in)
33031 * </PRE>
33032 *
33033 * @param left the destination base register
33034 * @param right the register containing bits that are shifted in
33035 * @param shiftBy must be ECX
33036 */
33037 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
33038 public final void emitSHRD_RegInd_Reg_Reg(GPR left, GPR right, GPR shiftBy) {
33039 if (VM.VerifyAssertions) VM._assert(shiftBy == ECX);
33040 int miStart = mi;
33041 generateREXprefix(false, right, null, left);
33042 setMachineCodes(mi++, (byte) 0x0F);
33043 setMachineCodes(mi++, (byte) 0xAD);
33044 emitRegIndirectRegOperands(left, right);
33045 if (lister != null) lister.RNRR(miStart, "SHRD", left, right, shiftBy);
33046 }
33047
33048 /**
33049 * Generate a register-displacement--register--register SHRD. That is,
33050 * <PRE>
33051 * [left + disp] <<= shiftBy (with bits from right shifted in)
33052 * </PRE>
33053 *
33054 * @param left the destination base register
33055 * @param disp the destination displacement
33056 * @param right the register containing bits that are shifted in
33057 * @param shiftBy must be ECX
33058 */
33059 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3,4})
33060 public final void emitSHRD_RegDisp_Reg_Reg(GPR left, Offset disp, GPR right, GPR shiftBy) {
33061 if (VM.VerifyAssertions) VM._assert(shiftBy == ECX);
33062 int miStart = mi;
33063 generateREXprefix(false, right, null, left);
33064 setMachineCodes(mi++, (byte) 0x0F);
33065 setMachineCodes(mi++, (byte) 0xAD);
33066 emitRegDispRegOperands(left, disp, right);
33067 if (lister != null) lister.RDRR(miStart, "SHRD", left, disp, right, shiftBy);
33068 }
33069
33070 /**
33071 * Generate a register-index--register--register SHRD. That is,
33072 * <PRE>
33073 * [leftBase + leftIndex<<scale + disp] <<= shiftBy (with bits from right shifted in)
33074 * </PRE>
33075 *
33076 * @param leftBase the destination base register
33077 * @param leftIndex the destination index register
33078 * @param scale the destination scale
33079 * @param disp the destination displacement
33080 * @param right the register containing bits that are shifted in
33081 * @param shiftBy must be ECX
33082 */
33083 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5,6})
33084 public final void emitSHRD_RegIdx_Reg_Reg(GPR leftBase, GPR leftIndex, short scale, Offset disp, GPR right, GPR shiftBy) {
33085 if (VM.VerifyAssertions) VM._assert(shiftBy == ECX);
33086 int miStart = mi;
33087 generateREXprefix(false, right, leftIndex, leftBase);
33088 setMachineCodes(mi++, (byte) 0x0F);
33089 setMachineCodes(mi++, (byte) 0xAD);
33090 emitSIBRegOperands(leftBase, leftIndex, scale, disp, right);
33091 if (lister != null) lister.RXDRR(miStart, "SHRD", leftBase, leftIndex, scale, disp, right, shiftBy);
33092 }
33093
33094 /**
33095 * Generate a register-index--register--register SHRD. That is,
33096 * <PRE>
33097 * [leftIndex<<scale + disp] <<= shiftBy (with bits from right shifted in)
33098 * </PRE>
33099 *
33100 * @param leftIndex the destination index register
33101 * @param scale the destination scale
33102 * @param disp the destination displacement
33103 * @param right the register containing bits that are shifted in
33104 * @param shiftBy must be ECX
33105 */
33106 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4,5})
33107 public final void emitSHRD_RegOff_Reg_Reg(GPR leftIndex, short scale, Offset disp, GPR right, GPR shiftBy) {
33108 if (VM.VerifyAssertions) VM._assert(shiftBy == ECX);
33109 int miStart = mi;
33110 generateREXprefix(false, right, leftIndex, null);
33111 setMachineCodes(mi++, (byte) 0x0F);
33112 setMachineCodes(mi++, (byte) 0xAD);
33113 emitRegOffRegOperands(leftIndex, scale, disp, right);
33114 if (lister != null) lister.RFDRR(miStart, "SHRD", leftIndex, scale, disp, right, shiftBy);
33115 }
33116
33117 /**
33118 * Generate a register-index--register--register SHRD. That is,
33119 * <PRE>
33120 * [disp] <<= shiftBy (with bits from right shifted in)
33121 * </PRE>
33122 *
33123 * @param disp the destination displacement
33124 * @param right the register containing bits that are shifted in
33125 * @param shiftBy must be ECX
33126 */
33127 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2,3})
33128 public final void emitSHRD_Abs_Reg_Reg(Address disp, GPR right, GPR shiftBy) {
33129 if (VM.VerifyAssertions) VM._assert(shiftBy == ECX);
33130 int miStart = mi;
33131 generateREXprefix(false, right, null, null);
33132 setMachineCodes(mi++, (byte) 0x0F);
33133 setMachineCodes(mi++, (byte) 0xAD);
33134 emitAbsRegOperands(disp, right);
33135 if (lister != null) lister.RARR(miStart, "SHRD", disp, right, shiftBy);
33136 }
33137
33138 /**
33139 * Generate a register--register--immediate SHRD. That is,
33140 * <PRE>
33141 * left <<= shiftBy (with bits from right shifted in)
33142 * </PRE>
33143 *
33144 * @param left the destination register
33145 * @param right the register containing bits that are shifted in
33146 * @param shiftBy the amount to shift by
33147 */
33148 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
33149 public final void emitSHRD_Reg_Reg_Imm_Quad(GPR left, GPR right, int shiftBy) {
33150 int miStart = mi;
33151 generateREXprefix(true, right, null, left);
33152 setMachineCodes(mi++, (byte) 0x0F);
33153 setMachineCodes(mi++, (byte) 0xAC);
33154 emitRegRegOperands(left, right);
33155 emitImm8((byte)shiftBy);
33156 if (lister != null) lister.RRI(miStart, "SHRD", left, right, shiftBy);
33157 }
33158
33159 /**
33160 * Generate a register-indirect--register--immediate SHRD. That is,
33161 * <PRE>
33162 * [left] <<= shiftBy (with bits from right shifted in)
33163 * </PRE>
33164 *
33165 * @param left the destination base register
33166 * @param right the register containing bits that are shifted in
33167 * @param shiftBy the amount to shift by
33168 */
33169 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
33170 public final void emitSHRD_RegInd_Reg_Imm_Quad(GPR left, GPR right, int shiftBy) {
33171 int miStart = mi;
33172 generateREXprefix(true, right, null, left);
33173 setMachineCodes(mi++, (byte) 0x0F);
33174 setMachineCodes(mi++, (byte) 0xAC);
33175 emitRegIndirectRegOperands(left, right);
33176 emitImm8((byte)shiftBy);
33177 if (lister != null) lister.RNRI(miStart, "SHRD", left, right, shiftBy);
33178 }
33179
33180 /**
33181 * Generate a register-displacement--register--immediate SHRD. That is,
33182 * <PRE>
33183 * [left + disp] <<= shiftBy (with bits from right shifted in)
33184 * </PRE>
33185 *
33186 * @param left the destination base register
33187 * @param disp the destination displacement
33188 * @param right the register containing bits that are shifted in
33189 * @param shiftBy the amount to shift by
33190 */
33191 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
33192 public final void emitSHRD_RegDisp_Reg_Imm_Quad(GPR left, Offset disp, GPR right, int shiftBy) {
33193 int miStart = mi;
33194 generateREXprefix(true, right, null, left);
33195 setMachineCodes(mi++, (byte) 0x0F);
33196 setMachineCodes(mi++, (byte) 0xAC);
33197 emitRegDispRegOperands(left, disp, right);
33198 emitImm8((byte)shiftBy);
33199 if (lister != null) lister.RDRI(miStart, "SHRD", left, disp, right, shiftBy);
33200 }
33201
33202 /**
33203 * Generate a register-index--register--immediate SHRD. That is,
33204 * <PRE>
33205 * [leftBase + leftIndex<<scale + disp] <<= shiftBy (with bits from right shifted in)
33206 * </PRE>
33207 *
33208 * @param leftBase the destination base register
33209 * @param leftIndex the destination index register
33210 * @param scale the destination scale
33211 * @param disp the destination displacement
33212 * @param right the register containing bits that are shifted in
33213 * @param shiftBy the amount to shift by
33214 */
33215 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
33216 public final void emitSHRD_RegIdx_Reg_Imm_Quad(GPR leftBase, GPR leftIndex, short scale, Offset disp, GPR right, int shiftBy) {
33217 int miStart = mi;
33218 generateREXprefix(true, right, leftIndex, leftBase);
33219 setMachineCodes(mi++, (byte) 0x0F);
33220 setMachineCodes(mi++, (byte) 0xAC);
33221 emitSIBRegOperands(leftBase, leftIndex, scale, disp, right);
33222 emitImm8((byte)shiftBy);
33223 if (lister != null) lister.RXDRI(miStart, "SHRD", leftBase, leftIndex, scale, disp, right, shiftBy);
33224 }
33225
33226 /**
33227 * Generate a register-offset--register--immediate SHRD. That is,
33228 * <PRE>
33229 * [leftIndex<<scale + disp] <<= shiftBy (with bits from right shifted in)
33230 * </PRE>
33231 *
33232 * @param leftIndex the destination index register
33233 * @param scale the destination scale
33234 * @param disp the destination displacement
33235 * @param right the register containing bits that are shifted in
33236 * @param shiftBy the amount to shift by
33237 */
33238 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
33239 public final void emitSHRD_RegOff_Reg_Imm_Quad(GPR leftIndex, short scale, Offset disp, GPR right, int shiftBy) {
33240 int miStart = mi;
33241 generateREXprefix(true, right, leftIndex, null);
33242 setMachineCodes(mi++, (byte) 0x0F);
33243 setMachineCodes(mi++, (byte) 0xAC);
33244 emitRegOffRegOperands(leftIndex, scale, disp, right);
33245 emitImm8((byte)shiftBy);
33246 if (lister != null) lister.RFDRI(miStart, "SHRD", leftIndex, scale, disp, right, shiftBy);
33247 }
33248
33249 /**
33250 * Generate an absolute--register--immediate SHRD. That is,
33251 * <PRE>
33252 * [disp] <<= shiftBy (with bits from right shifted in)
33253 * </PRE>
33254 *
33255 * @param disp the destination displacement
33256 * @param right the register containing bits that are shifted in
33257 * @param shiftBy the amount to shift by
33258 */
33259 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
33260 public final void emitSHRD_Abs_Reg_Imm_Quad(Address disp, GPR right, int shiftBy) {
33261 int miStart = mi;
33262 generateREXprefix(true, right, null, null);
33263 setMachineCodes(mi++, (byte) 0x0F);
33264 setMachineCodes(mi++, (byte) 0xAC);
33265 emitAbsRegOperands(disp, right);
33266 emitImm8((byte)shiftBy);
33267 if (lister != null) lister.RARI(miStart, "SHRD", disp, right, shiftBy);
33268 }
33269
33270 /**
33271 * Generate a register--register--register SHRD. That is,
33272 * <PRE>
33273 * left <<= shiftBy (with bits from right shifted in)
33274 * </PRE>
33275 *
33276 * @param left the destination register
33277 * @param right the register containing bits that are shifted in
33278 * @param shiftBy must be ECX
33279 */
33280 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
33281 public final void emitSHRD_Reg_Reg_Reg_Quad(GPR left, GPR right, GPR shiftBy) {
33282 if (VM.VerifyAssertions) VM._assert(shiftBy == ECX);
33283 int miStart = mi;
33284 generateREXprefix(true, right, null, left);
33285 setMachineCodes(mi++, (byte) 0x0F);
33286 setMachineCodes(mi++, (byte) 0xAD);
33287 emitRegRegOperands(left, right);
33288 if (lister != null) lister.RRR(miStart, "SHRD", left, right, shiftBy);
33289 }
33290
33291 /**
33292 * Generate a register-indirect--register--register SHRD. That is,
33293 * <PRE>
33294 * [left] <<= shiftBy (with bits from right shifted in)
33295 * </PRE>
33296 *
33297 * @param left the destination base register
33298 * @param right the register containing bits that are shifted in
33299 * @param shiftBy must be ECX
33300 */
33301 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
33302 public final void emitSHRD_RegInd_Reg_Reg_Quad(GPR left, GPR right, GPR shiftBy) {
33303 if (VM.VerifyAssertions) VM._assert(shiftBy == ECX);
33304 int miStart = mi;
33305 generateREXprefix(true, right, null, left);
33306 setMachineCodes(mi++, (byte) 0x0F);
33307 setMachineCodes(mi++, (byte) 0xAD);
33308 emitRegIndirectRegOperands(left, right);
33309 if (lister != null) lister.RNRR(miStart, "SHRD", left, right, shiftBy);
33310 }
33311
33312 /**
33313 * Generate a register-displacement--register--register SHRD. That is,
33314 * <PRE>
33315 * [left + disp] <<= shiftBy (with bits from right shifted in)
33316 * </PRE>
33317 *
33318 * @param left the destination base register
33319 * @param disp the destination displacement
33320 * @param right the register containing bits that are shifted in
33321 * @param shiftBy must be ECX
33322 */
33323 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3,4})
33324 public final void emitSHRD_RegDisp_Reg_Reg_Quad(GPR left, Offset disp, GPR right, GPR shiftBy) {
33325 if (VM.VerifyAssertions) VM._assert(shiftBy == ECX);
33326 int miStart = mi;
33327 generateREXprefix(true, right, null, left);
33328 setMachineCodes(mi++, (byte) 0x0F);
33329 setMachineCodes(mi++, (byte) 0xAD);
33330 emitRegDispRegOperands(left, disp, right);
33331 if (lister != null) lister.RDRR(miStart, "SHRD", left, disp, right, shiftBy);
33332 }
33333
33334 /**
33335 * Generate a register-index--register--register SHRD. That is,
33336 * <PRE>
33337 * [leftBase + leftIndex<<scale + disp] <<= shiftBy (with bits from right shifted in)
33338 * </PRE>
33339 *
33340 * @param leftBase the destination base register
33341 * @param leftIndex the destination index register
33342 * @param scale the destination scale
33343 * @param disp the destination displacement
33344 * @param right the register containing bits that are shifted in
33345 * @param shiftBy must be ECX
33346 */
33347 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5,6})
33348 public final void emitSHRD_RegIdx_Reg_Reg_Quad(GPR leftBase, GPR leftIndex, short scale, Offset disp, GPR right, GPR shiftBy) {
33349 if (VM.VerifyAssertions) VM._assert(shiftBy == ECX);
33350 int miStart = mi;
33351 generateREXprefix(true, right, leftIndex, leftBase);
33352 setMachineCodes(mi++, (byte) 0x0F);
33353 setMachineCodes(mi++, (byte) 0xAD);
33354 emitSIBRegOperands(leftBase, leftIndex, scale, disp, right);
33355 if (lister != null) lister.RXDRR(miStart, "SHRD", leftBase, leftIndex, scale, disp, right, shiftBy);
33356 }
33357
33358 /**
33359 * Generate a register-index--register--register SHRD. That is,
33360 * <PRE>
33361 * [leftIndex<<scale + disp] <<= shiftBy (with bits from right shifted in)
33362 * </PRE>
33363 *
33364 * @param leftIndex the destination index register
33365 * @param scale the destination scale
33366 * @param disp the destination displacement
33367 * @param right the register containing bits that are shifted in
33368 * @param shiftBy must be ECX
33369 */
33370 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4,5})
33371 public final void emitSHRD_RegOff_Reg_Reg_Quad(GPR leftIndex, short scale, Offset disp, GPR right, GPR shiftBy) {
33372 if (VM.VerifyAssertions) VM._assert(shiftBy == ECX);
33373 int miStart = mi;
33374 generateREXprefix(true, right, leftIndex, null);
33375 setMachineCodes(mi++, (byte) 0x0F);
33376 setMachineCodes(mi++, (byte) 0xAD);
33377 emitRegOffRegOperands(leftIndex, scale, disp, right);
33378 if (lister != null) lister.RFDRR(miStart, "SHRD", leftIndex, scale, disp, right, shiftBy);
33379 }
33380
33381 /**
33382 * Generate a register-index--register--register SHRD. That is,
33383 * <PRE>
33384 * [disp] <<= shiftBy (with bits from right shifted in)
33385 * </PRE>
33386 *
33387 * @param disp the destination displacement
33388 * @param right the register containing bits that are shifted in
33389 * @param shiftBy must be ECX
33390 */
33391 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2,3})
33392 public final void emitSHRD_Abs_Reg_Reg_Quad(Address disp, GPR right, GPR shiftBy) {
33393 if (VM.VerifyAssertions) VM._assert(shiftBy == ECX);
33394 int miStart = mi;
33395 generateREXprefix(true, right, null, null);
33396 setMachineCodes(mi++, (byte) 0x0F);
33397 setMachineCodes(mi++, (byte) 0xAD);
33398 emitAbsRegOperands(disp, right);
33399 if (lister != null) lister.RARR(miStart, "SHRD", disp, right, shiftBy);
33400 }
33401
33402 /**
33403 * Generate a register POP. That is,
33404 * <PRE>
33405 * pop dstReg, SP -= 4
33406 * </PRE>
33407 *
33408 * @param reg the destination register
33409 */
33410 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
33411 public final void emitPOP_Reg (GPR reg) {
33412 int miStart = mi;
33413 generateREXprefix(false, null, null, reg);
33414 setMachineCodes(mi++, (byte) (0x58 + reg.valueForOpcode()));
33415 if (lister != null) lister.R(miStart, "POP", reg);
33416 }
33417
33418 /**
33419 * Generate a register-displacement POP. That is,
33420 * <PRE>
33421 * pop [base + disp], SP -= 4
33422 * </PRE>
33423 *
33424 * @param base the base register
33425 * @param disp the displacement
33426 */
33427 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
33428 public final void emitPOP_RegDisp (GPR base, Offset disp) {
33429 int miStart = mi;
33430 generateREXprefix(false, null, null, base);
33431 setMachineCodes(mi++, (byte) 0x8F);
33432 emitRegDispRegOperands(base, disp, GPR.getForOpcode(0x0));
33433 if (lister != null) lister.RD(miStart, "POP", base, disp);
33434 }
33435
33436 /**
33437 * Generate a register-indirect POP. That is,
33438 * <PRE>
33439 * pop [base], SP -= 4
33440 * </PRE>
33441 *
33442 * @param base the base register
33443 */
33444 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
33445 public final void emitPOP_RegInd (GPR base) {
33446 int miStart = mi;
33447 generateREXprefix(false, null, null, base);
33448 setMachineCodes(mi++, (byte) 0x8F);
33449 emitRegIndirectRegOperands(base, GPR.getForOpcode(0x0));
33450 if (lister != null) lister.RN(miStart, "POP", base);
33451 }
33452
33453 /**
33454 * Generate a register-index POP. That is,
33455 * <PRE>
33456 * pop [base + index<<scale + disp], SP -= 4
33457 * </PRE>
33458 *
33459 * @param base the base register
33460 * @param index the index register
33461 * @param scale the scale
33462 * @param disp the displacement
33463 */
33464 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
33465 public final void emitPOP_RegIdx (GPR base, GPR index, short scale, Offset disp) {
33466 int miStart = mi;
33467 generateREXprefix(false, null, index, base);
33468 setMachineCodes(mi++, (byte) 0x8F);
33469 emitSIBRegOperands(base, index, scale, disp, GPR.getForOpcode(0x0));
33470 if (lister != null) lister.RXD(miStart, "POP", base, index, scale, disp);
33471 }
33472
33473 /**
33474 * Generate a register-offset POP. That is,
33475 * <PRE>
33476 * pop [index<<scale + disp], SP -= 4
33477 * </PRE>
33478 *
33479 * @param index the index register
33480 * @param scale the scale
33481 * @param disp the displacement
33482 */
33483 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
33484 public final void emitPOP_RegOff (GPR index, short scale, Offset disp) {
33485 int miStart = mi;
33486 generateREXprefix(false, null, index, null);
33487 setMachineCodes(mi++, (byte) 0x8F);
33488 emitRegOffRegOperands(index, scale, disp, GPR.getForOpcode(0x0));
33489 if (lister != null) lister.RFD(miStart, "POP", index, scale, disp);
33490 }
33491
33492 /**
33493 * Generate an absolute POP. That is,
33494 * <PRE>
33495 * pop [disp], SP -= 4
33496 * </PRE>
33497 *
33498 * @param disp the displacement
33499 */
33500 public final void emitPOP_Abs (Address disp) {
33501 int miStart = mi;
33502 setMachineCodes(mi++, (byte) 0x8F);
33503 emitAbsRegOperands(disp, GPR.getForOpcode(0x0));
33504 if (lister != null) lister.RA(miStart, "POP", disp);
33505 }
33506
33507 /**
33508 * Generate a register PUSH. That is,
33509 * <PRE>
33510 * push dstReg, SP += 4
33511 * </PRE>
33512 *
33513 * @param reg the destination register
33514 */
33515 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
33516 public final void emitPUSH_Reg (GPR reg) {
33517 int miStart = mi;
33518 generateREXprefix(false, null, null, reg);
33519 setMachineCodes(mi++, (byte) (0x50 + reg.valueForOpcode()));
33520 if (lister != null) lister.R(miStart, "PUSH", reg);
33521 }
33522
33523 /**
33524 * Generate a register-displacement PUSH. That is,
33525 * <PRE>
33526 * push [base + disp], SP += 4
33527 * </PRE>
33528 *
33529 * @param base the base register
33530 * @param disp the displacement
33531 */
33532 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
33533 public final void emitPUSH_RegDisp (GPR base, Offset disp) {
33534 int miStart = mi;
33535 generateREXprefix(false, null, null, base);
33536 setMachineCodes(mi++, (byte) 0xFF);
33537 emitRegDispRegOperands(base, disp, GPR.getForOpcode(0x6));
33538 if (lister != null) lister.RD(miStart, "PUSH", base, disp);
33539 }
33540
33541 /**
33542 * Generate a register-indirect PUSH. That is,
33543 * <PRE>
33544 * push [base], SP += 4
33545 * </PRE>
33546 *
33547 * @param base the base register
33548 */
33549 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
33550 public final void emitPUSH_RegInd (GPR base) {
33551 int miStart = mi;
33552 generateREXprefix(false, null, null, base);
33553 setMachineCodes(mi++, (byte) 0xFF);
33554 emitRegIndirectRegOperands(base, GPR.getForOpcode(0x6));
33555 if (lister != null) lister.RN(miStart, "PUSH", base);
33556 }
33557
33558 /**
33559 * Generate a register-index PUSH. That is,
33560 * <PRE>
33561 * push [base + index<<scale + disp], SP += 4
33562 * </PRE>
33563 *
33564 * @param base the base register
33565 * @param index the index register
33566 * @param scale the scale
33567 * @param disp the displacement
33568 */
33569 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
33570 public final void emitPUSH_RegIdx (GPR base, GPR index, short scale, Offset disp) {
33571 int miStart = mi;
33572 generateREXprefix(false, null, index, base);
33573 setMachineCodes(mi++, (byte) 0xFF);
33574 emitSIBRegOperands(base, index, scale, disp, GPR.getForOpcode(0x6));
33575 if (lister != null) lister.RXD(miStart, "PUSH", base, index, scale, disp);
33576 }
33577
33578 /**
33579 * Generate a register-offset PUSH. That is,
33580 * <PRE>
33581 * push [index<<scale + disp], SP += 4
33582 * </PRE>
33583 *
33584 * @param index the index register
33585 * @param scale the scale
33586 * @param disp the displacement
33587 */
33588 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
33589 public final void emitPUSH_RegOff (GPR index, short scale, Offset disp) {
33590 int miStart = mi;
33591 generateREXprefix(false, null, index, null);
33592 setMachineCodes(mi++, (byte) 0xFF);
33593 emitRegOffRegOperands(index, scale, disp, GPR.getForOpcode(0x6));
33594 if (lister != null) lister.RFD(miStart, "PUSH", index, scale, disp);
33595 }
33596
33597 /**
33598 * Generate an absolute PUSH. That is,
33599 * <PRE>
33600 * push [disp], SP += 4
33601 * </PRE>
33602 *
33603 * @param disp the displacement
33604 */
33605 public final void emitPUSH_Abs (Address disp) {
33606 int miStart = mi;
33607 setMachineCodes(mi++, (byte) 0xFF);
33608 emitAbsRegOperands(disp, GPR.getForOpcode(0x6));
33609 if (lister != null) lister.RA(miStart, "PUSH", disp);
33610 }
33611
33612 /**
33613 * Generate an immediate PUSH. That is,
33614 * <PRE>
33615 * push imm, SP += 4
33616 * </PRE>
33617 *
33618 * @param imm the immediate value
33619 */
33620 public final void emitPUSH_Imm(int imm) {
33621 int miStart = mi;
33622 if (fits(imm, 8)) {
33623 setMachineCodes(mi++, (byte) 0x6A);
33624 emitImm8(imm);
33625 } else {
33626 setMachineCodes(mi++, (byte) 0x68);
33627 emitImm32(imm);
33628 }
33629 if (lister != null) lister.I(miStart, "PUSH", imm);
33630 }
33631
33632
33633 /**
33634 * Generate a register--register ADDSS. That is,
33635 * <PRE>
33636 * dstReg <<= (quad) srcReg
33637 * </PRE>
33638 *
33639 * @param dstReg destination register
33640 * @param srcReg source register
33641 */
33642 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
33643 public final void emitADDSS_Reg_Reg(XMM dstReg, XMM srcReg) {
33644 int miStart = mi;
33645 setMachineCodes(mi++, (byte) 0xF3);
33646 generateREXprefix(false, dstReg, null, srcReg);
33647 setMachineCodes(mi++, (byte) 0x0F);
33648 setMachineCodes(mi++, (byte) 0x58);
33649 emitRegRegOperands(srcReg, dstReg);
33650 if (lister != null) lister.RR(miStart, "ADDSS", dstReg, srcReg);
33651 }
33652
33653 /**
33654 * Generate a register--register-displacement ADDSS. That is,
33655 * <PRE>
33656 * dstReg <<= (quad) [srcBase + srcDisp]
33657 * </PRE>
33658 *
33659 * @param dstReg destination register
33660 * @param srcBase the source base register
33661 * @param srcDisp the source displacement
33662 */
33663 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
33664 public final void emitADDSS_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
33665 int miStart = mi;
33666 setMachineCodes(mi++, (byte) 0xF3);
33667 generateREXprefix(false, dstReg, null, srcBase);
33668 setMachineCodes(mi++, (byte) 0x0F);
33669 setMachineCodes(mi++, (byte) 0x58);
33670 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
33671 if (lister != null) lister.RRD(miStart, "ADDSS", dstReg, srcBase, srcDisp);
33672 }
33673
33674 /**
33675 * Generate a register--register-offset ADDSS. That is,
33676 * <PRE>
33677 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
33678 * </PRE>
33679 *
33680 * @param dstReg destination register
33681 * @param srcIndex the source index register
33682 * @param srcScale the source scale
33683 * @param srcDisp the source displacement
33684 */
33685 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
33686 public final void emitADDSS_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
33687 int miStart = mi;
33688 setMachineCodes(mi++, (byte) 0xF3);
33689 generateREXprefix(false, dstReg, srcIndex, null);
33690 setMachineCodes(mi++, (byte) 0x0F);
33691 setMachineCodes(mi++, (byte) 0x58);
33692 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
33693 if (lister != null) lister.RRFD(miStart, "ADDSS", dstReg, srcIndex, srcScale, srcDisp);
33694 }
33695
33696 /**
33697 * Generate a register--absolute ADDSS. That is,
33698 * <PRE>
33699 * dstReg <<= (quad) [srcDisp]
33700 * </PRE>
33701 *
33702 * @param dstReg destination register
33703 * @param srcDisp the source displacement
33704 */
33705 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
33706 public final void emitADDSS_Reg_Abs(XMM dstReg, Address srcDisp) {
33707 int miStart = mi;
33708 setMachineCodes(mi++, (byte) 0xF3);
33709 generateREXprefix(false, dstReg, null, null);
33710 setMachineCodes(mi++, (byte) 0x0F);
33711 setMachineCodes(mi++, (byte) 0x58);
33712 emitAbsRegOperands(srcDisp, dstReg);
33713 if (lister != null) lister.RRA(miStart, "ADDSS", dstReg, srcDisp);
33714 }
33715
33716 /**
33717 * Generate a register--register-index ADDSS. That is,
33718 * <PRE>
33719 * dstReg <<= (quad) srcReg
33720 * </PRE>
33721 *
33722 * @param dstReg destination register
33723 * @param srcBase the source base register
33724 * @param srcIndex the source index register
33725 * @param srcScale the source scale
33726 * @param srcDisp the source displacement
33727 */
33728 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
33729 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
33730 public final void emitADDSS_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
33731 int miStart = mi;
33732 setMachineCodes(mi++, (byte) 0xF3);
33733 generateREXprefix(false, dstReg, srcIndex, srcBase);
33734 setMachineCodes(mi++, (byte) 0x0F);
33735 setMachineCodes(mi++, (byte) 0x58);
33736 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
33737 if (lister != null) lister.RRXD(miStart, "ADDSS", dstReg, srcBase, srcIndex, srcScale, srcDisp);
33738 }
33739
33740 /**
33741 * Generate a register--register-indirect ADDSS. That is,
33742 * <PRE>
33743 * dstReg <<= (quad) [srcBase]
33744 * </PRE>
33745 *
33746 * @param dstReg destination register
33747 * @param srcBase the source base register
33748 */
33749 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
33750 public final void emitADDSS_Reg_RegInd(XMM dstReg, GPR srcBase) {
33751 int miStart = mi;
33752 setMachineCodes(mi++, (byte) 0xF3);
33753 generateREXprefix(false, dstReg, null, srcBase);
33754 setMachineCodes(mi++, (byte) 0x0F);
33755 setMachineCodes(mi++, (byte) 0x58);
33756 emitRegIndirectRegOperands(srcBase, dstReg);
33757 if (lister != null) lister.RRN(miStart, "ADDSS", dstReg, srcBase);
33758 }
33759
33760
33761 /**
33762 * Generate a register--register SUBSS. That is,
33763 * <PRE>
33764 * dstReg <<= (quad) srcReg
33765 * </PRE>
33766 *
33767 * @param dstReg destination register
33768 * @param srcReg source register
33769 */
33770 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
33771 public final void emitSUBSS_Reg_Reg(XMM dstReg, XMM srcReg) {
33772 int miStart = mi;
33773 setMachineCodes(mi++, (byte) 0xF3);
33774 generateREXprefix(false, dstReg, null, srcReg);
33775 setMachineCodes(mi++, (byte) 0x0F);
33776 setMachineCodes(mi++, (byte) 0x5C);
33777 emitRegRegOperands(srcReg, dstReg);
33778 if (lister != null) lister.RR(miStart, "SUBSS", dstReg, srcReg);
33779 }
33780
33781 /**
33782 * Generate a register--register-displacement SUBSS. That is,
33783 * <PRE>
33784 * dstReg <<= (quad) [srcBase + srcDisp]
33785 * </PRE>
33786 *
33787 * @param dstReg destination register
33788 * @param srcBase the source base register
33789 * @param srcDisp the source displacement
33790 */
33791 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
33792 public final void emitSUBSS_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
33793 int miStart = mi;
33794 setMachineCodes(mi++, (byte) 0xF3);
33795 generateREXprefix(false, dstReg, null, srcBase);
33796 setMachineCodes(mi++, (byte) 0x0F);
33797 setMachineCodes(mi++, (byte) 0x5C);
33798 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
33799 if (lister != null) lister.RRD(miStart, "SUBSS", dstReg, srcBase, srcDisp);
33800 }
33801
33802 /**
33803 * Generate a register--register-offset SUBSS. That is,
33804 * <PRE>
33805 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
33806 * </PRE>
33807 *
33808 * @param dstReg destination register
33809 * @param srcIndex the source index register
33810 * @param srcScale the source scale
33811 * @param srcDisp the source displacement
33812 */
33813 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
33814 public final void emitSUBSS_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
33815 int miStart = mi;
33816 setMachineCodes(mi++, (byte) 0xF3);
33817 generateREXprefix(false, dstReg, srcIndex, null);
33818 setMachineCodes(mi++, (byte) 0x0F);
33819 setMachineCodes(mi++, (byte) 0x5C);
33820 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
33821 if (lister != null) lister.RRFD(miStart, "SUBSS", dstReg, srcIndex, srcScale, srcDisp);
33822 }
33823
33824 /**
33825 * Generate a register--absolute SUBSS. That is,
33826 * <PRE>
33827 * dstReg <<= (quad) [srcDisp]
33828 * </PRE>
33829 *
33830 * @param dstReg destination register
33831 * @param srcDisp the source displacement
33832 */
33833 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
33834 public final void emitSUBSS_Reg_Abs(XMM dstReg, Address srcDisp) {
33835 int miStart = mi;
33836 setMachineCodes(mi++, (byte) 0xF3);
33837 generateREXprefix(false, dstReg, null, null);
33838 setMachineCodes(mi++, (byte) 0x0F);
33839 setMachineCodes(mi++, (byte) 0x5C);
33840 emitAbsRegOperands(srcDisp, dstReg);
33841 if (lister != null) lister.RRA(miStart, "SUBSS", dstReg, srcDisp);
33842 }
33843
33844 /**
33845 * Generate a register--register-index SUBSS. That is,
33846 * <PRE>
33847 * dstReg <<= (quad) srcReg
33848 * </PRE>
33849 *
33850 * @param dstReg destination register
33851 * @param srcBase the source base register
33852 * @param srcIndex the source index register
33853 * @param srcScale the source scale
33854 * @param srcDisp the source displacement
33855 */
33856 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
33857 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
33858 public final void emitSUBSS_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
33859 int miStart = mi;
33860 setMachineCodes(mi++, (byte) 0xF3);
33861 generateREXprefix(false, dstReg, srcIndex, srcBase);
33862 setMachineCodes(mi++, (byte) 0x0F);
33863 setMachineCodes(mi++, (byte) 0x5C);
33864 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
33865 if (lister != null) lister.RRXD(miStart, "SUBSS", dstReg, srcBase, srcIndex, srcScale, srcDisp);
33866 }
33867
33868 /**
33869 * Generate a register--register-indirect SUBSS. That is,
33870 * <PRE>
33871 * dstReg <<= (quad) [srcBase]
33872 * </PRE>
33873 *
33874 * @param dstReg destination register
33875 * @param srcBase the source base register
33876 */
33877 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
33878 public final void emitSUBSS_Reg_RegInd(XMM dstReg, GPR srcBase) {
33879 int miStart = mi;
33880 setMachineCodes(mi++, (byte) 0xF3);
33881 generateREXprefix(false, dstReg, null, srcBase);
33882 setMachineCodes(mi++, (byte) 0x0F);
33883 setMachineCodes(mi++, (byte) 0x5C);
33884 emitRegIndirectRegOperands(srcBase, dstReg);
33885 if (lister != null) lister.RRN(miStart, "SUBSS", dstReg, srcBase);
33886 }
33887
33888
33889 /**
33890 * Generate a register--register MULSS. That is,
33891 * <PRE>
33892 * dstReg <<= (quad) srcReg
33893 * </PRE>
33894 *
33895 * @param dstReg destination register
33896 * @param srcReg source register
33897 */
33898 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
33899 public final void emitMULSS_Reg_Reg(XMM dstReg, XMM srcReg) {
33900 int miStart = mi;
33901 setMachineCodes(mi++, (byte) 0xF3);
33902 generateREXprefix(false, dstReg, null, srcReg);
33903 setMachineCodes(mi++, (byte) 0x0F);
33904 setMachineCodes(mi++, (byte) 0x59);
33905 emitRegRegOperands(srcReg, dstReg);
33906 if (lister != null) lister.RR(miStart, "MULSS", dstReg, srcReg);
33907 }
33908
33909 /**
33910 * Generate a register--register-displacement MULSS. That is,
33911 * <PRE>
33912 * dstReg <<= (quad) [srcBase + srcDisp]
33913 * </PRE>
33914 *
33915 * @param dstReg destination register
33916 * @param srcBase the source base register
33917 * @param srcDisp the source displacement
33918 */
33919 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
33920 public final void emitMULSS_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
33921 int miStart = mi;
33922 setMachineCodes(mi++, (byte) 0xF3);
33923 generateREXprefix(false, dstReg, null, srcBase);
33924 setMachineCodes(mi++, (byte) 0x0F);
33925 setMachineCodes(mi++, (byte) 0x59);
33926 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
33927 if (lister != null) lister.RRD(miStart, "MULSS", dstReg, srcBase, srcDisp);
33928 }
33929
33930 /**
33931 * Generate a register--register-offset MULSS. That is,
33932 * <PRE>
33933 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
33934 * </PRE>
33935 *
33936 * @param dstReg destination register
33937 * @param srcIndex the source index register
33938 * @param srcScale the source scale
33939 * @param srcDisp the source displacement
33940 */
33941 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
33942 public final void emitMULSS_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
33943 int miStart = mi;
33944 setMachineCodes(mi++, (byte) 0xF3);
33945 generateREXprefix(false, dstReg, srcIndex, null);
33946 setMachineCodes(mi++, (byte) 0x0F);
33947 setMachineCodes(mi++, (byte) 0x59);
33948 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
33949 if (lister != null) lister.RRFD(miStart, "MULSS", dstReg, srcIndex, srcScale, srcDisp);
33950 }
33951
33952 /**
33953 * Generate a register--absolute MULSS. That is,
33954 * <PRE>
33955 * dstReg <<= (quad) [srcDisp]
33956 * </PRE>
33957 *
33958 * @param dstReg destination register
33959 * @param srcDisp the source displacement
33960 */
33961 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
33962 public final void emitMULSS_Reg_Abs(XMM dstReg, Address srcDisp) {
33963 int miStart = mi;
33964 setMachineCodes(mi++, (byte) 0xF3);
33965 generateREXprefix(false, dstReg, null, null);
33966 setMachineCodes(mi++, (byte) 0x0F);
33967 setMachineCodes(mi++, (byte) 0x59);
33968 emitAbsRegOperands(srcDisp, dstReg);
33969 if (lister != null) lister.RRA(miStart, "MULSS", dstReg, srcDisp);
33970 }
33971
33972 /**
33973 * Generate a register--register-index MULSS. That is,
33974 * <PRE>
33975 * dstReg <<= (quad) srcReg
33976 * </PRE>
33977 *
33978 * @param dstReg destination register
33979 * @param srcBase the source base register
33980 * @param srcIndex the source index register
33981 * @param srcScale the source scale
33982 * @param srcDisp the source displacement
33983 */
33984 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
33985 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
33986 public final void emitMULSS_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
33987 int miStart = mi;
33988 setMachineCodes(mi++, (byte) 0xF3);
33989 generateREXprefix(false, dstReg, srcIndex, srcBase);
33990 setMachineCodes(mi++, (byte) 0x0F);
33991 setMachineCodes(mi++, (byte) 0x59);
33992 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
33993 if (lister != null) lister.RRXD(miStart, "MULSS", dstReg, srcBase, srcIndex, srcScale, srcDisp);
33994 }
33995
33996 /**
33997 * Generate a register--register-indirect MULSS. That is,
33998 * <PRE>
33999 * dstReg <<= (quad) [srcBase]
34000 * </PRE>
34001 *
34002 * @param dstReg destination register
34003 * @param srcBase the source base register
34004 */
34005 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
34006 public final void emitMULSS_Reg_RegInd(XMM dstReg, GPR srcBase) {
34007 int miStart = mi;
34008 setMachineCodes(mi++, (byte) 0xF3);
34009 generateREXprefix(false, dstReg, null, srcBase);
34010 setMachineCodes(mi++, (byte) 0x0F);
34011 setMachineCodes(mi++, (byte) 0x59);
34012 emitRegIndirectRegOperands(srcBase, dstReg);
34013 if (lister != null) lister.RRN(miStart, "MULSS", dstReg, srcBase);
34014 }
34015
34016
34017 /**
34018 * Generate a register--register DIVSS. That is,
34019 * <PRE>
34020 * dstReg <<= (quad) srcReg
34021 * </PRE>
34022 *
34023 * @param dstReg destination register
34024 * @param srcReg source register
34025 */
34026 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
34027 public final void emitDIVSS_Reg_Reg(XMM dstReg, XMM srcReg) {
34028 int miStart = mi;
34029 setMachineCodes(mi++, (byte) 0xF3);
34030 generateREXprefix(false, dstReg, null, srcReg);
34031 setMachineCodes(mi++, (byte) 0x0F);
34032 setMachineCodes(mi++, (byte) 0x5E);
34033 emitRegRegOperands(srcReg, dstReg);
34034 if (lister != null) lister.RR(miStart, "DIVSS", dstReg, srcReg);
34035 }
34036
34037 /**
34038 * Generate a register--register-displacement DIVSS. That is,
34039 * <PRE>
34040 * dstReg <<= (quad) [srcBase + srcDisp]
34041 * </PRE>
34042 *
34043 * @param dstReg destination register
34044 * @param srcBase the source base register
34045 * @param srcDisp the source displacement
34046 */
34047 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
34048 public final void emitDIVSS_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
34049 int miStart = mi;
34050 setMachineCodes(mi++, (byte) 0xF3);
34051 generateREXprefix(false, dstReg, null, srcBase);
34052 setMachineCodes(mi++, (byte) 0x0F);
34053 setMachineCodes(mi++, (byte) 0x5E);
34054 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
34055 if (lister != null) lister.RRD(miStart, "DIVSS", dstReg, srcBase, srcDisp);
34056 }
34057
34058 /**
34059 * Generate a register--register-offset DIVSS. That is,
34060 * <PRE>
34061 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
34062 * </PRE>
34063 *
34064 * @param dstReg destination register
34065 * @param srcIndex the source index register
34066 * @param srcScale the source scale
34067 * @param srcDisp the source displacement
34068 */
34069 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
34070 public final void emitDIVSS_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
34071 int miStart = mi;
34072 setMachineCodes(mi++, (byte) 0xF3);
34073 generateREXprefix(false, dstReg, srcIndex, null);
34074 setMachineCodes(mi++, (byte) 0x0F);
34075 setMachineCodes(mi++, (byte) 0x5E);
34076 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
34077 if (lister != null) lister.RRFD(miStart, "DIVSS", dstReg, srcIndex, srcScale, srcDisp);
34078 }
34079
34080 /**
34081 * Generate a register--absolute DIVSS. That is,
34082 * <PRE>
34083 * dstReg <<= (quad) [srcDisp]
34084 * </PRE>
34085 *
34086 * @param dstReg destination register
34087 * @param srcDisp the source displacement
34088 */
34089 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
34090 public final void emitDIVSS_Reg_Abs(XMM dstReg, Address srcDisp) {
34091 int miStart = mi;
34092 setMachineCodes(mi++, (byte) 0xF3);
34093 generateREXprefix(false, dstReg, null, null);
34094 setMachineCodes(mi++, (byte) 0x0F);
34095 setMachineCodes(mi++, (byte) 0x5E);
34096 emitAbsRegOperands(srcDisp, dstReg);
34097 if (lister != null) lister.RRA(miStart, "DIVSS", dstReg, srcDisp);
34098 }
34099
34100 /**
34101 * Generate a register--register-index DIVSS. That is,
34102 * <PRE>
34103 * dstReg <<= (quad) srcReg
34104 * </PRE>
34105 *
34106 * @param dstReg destination register
34107 * @param srcBase the source base register
34108 * @param srcIndex the source index register
34109 * @param srcScale the source scale
34110 * @param srcDisp the source displacement
34111 */
34112 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
34113 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
34114 public final void emitDIVSS_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
34115 int miStart = mi;
34116 setMachineCodes(mi++, (byte) 0xF3);
34117 generateREXprefix(false, dstReg, srcIndex, srcBase);
34118 setMachineCodes(mi++, (byte) 0x0F);
34119 setMachineCodes(mi++, (byte) 0x5E);
34120 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
34121 if (lister != null) lister.RRXD(miStart, "DIVSS", dstReg, srcBase, srcIndex, srcScale, srcDisp);
34122 }
34123
34124 /**
34125 * Generate a register--register-indirect DIVSS. That is,
34126 * <PRE>
34127 * dstReg <<= (quad) [srcBase]
34128 * </PRE>
34129 *
34130 * @param dstReg destination register
34131 * @param srcBase the source base register
34132 */
34133 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
34134 public final void emitDIVSS_Reg_RegInd(XMM dstReg, GPR srcBase) {
34135 int miStart = mi;
34136 setMachineCodes(mi++, (byte) 0xF3);
34137 generateREXprefix(false, dstReg, null, srcBase);
34138 setMachineCodes(mi++, (byte) 0x0F);
34139 setMachineCodes(mi++, (byte) 0x5E);
34140 emitRegIndirectRegOperands(srcBase, dstReg);
34141 if (lister != null) lister.RRN(miStart, "DIVSS", dstReg, srcBase);
34142 }
34143
34144
34145 /**
34146 * Generate a register--register MOVSS. That is,
34147 * <PRE>
34148 * dstReg <<= (quad) srcReg
34149 * </PRE>
34150 *
34151 * @param dstReg destination register
34152 * @param srcReg source register
34153 */
34154 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
34155 public final void emitMOVSS_Reg_Reg(XMM dstReg, XMM srcReg) {
34156 int miStart = mi;
34157 setMachineCodes(mi++, (byte) 0xF3);
34158 generateREXprefix(false, dstReg, null, srcReg);
34159 setMachineCodes(mi++, (byte) 0x0F);
34160 setMachineCodes(mi++, (byte) 0x10);
34161 emitRegRegOperands(srcReg, dstReg);
34162 if (lister != null) lister.RR(miStart, "MOVSS", dstReg, srcReg);
34163 }
34164
34165 /**
34166 * Generate a register--register-displacement MOVSS. That is,
34167 * <PRE>
34168 * dstReg <<= (quad) [srcBase + srcDisp]
34169 * </PRE>
34170 *
34171 * @param dstReg destination register
34172 * @param srcBase the source base register
34173 * @param srcDisp the source displacement
34174 */
34175 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
34176 public final void emitMOVSS_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
34177 int miStart = mi;
34178 setMachineCodes(mi++, (byte) 0xF3);
34179 generateREXprefix(false, dstReg, null, srcBase);
34180 setMachineCodes(mi++, (byte) 0x0F);
34181 setMachineCodes(mi++, (byte) 0x10);
34182 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
34183 if (lister != null) lister.RRD(miStart, "MOVSS", dstReg, srcBase, srcDisp);
34184 }
34185
34186 /**
34187 * Generate a register--register-offset MOVSS. That is,
34188 * <PRE>
34189 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
34190 * </PRE>
34191 *
34192 * @param dstReg destination register
34193 * @param srcIndex the source index register
34194 * @param srcScale the source scale
34195 * @param srcDisp the source displacement
34196 */
34197 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
34198 public final void emitMOVSS_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
34199 int miStart = mi;
34200 setMachineCodes(mi++, (byte) 0xF3);
34201 generateREXprefix(false, dstReg, srcIndex, null);
34202 setMachineCodes(mi++, (byte) 0x0F);
34203 setMachineCodes(mi++, (byte) 0x10);
34204 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
34205 if (lister != null) lister.RRFD(miStart, "MOVSS", dstReg, srcIndex, srcScale, srcDisp);
34206 }
34207
34208 /**
34209 * Generate a register--absolute MOVSS. That is,
34210 * <PRE>
34211 * dstReg <<= (quad) [srcDisp]
34212 * </PRE>
34213 *
34214 * @param dstReg destination register
34215 * @param srcDisp the source displacement
34216 */
34217 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
34218 public final void emitMOVSS_Reg_Abs(XMM dstReg, Address srcDisp) {
34219 int miStart = mi;
34220 setMachineCodes(mi++, (byte) 0xF3);
34221 generateREXprefix(false, dstReg, null, null);
34222 setMachineCodes(mi++, (byte) 0x0F);
34223 setMachineCodes(mi++, (byte) 0x10);
34224 emitAbsRegOperands(srcDisp, dstReg);
34225 if (lister != null) lister.RRA(miStart, "MOVSS", dstReg, srcDisp);
34226 }
34227
34228 /**
34229 * Generate a register--register-index MOVSS. That is,
34230 * <PRE>
34231 * dstReg <<= (quad) srcReg
34232 * </PRE>
34233 *
34234 * @param dstReg destination register
34235 * @param srcBase the source base register
34236 * @param srcIndex the source index register
34237 * @param srcScale the source scale
34238 * @param srcDisp the source displacement
34239 */
34240 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
34241 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
34242 public final void emitMOVSS_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
34243 int miStart = mi;
34244 setMachineCodes(mi++, (byte) 0xF3);
34245 generateREXprefix(false, dstReg, srcIndex, srcBase);
34246 setMachineCodes(mi++, (byte) 0x0F);
34247 setMachineCodes(mi++, (byte) 0x10);
34248 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
34249 if (lister != null) lister.RRXD(miStart, "MOVSS", dstReg, srcBase, srcIndex, srcScale, srcDisp);
34250 }
34251
34252 /**
34253 * Generate a register--register-indirect MOVSS. That is,
34254 * <PRE>
34255 * dstReg <<= (quad) [srcBase]
34256 * </PRE>
34257 *
34258 * @param dstReg destination register
34259 * @param srcBase the source base register
34260 */
34261 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
34262 public final void emitMOVSS_Reg_RegInd(XMM dstReg, GPR srcBase) {
34263 int miStart = mi;
34264 setMachineCodes(mi++, (byte) 0xF3);
34265 generateREXprefix(false, dstReg, null, srcBase);
34266 setMachineCodes(mi++, (byte) 0x0F);
34267 setMachineCodes(mi++, (byte) 0x10);
34268 emitRegIndirectRegOperands(srcBase, dstReg);
34269 if (lister != null) lister.RRN(miStart, "MOVSS", dstReg, srcBase);
34270 }
34271
34272
34273 /**
34274 * Generate a register-indirect--register MOVSS. That is,
34275 * <PRE>
34276 * [dstBase] <<= (quad) srcReg
34277 * </PRE>
34278 *
34279 * @param dstBase the destination base register
34280 * @param srcReg the source register
34281 */
34282 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
34283 public final void emitMOVSS_RegInd_Reg(GPR dstBase, XMM srcReg) {
34284 int miStart = mi;
34285 setMachineCodes(mi++, (byte) 0xF3);
34286 generateREXprefix(false, srcReg, null, dstBase);
34287 setMachineCodes(mi++, (byte) 0x0F);
34288 setMachineCodes(mi++, (byte) 0x11);
34289 emitRegIndirectRegOperands(dstBase, srcReg);
34290 if (lister != null) lister.RNR(miStart, "MOVSS", dstBase, srcReg);
34291 }
34292
34293 /**
34294 * Generate a register-offset--register MOVSS. That is,
34295 * <PRE>
34296 * [dstReg<<dstScale + dstDisp] <<= (quad) srcReg
34297 * </PRE>
34298 *
34299 * @param dstIndex the destination index register
34300 * @param dstScale the destination shift amount
34301 * @param dstDisp the destination displacement
34302 * @param srcReg the source register
34303 */
34304 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
34305 public final void emitMOVSS_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, XMM srcReg) {
34306 int miStart = mi;
34307 setMachineCodes(mi++, (byte) 0xF3);
34308 generateREXprefix(false, srcReg, dstIndex, null);
34309 setMachineCodes(mi++, (byte) 0x0F);
34310 setMachineCodes(mi++, (byte) 0x11);
34311 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
34312 if (lister != null) lister.RFDR(miStart, "MOVSS", dstIndex, dstScale, dstDisp, srcReg);
34313 }
34314
34315 /**
34316 * Generate a absolute--register MOVSS. That is,
34317 * <PRE>
34318 * [dstDisp] <<= (quad) srcReg
34319 * </PRE>
34320 *
34321 * @param dstDisp the destination displacement
34322 * @param srcReg the source register
34323 */
34324 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
34325 public final void emitMOVSS_Abs_Reg(Address dstDisp, XMM srcReg) {
34326 int miStart = mi;
34327 setMachineCodes(mi++, (byte) 0xF3);
34328 generateREXprefix(false, srcReg, null, null);
34329 setMachineCodes(mi++, (byte) 0x0F);
34330 setMachineCodes(mi++, (byte) 0x11);
34331 emitAbsRegOperands(dstDisp, srcReg);
34332 if (lister != null) lister.RAR(miStart, "MOVSS", dstDisp, srcReg);
34333 }
34334
34335 /**
34336 * Generate a register-index--register MOVSS. That is,
34337 * <PRE>
34338 * [dstBase + dstIndex<<dstScale + dstDisp] <<= (quad) srcReg
34339 * </PRE>
34340 *
34341 * @param dstBase the destination base register
34342 * @param dstIndex the destination index register
34343 * @param dstScale the destination shift amount
34344 * @param dstDisp the destination displacement
34345 * @param srcReg the source register
34346 */
34347 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
34348 public final void emitMOVSS_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, XMM srcReg) {
34349 int miStart = mi;
34350 setMachineCodes(mi++, (byte) 0xF3);
34351 generateREXprefix(false, srcReg, dstIndex, dstBase);
34352 setMachineCodes(mi++, (byte) 0x0F);
34353 setMachineCodes(mi++, (byte) 0x11);
34354 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
34355 if (lister != null) lister.RXDR(miStart, "MOVSS", dstBase, dstIndex, dstScale, dstDisp, srcReg);
34356 }
34357
34358 /**
34359 * Generate a register-displacement--register MOVSS. That is,
34360 * <PRE>
34361 * [dstBase + dstDisp] <<= (quad) srcReg
34362 * </PRE>
34363 *
34364 * @param dstBase the destination base register
34365 * @param dstDisp the destination displacement
34366 * @param srcReg the source register
34367 */
34368 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
34369 public final void emitMOVSS_RegDisp_Reg(GPR dstBase, Offset dstDisp, XMM srcReg) {
34370 int miStart = mi;
34371 setMachineCodes(mi++, (byte) 0xF3);
34372 generateREXprefix(false, srcReg, null, dstBase);
34373 setMachineCodes(mi++, (byte) 0x0F);
34374 setMachineCodes(mi++, (byte) 0x11);
34375 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
34376 if (lister != null) lister.RDR(miStart, "MOVSS", dstBase, dstDisp, srcReg);
34377 }
34378
34379
34380 /**
34381 * Generate a register--register MOVLPS. That is,
34382 * <PRE>
34383 * dstReg <<= (quad) srcReg
34384 * </PRE>
34385 *
34386 * @param dstReg destination register
34387 * @param srcReg source register
34388 */
34389 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
34390 public final void emitMOVLPS_Reg_Reg(XMM dstReg, XMM srcReg) {
34391 int miStart = mi;
34392 generateREXprefix(false, dstReg, null, srcReg);
34393 setMachineCodes(mi++, (byte) 0x0F);
34394 setMachineCodes(mi++, (byte) 0x12);
34395 emitRegRegOperands(srcReg, dstReg);
34396 if (lister != null) lister.RR(miStart, "MOVLPS", dstReg, srcReg);
34397 }
34398
34399 /**
34400 * Generate a register--register-displacement MOVLPS. That is,
34401 * <PRE>
34402 * dstReg <<= (quad) [srcBase + srcDisp]
34403 * </PRE>
34404 *
34405 * @param dstReg destination register
34406 * @param srcBase the source base register
34407 * @param srcDisp the source displacement
34408 */
34409 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
34410 public final void emitMOVLPS_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
34411 int miStart = mi;
34412 generateREXprefix(false, dstReg, null, srcBase);
34413 setMachineCodes(mi++, (byte) 0x0F);
34414 setMachineCodes(mi++, (byte) 0x12);
34415 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
34416 if (lister != null) lister.RRD(miStart, "MOVLPS", dstReg, srcBase, srcDisp);
34417 }
34418
34419 /**
34420 * Generate a register--register-offset MOVLPS. That is,
34421 * <PRE>
34422 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
34423 * </PRE>
34424 *
34425 * @param dstReg destination register
34426 * @param srcIndex the source index register
34427 * @param srcScale the source scale
34428 * @param srcDisp the source displacement
34429 */
34430 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
34431 public final void emitMOVLPS_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
34432 int miStart = mi;
34433 generateREXprefix(false, dstReg, srcIndex, null);
34434 setMachineCodes(mi++, (byte) 0x0F);
34435 setMachineCodes(mi++, (byte) 0x12);
34436 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
34437 if (lister != null) lister.RRFD(miStart, "MOVLPS", dstReg, srcIndex, srcScale, srcDisp);
34438 }
34439
34440 /**
34441 * Generate a register--absolute MOVLPS. That is,
34442 * <PRE>
34443 * dstReg <<= (quad) [srcDisp]
34444 * </PRE>
34445 *
34446 * @param dstReg destination register
34447 * @param srcDisp the source displacement
34448 */
34449 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
34450 public final void emitMOVLPS_Reg_Abs(XMM dstReg, Address srcDisp) {
34451 int miStart = mi;
34452 generateREXprefix(false, dstReg, null, null);
34453 setMachineCodes(mi++, (byte) 0x0F);
34454 setMachineCodes(mi++, (byte) 0x12);
34455 emitAbsRegOperands(srcDisp, dstReg);
34456 if (lister != null) lister.RRA(miStart, "MOVLPS", dstReg, srcDisp);
34457 }
34458
34459 /**
34460 * Generate a register--register-index MOVLPS. That is,
34461 * <PRE>
34462 * dstReg <<= (quad) srcReg
34463 * </PRE>
34464 *
34465 * @param dstReg destination register
34466 * @param srcBase the source base register
34467 * @param srcIndex the source index register
34468 * @param srcScale the source scale
34469 * @param srcDisp the source displacement
34470 */
34471 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
34472 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
34473 public final void emitMOVLPS_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
34474 int miStart = mi;
34475 generateREXprefix(false, dstReg, srcIndex, srcBase);
34476 setMachineCodes(mi++, (byte) 0x0F);
34477 setMachineCodes(mi++, (byte) 0x12);
34478 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
34479 if (lister != null) lister.RRXD(miStart, "MOVLPS", dstReg, srcBase, srcIndex, srcScale, srcDisp);
34480 }
34481
34482 /**
34483 * Generate a register--register-indirect MOVLPS. That is,
34484 * <PRE>
34485 * dstReg <<= (quad) [srcBase]
34486 * </PRE>
34487 *
34488 * @param dstReg destination register
34489 * @param srcBase the source base register
34490 */
34491 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
34492 public final void emitMOVLPS_Reg_RegInd(XMM dstReg, GPR srcBase) {
34493 int miStart = mi;
34494 generateREXprefix(false, dstReg, null, srcBase);
34495 setMachineCodes(mi++, (byte) 0x0F);
34496 setMachineCodes(mi++, (byte) 0x12);
34497 emitRegIndirectRegOperands(srcBase, dstReg);
34498 if (lister != null) lister.RRN(miStart, "MOVLPS", dstReg, srcBase);
34499 }
34500
34501
34502 /**
34503 * Generate a register-indirect--register MOVLPS. That is,
34504 * <PRE>
34505 * [dstBase] <<= (quad) srcReg
34506 * </PRE>
34507 *
34508 * @param dstBase the destination base register
34509 * @param srcReg the source register
34510 */
34511 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
34512 public final void emitMOVLPS_RegInd_Reg(GPR dstBase, XMM srcReg) {
34513 int miStart = mi;
34514 generateREXprefix(false, srcReg, null, dstBase);
34515 setMachineCodes(mi++, (byte) 0x0F);
34516 setMachineCodes(mi++, (byte) 0x13);
34517 emitRegIndirectRegOperands(dstBase, srcReg);
34518 if (lister != null) lister.RNR(miStart, "MOVLPS", dstBase, srcReg);
34519 }
34520
34521 /**
34522 * Generate a register-offset--register MOVLPS. That is,
34523 * <PRE>
34524 * [dstReg<<dstScale + dstDisp] <<= (quad) srcReg
34525 * </PRE>
34526 *
34527 * @param dstIndex the destination index register
34528 * @param dstScale the destination shift amount
34529 * @param dstDisp the destination displacement
34530 * @param srcReg the source register
34531 */
34532 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
34533 public final void emitMOVLPS_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, XMM srcReg) {
34534 int miStart = mi;
34535 generateREXprefix(false, srcReg, dstIndex, null);
34536 setMachineCodes(mi++, (byte) 0x0F);
34537 setMachineCodes(mi++, (byte) 0x13);
34538 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
34539 if (lister != null) lister.RFDR(miStart, "MOVLPS", dstIndex, dstScale, dstDisp, srcReg);
34540 }
34541
34542 /**
34543 * Generate a absolute--register MOVLPS. That is,
34544 * <PRE>
34545 * [dstDisp] <<= (quad) srcReg
34546 * </PRE>
34547 *
34548 * @param dstDisp the destination displacement
34549 * @param srcReg the source register
34550 */
34551 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
34552 public final void emitMOVLPS_Abs_Reg(Address dstDisp, XMM srcReg) {
34553 int miStart = mi;
34554 generateREXprefix(false, srcReg, null, null);
34555 setMachineCodes(mi++, (byte) 0x0F);
34556 setMachineCodes(mi++, (byte) 0x13);
34557 emitAbsRegOperands(dstDisp, srcReg);
34558 if (lister != null) lister.RAR(miStart, "MOVLPS", dstDisp, srcReg);
34559 }
34560
34561 /**
34562 * Generate a register-index--register MOVLPS. That is,
34563 * <PRE>
34564 * [dstBase + dstIndex<<dstScale + dstDisp] <<= (quad) srcReg
34565 * </PRE>
34566 *
34567 * @param dstBase the destination base register
34568 * @param dstIndex the destination index register
34569 * @param dstScale the destination shift amount
34570 * @param dstDisp the destination displacement
34571 * @param srcReg the source register
34572 */
34573 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
34574 public final void emitMOVLPS_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, XMM srcReg) {
34575 int miStart = mi;
34576 generateREXprefix(false, srcReg, dstIndex, dstBase);
34577 setMachineCodes(mi++, (byte) 0x0F);
34578 setMachineCodes(mi++, (byte) 0x13);
34579 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
34580 if (lister != null) lister.RXDR(miStart, "MOVLPS", dstBase, dstIndex, dstScale, dstDisp, srcReg);
34581 }
34582
34583 /**
34584 * Generate a register-displacement--register MOVLPS. That is,
34585 * <PRE>
34586 * [dstBase + dstDisp] <<= (quad) srcReg
34587 * </PRE>
34588 *
34589 * @param dstBase the destination base register
34590 * @param dstDisp the destination displacement
34591 * @param srcReg the source register
34592 */
34593 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
34594 public final void emitMOVLPS_RegDisp_Reg(GPR dstBase, Offset dstDisp, XMM srcReg) {
34595 int miStart = mi;
34596 generateREXprefix(false, srcReg, null, dstBase);
34597 setMachineCodes(mi++, (byte) 0x0F);
34598 setMachineCodes(mi++, (byte) 0x13);
34599 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
34600 if (lister != null) lister.RDR(miStart, "MOVLPS", dstBase, dstDisp, srcReg);
34601 }
34602
34603
34604 /**
34605 * Generate a register--register SQRTSS. That is,
34606 * <PRE>
34607 * dstReg <<= (quad) srcReg
34608 * </PRE>
34609 *
34610 * @param dstReg destination register
34611 * @param srcReg source register
34612 */
34613 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
34614 public final void emitSQRTSS_Reg_Reg(XMM dstReg, XMM srcReg) {
34615 int miStart = mi;
34616 setMachineCodes(mi++, (byte) 0xF3);
34617 generateREXprefix(false, dstReg, null, srcReg);
34618 setMachineCodes(mi++, (byte) 0x0F);
34619 setMachineCodes(mi++, (byte) 0x51);
34620 emitRegRegOperands(srcReg, dstReg);
34621 if (lister != null) lister.RR(miStart, "SQRTSS", dstReg, srcReg);
34622 }
34623
34624 /**
34625 * Generate a register--register-displacement SQRTSS. That is,
34626 * <PRE>
34627 * dstReg <<= (quad) [srcBase + srcDisp]
34628 * </PRE>
34629 *
34630 * @param dstReg destination register
34631 * @param srcBase the source base register
34632 * @param srcDisp the source displacement
34633 */
34634 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
34635 public final void emitSQRTSS_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
34636 int miStart = mi;
34637 setMachineCodes(mi++, (byte) 0xF3);
34638 generateREXprefix(false, dstReg, null, srcBase);
34639 setMachineCodes(mi++, (byte) 0x0F);
34640 setMachineCodes(mi++, (byte) 0x51);
34641 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
34642 if (lister != null) lister.RRD(miStart, "SQRTSS", dstReg, srcBase, srcDisp);
34643 }
34644
34645 /**
34646 * Generate a register--register-offset SQRTSS. That is,
34647 * <PRE>
34648 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
34649 * </PRE>
34650 *
34651 * @param dstReg destination register
34652 * @param srcIndex the source index register
34653 * @param srcScale the source scale
34654 * @param srcDisp the source displacement
34655 */
34656 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
34657 public final void emitSQRTSS_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
34658 int miStart = mi;
34659 setMachineCodes(mi++, (byte) 0xF3);
34660 generateREXprefix(false, dstReg, srcIndex, null);
34661 setMachineCodes(mi++, (byte) 0x0F);
34662 setMachineCodes(mi++, (byte) 0x51);
34663 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
34664 if (lister != null) lister.RRFD(miStart, "SQRTSS", dstReg, srcIndex, srcScale, srcDisp);
34665 }
34666
34667 /**
34668 * Generate a register--absolute SQRTSS. That is,
34669 * <PRE>
34670 * dstReg <<= (quad) [srcDisp]
34671 * </PRE>
34672 *
34673 * @param dstReg destination register
34674 * @param srcDisp the source displacement
34675 */
34676 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
34677 public final void emitSQRTSS_Reg_Abs(XMM dstReg, Address srcDisp) {
34678 int miStart = mi;
34679 setMachineCodes(mi++, (byte) 0xF3);
34680 generateREXprefix(false, dstReg, null, null);
34681 setMachineCodes(mi++, (byte) 0x0F);
34682 setMachineCodes(mi++, (byte) 0x51);
34683 emitAbsRegOperands(srcDisp, dstReg);
34684 if (lister != null) lister.RRA(miStart, "SQRTSS", dstReg, srcDisp);
34685 }
34686
34687 /**
34688 * Generate a register--register-index SQRTSS. That is,
34689 * <PRE>
34690 * dstReg <<= (quad) srcReg
34691 * </PRE>
34692 *
34693 * @param dstReg destination register
34694 * @param srcBase the source base register
34695 * @param srcIndex the source index register
34696 * @param srcScale the source scale
34697 * @param srcDisp the source displacement
34698 */
34699 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
34700 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
34701 public final void emitSQRTSS_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
34702 int miStart = mi;
34703 setMachineCodes(mi++, (byte) 0xF3);
34704 generateREXprefix(false, dstReg, srcIndex, srcBase);
34705 setMachineCodes(mi++, (byte) 0x0F);
34706 setMachineCodes(mi++, (byte) 0x51);
34707 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
34708 if (lister != null) lister.RRXD(miStart, "SQRTSS", dstReg, srcBase, srcIndex, srcScale, srcDisp);
34709 }
34710
34711 /**
34712 * Generate a register--register-indirect SQRTSS. That is,
34713 * <PRE>
34714 * dstReg <<= (quad) [srcBase]
34715 * </PRE>
34716 *
34717 * @param dstReg destination register
34718 * @param srcBase the source base register
34719 */
34720 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
34721 public final void emitSQRTSS_Reg_RegInd(XMM dstReg, GPR srcBase) {
34722 int miStart = mi;
34723 setMachineCodes(mi++, (byte) 0xF3);
34724 generateREXprefix(false, dstReg, null, srcBase);
34725 setMachineCodes(mi++, (byte) 0x0F);
34726 setMachineCodes(mi++, (byte) 0x51);
34727 emitRegIndirectRegOperands(srcBase, dstReg);
34728 if (lister != null) lister.RRN(miStart, "SQRTSS", dstReg, srcBase);
34729 }
34730
34731
34732 /**
34733 * Generate a register--register CVTSS2SD. That is,
34734 * <PRE>
34735 * dstReg <<= (quad) srcReg
34736 * </PRE>
34737 *
34738 * @param dstReg destination register
34739 * @param srcReg source register
34740 */
34741 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
34742 public final void emitCVTSS2SD_Reg_Reg(XMM dstReg, XMM srcReg) {
34743 int miStart = mi;
34744 setMachineCodes(mi++, (byte) 0xF3);
34745 generateREXprefix(false, dstReg, null, srcReg);
34746 setMachineCodes(mi++, (byte) 0x0F);
34747 setMachineCodes(mi++, (byte) 0x5A);
34748 emitRegRegOperands(srcReg, dstReg);
34749 if (lister != null) lister.RR(miStart, "CVTSS2SD", dstReg, srcReg);
34750 }
34751
34752 /**
34753 * Generate a register--register-displacement CVTSS2SD. That is,
34754 * <PRE>
34755 * dstReg <<= (quad) [srcBase + srcDisp]
34756 * </PRE>
34757 *
34758 * @param dstReg destination register
34759 * @param srcBase the source base register
34760 * @param srcDisp the source displacement
34761 */
34762 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
34763 public final void emitCVTSS2SD_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
34764 int miStart = mi;
34765 setMachineCodes(mi++, (byte) 0xF3);
34766 generateREXprefix(false, dstReg, null, srcBase);
34767 setMachineCodes(mi++, (byte) 0x0F);
34768 setMachineCodes(mi++, (byte) 0x5A);
34769 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
34770 if (lister != null) lister.RRD(miStart, "CVTSS2SD", dstReg, srcBase, srcDisp);
34771 }
34772
34773 /**
34774 * Generate a register--register-offset CVTSS2SD. That is,
34775 * <PRE>
34776 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
34777 * </PRE>
34778 *
34779 * @param dstReg destination register
34780 * @param srcIndex the source index register
34781 * @param srcScale the source scale
34782 * @param srcDisp the source displacement
34783 */
34784 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
34785 public final void emitCVTSS2SD_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
34786 int miStart = mi;
34787 setMachineCodes(mi++, (byte) 0xF3);
34788 generateREXprefix(false, dstReg, srcIndex, null);
34789 setMachineCodes(mi++, (byte) 0x0F);
34790 setMachineCodes(mi++, (byte) 0x5A);
34791 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
34792 if (lister != null) lister.RRFD(miStart, "CVTSS2SD", dstReg, srcIndex, srcScale, srcDisp);
34793 }
34794
34795 /**
34796 * Generate a register--absolute CVTSS2SD. That is,
34797 * <PRE>
34798 * dstReg <<= (quad) [srcDisp]
34799 * </PRE>
34800 *
34801 * @param dstReg destination register
34802 * @param srcDisp the source displacement
34803 */
34804 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
34805 public final void emitCVTSS2SD_Reg_Abs(XMM dstReg, Address srcDisp) {
34806 int miStart = mi;
34807 setMachineCodes(mi++, (byte) 0xF3);
34808 generateREXprefix(false, dstReg, null, null);
34809 setMachineCodes(mi++, (byte) 0x0F);
34810 setMachineCodes(mi++, (byte) 0x5A);
34811 emitAbsRegOperands(srcDisp, dstReg);
34812 if (lister != null) lister.RRA(miStart, "CVTSS2SD", dstReg, srcDisp);
34813 }
34814
34815 /**
34816 * Generate a register--register-index CVTSS2SD. That is,
34817 * <PRE>
34818 * dstReg <<= (quad) srcReg
34819 * </PRE>
34820 *
34821 * @param dstReg destination register
34822 * @param srcBase the source base register
34823 * @param srcIndex the source index register
34824 * @param srcScale the source scale
34825 * @param srcDisp the source displacement
34826 */
34827 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
34828 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
34829 public final void emitCVTSS2SD_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
34830 int miStart = mi;
34831 setMachineCodes(mi++, (byte) 0xF3);
34832 generateREXprefix(false, dstReg, srcIndex, srcBase);
34833 setMachineCodes(mi++, (byte) 0x0F);
34834 setMachineCodes(mi++, (byte) 0x5A);
34835 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
34836 if (lister != null) lister.RRXD(miStart, "CVTSS2SD", dstReg, srcBase, srcIndex, srcScale, srcDisp);
34837 }
34838
34839 /**
34840 * Generate a register--register-indirect CVTSS2SD. That is,
34841 * <PRE>
34842 * dstReg <<= (quad) [srcBase]
34843 * </PRE>
34844 *
34845 * @param dstReg destination register
34846 * @param srcBase the source base register
34847 */
34848 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
34849 public final void emitCVTSS2SD_Reg_RegInd(XMM dstReg, GPR srcBase) {
34850 int miStart = mi;
34851 setMachineCodes(mi++, (byte) 0xF3);
34852 generateREXprefix(false, dstReg, null, srcBase);
34853 setMachineCodes(mi++, (byte) 0x0F);
34854 setMachineCodes(mi++, (byte) 0x5A);
34855 emitRegIndirectRegOperands(srcBase, dstReg);
34856 if (lister != null) lister.RRN(miStart, "CVTSS2SD", dstReg, srcBase);
34857 }
34858
34859
34860 /**
34861 * Generate a register--register CVTSI2SS. That is,
34862 * <PRE>
34863 * dstReg <<= (quad) srcReg
34864 * </PRE>
34865 *
34866 * @param dstReg destination register
34867 * @param srcReg source register
34868 */
34869 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
34870 public final void emitCVTSI2SS_Reg_Reg(XMM dstReg, GPR srcReg) {
34871 int miStart = mi;
34872 setMachineCodes(mi++, (byte) 0xF3);
34873 generateREXprefix(false, dstReg, null, srcReg);
34874 setMachineCodes(mi++, (byte) 0x0F);
34875 setMachineCodes(mi++, (byte) 0x2A);
34876 emitRegRegOperands(srcReg, dstReg);
34877 if (lister != null) lister.RR(miStart, "CVTSI2SS", dstReg, srcReg);
34878 }
34879
34880 /**
34881 * Generate a register--register-displacement CVTSI2SS. That is,
34882 * <PRE>
34883 * dstReg <<= (quad) [srcBase + srcDisp]
34884 * </PRE>
34885 *
34886 * @param dstReg destination register
34887 * @param srcBase the source base register
34888 * @param srcDisp the source displacement
34889 */
34890 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
34891 public final void emitCVTSI2SS_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
34892 int miStart = mi;
34893 setMachineCodes(mi++, (byte) 0xF3);
34894 generateREXprefix(false, dstReg, null, srcBase);
34895 setMachineCodes(mi++, (byte) 0x0F);
34896 setMachineCodes(mi++, (byte) 0x2A);
34897 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
34898 if (lister != null) lister.RRD(miStart, "CVTSI2SS", dstReg, srcBase, srcDisp);
34899 }
34900
34901 /**
34902 * Generate a register--register-offset CVTSI2SS. That is,
34903 * <PRE>
34904 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
34905 * </PRE>
34906 *
34907 * @param dstReg destination register
34908 * @param srcIndex the source index register
34909 * @param srcScale the source scale
34910 * @param srcDisp the source displacement
34911 */
34912 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
34913 public final void emitCVTSI2SS_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
34914 int miStart = mi;
34915 setMachineCodes(mi++, (byte) 0xF3);
34916 generateREXprefix(false, dstReg, srcIndex, null);
34917 setMachineCodes(mi++, (byte) 0x0F);
34918 setMachineCodes(mi++, (byte) 0x2A);
34919 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
34920 if (lister != null) lister.RRFD(miStart, "CVTSI2SS", dstReg, srcIndex, srcScale, srcDisp);
34921 }
34922
34923 /**
34924 * Generate a register--absolute CVTSI2SS. That is,
34925 * <PRE>
34926 * dstReg <<= (quad) [srcDisp]
34927 * </PRE>
34928 *
34929 * @param dstReg destination register
34930 * @param srcDisp the source displacement
34931 */
34932 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
34933 public final void emitCVTSI2SS_Reg_Abs(XMM dstReg, Address srcDisp) {
34934 int miStart = mi;
34935 setMachineCodes(mi++, (byte) 0xF3);
34936 generateREXprefix(false, dstReg, null, null);
34937 setMachineCodes(mi++, (byte) 0x0F);
34938 setMachineCodes(mi++, (byte) 0x2A);
34939 emitAbsRegOperands(srcDisp, dstReg);
34940 if (lister != null) lister.RRA(miStart, "CVTSI2SS", dstReg, srcDisp);
34941 }
34942
34943 /**
34944 * Generate a register--register-index CVTSI2SS. That is,
34945 * <PRE>
34946 * dstReg <<= (quad) srcReg
34947 * </PRE>
34948 *
34949 * @param dstReg destination register
34950 * @param srcBase the source base register
34951 * @param srcIndex the source index register
34952 * @param srcScale the source scale
34953 * @param srcDisp the source displacement
34954 */
34955 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
34956 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
34957 public final void emitCVTSI2SS_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
34958 int miStart = mi;
34959 setMachineCodes(mi++, (byte) 0xF3);
34960 generateREXprefix(false, dstReg, srcIndex, srcBase);
34961 setMachineCodes(mi++, (byte) 0x0F);
34962 setMachineCodes(mi++, (byte) 0x2A);
34963 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
34964 if (lister != null) lister.RRXD(miStart, "CVTSI2SS", dstReg, srcBase, srcIndex, srcScale, srcDisp);
34965 }
34966
34967 /**
34968 * Generate a register--register-indirect CVTSI2SS. That is,
34969 * <PRE>
34970 * dstReg <<= (quad) [srcBase]
34971 * </PRE>
34972 *
34973 * @param dstReg destination register
34974 * @param srcBase the source base register
34975 */
34976 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
34977 public final void emitCVTSI2SS_Reg_RegInd(XMM dstReg, GPR srcBase) {
34978 int miStart = mi;
34979 setMachineCodes(mi++, (byte) 0xF3);
34980 generateREXprefix(false, dstReg, null, srcBase);
34981 setMachineCodes(mi++, (byte) 0x0F);
34982 setMachineCodes(mi++, (byte) 0x2A);
34983 emitRegIndirectRegOperands(srcBase, dstReg);
34984 if (lister != null) lister.RRN(miStart, "CVTSI2SS", dstReg, srcBase);
34985 }
34986
34987
34988 /**
34989 * Generate a register--register CVTSI2SS. That is,
34990 * <PRE>
34991 * dstReg <<= (quad) srcReg
34992 * </PRE>
34993 *
34994 * @param dstReg destination register
34995 * @param srcReg source register
34996 */
34997 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
34998 public final void emitCVTSI2SS_Reg_Reg_Quad(XMM dstReg, GPR srcReg) {
34999 int miStart = mi;
35000 setMachineCodes(mi++, (byte) 0xF3);
35001 generateREXprefix(true, dstReg, null, srcReg);
35002 setMachineCodes(mi++, (byte) 0x0F);
35003 setMachineCodes(mi++, (byte) 0x2A);
35004 emitRegRegOperands(srcReg, dstReg);
35005 if (lister != null) lister.RR(miStart, "CVTSI2SS", dstReg, srcReg);
35006 }
35007
35008 /**
35009 * Generate a register--register-displacement CVTSI2SS. That is,
35010 * <PRE>
35011 * dstReg <<= (quad) [srcBase + srcDisp]
35012 * </PRE>
35013 *
35014 * @param dstReg destination register
35015 * @param srcBase the source base register
35016 * @param srcDisp the source displacement
35017 */
35018 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
35019 public final void emitCVTSI2SS_Reg_RegDisp_Quad(XMM dstReg, GPR srcBase, Offset srcDisp) {
35020 int miStart = mi;
35021 setMachineCodes(mi++, (byte) 0xF3);
35022 generateREXprefix(true, dstReg, null, srcBase);
35023 setMachineCodes(mi++, (byte) 0x0F);
35024 setMachineCodes(mi++, (byte) 0x2A);
35025 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
35026 if (lister != null) lister.RRD(miStart, "CVTSI2SS", dstReg, srcBase, srcDisp);
35027 }
35028
35029 /**
35030 * Generate a register--register-offset CVTSI2SS. That is,
35031 * <PRE>
35032 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
35033 * </PRE>
35034 *
35035 * @param dstReg destination register
35036 * @param srcIndex the source index register
35037 * @param srcScale the source scale
35038 * @param srcDisp the source displacement
35039 */
35040 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
35041 public final void emitCVTSI2SS_Reg_RegOff_Quad(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
35042 int miStart = mi;
35043 setMachineCodes(mi++, (byte) 0xF3);
35044 generateREXprefix(true, dstReg, srcIndex, null);
35045 setMachineCodes(mi++, (byte) 0x0F);
35046 setMachineCodes(mi++, (byte) 0x2A);
35047 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
35048 if (lister != null) lister.RRFD(miStart, "CVTSI2SS", dstReg, srcIndex, srcScale, srcDisp);
35049 }
35050
35051 /**
35052 * Generate a register--absolute CVTSI2SS. That is,
35053 * <PRE>
35054 * dstReg <<= (quad) [srcDisp]
35055 * </PRE>
35056 *
35057 * @param dstReg destination register
35058 * @param srcDisp the source displacement
35059 */
35060 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
35061 public final void emitCVTSI2SS_Reg_Abs_Quad(XMM dstReg, Address srcDisp) {
35062 int miStart = mi;
35063 setMachineCodes(mi++, (byte) 0xF3);
35064 generateREXprefix(true, dstReg, null, null);
35065 setMachineCodes(mi++, (byte) 0x0F);
35066 setMachineCodes(mi++, (byte) 0x2A);
35067 emitAbsRegOperands(srcDisp, dstReg);
35068 if (lister != null) lister.RRA(miStart, "CVTSI2SS", dstReg, srcDisp);
35069 }
35070
35071 /**
35072 * Generate a register--register-index CVTSI2SS. That is,
35073 * <PRE>
35074 * dstReg <<= (quad) srcReg
35075 * </PRE>
35076 *
35077 * @param dstReg destination register
35078 * @param srcBase the source base register
35079 * @param srcIndex the source index register
35080 * @param srcScale the source scale
35081 * @param srcDisp the source displacement
35082 */
35083 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
35084 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
35085 public final void emitCVTSI2SS_Reg_RegIdx_Quad(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
35086 int miStart = mi;
35087 setMachineCodes(mi++, (byte) 0xF3);
35088 generateREXprefix(true, dstReg, srcIndex, srcBase);
35089 setMachineCodes(mi++, (byte) 0x0F);
35090 setMachineCodes(mi++, (byte) 0x2A);
35091 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
35092 if (lister != null) lister.RRXD(miStart, "CVTSI2SS", dstReg, srcBase, srcIndex, srcScale, srcDisp);
35093 }
35094
35095 /**
35096 * Generate a register--register-indirect CVTSI2SS. That is,
35097 * <PRE>
35098 * dstReg <<= (quad) [srcBase]
35099 * </PRE>
35100 *
35101 * @param dstReg destination register
35102 * @param srcBase the source base register
35103 */
35104 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
35105 public final void emitCVTSI2SS_Reg_RegInd_Quad(XMM dstReg, GPR srcBase) {
35106 int miStart = mi;
35107 setMachineCodes(mi++, (byte) 0xF3);
35108 generateREXprefix(true, dstReg, null, srcBase);
35109 setMachineCodes(mi++, (byte) 0x0F);
35110 setMachineCodes(mi++, (byte) 0x2A);
35111 emitRegIndirectRegOperands(srcBase, dstReg);
35112 if (lister != null) lister.RRN(miStart, "CVTSI2SS", dstReg, srcBase);
35113 }
35114
35115
35116 /**
35117 * Generate a register--register CVTSS2SI. That is,
35118 * <PRE>
35119 * dstReg <<= (quad) srcReg
35120 * </PRE>
35121 *
35122 * @param dstReg destination register
35123 * @param srcReg source register
35124 */
35125 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
35126 public final void emitCVTSS2SI_Reg_Reg(GPR dstReg, XMM srcReg) {
35127 int miStart = mi;
35128 setMachineCodes(mi++, (byte) 0xF3);
35129 generateREXprefix(false, dstReg, null, srcReg);
35130 setMachineCodes(mi++, (byte) 0x0F);
35131 setMachineCodes(mi++, (byte) 0x2D);
35132 emitRegRegOperands(srcReg, dstReg);
35133 if (lister != null) lister.RR(miStart, "CVTSS2SI", dstReg, srcReg);
35134 }
35135
35136 /**
35137 * Generate a register--register-displacement CVTSS2SI. That is,
35138 * <PRE>
35139 * dstReg <<= (quad) [srcBase + srcDisp]
35140 * </PRE>
35141 *
35142 * @param dstReg destination register
35143 * @param srcBase the source base register
35144 * @param srcDisp the source displacement
35145 */
35146 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
35147 public final void emitCVTSS2SI_Reg_RegDisp(GPR dstReg, GPR srcBase, Offset srcDisp) {
35148 int miStart = mi;
35149 setMachineCodes(mi++, (byte) 0xF3);
35150 generateREXprefix(false, dstReg, null, srcBase);
35151 setMachineCodes(mi++, (byte) 0x0F);
35152 setMachineCodes(mi++, (byte) 0x2D);
35153 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
35154 if (lister != null) lister.RRD(miStart, "CVTSS2SI", dstReg, srcBase, srcDisp);
35155 }
35156
35157 /**
35158 * Generate a register--register-offset CVTSS2SI. That is,
35159 * <PRE>
35160 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
35161 * </PRE>
35162 *
35163 * @param dstReg destination register
35164 * @param srcIndex the source index register
35165 * @param srcScale the source scale
35166 * @param srcDisp the source displacement
35167 */
35168 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
35169 public final void emitCVTSS2SI_Reg_RegOff(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
35170 int miStart = mi;
35171 setMachineCodes(mi++, (byte) 0xF3);
35172 generateREXprefix(false, dstReg, srcIndex, null);
35173 setMachineCodes(mi++, (byte) 0x0F);
35174 setMachineCodes(mi++, (byte) 0x2D);
35175 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
35176 if (lister != null) lister.RRFD(miStart, "CVTSS2SI", dstReg, srcIndex, srcScale, srcDisp);
35177 }
35178
35179 /**
35180 * Generate a register--absolute CVTSS2SI. That is,
35181 * <PRE>
35182 * dstReg <<= (quad) [srcDisp]
35183 * </PRE>
35184 *
35185 * @param dstReg destination register
35186 * @param srcDisp the source displacement
35187 */
35188 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
35189 public final void emitCVTSS2SI_Reg_Abs(GPR dstReg, Address srcDisp) {
35190 int miStart = mi;
35191 setMachineCodes(mi++, (byte) 0xF3);
35192 generateREXprefix(false, dstReg, null, null);
35193 setMachineCodes(mi++, (byte) 0x0F);
35194 setMachineCodes(mi++, (byte) 0x2D);
35195 emitAbsRegOperands(srcDisp, dstReg);
35196 if (lister != null) lister.RRA(miStart, "CVTSS2SI", dstReg, srcDisp);
35197 }
35198
35199 /**
35200 * Generate a register--register-index CVTSS2SI. That is,
35201 * <PRE>
35202 * dstReg <<= (quad) srcReg
35203 * </PRE>
35204 *
35205 * @param dstReg destination register
35206 * @param srcBase the source base register
35207 * @param srcIndex the source index register
35208 * @param srcScale the source scale
35209 * @param srcDisp the source displacement
35210 */
35211 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
35212 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
35213 public final void emitCVTSS2SI_Reg_RegIdx(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
35214 int miStart = mi;
35215 setMachineCodes(mi++, (byte) 0xF3);
35216 generateREXprefix(false, dstReg, srcIndex, srcBase);
35217 setMachineCodes(mi++, (byte) 0x0F);
35218 setMachineCodes(mi++, (byte) 0x2D);
35219 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
35220 if (lister != null) lister.RRXD(miStart, "CVTSS2SI", dstReg, srcBase, srcIndex, srcScale, srcDisp);
35221 }
35222
35223 /**
35224 * Generate a register--register-indirect CVTSS2SI. That is,
35225 * <PRE>
35226 * dstReg <<= (quad) [srcBase]
35227 * </PRE>
35228 *
35229 * @param dstReg destination register
35230 * @param srcBase the source base register
35231 */
35232 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
35233 public final void emitCVTSS2SI_Reg_RegInd(GPR dstReg, GPR srcBase) {
35234 int miStart = mi;
35235 setMachineCodes(mi++, (byte) 0xF3);
35236 generateREXprefix(false, dstReg, null, srcBase);
35237 setMachineCodes(mi++, (byte) 0x0F);
35238 setMachineCodes(mi++, (byte) 0x2D);
35239 emitRegIndirectRegOperands(srcBase, dstReg);
35240 if (lister != null) lister.RRN(miStart, "CVTSS2SI", dstReg, srcBase);
35241 }
35242
35243
35244 /**
35245 * Generate a register--register CVTSS2SI. That is,
35246 * <PRE>
35247 * dstReg <<= (quad) srcReg
35248 * </PRE>
35249 *
35250 * @param dstReg destination register
35251 * @param srcReg source register
35252 */
35253 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
35254 public final void emitCVTSS2SI_Reg_Reg_Quad(GPR dstReg, XMM srcReg) {
35255 int miStart = mi;
35256 setMachineCodes(mi++, (byte) 0xF3);
35257 generateREXprefix(true, dstReg, null, srcReg);
35258 setMachineCodes(mi++, (byte) 0x0F);
35259 setMachineCodes(mi++, (byte) 0x2D);
35260 emitRegRegOperands(srcReg, dstReg);
35261 if (lister != null) lister.RR(miStart, "CVTSS2SI", dstReg, srcReg);
35262 }
35263
35264 /**
35265 * Generate a register--register-displacement CVTSS2SI. That is,
35266 * <PRE>
35267 * dstReg <<= (quad) [srcBase + srcDisp]
35268 * </PRE>
35269 *
35270 * @param dstReg destination register
35271 * @param srcBase the source base register
35272 * @param srcDisp the source displacement
35273 */
35274 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
35275 public final void emitCVTSS2SI_Reg_RegDisp_Quad(GPR dstReg, GPR srcBase, Offset srcDisp) {
35276 int miStart = mi;
35277 setMachineCodes(mi++, (byte) 0xF3);
35278 generateREXprefix(true, dstReg, null, srcBase);
35279 setMachineCodes(mi++, (byte) 0x0F);
35280 setMachineCodes(mi++, (byte) 0x2D);
35281 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
35282 if (lister != null) lister.RRD(miStart, "CVTSS2SI", dstReg, srcBase, srcDisp);
35283 }
35284
35285 /**
35286 * Generate a register--register-offset CVTSS2SI. That is,
35287 * <PRE>
35288 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
35289 * </PRE>
35290 *
35291 * @param dstReg destination register
35292 * @param srcIndex the source index register
35293 * @param srcScale the source scale
35294 * @param srcDisp the source displacement
35295 */
35296 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
35297 public final void emitCVTSS2SI_Reg_RegOff_Quad(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
35298 int miStart = mi;
35299 setMachineCodes(mi++, (byte) 0xF3);
35300 generateREXprefix(true, dstReg, srcIndex, null);
35301 setMachineCodes(mi++, (byte) 0x0F);
35302 setMachineCodes(mi++, (byte) 0x2D);
35303 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
35304 if (lister != null) lister.RRFD(miStart, "CVTSS2SI", dstReg, srcIndex, srcScale, srcDisp);
35305 }
35306
35307 /**
35308 * Generate a register--absolute CVTSS2SI. That is,
35309 * <PRE>
35310 * dstReg <<= (quad) [srcDisp]
35311 * </PRE>
35312 *
35313 * @param dstReg destination register
35314 * @param srcDisp the source displacement
35315 */
35316 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
35317 public final void emitCVTSS2SI_Reg_Abs_Quad(GPR dstReg, Address srcDisp) {
35318 int miStart = mi;
35319 setMachineCodes(mi++, (byte) 0xF3);
35320 generateREXprefix(true, dstReg, null, null);
35321 setMachineCodes(mi++, (byte) 0x0F);
35322 setMachineCodes(mi++, (byte) 0x2D);
35323 emitAbsRegOperands(srcDisp, dstReg);
35324 if (lister != null) lister.RRA(miStart, "CVTSS2SI", dstReg, srcDisp);
35325 }
35326
35327 /**
35328 * Generate a register--register-index CVTSS2SI. That is,
35329 * <PRE>
35330 * dstReg <<= (quad) srcReg
35331 * </PRE>
35332 *
35333 * @param dstReg destination register
35334 * @param srcBase the source base register
35335 * @param srcIndex the source index register
35336 * @param srcScale the source scale
35337 * @param srcDisp the source displacement
35338 */
35339 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
35340 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
35341 public final void emitCVTSS2SI_Reg_RegIdx_Quad(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
35342 int miStart = mi;
35343 setMachineCodes(mi++, (byte) 0xF3);
35344 generateREXprefix(true, dstReg, srcIndex, srcBase);
35345 setMachineCodes(mi++, (byte) 0x0F);
35346 setMachineCodes(mi++, (byte) 0x2D);
35347 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
35348 if (lister != null) lister.RRXD(miStart, "CVTSS2SI", dstReg, srcBase, srcIndex, srcScale, srcDisp);
35349 }
35350
35351 /**
35352 * Generate a register--register-indirect CVTSS2SI. That is,
35353 * <PRE>
35354 * dstReg <<= (quad) [srcBase]
35355 * </PRE>
35356 *
35357 * @param dstReg destination register
35358 * @param srcBase the source base register
35359 */
35360 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
35361 public final void emitCVTSS2SI_Reg_RegInd_Quad(GPR dstReg, GPR srcBase) {
35362 int miStart = mi;
35363 setMachineCodes(mi++, (byte) 0xF3);
35364 generateREXprefix(true, dstReg, null, srcBase);
35365 setMachineCodes(mi++, (byte) 0x0F);
35366 setMachineCodes(mi++, (byte) 0x2D);
35367 emitRegIndirectRegOperands(srcBase, dstReg);
35368 if (lister != null) lister.RRN(miStart, "CVTSS2SI", dstReg, srcBase);
35369 }
35370
35371
35372 /**
35373 * Generate a register--register CVTTSS2SI. That is,
35374 * <PRE>
35375 * dstReg <<= (quad) srcReg
35376 * </PRE>
35377 *
35378 * @param dstReg destination register
35379 * @param srcReg source register
35380 */
35381 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
35382 public final void emitCVTTSS2SI_Reg_Reg(GPR dstReg, XMM srcReg) {
35383 int miStart = mi;
35384 setMachineCodes(mi++, (byte) 0xF3);
35385 generateREXprefix(false, dstReg, null, srcReg);
35386 setMachineCodes(mi++, (byte) 0x0F);
35387 setMachineCodes(mi++, (byte) 0x2C);
35388 emitRegRegOperands(srcReg, dstReg);
35389 if (lister != null) lister.RR(miStart, "CVTTSS2SI", dstReg, srcReg);
35390 }
35391
35392 /**
35393 * Generate a register--register-displacement CVTTSS2SI. That is,
35394 * <PRE>
35395 * dstReg <<= (quad) [srcBase + srcDisp]
35396 * </PRE>
35397 *
35398 * @param dstReg destination register
35399 * @param srcBase the source base register
35400 * @param srcDisp the source displacement
35401 */
35402 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
35403 public final void emitCVTTSS2SI_Reg_RegDisp(GPR dstReg, GPR srcBase, Offset srcDisp) {
35404 int miStart = mi;
35405 setMachineCodes(mi++, (byte) 0xF3);
35406 generateREXprefix(false, dstReg, null, srcBase);
35407 setMachineCodes(mi++, (byte) 0x0F);
35408 setMachineCodes(mi++, (byte) 0x2C);
35409 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
35410 if (lister != null) lister.RRD(miStart, "CVTTSS2SI", dstReg, srcBase, srcDisp);
35411 }
35412
35413 /**
35414 * Generate a register--register-offset CVTTSS2SI. That is,
35415 * <PRE>
35416 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
35417 * </PRE>
35418 *
35419 * @param dstReg destination register
35420 * @param srcIndex the source index register
35421 * @param srcScale the source scale
35422 * @param srcDisp the source displacement
35423 */
35424 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
35425 public final void emitCVTTSS2SI_Reg_RegOff(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
35426 int miStart = mi;
35427 setMachineCodes(mi++, (byte) 0xF3);
35428 generateREXprefix(false, dstReg, srcIndex, null);
35429 setMachineCodes(mi++, (byte) 0x0F);
35430 setMachineCodes(mi++, (byte) 0x2C);
35431 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
35432 if (lister != null) lister.RRFD(miStart, "CVTTSS2SI", dstReg, srcIndex, srcScale, srcDisp);
35433 }
35434
35435 /**
35436 * Generate a register--absolute CVTTSS2SI. That is,
35437 * <PRE>
35438 * dstReg <<= (quad) [srcDisp]
35439 * </PRE>
35440 *
35441 * @param dstReg destination register
35442 * @param srcDisp the source displacement
35443 */
35444 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
35445 public final void emitCVTTSS2SI_Reg_Abs(GPR dstReg, Address srcDisp) {
35446 int miStart = mi;
35447 setMachineCodes(mi++, (byte) 0xF3);
35448 generateREXprefix(false, dstReg, null, null);
35449 setMachineCodes(mi++, (byte) 0x0F);
35450 setMachineCodes(mi++, (byte) 0x2C);
35451 emitAbsRegOperands(srcDisp, dstReg);
35452 if (lister != null) lister.RRA(miStart, "CVTTSS2SI", dstReg, srcDisp);
35453 }
35454
35455 /**
35456 * Generate a register--register-index CVTTSS2SI. That is,
35457 * <PRE>
35458 * dstReg <<= (quad) srcReg
35459 * </PRE>
35460 *
35461 * @param dstReg destination register
35462 * @param srcBase the source base register
35463 * @param srcIndex the source index register
35464 * @param srcScale the source scale
35465 * @param srcDisp the source displacement
35466 */
35467 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
35468 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
35469 public final void emitCVTTSS2SI_Reg_RegIdx(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
35470 int miStart = mi;
35471 setMachineCodes(mi++, (byte) 0xF3);
35472 generateREXprefix(false, dstReg, srcIndex, srcBase);
35473 setMachineCodes(mi++, (byte) 0x0F);
35474 setMachineCodes(mi++, (byte) 0x2C);
35475 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
35476 if (lister != null) lister.RRXD(miStart, "CVTTSS2SI", dstReg, srcBase, srcIndex, srcScale, srcDisp);
35477 }
35478
35479 /**
35480 * Generate a register--register-indirect CVTTSS2SI. That is,
35481 * <PRE>
35482 * dstReg <<= (quad) [srcBase]
35483 * </PRE>
35484 *
35485 * @param dstReg destination register
35486 * @param srcBase the source base register
35487 */
35488 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
35489 public final void emitCVTTSS2SI_Reg_RegInd(GPR dstReg, GPR srcBase) {
35490 int miStart = mi;
35491 setMachineCodes(mi++, (byte) 0xF3);
35492 generateREXprefix(false, dstReg, null, srcBase);
35493 setMachineCodes(mi++, (byte) 0x0F);
35494 setMachineCodes(mi++, (byte) 0x2C);
35495 emitRegIndirectRegOperands(srcBase, dstReg);
35496 if (lister != null) lister.RRN(miStart, "CVTTSS2SI", dstReg, srcBase);
35497 }
35498
35499
35500 /**
35501 * Generate a register--register CVTTSS2SI. That is,
35502 * <PRE>
35503 * dstReg <<= (quad) srcReg
35504 * </PRE>
35505 *
35506 * @param dstReg destination register
35507 * @param srcReg source register
35508 */
35509 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
35510 public final void emitCVTTSS2SI_Reg_Reg_Quad(GPR dstReg, XMM srcReg) {
35511 int miStart = mi;
35512 setMachineCodes(mi++, (byte) 0xF3);
35513 generateREXprefix(true, dstReg, null, srcReg);
35514 setMachineCodes(mi++, (byte) 0x0F);
35515 setMachineCodes(mi++, (byte) 0x2C);
35516 emitRegRegOperands(srcReg, dstReg);
35517 if (lister != null) lister.RR(miStart, "CVTTSS2SI", dstReg, srcReg);
35518 }
35519
35520 /**
35521 * Generate a register--register-displacement CVTTSS2SI. That is,
35522 * <PRE>
35523 * dstReg <<= (quad) [srcBase + srcDisp]
35524 * </PRE>
35525 *
35526 * @param dstReg destination register
35527 * @param srcBase the source base register
35528 * @param srcDisp the source displacement
35529 */
35530 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
35531 public final void emitCVTTSS2SI_Reg_RegDisp_Quad(GPR dstReg, GPR srcBase, Offset srcDisp) {
35532 int miStart = mi;
35533 setMachineCodes(mi++, (byte) 0xF3);
35534 generateREXprefix(true, dstReg, null, srcBase);
35535 setMachineCodes(mi++, (byte) 0x0F);
35536 setMachineCodes(mi++, (byte) 0x2C);
35537 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
35538 if (lister != null) lister.RRD(miStart, "CVTTSS2SI", dstReg, srcBase, srcDisp);
35539 }
35540
35541 /**
35542 * Generate a register--register-offset CVTTSS2SI. That is,
35543 * <PRE>
35544 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
35545 * </PRE>
35546 *
35547 * @param dstReg destination register
35548 * @param srcIndex the source index register
35549 * @param srcScale the source scale
35550 * @param srcDisp the source displacement
35551 */
35552 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
35553 public final void emitCVTTSS2SI_Reg_RegOff_Quad(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
35554 int miStart = mi;
35555 setMachineCodes(mi++, (byte) 0xF3);
35556 generateREXprefix(true, dstReg, srcIndex, null);
35557 setMachineCodes(mi++, (byte) 0x0F);
35558 setMachineCodes(mi++, (byte) 0x2C);
35559 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
35560 if (lister != null) lister.RRFD(miStart, "CVTTSS2SI", dstReg, srcIndex, srcScale, srcDisp);
35561 }
35562
35563 /**
35564 * Generate a register--absolute CVTTSS2SI. That is,
35565 * <PRE>
35566 * dstReg <<= (quad) [srcDisp]
35567 * </PRE>
35568 *
35569 * @param dstReg destination register
35570 * @param srcDisp the source displacement
35571 */
35572 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
35573 public final void emitCVTTSS2SI_Reg_Abs_Quad(GPR dstReg, Address srcDisp) {
35574 int miStart = mi;
35575 setMachineCodes(mi++, (byte) 0xF3);
35576 generateREXprefix(true, dstReg, null, null);
35577 setMachineCodes(mi++, (byte) 0x0F);
35578 setMachineCodes(mi++, (byte) 0x2C);
35579 emitAbsRegOperands(srcDisp, dstReg);
35580 if (lister != null) lister.RRA(miStart, "CVTTSS2SI", dstReg, srcDisp);
35581 }
35582
35583 /**
35584 * Generate a register--register-index CVTTSS2SI. That is,
35585 * <PRE>
35586 * dstReg <<= (quad) srcReg
35587 * </PRE>
35588 *
35589 * @param dstReg destination register
35590 * @param srcBase the source base register
35591 * @param srcIndex the source index register
35592 * @param srcScale the source scale
35593 * @param srcDisp the source displacement
35594 */
35595 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
35596 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
35597 public final void emitCVTTSS2SI_Reg_RegIdx_Quad(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
35598 int miStart = mi;
35599 setMachineCodes(mi++, (byte) 0xF3);
35600 generateREXprefix(true, dstReg, srcIndex, srcBase);
35601 setMachineCodes(mi++, (byte) 0x0F);
35602 setMachineCodes(mi++, (byte) 0x2C);
35603 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
35604 if (lister != null) lister.RRXD(miStart, "CVTTSS2SI", dstReg, srcBase, srcIndex, srcScale, srcDisp);
35605 }
35606
35607 /**
35608 * Generate a register--register-indirect CVTTSS2SI. That is,
35609 * <PRE>
35610 * dstReg <<= (quad) [srcBase]
35611 * </PRE>
35612 *
35613 * @param dstReg destination register
35614 * @param srcBase the source base register
35615 */
35616 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
35617 public final void emitCVTTSS2SI_Reg_RegInd_Quad(GPR dstReg, GPR srcBase) {
35618 int miStart = mi;
35619 setMachineCodes(mi++, (byte) 0xF3);
35620 generateREXprefix(true, dstReg, null, srcBase);
35621 setMachineCodes(mi++, (byte) 0x0F);
35622 setMachineCodes(mi++, (byte) 0x2C);
35623 emitRegIndirectRegOperands(srcBase, dstReg);
35624 if (lister != null) lister.RRN(miStart, "CVTTSS2SI", dstReg, srcBase);
35625 }
35626
35627
35628 /**
35629 * Generate a register--register UCOMISS. That is,
35630 * <PRE>
35631 * dstReg <<= (quad) srcReg
35632 * </PRE>
35633 *
35634 * @param dstReg destination register
35635 * @param srcReg source register
35636 */
35637 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
35638 public final void emitUCOMISS_Reg_Reg(XMM dstReg, XMM srcReg) {
35639 int miStart = mi;
35640 generateREXprefix(false, dstReg, null, srcReg);
35641 setMachineCodes(mi++, (byte) 0x0F);
35642 setMachineCodes(mi++, (byte) 0x2E);
35643 emitRegRegOperands(srcReg, dstReg);
35644 if (lister != null) lister.RR(miStart, "UCOMISS", dstReg, srcReg);
35645 }
35646
35647 /**
35648 * Generate a register--register-displacement UCOMISS. That is,
35649 * <PRE>
35650 * dstReg <<= (quad) [srcBase + srcDisp]
35651 * </PRE>
35652 *
35653 * @param dstReg destination register
35654 * @param srcBase the source base register
35655 * @param srcDisp the source displacement
35656 */
35657 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
35658 public final void emitUCOMISS_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
35659 int miStart = mi;
35660 generateREXprefix(false, dstReg, null, srcBase);
35661 setMachineCodes(mi++, (byte) 0x0F);
35662 setMachineCodes(mi++, (byte) 0x2E);
35663 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
35664 if (lister != null) lister.RRD(miStart, "UCOMISS", dstReg, srcBase, srcDisp);
35665 }
35666
35667 /**
35668 * Generate a register--register-offset UCOMISS. That is,
35669 * <PRE>
35670 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
35671 * </PRE>
35672 *
35673 * @param dstReg destination register
35674 * @param srcIndex the source index register
35675 * @param srcScale the source scale
35676 * @param srcDisp the source displacement
35677 */
35678 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
35679 public final void emitUCOMISS_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
35680 int miStart = mi;
35681 generateREXprefix(false, dstReg, srcIndex, null);
35682 setMachineCodes(mi++, (byte) 0x0F);
35683 setMachineCodes(mi++, (byte) 0x2E);
35684 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
35685 if (lister != null) lister.RRFD(miStart, "UCOMISS", dstReg, srcIndex, srcScale, srcDisp);
35686 }
35687
35688 /**
35689 * Generate a register--absolute UCOMISS. That is,
35690 * <PRE>
35691 * dstReg <<= (quad) [srcDisp]
35692 * </PRE>
35693 *
35694 * @param dstReg destination register
35695 * @param srcDisp the source displacement
35696 */
35697 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
35698 public final void emitUCOMISS_Reg_Abs(XMM dstReg, Address srcDisp) {
35699 int miStart = mi;
35700 generateREXprefix(false, dstReg, null, null);
35701 setMachineCodes(mi++, (byte) 0x0F);
35702 setMachineCodes(mi++, (byte) 0x2E);
35703 emitAbsRegOperands(srcDisp, dstReg);
35704 if (lister != null) lister.RRA(miStart, "UCOMISS", dstReg, srcDisp);
35705 }
35706
35707 /**
35708 * Generate a register--register-index UCOMISS. That is,
35709 * <PRE>
35710 * dstReg <<= (quad) srcReg
35711 * </PRE>
35712 *
35713 * @param dstReg destination register
35714 * @param srcBase the source base register
35715 * @param srcIndex the source index register
35716 * @param srcScale the source scale
35717 * @param srcDisp the source displacement
35718 */
35719 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
35720 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
35721 public final void emitUCOMISS_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
35722 int miStart = mi;
35723 generateREXprefix(false, dstReg, srcIndex, srcBase);
35724 setMachineCodes(mi++, (byte) 0x0F);
35725 setMachineCodes(mi++, (byte) 0x2E);
35726 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
35727 if (lister != null) lister.RRXD(miStart, "UCOMISS", dstReg, srcBase, srcIndex, srcScale, srcDisp);
35728 }
35729
35730 /**
35731 * Generate a register--register-indirect UCOMISS. That is,
35732 * <PRE>
35733 * dstReg <<= (quad) [srcBase]
35734 * </PRE>
35735 *
35736 * @param dstReg destination register
35737 * @param srcBase the source base register
35738 */
35739 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
35740 public final void emitUCOMISS_Reg_RegInd(XMM dstReg, GPR srcBase) {
35741 int miStart = mi;
35742 generateREXprefix(false, dstReg, null, srcBase);
35743 setMachineCodes(mi++, (byte) 0x0F);
35744 setMachineCodes(mi++, (byte) 0x2E);
35745 emitRegIndirectRegOperands(srcBase, dstReg);
35746 if (lister != null) lister.RRN(miStart, "UCOMISS", dstReg, srcBase);
35747 }
35748
35749
35750 /**
35751 * Generate a register--register CMPEQSS. That is,
35752 * <PRE>
35753 * dstReg <<= (quad) srcReg
35754 * </PRE>
35755 *
35756 * @param dstReg destination register
35757 * @param srcReg source register
35758 */
35759 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
35760 public final void emitCMPEQSS_Reg_Reg(XMM dstReg, XMM srcReg) {
35761 int miStart = mi;
35762 setMachineCodes(mi++, (byte) 0xF3);
35763 generateREXprefix(false, dstReg, null, srcReg);
35764 setMachineCodes(mi++, (byte) 0x0F);
35765 setMachineCodes(mi++, (byte) 0xC2);
35766 emitRegRegOperands(srcReg, dstReg);
35767 setMachineCodes(mi++, (byte) 0);
35768 if (lister != null) lister.RR(miStart, "CMPEQSS", dstReg, srcReg);
35769 }
35770
35771 /**
35772 * Generate a register--register-displacement CMPEQSS. That is,
35773 * <PRE>
35774 * dstReg <<= (quad) [srcBase + srcDisp]
35775 * </PRE>
35776 *
35777 * @param dstReg destination register
35778 * @param srcBase the source base register
35779 * @param srcDisp the source displacement
35780 */
35781 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
35782 public final void emitCMPEQSS_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
35783 int miStart = mi;
35784 setMachineCodes(mi++, (byte) 0xF3);
35785 generateREXprefix(false, dstReg, null, srcBase);
35786 setMachineCodes(mi++, (byte) 0x0F);
35787 setMachineCodes(mi++, (byte) 0xC2);
35788 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
35789 setMachineCodes(mi++, (byte) 0);
35790 if (lister != null) lister.RRD(miStart, "CMPEQSS", dstReg, srcBase, srcDisp);
35791 }
35792
35793 /**
35794 * Generate a register--register-offset CMPEQSS. That is,
35795 * <PRE>
35796 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
35797 * </PRE>
35798 *
35799 * @param dstReg destination register
35800 * @param srcIndex the source index register
35801 * @param srcScale the source scale
35802 * @param srcDisp the source displacement
35803 */
35804 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
35805 public final void emitCMPEQSS_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
35806 int miStart = mi;
35807 setMachineCodes(mi++, (byte) 0xF3);
35808 generateREXprefix(false, dstReg, srcIndex, null);
35809 setMachineCodes(mi++, (byte) 0x0F);
35810 setMachineCodes(mi++, (byte) 0xC2);
35811 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
35812 setMachineCodes(mi++, (byte) 0);
35813 if (lister != null) lister.RRFD(miStart, "CMPEQSS", dstReg, srcIndex, srcScale, srcDisp);
35814 }
35815
35816 /**
35817 * Generate a register--absolute CMPEQSS. That is,
35818 * <PRE>
35819 * dstReg <<= (quad) [srcDisp]
35820 * </PRE>
35821 *
35822 * @param dstReg destination register
35823 * @param srcDisp the source displacement
35824 */
35825 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
35826 public final void emitCMPEQSS_Reg_Abs(XMM dstReg, Address srcDisp) {
35827 int miStart = mi;
35828 setMachineCodes(mi++, (byte) 0xF3);
35829 generateREXprefix(false, dstReg, null, null);
35830 setMachineCodes(mi++, (byte) 0x0F);
35831 setMachineCodes(mi++, (byte) 0xC2);
35832 emitAbsRegOperands(srcDisp, dstReg);
35833 setMachineCodes(mi++, (byte) 0);
35834 if (lister != null) lister.RRA(miStart, "CMPEQSS", dstReg, srcDisp);
35835 }
35836
35837 /**
35838 * Generate a register--register-index CMPEQSS. That is,
35839 * <PRE>
35840 * dstReg <<= (quad) srcReg
35841 * </PRE>
35842 *
35843 * @param dstReg destination register
35844 * @param srcBase the source base register
35845 * @param srcIndex the source index register
35846 * @param srcScale the source scale
35847 * @param srcDisp the source displacement
35848 */
35849 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
35850 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
35851 public final void emitCMPEQSS_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
35852 int miStart = mi;
35853 setMachineCodes(mi++, (byte) 0xF3);
35854 generateREXprefix(false, dstReg, srcIndex, srcBase);
35855 setMachineCodes(mi++, (byte) 0x0F);
35856 setMachineCodes(mi++, (byte) 0xC2);
35857 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
35858 setMachineCodes(mi++, (byte) 0);
35859 if (lister != null) lister.RRXD(miStart, "CMPEQSS", dstReg, srcBase, srcIndex, srcScale, srcDisp);
35860 }
35861
35862 /**
35863 * Generate a register--register-indirect CMPEQSS. That is,
35864 * <PRE>
35865 * dstReg <<= (quad) [srcBase]
35866 * </PRE>
35867 *
35868 * @param dstReg destination register
35869 * @param srcBase the source base register
35870 */
35871 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
35872 public final void emitCMPEQSS_Reg_RegInd(XMM dstReg, GPR srcBase) {
35873 int miStart = mi;
35874 setMachineCodes(mi++, (byte) 0xF3);
35875 generateREXprefix(false, dstReg, null, srcBase);
35876 setMachineCodes(mi++, (byte) 0x0F);
35877 setMachineCodes(mi++, (byte) 0xC2);
35878 emitRegIndirectRegOperands(srcBase, dstReg);
35879 setMachineCodes(mi++, (byte) 0);
35880 if (lister != null) lister.RRN(miStart, "CMPEQSS", dstReg, srcBase);
35881 }
35882
35883
35884 /**
35885 * Generate a register--register CMPLTSS. That is,
35886 * <PRE>
35887 * dstReg <<= (quad) srcReg
35888 * </PRE>
35889 *
35890 * @param dstReg destination register
35891 * @param srcReg source register
35892 */
35893 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
35894 public final void emitCMPLTSS_Reg_Reg(XMM dstReg, XMM srcReg) {
35895 int miStart = mi;
35896 setMachineCodes(mi++, (byte) 0xF3);
35897 generateREXprefix(false, dstReg, null, srcReg);
35898 setMachineCodes(mi++, (byte) 0x0F);
35899 setMachineCodes(mi++, (byte) 0xC2);
35900 emitRegRegOperands(srcReg, dstReg);
35901 setMachineCodes(mi++, (byte) 1);
35902 if (lister != null) lister.RR(miStart, "CMPLTSS", dstReg, srcReg);
35903 }
35904
35905 /**
35906 * Generate a register--register-displacement CMPLTSS. That is,
35907 * <PRE>
35908 * dstReg <<= (quad) [srcBase + srcDisp]
35909 * </PRE>
35910 *
35911 * @param dstReg destination register
35912 * @param srcBase the source base register
35913 * @param srcDisp the source displacement
35914 */
35915 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
35916 public final void emitCMPLTSS_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
35917 int miStart = mi;
35918 setMachineCodes(mi++, (byte) 0xF3);
35919 generateREXprefix(false, dstReg, null, srcBase);
35920 setMachineCodes(mi++, (byte) 0x0F);
35921 setMachineCodes(mi++, (byte) 0xC2);
35922 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
35923 setMachineCodes(mi++, (byte) 1);
35924 if (lister != null) lister.RRD(miStart, "CMPLTSS", dstReg, srcBase, srcDisp);
35925 }
35926
35927 /**
35928 * Generate a register--register-offset CMPLTSS. That is,
35929 * <PRE>
35930 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
35931 * </PRE>
35932 *
35933 * @param dstReg destination register
35934 * @param srcIndex the source index register
35935 * @param srcScale the source scale
35936 * @param srcDisp the source displacement
35937 */
35938 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
35939 public final void emitCMPLTSS_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
35940 int miStart = mi;
35941 setMachineCodes(mi++, (byte) 0xF3);
35942 generateREXprefix(false, dstReg, srcIndex, null);
35943 setMachineCodes(mi++, (byte) 0x0F);
35944 setMachineCodes(mi++, (byte) 0xC2);
35945 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
35946 setMachineCodes(mi++, (byte) 1);
35947 if (lister != null) lister.RRFD(miStart, "CMPLTSS", dstReg, srcIndex, srcScale, srcDisp);
35948 }
35949
35950 /**
35951 * Generate a register--absolute CMPLTSS. That is,
35952 * <PRE>
35953 * dstReg <<= (quad) [srcDisp]
35954 * </PRE>
35955 *
35956 * @param dstReg destination register
35957 * @param srcDisp the source displacement
35958 */
35959 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
35960 public final void emitCMPLTSS_Reg_Abs(XMM dstReg, Address srcDisp) {
35961 int miStart = mi;
35962 setMachineCodes(mi++, (byte) 0xF3);
35963 generateREXprefix(false, dstReg, null, null);
35964 setMachineCodes(mi++, (byte) 0x0F);
35965 setMachineCodes(mi++, (byte) 0xC2);
35966 emitAbsRegOperands(srcDisp, dstReg);
35967 setMachineCodes(mi++, (byte) 1);
35968 if (lister != null) lister.RRA(miStart, "CMPLTSS", dstReg, srcDisp);
35969 }
35970
35971 /**
35972 * Generate a register--register-index CMPLTSS. That is,
35973 * <PRE>
35974 * dstReg <<= (quad) srcReg
35975 * </PRE>
35976 *
35977 * @param dstReg destination register
35978 * @param srcBase the source base register
35979 * @param srcIndex the source index register
35980 * @param srcScale the source scale
35981 * @param srcDisp the source displacement
35982 */
35983 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
35984 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
35985 public final void emitCMPLTSS_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
35986 int miStart = mi;
35987 setMachineCodes(mi++, (byte) 0xF3);
35988 generateREXprefix(false, dstReg, srcIndex, srcBase);
35989 setMachineCodes(mi++, (byte) 0x0F);
35990 setMachineCodes(mi++, (byte) 0xC2);
35991 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
35992 setMachineCodes(mi++, (byte) 1);
35993 if (lister != null) lister.RRXD(miStart, "CMPLTSS", dstReg, srcBase, srcIndex, srcScale, srcDisp);
35994 }
35995
35996 /**
35997 * Generate a register--register-indirect CMPLTSS. That is,
35998 * <PRE>
35999 * dstReg <<= (quad) [srcBase]
36000 * </PRE>
36001 *
36002 * @param dstReg destination register
36003 * @param srcBase the source base register
36004 */
36005 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
36006 public final void emitCMPLTSS_Reg_RegInd(XMM dstReg, GPR srcBase) {
36007 int miStart = mi;
36008 setMachineCodes(mi++, (byte) 0xF3);
36009 generateREXprefix(false, dstReg, null, srcBase);
36010 setMachineCodes(mi++, (byte) 0x0F);
36011 setMachineCodes(mi++, (byte) 0xC2);
36012 emitRegIndirectRegOperands(srcBase, dstReg);
36013 setMachineCodes(mi++, (byte) 1);
36014 if (lister != null) lister.RRN(miStart, "CMPLTSS", dstReg, srcBase);
36015 }
36016
36017
36018 /**
36019 * Generate a register--register CMPLESS. That is,
36020 * <PRE>
36021 * dstReg <<= (quad) srcReg
36022 * </PRE>
36023 *
36024 * @param dstReg destination register
36025 * @param srcReg source register
36026 */
36027 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
36028 public final void emitCMPLESS_Reg_Reg(XMM dstReg, XMM srcReg) {
36029 int miStart = mi;
36030 setMachineCodes(mi++, (byte) 0xF3);
36031 generateREXprefix(false, dstReg, null, srcReg);
36032 setMachineCodes(mi++, (byte) 0x0F);
36033 setMachineCodes(mi++, (byte) 0xC2);
36034 emitRegRegOperands(srcReg, dstReg);
36035 setMachineCodes(mi++, (byte) 2);
36036 if (lister != null) lister.RR(miStart, "CMPLESS", dstReg, srcReg);
36037 }
36038
36039 /**
36040 * Generate a register--register-displacement CMPLESS. That is,
36041 * <PRE>
36042 * dstReg <<= (quad) [srcBase + srcDisp]
36043 * </PRE>
36044 *
36045 * @param dstReg destination register
36046 * @param srcBase the source base register
36047 * @param srcDisp the source displacement
36048 */
36049 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
36050 public final void emitCMPLESS_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
36051 int miStart = mi;
36052 setMachineCodes(mi++, (byte) 0xF3);
36053 generateREXprefix(false, dstReg, null, srcBase);
36054 setMachineCodes(mi++, (byte) 0x0F);
36055 setMachineCodes(mi++, (byte) 0xC2);
36056 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
36057 setMachineCodes(mi++, (byte) 2);
36058 if (lister != null) lister.RRD(miStart, "CMPLESS", dstReg, srcBase, srcDisp);
36059 }
36060
36061 /**
36062 * Generate a register--register-offset CMPLESS. That is,
36063 * <PRE>
36064 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
36065 * </PRE>
36066 *
36067 * @param dstReg destination register
36068 * @param srcIndex the source index register
36069 * @param srcScale the source scale
36070 * @param srcDisp the source displacement
36071 */
36072 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
36073 public final void emitCMPLESS_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
36074 int miStart = mi;
36075 setMachineCodes(mi++, (byte) 0xF3);
36076 generateREXprefix(false, dstReg, srcIndex, null);
36077 setMachineCodes(mi++, (byte) 0x0F);
36078 setMachineCodes(mi++, (byte) 0xC2);
36079 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
36080 setMachineCodes(mi++, (byte) 2);
36081 if (lister != null) lister.RRFD(miStart, "CMPLESS", dstReg, srcIndex, srcScale, srcDisp);
36082 }
36083
36084 /**
36085 * Generate a register--absolute CMPLESS. That is,
36086 * <PRE>
36087 * dstReg <<= (quad) [srcDisp]
36088 * </PRE>
36089 *
36090 * @param dstReg destination register
36091 * @param srcDisp the source displacement
36092 */
36093 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
36094 public final void emitCMPLESS_Reg_Abs(XMM dstReg, Address srcDisp) {
36095 int miStart = mi;
36096 setMachineCodes(mi++, (byte) 0xF3);
36097 generateREXprefix(false, dstReg, null, null);
36098 setMachineCodes(mi++, (byte) 0x0F);
36099 setMachineCodes(mi++, (byte) 0xC2);
36100 emitAbsRegOperands(srcDisp, dstReg);
36101 setMachineCodes(mi++, (byte) 2);
36102 if (lister != null) lister.RRA(miStart, "CMPLESS", dstReg, srcDisp);
36103 }
36104
36105 /**
36106 * Generate a register--register-index CMPLESS. That is,
36107 * <PRE>
36108 * dstReg <<= (quad) srcReg
36109 * </PRE>
36110 *
36111 * @param dstReg destination register
36112 * @param srcBase the source base register
36113 * @param srcIndex the source index register
36114 * @param srcScale the source scale
36115 * @param srcDisp the source displacement
36116 */
36117 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
36118 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
36119 public final void emitCMPLESS_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
36120 int miStart = mi;
36121 setMachineCodes(mi++, (byte) 0xF3);
36122 generateREXprefix(false, dstReg, srcIndex, srcBase);
36123 setMachineCodes(mi++, (byte) 0x0F);
36124 setMachineCodes(mi++, (byte) 0xC2);
36125 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
36126 setMachineCodes(mi++, (byte) 2);
36127 if (lister != null) lister.RRXD(miStart, "CMPLESS", dstReg, srcBase, srcIndex, srcScale, srcDisp);
36128 }
36129
36130 /**
36131 * Generate a register--register-indirect CMPLESS. That is,
36132 * <PRE>
36133 * dstReg <<= (quad) [srcBase]
36134 * </PRE>
36135 *
36136 * @param dstReg destination register
36137 * @param srcBase the source base register
36138 */
36139 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
36140 public final void emitCMPLESS_Reg_RegInd(XMM dstReg, GPR srcBase) {
36141 int miStart = mi;
36142 setMachineCodes(mi++, (byte) 0xF3);
36143 generateREXprefix(false, dstReg, null, srcBase);
36144 setMachineCodes(mi++, (byte) 0x0F);
36145 setMachineCodes(mi++, (byte) 0xC2);
36146 emitRegIndirectRegOperands(srcBase, dstReg);
36147 setMachineCodes(mi++, (byte) 2);
36148 if (lister != null) lister.RRN(miStart, "CMPLESS", dstReg, srcBase);
36149 }
36150
36151
36152 /**
36153 * Generate a register--register CMPUNORDSS. That is,
36154 * <PRE>
36155 * dstReg <<= (quad) srcReg
36156 * </PRE>
36157 *
36158 * @param dstReg destination register
36159 * @param srcReg source register
36160 */
36161 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
36162 public final void emitCMPUNORDSS_Reg_Reg(XMM dstReg, XMM srcReg) {
36163 int miStart = mi;
36164 setMachineCodes(mi++, (byte) 0xF3);
36165 generateREXprefix(false, dstReg, null, srcReg);
36166 setMachineCodes(mi++, (byte) 0x0F);
36167 setMachineCodes(mi++, (byte) 0xC2);
36168 emitRegRegOperands(srcReg, dstReg);
36169 setMachineCodes(mi++, (byte) 3);
36170 if (lister != null) lister.RR(miStart, "CMPUNORDSS", dstReg, srcReg);
36171 }
36172
36173 /**
36174 * Generate a register--register-displacement CMPUNORDSS. That is,
36175 * <PRE>
36176 * dstReg <<= (quad) [srcBase + srcDisp]
36177 * </PRE>
36178 *
36179 * @param dstReg destination register
36180 * @param srcBase the source base register
36181 * @param srcDisp the source displacement
36182 */
36183 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
36184 public final void emitCMPUNORDSS_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
36185 int miStart = mi;
36186 setMachineCodes(mi++, (byte) 0xF3);
36187 generateREXprefix(false, dstReg, null, srcBase);
36188 setMachineCodes(mi++, (byte) 0x0F);
36189 setMachineCodes(mi++, (byte) 0xC2);
36190 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
36191 setMachineCodes(mi++, (byte) 3);
36192 if (lister != null) lister.RRD(miStart, "CMPUNORDSS", dstReg, srcBase, srcDisp);
36193 }
36194
36195 /**
36196 * Generate a register--register-offset CMPUNORDSS. That is,
36197 * <PRE>
36198 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
36199 * </PRE>
36200 *
36201 * @param dstReg destination register
36202 * @param srcIndex the source index register
36203 * @param srcScale the source scale
36204 * @param srcDisp the source displacement
36205 */
36206 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
36207 public final void emitCMPUNORDSS_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
36208 int miStart = mi;
36209 setMachineCodes(mi++, (byte) 0xF3);
36210 generateREXprefix(false, dstReg, srcIndex, null);
36211 setMachineCodes(mi++, (byte) 0x0F);
36212 setMachineCodes(mi++, (byte) 0xC2);
36213 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
36214 setMachineCodes(mi++, (byte) 3);
36215 if (lister != null) lister.RRFD(miStart, "CMPUNORDSS", dstReg, srcIndex, srcScale, srcDisp);
36216 }
36217
36218 /**
36219 * Generate a register--absolute CMPUNORDSS. That is,
36220 * <PRE>
36221 * dstReg <<= (quad) [srcDisp]
36222 * </PRE>
36223 *
36224 * @param dstReg destination register
36225 * @param srcDisp the source displacement
36226 */
36227 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
36228 public final void emitCMPUNORDSS_Reg_Abs(XMM dstReg, Address srcDisp) {
36229 int miStart = mi;
36230 setMachineCodes(mi++, (byte) 0xF3);
36231 generateREXprefix(false, dstReg, null, null);
36232 setMachineCodes(mi++, (byte) 0x0F);
36233 setMachineCodes(mi++, (byte) 0xC2);
36234 emitAbsRegOperands(srcDisp, dstReg);
36235 setMachineCodes(mi++, (byte) 3);
36236 if (lister != null) lister.RRA(miStart, "CMPUNORDSS", dstReg, srcDisp);
36237 }
36238
36239 /**
36240 * Generate a register--register-index CMPUNORDSS. That is,
36241 * <PRE>
36242 * dstReg <<= (quad) srcReg
36243 * </PRE>
36244 *
36245 * @param dstReg destination register
36246 * @param srcBase the source base register
36247 * @param srcIndex the source index register
36248 * @param srcScale the source scale
36249 * @param srcDisp the source displacement
36250 */
36251 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
36252 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
36253 public final void emitCMPUNORDSS_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
36254 int miStart = mi;
36255 setMachineCodes(mi++, (byte) 0xF3);
36256 generateREXprefix(false, dstReg, srcIndex, srcBase);
36257 setMachineCodes(mi++, (byte) 0x0F);
36258 setMachineCodes(mi++, (byte) 0xC2);
36259 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
36260 setMachineCodes(mi++, (byte) 3);
36261 if (lister != null) lister.RRXD(miStart, "CMPUNORDSS", dstReg, srcBase, srcIndex, srcScale, srcDisp);
36262 }
36263
36264 /**
36265 * Generate a register--register-indirect CMPUNORDSS. That is,
36266 * <PRE>
36267 * dstReg <<= (quad) [srcBase]
36268 * </PRE>
36269 *
36270 * @param dstReg destination register
36271 * @param srcBase the source base register
36272 */
36273 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
36274 public final void emitCMPUNORDSS_Reg_RegInd(XMM dstReg, GPR srcBase) {
36275 int miStart = mi;
36276 setMachineCodes(mi++, (byte) 0xF3);
36277 generateREXprefix(false, dstReg, null, srcBase);
36278 setMachineCodes(mi++, (byte) 0x0F);
36279 setMachineCodes(mi++, (byte) 0xC2);
36280 emitRegIndirectRegOperands(srcBase, dstReg);
36281 setMachineCodes(mi++, (byte) 3);
36282 if (lister != null) lister.RRN(miStart, "CMPUNORDSS", dstReg, srcBase);
36283 }
36284
36285
36286 /**
36287 * Generate a register--register CMPNESS. That is,
36288 * <PRE>
36289 * dstReg <<= (quad) srcReg
36290 * </PRE>
36291 *
36292 * @param dstReg destination register
36293 * @param srcReg source register
36294 */
36295 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
36296 public final void emitCMPNESS_Reg_Reg(XMM dstReg, XMM srcReg) {
36297 int miStart = mi;
36298 setMachineCodes(mi++, (byte) 0xF3);
36299 generateREXprefix(false, dstReg, null, srcReg);
36300 setMachineCodes(mi++, (byte) 0x0F);
36301 setMachineCodes(mi++, (byte) 0xC2);
36302 emitRegRegOperands(srcReg, dstReg);
36303 setMachineCodes(mi++, (byte) 4);
36304 if (lister != null) lister.RR(miStart, "CMPNESS", dstReg, srcReg);
36305 }
36306
36307 /**
36308 * Generate a register--register-displacement CMPNESS. That is,
36309 * <PRE>
36310 * dstReg <<= (quad) [srcBase + srcDisp]
36311 * </PRE>
36312 *
36313 * @param dstReg destination register
36314 * @param srcBase the source base register
36315 * @param srcDisp the source displacement
36316 */
36317 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
36318 public final void emitCMPNESS_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
36319 int miStart = mi;
36320 setMachineCodes(mi++, (byte) 0xF3);
36321 generateREXprefix(false, dstReg, null, srcBase);
36322 setMachineCodes(mi++, (byte) 0x0F);
36323 setMachineCodes(mi++, (byte) 0xC2);
36324 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
36325 setMachineCodes(mi++, (byte) 4);
36326 if (lister != null) lister.RRD(miStart, "CMPNESS", dstReg, srcBase, srcDisp);
36327 }
36328
36329 /**
36330 * Generate a register--register-offset CMPNESS. That is,
36331 * <PRE>
36332 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
36333 * </PRE>
36334 *
36335 * @param dstReg destination register
36336 * @param srcIndex the source index register
36337 * @param srcScale the source scale
36338 * @param srcDisp the source displacement
36339 */
36340 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
36341 public final void emitCMPNESS_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
36342 int miStart = mi;
36343 setMachineCodes(mi++, (byte) 0xF3);
36344 generateREXprefix(false, dstReg, srcIndex, null);
36345 setMachineCodes(mi++, (byte) 0x0F);
36346 setMachineCodes(mi++, (byte) 0xC2);
36347 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
36348 setMachineCodes(mi++, (byte) 4);
36349 if (lister != null) lister.RRFD(miStart, "CMPNESS", dstReg, srcIndex, srcScale, srcDisp);
36350 }
36351
36352 /**
36353 * Generate a register--absolute CMPNESS. That is,
36354 * <PRE>
36355 * dstReg <<= (quad) [srcDisp]
36356 * </PRE>
36357 *
36358 * @param dstReg destination register
36359 * @param srcDisp the source displacement
36360 */
36361 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
36362 public final void emitCMPNESS_Reg_Abs(XMM dstReg, Address srcDisp) {
36363 int miStart = mi;
36364 setMachineCodes(mi++, (byte) 0xF3);
36365 generateREXprefix(false, dstReg, null, null);
36366 setMachineCodes(mi++, (byte) 0x0F);
36367 setMachineCodes(mi++, (byte) 0xC2);
36368 emitAbsRegOperands(srcDisp, dstReg);
36369 setMachineCodes(mi++, (byte) 4);
36370 if (lister != null) lister.RRA(miStart, "CMPNESS", dstReg, srcDisp);
36371 }
36372
36373 /**
36374 * Generate a register--register-index CMPNESS. That is,
36375 * <PRE>
36376 * dstReg <<= (quad) srcReg
36377 * </PRE>
36378 *
36379 * @param dstReg destination register
36380 * @param srcBase the source base register
36381 * @param srcIndex the source index register
36382 * @param srcScale the source scale
36383 * @param srcDisp the source displacement
36384 */
36385 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
36386 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
36387 public final void emitCMPNESS_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
36388 int miStart = mi;
36389 setMachineCodes(mi++, (byte) 0xF3);
36390 generateREXprefix(false, dstReg, srcIndex, srcBase);
36391 setMachineCodes(mi++, (byte) 0x0F);
36392 setMachineCodes(mi++, (byte) 0xC2);
36393 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
36394 setMachineCodes(mi++, (byte) 4);
36395 if (lister != null) lister.RRXD(miStart, "CMPNESS", dstReg, srcBase, srcIndex, srcScale, srcDisp);
36396 }
36397
36398 /**
36399 * Generate a register--register-indirect CMPNESS. That is,
36400 * <PRE>
36401 * dstReg <<= (quad) [srcBase]
36402 * </PRE>
36403 *
36404 * @param dstReg destination register
36405 * @param srcBase the source base register
36406 */
36407 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
36408 public final void emitCMPNESS_Reg_RegInd(XMM dstReg, GPR srcBase) {
36409 int miStart = mi;
36410 setMachineCodes(mi++, (byte) 0xF3);
36411 generateREXprefix(false, dstReg, null, srcBase);
36412 setMachineCodes(mi++, (byte) 0x0F);
36413 setMachineCodes(mi++, (byte) 0xC2);
36414 emitRegIndirectRegOperands(srcBase, dstReg);
36415 setMachineCodes(mi++, (byte) 4);
36416 if (lister != null) lister.RRN(miStart, "CMPNESS", dstReg, srcBase);
36417 }
36418
36419
36420 /**
36421 * Generate a register--register CMPNLTSS. That is,
36422 * <PRE>
36423 * dstReg <<= (quad) srcReg
36424 * </PRE>
36425 *
36426 * @param dstReg destination register
36427 * @param srcReg source register
36428 */
36429 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
36430 public final void emitCMPNLTSS_Reg_Reg(XMM dstReg, XMM srcReg) {
36431 int miStart = mi;
36432 setMachineCodes(mi++, (byte) 0xF3);
36433 generateREXprefix(false, dstReg, null, srcReg);
36434 setMachineCodes(mi++, (byte) 0x0F);
36435 setMachineCodes(mi++, (byte) 0xC2);
36436 emitRegRegOperands(srcReg, dstReg);
36437 setMachineCodes(mi++, (byte) 5);
36438 if (lister != null) lister.RR(miStart, "CMPNLTSS", dstReg, srcReg);
36439 }
36440
36441 /**
36442 * Generate a register--register-displacement CMPNLTSS. That is,
36443 * <PRE>
36444 * dstReg <<= (quad) [srcBase + srcDisp]
36445 * </PRE>
36446 *
36447 * @param dstReg destination register
36448 * @param srcBase the source base register
36449 * @param srcDisp the source displacement
36450 */
36451 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
36452 public final void emitCMPNLTSS_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
36453 int miStart = mi;
36454 setMachineCodes(mi++, (byte) 0xF3);
36455 generateREXprefix(false, dstReg, null, srcBase);
36456 setMachineCodes(mi++, (byte) 0x0F);
36457 setMachineCodes(mi++, (byte) 0xC2);
36458 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
36459 setMachineCodes(mi++, (byte) 5);
36460 if (lister != null) lister.RRD(miStart, "CMPNLTSS", dstReg, srcBase, srcDisp);
36461 }
36462
36463 /**
36464 * Generate a register--register-offset CMPNLTSS. That is,
36465 * <PRE>
36466 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
36467 * </PRE>
36468 *
36469 * @param dstReg destination register
36470 * @param srcIndex the source index register
36471 * @param srcScale the source scale
36472 * @param srcDisp the source displacement
36473 */
36474 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
36475 public final void emitCMPNLTSS_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
36476 int miStart = mi;
36477 setMachineCodes(mi++, (byte) 0xF3);
36478 generateREXprefix(false, dstReg, srcIndex, null);
36479 setMachineCodes(mi++, (byte) 0x0F);
36480 setMachineCodes(mi++, (byte) 0xC2);
36481 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
36482 setMachineCodes(mi++, (byte) 5);
36483 if (lister != null) lister.RRFD(miStart, "CMPNLTSS", dstReg, srcIndex, srcScale, srcDisp);
36484 }
36485
36486 /**
36487 * Generate a register--absolute CMPNLTSS. That is,
36488 * <PRE>
36489 * dstReg <<= (quad) [srcDisp]
36490 * </PRE>
36491 *
36492 * @param dstReg destination register
36493 * @param srcDisp the source displacement
36494 */
36495 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
36496 public final void emitCMPNLTSS_Reg_Abs(XMM dstReg, Address srcDisp) {
36497 int miStart = mi;
36498 setMachineCodes(mi++, (byte) 0xF3);
36499 generateREXprefix(false, dstReg, null, null);
36500 setMachineCodes(mi++, (byte) 0x0F);
36501 setMachineCodes(mi++, (byte) 0xC2);
36502 emitAbsRegOperands(srcDisp, dstReg);
36503 setMachineCodes(mi++, (byte) 5);
36504 if (lister != null) lister.RRA(miStart, "CMPNLTSS", dstReg, srcDisp);
36505 }
36506
36507 /**
36508 * Generate a register--register-index CMPNLTSS. That is,
36509 * <PRE>
36510 * dstReg <<= (quad) srcReg
36511 * </PRE>
36512 *
36513 * @param dstReg destination register
36514 * @param srcBase the source base register
36515 * @param srcIndex the source index register
36516 * @param srcScale the source scale
36517 * @param srcDisp the source displacement
36518 */
36519 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
36520 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
36521 public final void emitCMPNLTSS_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
36522 int miStart = mi;
36523 setMachineCodes(mi++, (byte) 0xF3);
36524 generateREXprefix(false, dstReg, srcIndex, srcBase);
36525 setMachineCodes(mi++, (byte) 0x0F);
36526 setMachineCodes(mi++, (byte) 0xC2);
36527 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
36528 setMachineCodes(mi++, (byte) 5);
36529 if (lister != null) lister.RRXD(miStart, "CMPNLTSS", dstReg, srcBase, srcIndex, srcScale, srcDisp);
36530 }
36531
36532 /**
36533 * Generate a register--register-indirect CMPNLTSS. That is,
36534 * <PRE>
36535 * dstReg <<= (quad) [srcBase]
36536 * </PRE>
36537 *
36538 * @param dstReg destination register
36539 * @param srcBase the source base register
36540 */
36541 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
36542 public final void emitCMPNLTSS_Reg_RegInd(XMM dstReg, GPR srcBase) {
36543 int miStart = mi;
36544 setMachineCodes(mi++, (byte) 0xF3);
36545 generateREXprefix(false, dstReg, null, srcBase);
36546 setMachineCodes(mi++, (byte) 0x0F);
36547 setMachineCodes(mi++, (byte) 0xC2);
36548 emitRegIndirectRegOperands(srcBase, dstReg);
36549 setMachineCodes(mi++, (byte) 5);
36550 if (lister != null) lister.RRN(miStart, "CMPNLTSS", dstReg, srcBase);
36551 }
36552
36553
36554 /**
36555 * Generate a register--register CMPNLESS. That is,
36556 * <PRE>
36557 * dstReg <<= (quad) srcReg
36558 * </PRE>
36559 *
36560 * @param dstReg destination register
36561 * @param srcReg source register
36562 */
36563 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
36564 public final void emitCMPNLESS_Reg_Reg(XMM dstReg, XMM srcReg) {
36565 int miStart = mi;
36566 setMachineCodes(mi++, (byte) 0xF3);
36567 generateREXprefix(false, dstReg, null, srcReg);
36568 setMachineCodes(mi++, (byte) 0x0F);
36569 setMachineCodes(mi++, (byte) 0xC2);
36570 emitRegRegOperands(srcReg, dstReg);
36571 setMachineCodes(mi++, (byte) 6);
36572 if (lister != null) lister.RR(miStart, "CMPNLESS", dstReg, srcReg);
36573 }
36574
36575 /**
36576 * Generate a register--register-displacement CMPNLESS. That is,
36577 * <PRE>
36578 * dstReg <<= (quad) [srcBase + srcDisp]
36579 * </PRE>
36580 *
36581 * @param dstReg destination register
36582 * @param srcBase the source base register
36583 * @param srcDisp the source displacement
36584 */
36585 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
36586 public final void emitCMPNLESS_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
36587 int miStart = mi;
36588 setMachineCodes(mi++, (byte) 0xF3);
36589 generateREXprefix(false, dstReg, null, srcBase);
36590 setMachineCodes(mi++, (byte) 0x0F);
36591 setMachineCodes(mi++, (byte) 0xC2);
36592 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
36593 setMachineCodes(mi++, (byte) 6);
36594 if (lister != null) lister.RRD(miStart, "CMPNLESS", dstReg, srcBase, srcDisp);
36595 }
36596
36597 /**
36598 * Generate a register--register-offset CMPNLESS. That is,
36599 * <PRE>
36600 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
36601 * </PRE>
36602 *
36603 * @param dstReg destination register
36604 * @param srcIndex the source index register
36605 * @param srcScale the source scale
36606 * @param srcDisp the source displacement
36607 */
36608 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
36609 public final void emitCMPNLESS_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
36610 int miStart = mi;
36611 setMachineCodes(mi++, (byte) 0xF3);
36612 generateREXprefix(false, dstReg, srcIndex, null);
36613 setMachineCodes(mi++, (byte) 0x0F);
36614 setMachineCodes(mi++, (byte) 0xC2);
36615 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
36616 setMachineCodes(mi++, (byte) 6);
36617 if (lister != null) lister.RRFD(miStart, "CMPNLESS", dstReg, srcIndex, srcScale, srcDisp);
36618 }
36619
36620 /**
36621 * Generate a register--absolute CMPNLESS. That is,
36622 * <PRE>
36623 * dstReg <<= (quad) [srcDisp]
36624 * </PRE>
36625 *
36626 * @param dstReg destination register
36627 * @param srcDisp the source displacement
36628 */
36629 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
36630 public final void emitCMPNLESS_Reg_Abs(XMM dstReg, Address srcDisp) {
36631 int miStart = mi;
36632 setMachineCodes(mi++, (byte) 0xF3);
36633 generateREXprefix(false, dstReg, null, null);
36634 setMachineCodes(mi++, (byte) 0x0F);
36635 setMachineCodes(mi++, (byte) 0xC2);
36636 emitAbsRegOperands(srcDisp, dstReg);
36637 setMachineCodes(mi++, (byte) 6);
36638 if (lister != null) lister.RRA(miStart, "CMPNLESS", dstReg, srcDisp);
36639 }
36640
36641 /**
36642 * Generate a register--register-index CMPNLESS. That is,
36643 * <PRE>
36644 * dstReg <<= (quad) srcReg
36645 * </PRE>
36646 *
36647 * @param dstReg destination register
36648 * @param srcBase the source base register
36649 * @param srcIndex the source index register
36650 * @param srcScale the source scale
36651 * @param srcDisp the source displacement
36652 */
36653 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
36654 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
36655 public final void emitCMPNLESS_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
36656 int miStart = mi;
36657 setMachineCodes(mi++, (byte) 0xF3);
36658 generateREXprefix(false, dstReg, srcIndex, srcBase);
36659 setMachineCodes(mi++, (byte) 0x0F);
36660 setMachineCodes(mi++, (byte) 0xC2);
36661 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
36662 setMachineCodes(mi++, (byte) 6);
36663 if (lister != null) lister.RRXD(miStart, "CMPNLESS", dstReg, srcBase, srcIndex, srcScale, srcDisp);
36664 }
36665
36666 /**
36667 * Generate a register--register-indirect CMPNLESS. That is,
36668 * <PRE>
36669 * dstReg <<= (quad) [srcBase]
36670 * </PRE>
36671 *
36672 * @param dstReg destination register
36673 * @param srcBase the source base register
36674 */
36675 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
36676 public final void emitCMPNLESS_Reg_RegInd(XMM dstReg, GPR srcBase) {
36677 int miStart = mi;
36678 setMachineCodes(mi++, (byte) 0xF3);
36679 generateREXprefix(false, dstReg, null, srcBase);
36680 setMachineCodes(mi++, (byte) 0x0F);
36681 setMachineCodes(mi++, (byte) 0xC2);
36682 emitRegIndirectRegOperands(srcBase, dstReg);
36683 setMachineCodes(mi++, (byte) 6);
36684 if (lister != null) lister.RRN(miStart, "CMPNLESS", dstReg, srcBase);
36685 }
36686
36687
36688 /**
36689 * Generate a register--register CMPORDSS. That is,
36690 * <PRE>
36691 * dstReg <<= (quad) srcReg
36692 * </PRE>
36693 *
36694 * @param dstReg destination register
36695 * @param srcReg source register
36696 */
36697 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
36698 public final void emitCMPORDSS_Reg_Reg(XMM dstReg, XMM srcReg) {
36699 int miStart = mi;
36700 setMachineCodes(mi++, (byte) 0xF3);
36701 generateREXprefix(false, dstReg, null, srcReg);
36702 setMachineCodes(mi++, (byte) 0x0F);
36703 setMachineCodes(mi++, (byte) 0xC2);
36704 emitRegRegOperands(srcReg, dstReg);
36705 setMachineCodes(mi++, (byte) 7);
36706 if (lister != null) lister.RR(miStart, "CMPORDSS", dstReg, srcReg);
36707 }
36708
36709 /**
36710 * Generate a register--register-displacement CMPORDSS. That is,
36711 * <PRE>
36712 * dstReg <<= (quad) [srcBase + srcDisp]
36713 * </PRE>
36714 *
36715 * @param dstReg destination register
36716 * @param srcBase the source base register
36717 * @param srcDisp the source displacement
36718 */
36719 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
36720 public final void emitCMPORDSS_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
36721 int miStart = mi;
36722 setMachineCodes(mi++, (byte) 0xF3);
36723 generateREXprefix(false, dstReg, null, srcBase);
36724 setMachineCodes(mi++, (byte) 0x0F);
36725 setMachineCodes(mi++, (byte) 0xC2);
36726 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
36727 setMachineCodes(mi++, (byte) 7);
36728 if (lister != null) lister.RRD(miStart, "CMPORDSS", dstReg, srcBase, srcDisp);
36729 }
36730
36731 /**
36732 * Generate a register--register-offset CMPORDSS. That is,
36733 * <PRE>
36734 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
36735 * </PRE>
36736 *
36737 * @param dstReg destination register
36738 * @param srcIndex the source index register
36739 * @param srcScale the source scale
36740 * @param srcDisp the source displacement
36741 */
36742 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
36743 public final void emitCMPORDSS_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
36744 int miStart = mi;
36745 setMachineCodes(mi++, (byte) 0xF3);
36746 generateREXprefix(false, dstReg, srcIndex, null);
36747 setMachineCodes(mi++, (byte) 0x0F);
36748 setMachineCodes(mi++, (byte) 0xC2);
36749 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
36750 setMachineCodes(mi++, (byte) 7);
36751 if (lister != null) lister.RRFD(miStart, "CMPORDSS", dstReg, srcIndex, srcScale, srcDisp);
36752 }
36753
36754 /**
36755 * Generate a register--absolute CMPORDSS. That is,
36756 * <PRE>
36757 * dstReg <<= (quad) [srcDisp]
36758 * </PRE>
36759 *
36760 * @param dstReg destination register
36761 * @param srcDisp the source displacement
36762 */
36763 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
36764 public final void emitCMPORDSS_Reg_Abs(XMM dstReg, Address srcDisp) {
36765 int miStart = mi;
36766 setMachineCodes(mi++, (byte) 0xF3);
36767 generateREXprefix(false, dstReg, null, null);
36768 setMachineCodes(mi++, (byte) 0x0F);
36769 setMachineCodes(mi++, (byte) 0xC2);
36770 emitAbsRegOperands(srcDisp, dstReg);
36771 setMachineCodes(mi++, (byte) 7);
36772 if (lister != null) lister.RRA(miStart, "CMPORDSS", dstReg, srcDisp);
36773 }
36774
36775 /**
36776 * Generate a register--register-index CMPORDSS. That is,
36777 * <PRE>
36778 * dstReg <<= (quad) srcReg
36779 * </PRE>
36780 *
36781 * @param dstReg destination register
36782 * @param srcBase the source base register
36783 * @param srcIndex the source index register
36784 * @param srcScale the source scale
36785 * @param srcDisp the source displacement
36786 */
36787 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
36788 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
36789 public final void emitCMPORDSS_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
36790 int miStart = mi;
36791 setMachineCodes(mi++, (byte) 0xF3);
36792 generateREXprefix(false, dstReg, srcIndex, srcBase);
36793 setMachineCodes(mi++, (byte) 0x0F);
36794 setMachineCodes(mi++, (byte) 0xC2);
36795 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
36796 setMachineCodes(mi++, (byte) 7);
36797 if (lister != null) lister.RRXD(miStart, "CMPORDSS", dstReg, srcBase, srcIndex, srcScale, srcDisp);
36798 }
36799
36800 /**
36801 * Generate a register--register-indirect CMPORDSS. That is,
36802 * <PRE>
36803 * dstReg <<= (quad) [srcBase]
36804 * </PRE>
36805 *
36806 * @param dstReg destination register
36807 * @param srcBase the source base register
36808 */
36809 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
36810 public final void emitCMPORDSS_Reg_RegInd(XMM dstReg, GPR srcBase) {
36811 int miStart = mi;
36812 setMachineCodes(mi++, (byte) 0xF3);
36813 generateREXprefix(false, dstReg, null, srcBase);
36814 setMachineCodes(mi++, (byte) 0x0F);
36815 setMachineCodes(mi++, (byte) 0xC2);
36816 emitRegIndirectRegOperands(srcBase, dstReg);
36817 setMachineCodes(mi++, (byte) 7);
36818 if (lister != null) lister.RRN(miStart, "CMPORDSS", dstReg, srcBase);
36819 }
36820
36821
36822 /**
36823 * Generate a register--register MOVD. That is,
36824 * <PRE>
36825 * dstReg <<= (quad) srcReg
36826 * </PRE>
36827 *
36828 * @param dstReg destination register
36829 * @param srcReg source register
36830 */
36831 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
36832 public final void emitMOVD_Reg_Reg(GPR dstReg, MM srcReg) {
36833 int miStart = mi;
36834 generateREXprefix(false, srcReg, null, dstReg);
36835 setMachineCodes(mi++, (byte) 0x0F);
36836 setMachineCodes(mi++, (byte) 0x7E);
36837 emitRegRegOperands(dstReg, srcReg);
36838 if (lister != null) lister.RR(miStart, "MOVD", dstReg, srcReg);
36839 }
36840
36841 /**
36842 * Generate a register-indirect--register MOVD. That is,
36843 * <PRE>
36844 * [dstBase] <<= (quad) srcReg
36845 * </PRE>
36846 *
36847 * @param dstBase the destination base register
36848 * @param srcReg the source register
36849 */
36850 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
36851 public final void emitMOVD_RegInd_Reg(GPR dstBase, MM srcReg) {
36852 int miStart = mi;
36853 generateREXprefix(false, srcReg, null, dstBase);
36854 setMachineCodes(mi++, (byte) 0x0F);
36855 setMachineCodes(mi++, (byte) 0x7E);
36856 emitRegIndirectRegOperands(dstBase, srcReg);
36857 if (lister != null) lister.RNR(miStart, "MOVD", dstBase, srcReg);
36858 }
36859
36860 /**
36861 * Generate a register-offset--register MOVD. That is,
36862 * <PRE>
36863 * [dstReg<<dstScale + dstDisp] <<= (quad) srcReg
36864 * </PRE>
36865 *
36866 * @param dstIndex the destination index register
36867 * @param dstScale the destination shift amount
36868 * @param dstDisp the destination displacement
36869 * @param srcReg the source register
36870 */
36871 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
36872 public final void emitMOVD_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, MM srcReg) {
36873 int miStart = mi;
36874 generateREXprefix(false, srcReg, dstIndex, null);
36875 setMachineCodes(mi++, (byte) 0x0F);
36876 setMachineCodes(mi++, (byte) 0x7E);
36877 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
36878 if (lister != null) lister.RFDR(miStart, "MOVD", dstIndex, dstScale, dstDisp, srcReg);
36879 }
36880
36881 /**
36882 * Generate a absolute--register MOVD. That is,
36883 * <PRE>
36884 * [dstDisp] <<= (quad) srcReg
36885 * </PRE>
36886 *
36887 * @param dstDisp the destination displacement
36888 * @param srcReg the source register
36889 */
36890 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
36891 public final void emitMOVD_Abs_Reg(Address dstDisp, MM srcReg) {
36892 int miStart = mi;
36893 generateREXprefix(false, srcReg, null, null);
36894 setMachineCodes(mi++, (byte) 0x0F);
36895 setMachineCodes(mi++, (byte) 0x7E);
36896 emitAbsRegOperands(dstDisp, srcReg);
36897 if (lister != null) lister.RAR(miStart, "MOVD", dstDisp, srcReg);
36898 }
36899
36900 /**
36901 * Generate a register-index--register MOVD. That is,
36902 * <PRE>
36903 * [dstBase + dstIndex<<dstScale + dstDisp] <<= (quad) srcReg
36904 * </PRE>
36905 *
36906 * @param dstBase the destination base register
36907 * @param dstIndex the destination index register
36908 * @param dstScale the destination shift amount
36909 * @param dstDisp the destination displacement
36910 * @param srcReg the source register
36911 */
36912 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
36913 public final void emitMOVD_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, MM srcReg) {
36914 int miStart = mi;
36915 generateREXprefix(false, srcReg, dstIndex, dstBase);
36916 setMachineCodes(mi++, (byte) 0x0F);
36917 setMachineCodes(mi++, (byte) 0x7E);
36918 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
36919 if (lister != null) lister.RXDR(miStart, "MOVD", dstBase, dstIndex, dstScale, dstDisp, srcReg);
36920 }
36921
36922 /**
36923 * Generate a register-displacement--register MOVD. That is,
36924 * <PRE>
36925 * [dstBase + dstDisp] <<= (quad) srcReg
36926 * </PRE>
36927 *
36928 * @param dstBase the destination base register
36929 * @param dstDisp the destination displacement
36930 * @param srcReg the source register
36931 */
36932 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
36933 public final void emitMOVD_RegDisp_Reg(GPR dstBase, Offset dstDisp, MM srcReg) {
36934 int miStart = mi;
36935 generateREXprefix(false, srcReg, null, dstBase);
36936 setMachineCodes(mi++, (byte) 0x0F);
36937 setMachineCodes(mi++, (byte) 0x7E);
36938 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
36939 if (lister != null) lister.RDR(miStart, "MOVD", dstBase, dstDisp, srcReg);
36940 }
36941
36942
36943 /**
36944 * Generate a register--register MOVD. That is,
36945 * <PRE>
36946 * dstReg <<= (quad) srcReg
36947 * </PRE>
36948 *
36949 * @param dstReg destination register
36950 * @param srcReg source register
36951 */
36952 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
36953 public final void emitMOVD_Reg_Reg(MM dstReg, GPR srcReg) {
36954 int miStart = mi;
36955 generateREXprefix(false, dstReg, null, srcReg);
36956 setMachineCodes(mi++, (byte) 0x0F);
36957 setMachineCodes(mi++, (byte) 0x6E);
36958 emitRegRegOperands(srcReg, dstReg);
36959 if (lister != null) lister.RR(miStart, "MOVD", dstReg, srcReg);
36960 }
36961
36962 /**
36963 * Generate a register--register-displacement MOVD. That is,
36964 * <PRE>
36965 * dstReg <<= (quad) [srcBase + srcDisp]
36966 * </PRE>
36967 *
36968 * @param dstReg destination register
36969 * @param srcBase the source base register
36970 * @param srcDisp the source displacement
36971 */
36972 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
36973 public final void emitMOVD_Reg_RegDisp(MM dstReg, GPR srcBase, Offset srcDisp) {
36974 int miStart = mi;
36975 generateREXprefix(false, dstReg, null, srcBase);
36976 setMachineCodes(mi++, (byte) 0x0F);
36977 setMachineCodes(mi++, (byte) 0x6E);
36978 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
36979 if (lister != null) lister.RRD(miStart, "MOVD", dstReg, srcBase, srcDisp);
36980 }
36981
36982 /**
36983 * Generate a register--register-offset MOVD. That is,
36984 * <PRE>
36985 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
36986 * </PRE>
36987 *
36988 * @param dstReg destination register
36989 * @param srcIndex the source index register
36990 * @param srcScale the source scale
36991 * @param srcDisp the source displacement
36992 */
36993 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
36994 public final void emitMOVD_Reg_RegOff(MM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
36995 int miStart = mi;
36996 generateREXprefix(false, dstReg, srcIndex, null);
36997 setMachineCodes(mi++, (byte) 0x0F);
36998 setMachineCodes(mi++, (byte) 0x6E);
36999 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
37000 if (lister != null) lister.RRFD(miStart, "MOVD", dstReg, srcIndex, srcScale, srcDisp);
37001 }
37002
37003 /**
37004 * Generate a register--absolute MOVD. That is,
37005 * <PRE>
37006 * dstReg <<= (quad) [srcDisp]
37007 * </PRE>
37008 *
37009 * @param dstReg destination register
37010 * @param srcDisp the source displacement
37011 */
37012 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
37013 public final void emitMOVD_Reg_Abs(MM dstReg, Address srcDisp) {
37014 int miStart = mi;
37015 generateREXprefix(false, dstReg, null, null);
37016 setMachineCodes(mi++, (byte) 0x0F);
37017 setMachineCodes(mi++, (byte) 0x6E);
37018 emitAbsRegOperands(srcDisp, dstReg);
37019 if (lister != null) lister.RRA(miStart, "MOVD", dstReg, srcDisp);
37020 }
37021
37022 /**
37023 * Generate a register--register-index MOVD. That is,
37024 * <PRE>
37025 * dstReg <<= (quad) srcReg
37026 * </PRE>
37027 *
37028 * @param dstReg destination register
37029 * @param srcBase the source base register
37030 * @param srcIndex the source index register
37031 * @param srcScale the source scale
37032 * @param srcDisp the source displacement
37033 */
37034 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
37035 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
37036 public final void emitMOVD_Reg_RegIdx(MM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
37037 int miStart = mi;
37038 generateREXprefix(false, dstReg, srcIndex, srcBase);
37039 setMachineCodes(mi++, (byte) 0x0F);
37040 setMachineCodes(mi++, (byte) 0x6E);
37041 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
37042 if (lister != null) lister.RRXD(miStart, "MOVD", dstReg, srcBase, srcIndex, srcScale, srcDisp);
37043 }
37044
37045 /**
37046 * Generate a register--register-indirect MOVD. That is,
37047 * <PRE>
37048 * dstReg <<= (quad) [srcBase]
37049 * </PRE>
37050 *
37051 * @param dstReg destination register
37052 * @param srcBase the source base register
37053 */
37054 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
37055 public final void emitMOVD_Reg_RegInd(MM dstReg, GPR srcBase) {
37056 int miStart = mi;
37057 generateREXprefix(false, dstReg, null, srcBase);
37058 setMachineCodes(mi++, (byte) 0x0F);
37059 setMachineCodes(mi++, (byte) 0x6E);
37060 emitRegIndirectRegOperands(srcBase, dstReg);
37061 if (lister != null) lister.RRN(miStart, "MOVD", dstReg, srcBase);
37062 }
37063
37064
37065 /**
37066 * Generate a register--register MOVD. That is,
37067 * <PRE>
37068 * dstReg <<= (quad) srcReg
37069 * </PRE>
37070 *
37071 * @param dstReg destination register
37072 * @param srcReg source register
37073 */
37074 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
37075 public final void emitMOVD_Reg_Reg(GPR dstReg, XMM srcReg) {
37076 int miStart = mi;
37077 setMachineCodes(mi++, (byte) 0x66);
37078 generateREXprefix(false, srcReg, null, dstReg);
37079 setMachineCodes(mi++, (byte) 0x0F);
37080 setMachineCodes(mi++, (byte) 0x7E);
37081 emitRegRegOperands(dstReg, srcReg);
37082 if (lister != null) lister.RR(miStart, "MOVD", dstReg, srcReg);
37083 }
37084
37085 /**
37086 * Generate a register-indirect--register MOVD. That is,
37087 * <PRE>
37088 * [dstBase] <<= (quad) srcReg
37089 * </PRE>
37090 *
37091 * @param dstBase the destination base register
37092 * @param srcReg the source register
37093 */
37094 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
37095 public final void emitMOVD_RegInd_Reg(GPR dstBase, XMM srcReg) {
37096 int miStart = mi;
37097 setMachineCodes(mi++, (byte) 0x66);
37098 generateREXprefix(false, srcReg, null, dstBase);
37099 setMachineCodes(mi++, (byte) 0x0F);
37100 setMachineCodes(mi++, (byte) 0x7E);
37101 emitRegIndirectRegOperands(dstBase, srcReg);
37102 if (lister != null) lister.RNR(miStart, "MOVD", dstBase, srcReg);
37103 }
37104
37105 /**
37106 * Generate a register-offset--register MOVD. That is,
37107 * <PRE>
37108 * [dstReg<<dstScale + dstDisp] <<= (quad) srcReg
37109 * </PRE>
37110 *
37111 * @param dstIndex the destination index register
37112 * @param dstScale the destination shift amount
37113 * @param dstDisp the destination displacement
37114 * @param srcReg the source register
37115 */
37116 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
37117 public final void emitMOVD_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, XMM srcReg) {
37118 int miStart = mi;
37119 setMachineCodes(mi++, (byte) 0x66);
37120 generateREXprefix(false, srcReg, dstIndex, null);
37121 setMachineCodes(mi++, (byte) 0x0F);
37122 setMachineCodes(mi++, (byte) 0x7E);
37123 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
37124 if (lister != null) lister.RFDR(miStart, "MOVD", dstIndex, dstScale, dstDisp, srcReg);
37125 }
37126
37127 /**
37128 * Generate a absolute--register MOVD. That is,
37129 * <PRE>
37130 * [dstDisp] <<= (quad) srcReg
37131 * </PRE>
37132 *
37133 * @param dstDisp the destination displacement
37134 * @param srcReg the source register
37135 */
37136 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
37137 public final void emitMOVD_Abs_Reg(Address dstDisp, XMM srcReg) {
37138 int miStart = mi;
37139 setMachineCodes(mi++, (byte) 0x66);
37140 generateREXprefix(false, srcReg, null, null);
37141 setMachineCodes(mi++, (byte) 0x0F);
37142 setMachineCodes(mi++, (byte) 0x7E);
37143 emitAbsRegOperands(dstDisp, srcReg);
37144 if (lister != null) lister.RAR(miStart, "MOVD", dstDisp, srcReg);
37145 }
37146
37147 /**
37148 * Generate a register-index--register MOVD. That is,
37149 * <PRE>
37150 * [dstBase + dstIndex<<dstScale + dstDisp] <<= (quad) srcReg
37151 * </PRE>
37152 *
37153 * @param dstBase the destination base register
37154 * @param dstIndex the destination index register
37155 * @param dstScale the destination shift amount
37156 * @param dstDisp the destination displacement
37157 * @param srcReg the source register
37158 */
37159 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
37160 public final void emitMOVD_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, XMM srcReg) {
37161 int miStart = mi;
37162 setMachineCodes(mi++, (byte) 0x66);
37163 generateREXprefix(false, srcReg, dstIndex, dstBase);
37164 setMachineCodes(mi++, (byte) 0x0F);
37165 setMachineCodes(mi++, (byte) 0x7E);
37166 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
37167 if (lister != null) lister.RXDR(miStart, "MOVD", dstBase, dstIndex, dstScale, dstDisp, srcReg);
37168 }
37169
37170 /**
37171 * Generate a register-displacement--register MOVD. That is,
37172 * <PRE>
37173 * [dstBase + dstDisp] <<= (quad) srcReg
37174 * </PRE>
37175 *
37176 * @param dstBase the destination base register
37177 * @param dstDisp the destination displacement
37178 * @param srcReg the source register
37179 */
37180 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
37181 public final void emitMOVD_RegDisp_Reg(GPR dstBase, Offset dstDisp, XMM srcReg) {
37182 int miStart = mi;
37183 setMachineCodes(mi++, (byte) 0x66);
37184 generateREXprefix(false, srcReg, null, dstBase);
37185 setMachineCodes(mi++, (byte) 0x0F);
37186 setMachineCodes(mi++, (byte) 0x7E);
37187 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
37188 if (lister != null) lister.RDR(miStart, "MOVD", dstBase, dstDisp, srcReg);
37189 }
37190
37191
37192 /**
37193 * Generate a register--register MOVD. That is,
37194 * <PRE>
37195 * dstReg <<= (quad) srcReg
37196 * </PRE>
37197 *
37198 * @param dstReg destination register
37199 * @param srcReg source register
37200 */
37201 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
37202 public final void emitMOVD_Reg_Reg(XMM dstReg, GPR srcReg) {
37203 int miStart = mi;
37204 setMachineCodes(mi++, (byte) 0x66);
37205 generateREXprefix(false, dstReg, null, srcReg);
37206 setMachineCodes(mi++, (byte) 0x0F);
37207 setMachineCodes(mi++, (byte) 0x6E);
37208 emitRegRegOperands(srcReg, dstReg);
37209 if (lister != null) lister.RR(miStart, "MOVD", dstReg, srcReg);
37210 }
37211
37212 /**
37213 * Generate a register--register-displacement MOVD. That is,
37214 * <PRE>
37215 * dstReg <<= (quad) [srcBase + srcDisp]
37216 * </PRE>
37217 *
37218 * @param dstReg destination register
37219 * @param srcBase the source base register
37220 * @param srcDisp the source displacement
37221 */
37222 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
37223 public final void emitMOVD_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
37224 int miStart = mi;
37225 setMachineCodes(mi++, (byte) 0x66);
37226 generateREXprefix(false, dstReg, null, srcBase);
37227 setMachineCodes(mi++, (byte) 0x0F);
37228 setMachineCodes(mi++, (byte) 0x6E);
37229 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
37230 if (lister != null) lister.RRD(miStart, "MOVD", dstReg, srcBase, srcDisp);
37231 }
37232
37233 /**
37234 * Generate a register--register-offset MOVD. That is,
37235 * <PRE>
37236 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
37237 * </PRE>
37238 *
37239 * @param dstReg destination register
37240 * @param srcIndex the source index register
37241 * @param srcScale the source scale
37242 * @param srcDisp the source displacement
37243 */
37244 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
37245 public final void emitMOVD_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
37246 int miStart = mi;
37247 setMachineCodes(mi++, (byte) 0x66);
37248 generateREXprefix(false, dstReg, srcIndex, null);
37249 setMachineCodes(mi++, (byte) 0x0F);
37250 setMachineCodes(mi++, (byte) 0x6E);
37251 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
37252 if (lister != null) lister.RRFD(miStart, "MOVD", dstReg, srcIndex, srcScale, srcDisp);
37253 }
37254
37255 /**
37256 * Generate a register--absolute MOVD. That is,
37257 * <PRE>
37258 * dstReg <<= (quad) [srcDisp]
37259 * </PRE>
37260 *
37261 * @param dstReg destination register
37262 * @param srcDisp the source displacement
37263 */
37264 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
37265 public final void emitMOVD_Reg_Abs(XMM dstReg, Address srcDisp) {
37266 int miStart = mi;
37267 setMachineCodes(mi++, (byte) 0x66);
37268 generateREXprefix(false, dstReg, null, null);
37269 setMachineCodes(mi++, (byte) 0x0F);
37270 setMachineCodes(mi++, (byte) 0x6E);
37271 emitAbsRegOperands(srcDisp, dstReg);
37272 if (lister != null) lister.RRA(miStart, "MOVD", dstReg, srcDisp);
37273 }
37274
37275 /**
37276 * Generate a register--register-index MOVD. That is,
37277 * <PRE>
37278 * dstReg <<= (quad) srcReg
37279 * </PRE>
37280 *
37281 * @param dstReg destination register
37282 * @param srcBase the source base register
37283 * @param srcIndex the source index register
37284 * @param srcScale the source scale
37285 * @param srcDisp the source displacement
37286 */
37287 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
37288 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
37289 public final void emitMOVD_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
37290 int miStart = mi;
37291 setMachineCodes(mi++, (byte) 0x66);
37292 generateREXprefix(false, dstReg, srcIndex, srcBase);
37293 setMachineCodes(mi++, (byte) 0x0F);
37294 setMachineCodes(mi++, (byte) 0x6E);
37295 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
37296 if (lister != null) lister.RRXD(miStart, "MOVD", dstReg, srcBase, srcIndex, srcScale, srcDisp);
37297 }
37298
37299 /**
37300 * Generate a register--register-indirect MOVD. That is,
37301 * <PRE>
37302 * dstReg <<= (quad) [srcBase]
37303 * </PRE>
37304 *
37305 * @param dstReg destination register
37306 * @param srcBase the source base register
37307 */
37308 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
37309 public final void emitMOVD_Reg_RegInd(XMM dstReg, GPR srcBase) {
37310 int miStart = mi;
37311 setMachineCodes(mi++, (byte) 0x66);
37312 generateREXprefix(false, dstReg, null, srcBase);
37313 setMachineCodes(mi++, (byte) 0x0F);
37314 setMachineCodes(mi++, (byte) 0x6E);
37315 emitRegIndirectRegOperands(srcBase, dstReg);
37316 if (lister != null) lister.RRN(miStart, "MOVD", dstReg, srcBase);
37317 }
37318
37319
37320 /**
37321 * Generate a register--register MOVQ. That is,
37322 * <PRE>
37323 * dstReg <<= (quad) srcReg
37324 * </PRE>
37325 *
37326 * @param dstReg destination register
37327 * @param srcReg source register
37328 */
37329 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
37330 public final void emitMOVQ_Reg_Reg(MM dstReg, MM srcReg) {
37331 int miStart = mi;
37332 generateREXprefix(false, dstReg, null, srcReg);
37333 setMachineCodes(mi++, (byte) 0x0F);
37334 setMachineCodes(mi++, (byte) 0x6F);
37335 emitRegRegOperands(srcReg, dstReg);
37336 if (lister != null) lister.RR(miStart, "MOVQ", dstReg, srcReg);
37337 }
37338
37339 /**
37340 * Generate a register--register-displacement MOVQ. That is,
37341 * <PRE>
37342 * dstReg <<= (quad) [srcBase + srcDisp]
37343 * </PRE>
37344 *
37345 * @param dstReg destination register
37346 * @param srcBase the source base register
37347 * @param srcDisp the source displacement
37348 */
37349 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
37350 public final void emitMOVQ_Reg_RegDisp(MM dstReg, GPR srcBase, Offset srcDisp) {
37351 int miStart = mi;
37352 generateREXprefix(false, dstReg, null, srcBase);
37353 setMachineCodes(mi++, (byte) 0x0F);
37354 setMachineCodes(mi++, (byte) 0x6F);
37355 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
37356 if (lister != null) lister.RRD(miStart, "MOVQ", dstReg, srcBase, srcDisp);
37357 }
37358
37359 /**
37360 * Generate a register--register-offset MOVQ. That is,
37361 * <PRE>
37362 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
37363 * </PRE>
37364 *
37365 * @param dstReg destination register
37366 * @param srcIndex the source index register
37367 * @param srcScale the source scale
37368 * @param srcDisp the source displacement
37369 */
37370 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
37371 public final void emitMOVQ_Reg_RegOff(MM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
37372 int miStart = mi;
37373 generateREXprefix(false, dstReg, srcIndex, null);
37374 setMachineCodes(mi++, (byte) 0x0F);
37375 setMachineCodes(mi++, (byte) 0x6F);
37376 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
37377 if (lister != null) lister.RRFD(miStart, "MOVQ", dstReg, srcIndex, srcScale, srcDisp);
37378 }
37379
37380 /**
37381 * Generate a register--absolute MOVQ. That is,
37382 * <PRE>
37383 * dstReg <<= (quad) [srcDisp]
37384 * </PRE>
37385 *
37386 * @param dstReg destination register
37387 * @param srcDisp the source displacement
37388 */
37389 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
37390 public final void emitMOVQ_Reg_Abs(MM dstReg, Address srcDisp) {
37391 int miStart = mi;
37392 generateREXprefix(false, dstReg, null, null);
37393 setMachineCodes(mi++, (byte) 0x0F);
37394 setMachineCodes(mi++, (byte) 0x6F);
37395 emitAbsRegOperands(srcDisp, dstReg);
37396 if (lister != null) lister.RRA(miStart, "MOVQ", dstReg, srcDisp);
37397 }
37398
37399 /**
37400 * Generate a register--register-index MOVQ. That is,
37401 * <PRE>
37402 * dstReg <<= (quad) srcReg
37403 * </PRE>
37404 *
37405 * @param dstReg destination register
37406 * @param srcBase the source base register
37407 * @param srcIndex the source index register
37408 * @param srcScale the source scale
37409 * @param srcDisp the source displacement
37410 */
37411 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
37412 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
37413 public final void emitMOVQ_Reg_RegIdx(MM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
37414 int miStart = mi;
37415 generateREXprefix(false, dstReg, srcIndex, srcBase);
37416 setMachineCodes(mi++, (byte) 0x0F);
37417 setMachineCodes(mi++, (byte) 0x6F);
37418 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
37419 if (lister != null) lister.RRXD(miStart, "MOVQ", dstReg, srcBase, srcIndex, srcScale, srcDisp);
37420 }
37421
37422 /**
37423 * Generate a register--register-indirect MOVQ. That is,
37424 * <PRE>
37425 * dstReg <<= (quad) [srcBase]
37426 * </PRE>
37427 *
37428 * @param dstReg destination register
37429 * @param srcBase the source base register
37430 */
37431 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
37432 public final void emitMOVQ_Reg_RegInd(MM dstReg, GPR srcBase) {
37433 int miStart = mi;
37434 generateREXprefix(false, dstReg, null, srcBase);
37435 setMachineCodes(mi++, (byte) 0x0F);
37436 setMachineCodes(mi++, (byte) 0x6F);
37437 emitRegIndirectRegOperands(srcBase, dstReg);
37438 if (lister != null) lister.RRN(miStart, "MOVQ", dstReg, srcBase);
37439 }
37440
37441
37442 /**
37443 * Generate a register-indirect--register MOVQ. That is,
37444 * <PRE>
37445 * [dstBase] <<= (quad) srcReg
37446 * </PRE>
37447 *
37448 * @param dstBase the destination base register
37449 * @param srcReg the source register
37450 */
37451 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
37452 public final void emitMOVQ_RegInd_Reg(GPR dstBase, MM srcReg) {
37453 int miStart = mi;
37454 generateREXprefix(false, srcReg, null, dstBase);
37455 setMachineCodes(mi++, (byte) 0x0F);
37456 setMachineCodes(mi++, (byte) 0x7F);
37457 emitRegIndirectRegOperands(dstBase, srcReg);
37458 if (lister != null) lister.RNR(miStart, "MOVQ", dstBase, srcReg);
37459 }
37460
37461 /**
37462 * Generate a register-offset--register MOVQ. That is,
37463 * <PRE>
37464 * [dstReg<<dstScale + dstDisp] <<= (quad) srcReg
37465 * </PRE>
37466 *
37467 * @param dstIndex the destination index register
37468 * @param dstScale the destination shift amount
37469 * @param dstDisp the destination displacement
37470 * @param srcReg the source register
37471 */
37472 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
37473 public final void emitMOVQ_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, MM srcReg) {
37474 int miStart = mi;
37475 generateREXprefix(false, srcReg, dstIndex, null);
37476 setMachineCodes(mi++, (byte) 0x0F);
37477 setMachineCodes(mi++, (byte) 0x7F);
37478 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
37479 if (lister != null) lister.RFDR(miStart, "MOVQ", dstIndex, dstScale, dstDisp, srcReg);
37480 }
37481
37482 /**
37483 * Generate a absolute--register MOVQ. That is,
37484 * <PRE>
37485 * [dstDisp] <<= (quad) srcReg
37486 * </PRE>
37487 *
37488 * @param dstDisp the destination displacement
37489 * @param srcReg the source register
37490 */
37491 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
37492 public final void emitMOVQ_Abs_Reg(Address dstDisp, MM srcReg) {
37493 int miStart = mi;
37494 generateREXprefix(false, srcReg, null, null);
37495 setMachineCodes(mi++, (byte) 0x0F);
37496 setMachineCodes(mi++, (byte) 0x7F);
37497 emitAbsRegOperands(dstDisp, srcReg);
37498 if (lister != null) lister.RAR(miStart, "MOVQ", dstDisp, srcReg);
37499 }
37500
37501 /**
37502 * Generate a register-index--register MOVQ. That is,
37503 * <PRE>
37504 * [dstBase + dstIndex<<dstScale + dstDisp] <<= (quad) srcReg
37505 * </PRE>
37506 *
37507 * @param dstBase the destination base register
37508 * @param dstIndex the destination index register
37509 * @param dstScale the destination shift amount
37510 * @param dstDisp the destination displacement
37511 * @param srcReg the source register
37512 */
37513 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
37514 public final void emitMOVQ_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, MM srcReg) {
37515 int miStart = mi;
37516 generateREXprefix(false, srcReg, dstIndex, dstBase);
37517 setMachineCodes(mi++, (byte) 0x0F);
37518 setMachineCodes(mi++, (byte) 0x7F);
37519 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
37520 if (lister != null) lister.RXDR(miStart, "MOVQ", dstBase, dstIndex, dstScale, dstDisp, srcReg);
37521 }
37522
37523 /**
37524 * Generate a register-displacement--register MOVQ. That is,
37525 * <PRE>
37526 * [dstBase + dstDisp] <<= (quad) srcReg
37527 * </PRE>
37528 *
37529 * @param dstBase the destination base register
37530 * @param dstDisp the destination displacement
37531 * @param srcReg the source register
37532 */
37533 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
37534 public final void emitMOVQ_RegDisp_Reg(GPR dstBase, Offset dstDisp, MM srcReg) {
37535 int miStart = mi;
37536 generateREXprefix(false, srcReg, null, dstBase);
37537 setMachineCodes(mi++, (byte) 0x0F);
37538 setMachineCodes(mi++, (byte) 0x7F);
37539 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
37540 if (lister != null) lister.RDR(miStart, "MOVQ", dstBase, dstDisp, srcReg);
37541 }
37542
37543
37544 /**
37545 * Generate a register--register MOVQ. That is,
37546 * <PRE>
37547 * dstReg <<= (quad) srcReg
37548 * </PRE>
37549 *
37550 * @param dstReg destination register
37551 * @param srcReg source register
37552 */
37553 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
37554 public final void emitMOVQ_Reg_Reg(XMM dstReg, XMM srcReg) {
37555 int miStart = mi;
37556 setMachineCodes(mi++, (byte) 0xF3);
37557 generateREXprefix(false, dstReg, null, srcReg);
37558 setMachineCodes(mi++, (byte) 0x0F);
37559 setMachineCodes(mi++, (byte) 0x7E);
37560 emitRegRegOperands(srcReg, dstReg);
37561 if (lister != null) lister.RR(miStart, "MOVQ", dstReg, srcReg);
37562 }
37563
37564 /**
37565 * Generate a register--register-displacement MOVQ. That is,
37566 * <PRE>
37567 * dstReg <<= (quad) [srcBase + srcDisp]
37568 * </PRE>
37569 *
37570 * @param dstReg destination register
37571 * @param srcBase the source base register
37572 * @param srcDisp the source displacement
37573 */
37574 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
37575 public final void emitMOVQ_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
37576 int miStart = mi;
37577 setMachineCodes(mi++, (byte) 0xF3);
37578 generateREXprefix(false, dstReg, null, srcBase);
37579 setMachineCodes(mi++, (byte) 0x0F);
37580 setMachineCodes(mi++, (byte) 0x7E);
37581 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
37582 if (lister != null) lister.RRD(miStart, "MOVQ", dstReg, srcBase, srcDisp);
37583 }
37584
37585 /**
37586 * Generate a register--register-offset MOVQ. That is,
37587 * <PRE>
37588 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
37589 * </PRE>
37590 *
37591 * @param dstReg destination register
37592 * @param srcIndex the source index register
37593 * @param srcScale the source scale
37594 * @param srcDisp the source displacement
37595 */
37596 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
37597 public final void emitMOVQ_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
37598 int miStart = mi;
37599 setMachineCodes(mi++, (byte) 0xF3);
37600 generateREXprefix(false, dstReg, srcIndex, null);
37601 setMachineCodes(mi++, (byte) 0x0F);
37602 setMachineCodes(mi++, (byte) 0x7E);
37603 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
37604 if (lister != null) lister.RRFD(miStart, "MOVQ", dstReg, srcIndex, srcScale, srcDisp);
37605 }
37606
37607 /**
37608 * Generate a register--absolute MOVQ. That is,
37609 * <PRE>
37610 * dstReg <<= (quad) [srcDisp]
37611 * </PRE>
37612 *
37613 * @param dstReg destination register
37614 * @param srcDisp the source displacement
37615 */
37616 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
37617 public final void emitMOVQ_Reg_Abs(XMM dstReg, Address srcDisp) {
37618 int miStart = mi;
37619 setMachineCodes(mi++, (byte) 0xF3);
37620 generateREXprefix(false, dstReg, null, null);
37621 setMachineCodes(mi++, (byte) 0x0F);
37622 setMachineCodes(mi++, (byte) 0x7E);
37623 emitAbsRegOperands(srcDisp, dstReg);
37624 if (lister != null) lister.RRA(miStart, "MOVQ", dstReg, srcDisp);
37625 }
37626
37627 /**
37628 * Generate a register--register-index MOVQ. That is,
37629 * <PRE>
37630 * dstReg <<= (quad) srcReg
37631 * </PRE>
37632 *
37633 * @param dstReg destination register
37634 * @param srcBase the source base register
37635 * @param srcIndex the source index register
37636 * @param srcScale the source scale
37637 * @param srcDisp the source displacement
37638 */
37639 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
37640 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
37641 public final void emitMOVQ_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
37642 int miStart = mi;
37643 setMachineCodes(mi++, (byte) 0xF3);
37644 generateREXprefix(false, dstReg, srcIndex, srcBase);
37645 setMachineCodes(mi++, (byte) 0x0F);
37646 setMachineCodes(mi++, (byte) 0x7E);
37647 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
37648 if (lister != null) lister.RRXD(miStart, "MOVQ", dstReg, srcBase, srcIndex, srcScale, srcDisp);
37649 }
37650
37651 /**
37652 * Generate a register--register-indirect MOVQ. That is,
37653 * <PRE>
37654 * dstReg <<= (quad) [srcBase]
37655 * </PRE>
37656 *
37657 * @param dstReg destination register
37658 * @param srcBase the source base register
37659 */
37660 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
37661 public final void emitMOVQ_Reg_RegInd(XMM dstReg, GPR srcBase) {
37662 int miStart = mi;
37663 setMachineCodes(mi++, (byte) 0xF3);
37664 generateREXprefix(false, dstReg, null, srcBase);
37665 setMachineCodes(mi++, (byte) 0x0F);
37666 setMachineCodes(mi++, (byte) 0x7E);
37667 emitRegIndirectRegOperands(srcBase, dstReg);
37668 if (lister != null) lister.RRN(miStart, "MOVQ", dstReg, srcBase);
37669 }
37670
37671
37672 /**
37673 * Generate a register-indirect--register MOVQ. That is,
37674 * <PRE>
37675 * [dstBase] <<= (quad) srcReg
37676 * </PRE>
37677 *
37678 * @param dstBase the destination base register
37679 * @param srcReg the source register
37680 */
37681 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
37682 public final void emitMOVQ_RegInd_Reg(GPR dstBase, XMM srcReg) {
37683 int miStart = mi;
37684 setMachineCodes(mi++, (byte) 0x66);
37685 generateREXprefix(false, srcReg, null, dstBase);
37686 setMachineCodes(mi++, (byte) 0x0F);
37687 setMachineCodes(mi++, (byte) 0xD6);
37688 emitRegIndirectRegOperands(dstBase, srcReg);
37689 if (lister != null) lister.RNR(miStart, "MOVQ", dstBase, srcReg);
37690 }
37691
37692 /**
37693 * Generate a register-offset--register MOVQ. That is,
37694 * <PRE>
37695 * [dstReg<<dstScale + dstDisp] <<= (quad) srcReg
37696 * </PRE>
37697 *
37698 * @param dstIndex the destination index register
37699 * @param dstScale the destination shift amount
37700 * @param dstDisp the destination displacement
37701 * @param srcReg the source register
37702 */
37703 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
37704 public final void emitMOVQ_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, XMM srcReg) {
37705 int miStart = mi;
37706 setMachineCodes(mi++, (byte) 0x66);
37707 generateREXprefix(false, srcReg, dstIndex, null);
37708 setMachineCodes(mi++, (byte) 0x0F);
37709 setMachineCodes(mi++, (byte) 0xD6);
37710 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
37711 if (lister != null) lister.RFDR(miStart, "MOVQ", dstIndex, dstScale, dstDisp, srcReg);
37712 }
37713
37714 /**
37715 * Generate a absolute--register MOVQ. That is,
37716 * <PRE>
37717 * [dstDisp] <<= (quad) srcReg
37718 * </PRE>
37719 *
37720 * @param dstDisp the destination displacement
37721 * @param srcReg the source register
37722 */
37723 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
37724 public final void emitMOVQ_Abs_Reg(Address dstDisp, XMM srcReg) {
37725 int miStart = mi;
37726 setMachineCodes(mi++, (byte) 0x66);
37727 generateREXprefix(false, srcReg, null, null);
37728 setMachineCodes(mi++, (byte) 0x0F);
37729 setMachineCodes(mi++, (byte) 0xD6);
37730 emitAbsRegOperands(dstDisp, srcReg);
37731 if (lister != null) lister.RAR(miStart, "MOVQ", dstDisp, srcReg);
37732 }
37733
37734 /**
37735 * Generate a register-index--register MOVQ. That is,
37736 * <PRE>
37737 * [dstBase + dstIndex<<dstScale + dstDisp] <<= (quad) srcReg
37738 * </PRE>
37739 *
37740 * @param dstBase the destination base register
37741 * @param dstIndex the destination index register
37742 * @param dstScale the destination shift amount
37743 * @param dstDisp the destination displacement
37744 * @param srcReg the source register
37745 */
37746 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
37747 public final void emitMOVQ_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, XMM srcReg) {
37748 int miStart = mi;
37749 setMachineCodes(mi++, (byte) 0x66);
37750 generateREXprefix(false, srcReg, dstIndex, dstBase);
37751 setMachineCodes(mi++, (byte) 0x0F);
37752 setMachineCodes(mi++, (byte) 0xD6);
37753 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
37754 if (lister != null) lister.RXDR(miStart, "MOVQ", dstBase, dstIndex, dstScale, dstDisp, srcReg);
37755 }
37756
37757 /**
37758 * Generate a register-displacement--register MOVQ. That is,
37759 * <PRE>
37760 * [dstBase + dstDisp] <<= (quad) srcReg
37761 * </PRE>
37762 *
37763 * @param dstBase the destination base register
37764 * @param dstDisp the destination displacement
37765 * @param srcReg the source register
37766 */
37767 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
37768 public final void emitMOVQ_RegDisp_Reg(GPR dstBase, Offset dstDisp, XMM srcReg) {
37769 int miStart = mi;
37770 setMachineCodes(mi++, (byte) 0x66);
37771 generateREXprefix(false, srcReg, null, dstBase);
37772 setMachineCodes(mi++, (byte) 0x0F);
37773 setMachineCodes(mi++, (byte) 0xD6);
37774 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
37775 if (lister != null) lister.RDR(miStart, "MOVQ", dstBase, dstDisp, srcReg);
37776 }
37777
37778
37779 /**
37780 * Generate a register--register ADDSD. That is,
37781 * <PRE>
37782 * dstReg <<= (quad) srcReg
37783 * </PRE>
37784 *
37785 * @param dstReg destination register
37786 * @param srcReg source register
37787 */
37788 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
37789 public final void emitADDSD_Reg_Reg(XMM dstReg, XMM srcReg) {
37790 int miStart = mi;
37791 setMachineCodes(mi++, (byte) 0xF2);
37792 generateREXprefix(false, dstReg, null, srcReg);
37793 setMachineCodes(mi++, (byte) 0x0F);
37794 setMachineCodes(mi++, (byte) 0x58);
37795 emitRegRegOperands(srcReg, dstReg);
37796 if (lister != null) lister.RR(miStart, "ADDSD", dstReg, srcReg);
37797 }
37798
37799 /**
37800 * Generate a register--register-displacement ADDSD. That is,
37801 * <PRE>
37802 * dstReg <<= (quad) [srcBase + srcDisp]
37803 * </PRE>
37804 *
37805 * @param dstReg destination register
37806 * @param srcBase the source base register
37807 * @param srcDisp the source displacement
37808 */
37809 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
37810 public final void emitADDSD_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
37811 int miStart = mi;
37812 setMachineCodes(mi++, (byte) 0xF2);
37813 generateREXprefix(false, dstReg, null, srcBase);
37814 setMachineCodes(mi++, (byte) 0x0F);
37815 setMachineCodes(mi++, (byte) 0x58);
37816 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
37817 if (lister != null) lister.RRD(miStart, "ADDSD", dstReg, srcBase, srcDisp);
37818 }
37819
37820 /**
37821 * Generate a register--register-offset ADDSD. That is,
37822 * <PRE>
37823 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
37824 * </PRE>
37825 *
37826 * @param dstReg destination register
37827 * @param srcIndex the source index register
37828 * @param srcScale the source scale
37829 * @param srcDisp the source displacement
37830 */
37831 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
37832 public final void emitADDSD_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
37833 int miStart = mi;
37834 setMachineCodes(mi++, (byte) 0xF2);
37835 generateREXprefix(false, dstReg, srcIndex, null);
37836 setMachineCodes(mi++, (byte) 0x0F);
37837 setMachineCodes(mi++, (byte) 0x58);
37838 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
37839 if (lister != null) lister.RRFD(miStart, "ADDSD", dstReg, srcIndex, srcScale, srcDisp);
37840 }
37841
37842 /**
37843 * Generate a register--absolute ADDSD. That is,
37844 * <PRE>
37845 * dstReg <<= (quad) [srcDisp]
37846 * </PRE>
37847 *
37848 * @param dstReg destination register
37849 * @param srcDisp the source displacement
37850 */
37851 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
37852 public final void emitADDSD_Reg_Abs(XMM dstReg, Address srcDisp) {
37853 int miStart = mi;
37854 setMachineCodes(mi++, (byte) 0xF2);
37855 generateREXprefix(false, dstReg, null, null);
37856 setMachineCodes(mi++, (byte) 0x0F);
37857 setMachineCodes(mi++, (byte) 0x58);
37858 emitAbsRegOperands(srcDisp, dstReg);
37859 if (lister != null) lister.RRA(miStart, "ADDSD", dstReg, srcDisp);
37860 }
37861
37862 /**
37863 * Generate a register--register-index ADDSD. That is,
37864 * <PRE>
37865 * dstReg <<= (quad) srcReg
37866 * </PRE>
37867 *
37868 * @param dstReg destination register
37869 * @param srcBase the source base register
37870 * @param srcIndex the source index register
37871 * @param srcScale the source scale
37872 * @param srcDisp the source displacement
37873 */
37874 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
37875 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
37876 public final void emitADDSD_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
37877 int miStart = mi;
37878 setMachineCodes(mi++, (byte) 0xF2);
37879 generateREXprefix(false, dstReg, srcIndex, srcBase);
37880 setMachineCodes(mi++, (byte) 0x0F);
37881 setMachineCodes(mi++, (byte) 0x58);
37882 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
37883 if (lister != null) lister.RRXD(miStart, "ADDSD", dstReg, srcBase, srcIndex, srcScale, srcDisp);
37884 }
37885
37886 /**
37887 * Generate a register--register-indirect ADDSD. That is,
37888 * <PRE>
37889 * dstReg <<= (quad) [srcBase]
37890 * </PRE>
37891 *
37892 * @param dstReg destination register
37893 * @param srcBase the source base register
37894 */
37895 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
37896 public final void emitADDSD_Reg_RegInd(XMM dstReg, GPR srcBase) {
37897 int miStart = mi;
37898 setMachineCodes(mi++, (byte) 0xF2);
37899 generateREXprefix(false, dstReg, null, srcBase);
37900 setMachineCodes(mi++, (byte) 0x0F);
37901 setMachineCodes(mi++, (byte) 0x58);
37902 emitRegIndirectRegOperands(srcBase, dstReg);
37903 if (lister != null) lister.RRN(miStart, "ADDSD", dstReg, srcBase);
37904 }
37905
37906
37907 /**
37908 * Generate a register--register SUBSD. That is,
37909 * <PRE>
37910 * dstReg <<= (quad) srcReg
37911 * </PRE>
37912 *
37913 * @param dstReg destination register
37914 * @param srcReg source register
37915 */
37916 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
37917 public final void emitSUBSD_Reg_Reg(XMM dstReg, XMM srcReg) {
37918 int miStart = mi;
37919 setMachineCodes(mi++, (byte) 0xF2);
37920 generateREXprefix(false, dstReg, null, srcReg);
37921 setMachineCodes(mi++, (byte) 0x0F);
37922 setMachineCodes(mi++, (byte) 0x5C);
37923 emitRegRegOperands(srcReg, dstReg);
37924 if (lister != null) lister.RR(miStart, "SUBSD", dstReg, srcReg);
37925 }
37926
37927 /**
37928 * Generate a register--register-displacement SUBSD. That is,
37929 * <PRE>
37930 * dstReg <<= (quad) [srcBase + srcDisp]
37931 * </PRE>
37932 *
37933 * @param dstReg destination register
37934 * @param srcBase the source base register
37935 * @param srcDisp the source displacement
37936 */
37937 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
37938 public final void emitSUBSD_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
37939 int miStart = mi;
37940 setMachineCodes(mi++, (byte) 0xF2);
37941 generateREXprefix(false, dstReg, null, srcBase);
37942 setMachineCodes(mi++, (byte) 0x0F);
37943 setMachineCodes(mi++, (byte) 0x5C);
37944 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
37945 if (lister != null) lister.RRD(miStart, "SUBSD", dstReg, srcBase, srcDisp);
37946 }
37947
37948 /**
37949 * Generate a register--register-offset SUBSD. That is,
37950 * <PRE>
37951 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
37952 * </PRE>
37953 *
37954 * @param dstReg destination register
37955 * @param srcIndex the source index register
37956 * @param srcScale the source scale
37957 * @param srcDisp the source displacement
37958 */
37959 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
37960 public final void emitSUBSD_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
37961 int miStart = mi;
37962 setMachineCodes(mi++, (byte) 0xF2);
37963 generateREXprefix(false, dstReg, srcIndex, null);
37964 setMachineCodes(mi++, (byte) 0x0F);
37965 setMachineCodes(mi++, (byte) 0x5C);
37966 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
37967 if (lister != null) lister.RRFD(miStart, "SUBSD", dstReg, srcIndex, srcScale, srcDisp);
37968 }
37969
37970 /**
37971 * Generate a register--absolute SUBSD. That is,
37972 * <PRE>
37973 * dstReg <<= (quad) [srcDisp]
37974 * </PRE>
37975 *
37976 * @param dstReg destination register
37977 * @param srcDisp the source displacement
37978 */
37979 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
37980 public final void emitSUBSD_Reg_Abs(XMM dstReg, Address srcDisp) {
37981 int miStart = mi;
37982 setMachineCodes(mi++, (byte) 0xF2);
37983 generateREXprefix(false, dstReg, null, null);
37984 setMachineCodes(mi++, (byte) 0x0F);
37985 setMachineCodes(mi++, (byte) 0x5C);
37986 emitAbsRegOperands(srcDisp, dstReg);
37987 if (lister != null) lister.RRA(miStart, "SUBSD", dstReg, srcDisp);
37988 }
37989
37990 /**
37991 * Generate a register--register-index SUBSD. That is,
37992 * <PRE>
37993 * dstReg <<= (quad) srcReg
37994 * </PRE>
37995 *
37996 * @param dstReg destination register
37997 * @param srcBase the source base register
37998 * @param srcIndex the source index register
37999 * @param srcScale the source scale
38000 * @param srcDisp the source displacement
38001 */
38002 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
38003 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
38004 public final void emitSUBSD_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
38005 int miStart = mi;
38006 setMachineCodes(mi++, (byte) 0xF2);
38007 generateREXprefix(false, dstReg, srcIndex, srcBase);
38008 setMachineCodes(mi++, (byte) 0x0F);
38009 setMachineCodes(mi++, (byte) 0x5C);
38010 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
38011 if (lister != null) lister.RRXD(miStart, "SUBSD", dstReg, srcBase, srcIndex, srcScale, srcDisp);
38012 }
38013
38014 /**
38015 * Generate a register--register-indirect SUBSD. That is,
38016 * <PRE>
38017 * dstReg <<= (quad) [srcBase]
38018 * </PRE>
38019 *
38020 * @param dstReg destination register
38021 * @param srcBase the source base register
38022 */
38023 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
38024 public final void emitSUBSD_Reg_RegInd(XMM dstReg, GPR srcBase) {
38025 int miStart = mi;
38026 setMachineCodes(mi++, (byte) 0xF2);
38027 generateREXprefix(false, dstReg, null, srcBase);
38028 setMachineCodes(mi++, (byte) 0x0F);
38029 setMachineCodes(mi++, (byte) 0x5C);
38030 emitRegIndirectRegOperands(srcBase, dstReg);
38031 if (lister != null) lister.RRN(miStart, "SUBSD", dstReg, srcBase);
38032 }
38033
38034
38035 /**
38036 * Generate a register--register MULSD. That is,
38037 * <PRE>
38038 * dstReg <<= (quad) srcReg
38039 * </PRE>
38040 *
38041 * @param dstReg destination register
38042 * @param srcReg source register
38043 */
38044 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
38045 public final void emitMULSD_Reg_Reg(XMM dstReg, XMM srcReg) {
38046 int miStart = mi;
38047 setMachineCodes(mi++, (byte) 0xF2);
38048 generateREXprefix(false, dstReg, null, srcReg);
38049 setMachineCodes(mi++, (byte) 0x0F);
38050 setMachineCodes(mi++, (byte) 0x59);
38051 emitRegRegOperands(srcReg, dstReg);
38052 if (lister != null) lister.RR(miStart, "MULSD", dstReg, srcReg);
38053 }
38054
38055 /**
38056 * Generate a register--register-displacement MULSD. That is,
38057 * <PRE>
38058 * dstReg <<= (quad) [srcBase + srcDisp]
38059 * </PRE>
38060 *
38061 * @param dstReg destination register
38062 * @param srcBase the source base register
38063 * @param srcDisp the source displacement
38064 */
38065 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
38066 public final void emitMULSD_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
38067 int miStart = mi;
38068 setMachineCodes(mi++, (byte) 0xF2);
38069 generateREXprefix(false, dstReg, null, srcBase);
38070 setMachineCodes(mi++, (byte) 0x0F);
38071 setMachineCodes(mi++, (byte) 0x59);
38072 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
38073 if (lister != null) lister.RRD(miStart, "MULSD", dstReg, srcBase, srcDisp);
38074 }
38075
38076 /**
38077 * Generate a register--register-offset MULSD. That is,
38078 * <PRE>
38079 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
38080 * </PRE>
38081 *
38082 * @param dstReg destination register
38083 * @param srcIndex the source index register
38084 * @param srcScale the source scale
38085 * @param srcDisp the source displacement
38086 */
38087 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
38088 public final void emitMULSD_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
38089 int miStart = mi;
38090 setMachineCodes(mi++, (byte) 0xF2);
38091 generateREXprefix(false, dstReg, srcIndex, null);
38092 setMachineCodes(mi++, (byte) 0x0F);
38093 setMachineCodes(mi++, (byte) 0x59);
38094 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
38095 if (lister != null) lister.RRFD(miStart, "MULSD", dstReg, srcIndex, srcScale, srcDisp);
38096 }
38097
38098 /**
38099 * Generate a register--absolute MULSD. That is,
38100 * <PRE>
38101 * dstReg <<= (quad) [srcDisp]
38102 * </PRE>
38103 *
38104 * @param dstReg destination register
38105 * @param srcDisp the source displacement
38106 */
38107 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
38108 public final void emitMULSD_Reg_Abs(XMM dstReg, Address srcDisp) {
38109 int miStart = mi;
38110 setMachineCodes(mi++, (byte) 0xF2);
38111 generateREXprefix(false, dstReg, null, null);
38112 setMachineCodes(mi++, (byte) 0x0F);
38113 setMachineCodes(mi++, (byte) 0x59);
38114 emitAbsRegOperands(srcDisp, dstReg);
38115 if (lister != null) lister.RRA(miStart, "MULSD", dstReg, srcDisp);
38116 }
38117
38118 /**
38119 * Generate a register--register-index MULSD. That is,
38120 * <PRE>
38121 * dstReg <<= (quad) srcReg
38122 * </PRE>
38123 *
38124 * @param dstReg destination register
38125 * @param srcBase the source base register
38126 * @param srcIndex the source index register
38127 * @param srcScale the source scale
38128 * @param srcDisp the source displacement
38129 */
38130 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
38131 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
38132 public final void emitMULSD_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
38133 int miStart = mi;
38134 setMachineCodes(mi++, (byte) 0xF2);
38135 generateREXprefix(false, dstReg, srcIndex, srcBase);
38136 setMachineCodes(mi++, (byte) 0x0F);
38137 setMachineCodes(mi++, (byte) 0x59);
38138 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
38139 if (lister != null) lister.RRXD(miStart, "MULSD", dstReg, srcBase, srcIndex, srcScale, srcDisp);
38140 }
38141
38142 /**
38143 * Generate a register--register-indirect MULSD. That is,
38144 * <PRE>
38145 * dstReg <<= (quad) [srcBase]
38146 * </PRE>
38147 *
38148 * @param dstReg destination register
38149 * @param srcBase the source base register
38150 */
38151 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
38152 public final void emitMULSD_Reg_RegInd(XMM dstReg, GPR srcBase) {
38153 int miStart = mi;
38154 setMachineCodes(mi++, (byte) 0xF2);
38155 generateREXprefix(false, dstReg, null, srcBase);
38156 setMachineCodes(mi++, (byte) 0x0F);
38157 setMachineCodes(mi++, (byte) 0x59);
38158 emitRegIndirectRegOperands(srcBase, dstReg);
38159 if (lister != null) lister.RRN(miStart, "MULSD", dstReg, srcBase);
38160 }
38161
38162
38163 /**
38164 * Generate a register--register DIVSD. That is,
38165 * <PRE>
38166 * dstReg <<= (quad) srcReg
38167 * </PRE>
38168 *
38169 * @param dstReg destination register
38170 * @param srcReg source register
38171 */
38172 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
38173 public final void emitDIVSD_Reg_Reg(XMM dstReg, XMM srcReg) {
38174 int miStart = mi;
38175 setMachineCodes(mi++, (byte) 0xF2);
38176 generateREXprefix(false, dstReg, null, srcReg);
38177 setMachineCodes(mi++, (byte) 0x0F);
38178 setMachineCodes(mi++, (byte) 0x5E);
38179 emitRegRegOperands(srcReg, dstReg);
38180 if (lister != null) lister.RR(miStart, "DIVSD", dstReg, srcReg);
38181 }
38182
38183 /**
38184 * Generate a register--register-displacement DIVSD. That is,
38185 * <PRE>
38186 * dstReg <<= (quad) [srcBase + srcDisp]
38187 * </PRE>
38188 *
38189 * @param dstReg destination register
38190 * @param srcBase the source base register
38191 * @param srcDisp the source displacement
38192 */
38193 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
38194 public final void emitDIVSD_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
38195 int miStart = mi;
38196 setMachineCodes(mi++, (byte) 0xF2);
38197 generateREXprefix(false, dstReg, null, srcBase);
38198 setMachineCodes(mi++, (byte) 0x0F);
38199 setMachineCodes(mi++, (byte) 0x5E);
38200 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
38201 if (lister != null) lister.RRD(miStart, "DIVSD", dstReg, srcBase, srcDisp);
38202 }
38203
38204 /**
38205 * Generate a register--register-offset DIVSD. That is,
38206 * <PRE>
38207 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
38208 * </PRE>
38209 *
38210 * @param dstReg destination register
38211 * @param srcIndex the source index register
38212 * @param srcScale the source scale
38213 * @param srcDisp the source displacement
38214 */
38215 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
38216 public final void emitDIVSD_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
38217 int miStart = mi;
38218 setMachineCodes(mi++, (byte) 0xF2);
38219 generateREXprefix(false, dstReg, srcIndex, null);
38220 setMachineCodes(mi++, (byte) 0x0F);
38221 setMachineCodes(mi++, (byte) 0x5E);
38222 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
38223 if (lister != null) lister.RRFD(miStart, "DIVSD", dstReg, srcIndex, srcScale, srcDisp);
38224 }
38225
38226 /**
38227 * Generate a register--absolute DIVSD. That is,
38228 * <PRE>
38229 * dstReg <<= (quad) [srcDisp]
38230 * </PRE>
38231 *
38232 * @param dstReg destination register
38233 * @param srcDisp the source displacement
38234 */
38235 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
38236 public final void emitDIVSD_Reg_Abs(XMM dstReg, Address srcDisp) {
38237 int miStart = mi;
38238 setMachineCodes(mi++, (byte) 0xF2);
38239 generateREXprefix(false, dstReg, null, null);
38240 setMachineCodes(mi++, (byte) 0x0F);
38241 setMachineCodes(mi++, (byte) 0x5E);
38242 emitAbsRegOperands(srcDisp, dstReg);
38243 if (lister != null) lister.RRA(miStart, "DIVSD", dstReg, srcDisp);
38244 }
38245
38246 /**
38247 * Generate a register--register-index DIVSD. That is,
38248 * <PRE>
38249 * dstReg <<= (quad) srcReg
38250 * </PRE>
38251 *
38252 * @param dstReg destination register
38253 * @param srcBase the source base register
38254 * @param srcIndex the source index register
38255 * @param srcScale the source scale
38256 * @param srcDisp the source displacement
38257 */
38258 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
38259 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
38260 public final void emitDIVSD_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
38261 int miStart = mi;
38262 setMachineCodes(mi++, (byte) 0xF2);
38263 generateREXprefix(false, dstReg, srcIndex, srcBase);
38264 setMachineCodes(mi++, (byte) 0x0F);
38265 setMachineCodes(mi++, (byte) 0x5E);
38266 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
38267 if (lister != null) lister.RRXD(miStart, "DIVSD", dstReg, srcBase, srcIndex, srcScale, srcDisp);
38268 }
38269
38270 /**
38271 * Generate a register--register-indirect DIVSD. That is,
38272 * <PRE>
38273 * dstReg <<= (quad) [srcBase]
38274 * </PRE>
38275 *
38276 * @param dstReg destination register
38277 * @param srcBase the source base register
38278 */
38279 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
38280 public final void emitDIVSD_Reg_RegInd(XMM dstReg, GPR srcBase) {
38281 int miStart = mi;
38282 setMachineCodes(mi++, (byte) 0xF2);
38283 generateREXprefix(false, dstReg, null, srcBase);
38284 setMachineCodes(mi++, (byte) 0x0F);
38285 setMachineCodes(mi++, (byte) 0x5E);
38286 emitRegIndirectRegOperands(srcBase, dstReg);
38287 if (lister != null) lister.RRN(miStart, "DIVSD", dstReg, srcBase);
38288 }
38289
38290
38291 /**
38292 * Generate a register--register MOVSD. That is,
38293 * <PRE>
38294 * dstReg <<= (quad) srcReg
38295 * </PRE>
38296 *
38297 * @param dstReg destination register
38298 * @param srcReg source register
38299 */
38300 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
38301 public final void emitMOVSD_Reg_Reg(XMM dstReg, XMM srcReg) {
38302 int miStart = mi;
38303 setMachineCodes(mi++, (byte) 0xF2);
38304 generateREXprefix(false, dstReg, null, srcReg);
38305 setMachineCodes(mi++, (byte) 0x0F);
38306 setMachineCodes(mi++, (byte) 0x10);
38307 emitRegRegOperands(srcReg, dstReg);
38308 if (lister != null) lister.RR(miStart, "MOVSD", dstReg, srcReg);
38309 }
38310
38311 /**
38312 * Generate a register--register-displacement MOVSD. That is,
38313 * <PRE>
38314 * dstReg <<= (quad) [srcBase + srcDisp]
38315 * </PRE>
38316 *
38317 * @param dstReg destination register
38318 * @param srcBase the source base register
38319 * @param srcDisp the source displacement
38320 */
38321 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
38322 public final void emitMOVSD_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
38323 int miStart = mi;
38324 setMachineCodes(mi++, (byte) 0xF2);
38325 generateREXprefix(false, dstReg, null, srcBase);
38326 setMachineCodes(mi++, (byte) 0x0F);
38327 setMachineCodes(mi++, (byte) 0x10);
38328 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
38329 if (lister != null) lister.RRD(miStart, "MOVSD", dstReg, srcBase, srcDisp);
38330 }
38331
38332 /**
38333 * Generate a register--register-offset MOVSD. That is,
38334 * <PRE>
38335 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
38336 * </PRE>
38337 *
38338 * @param dstReg destination register
38339 * @param srcIndex the source index register
38340 * @param srcScale the source scale
38341 * @param srcDisp the source displacement
38342 */
38343 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
38344 public final void emitMOVSD_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
38345 int miStart = mi;
38346 setMachineCodes(mi++, (byte) 0xF2);
38347 generateREXprefix(false, dstReg, srcIndex, null);
38348 setMachineCodes(mi++, (byte) 0x0F);
38349 setMachineCodes(mi++, (byte) 0x10);
38350 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
38351 if (lister != null) lister.RRFD(miStart, "MOVSD", dstReg, srcIndex, srcScale, srcDisp);
38352 }
38353
38354 /**
38355 * Generate a register--absolute MOVSD. That is,
38356 * <PRE>
38357 * dstReg <<= (quad) [srcDisp]
38358 * </PRE>
38359 *
38360 * @param dstReg destination register
38361 * @param srcDisp the source displacement
38362 */
38363 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
38364 public final void emitMOVSD_Reg_Abs(XMM dstReg, Address srcDisp) {
38365 int miStart = mi;
38366 setMachineCodes(mi++, (byte) 0xF2);
38367 generateREXprefix(false, dstReg, null, null);
38368 setMachineCodes(mi++, (byte) 0x0F);
38369 setMachineCodes(mi++, (byte) 0x10);
38370 emitAbsRegOperands(srcDisp, dstReg);
38371 if (lister != null) lister.RRA(miStart, "MOVSD", dstReg, srcDisp);
38372 }
38373
38374 /**
38375 * Generate a register--register-index MOVSD. That is,
38376 * <PRE>
38377 * dstReg <<= (quad) srcReg
38378 * </PRE>
38379 *
38380 * @param dstReg destination register
38381 * @param srcBase the source base register
38382 * @param srcIndex the source index register
38383 * @param srcScale the source scale
38384 * @param srcDisp the source displacement
38385 */
38386 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
38387 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
38388 public final void emitMOVSD_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
38389 int miStart = mi;
38390 setMachineCodes(mi++, (byte) 0xF2);
38391 generateREXprefix(false, dstReg, srcIndex, srcBase);
38392 setMachineCodes(mi++, (byte) 0x0F);
38393 setMachineCodes(mi++, (byte) 0x10);
38394 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
38395 if (lister != null) lister.RRXD(miStart, "MOVSD", dstReg, srcBase, srcIndex, srcScale, srcDisp);
38396 }
38397
38398 /**
38399 * Generate a register--register-indirect MOVSD. That is,
38400 * <PRE>
38401 * dstReg <<= (quad) [srcBase]
38402 * </PRE>
38403 *
38404 * @param dstReg destination register
38405 * @param srcBase the source base register
38406 */
38407 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
38408 public final void emitMOVSD_Reg_RegInd(XMM dstReg, GPR srcBase) {
38409 int miStart = mi;
38410 setMachineCodes(mi++, (byte) 0xF2);
38411 generateREXprefix(false, dstReg, null, srcBase);
38412 setMachineCodes(mi++, (byte) 0x0F);
38413 setMachineCodes(mi++, (byte) 0x10);
38414 emitRegIndirectRegOperands(srcBase, dstReg);
38415 if (lister != null) lister.RRN(miStart, "MOVSD", dstReg, srcBase);
38416 }
38417
38418
38419 /**
38420 * Generate a register-indirect--register MOVSD. That is,
38421 * <PRE>
38422 * [dstBase] <<= (quad) srcReg
38423 * </PRE>
38424 *
38425 * @param dstBase the destination base register
38426 * @param srcReg the source register
38427 */
38428 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
38429 public final void emitMOVSD_RegInd_Reg(GPR dstBase, XMM srcReg) {
38430 int miStart = mi;
38431 setMachineCodes(mi++, (byte) 0xF2);
38432 generateREXprefix(false, srcReg, null, dstBase);
38433 setMachineCodes(mi++, (byte) 0x0F);
38434 setMachineCodes(mi++, (byte) 0x11);
38435 emitRegIndirectRegOperands(dstBase, srcReg);
38436 if (lister != null) lister.RNR(miStart, "MOVSD", dstBase, srcReg);
38437 }
38438
38439 /**
38440 * Generate a register-offset--register MOVSD. That is,
38441 * <PRE>
38442 * [dstReg<<dstScale + dstDisp] <<= (quad) srcReg
38443 * </PRE>
38444 *
38445 * @param dstIndex the destination index register
38446 * @param dstScale the destination shift amount
38447 * @param dstDisp the destination displacement
38448 * @param srcReg the source register
38449 */
38450 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
38451 public final void emitMOVSD_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, XMM srcReg) {
38452 int miStart = mi;
38453 setMachineCodes(mi++, (byte) 0xF2);
38454 generateREXprefix(false, srcReg, dstIndex, null);
38455 setMachineCodes(mi++, (byte) 0x0F);
38456 setMachineCodes(mi++, (byte) 0x11);
38457 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
38458 if (lister != null) lister.RFDR(miStart, "MOVSD", dstIndex, dstScale, dstDisp, srcReg);
38459 }
38460
38461 /**
38462 * Generate a absolute--register MOVSD. That is,
38463 * <PRE>
38464 * [dstDisp] <<= (quad) srcReg
38465 * </PRE>
38466 *
38467 * @param dstDisp the destination displacement
38468 * @param srcReg the source register
38469 */
38470 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
38471 public final void emitMOVSD_Abs_Reg(Address dstDisp, XMM srcReg) {
38472 int miStart = mi;
38473 setMachineCodes(mi++, (byte) 0xF2);
38474 generateREXprefix(false, srcReg, null, null);
38475 setMachineCodes(mi++, (byte) 0x0F);
38476 setMachineCodes(mi++, (byte) 0x11);
38477 emitAbsRegOperands(dstDisp, srcReg);
38478 if (lister != null) lister.RAR(miStart, "MOVSD", dstDisp, srcReg);
38479 }
38480
38481 /**
38482 * Generate a register-index--register MOVSD. That is,
38483 * <PRE>
38484 * [dstBase + dstIndex<<dstScale + dstDisp] <<= (quad) srcReg
38485 * </PRE>
38486 *
38487 * @param dstBase the destination base register
38488 * @param dstIndex the destination index register
38489 * @param dstScale the destination shift amount
38490 * @param dstDisp the destination displacement
38491 * @param srcReg the source register
38492 */
38493 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
38494 public final void emitMOVSD_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, XMM srcReg) {
38495 int miStart = mi;
38496 setMachineCodes(mi++, (byte) 0xF2);
38497 generateREXprefix(false, srcReg, dstIndex, dstBase);
38498 setMachineCodes(mi++, (byte) 0x0F);
38499 setMachineCodes(mi++, (byte) 0x11);
38500 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
38501 if (lister != null) lister.RXDR(miStart, "MOVSD", dstBase, dstIndex, dstScale, dstDisp, srcReg);
38502 }
38503
38504 /**
38505 * Generate a register-displacement--register MOVSD. That is,
38506 * <PRE>
38507 * [dstBase + dstDisp] <<= (quad) srcReg
38508 * </PRE>
38509 *
38510 * @param dstBase the destination base register
38511 * @param dstDisp the destination displacement
38512 * @param srcReg the source register
38513 */
38514 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
38515 public final void emitMOVSD_RegDisp_Reg(GPR dstBase, Offset dstDisp, XMM srcReg) {
38516 int miStart = mi;
38517 setMachineCodes(mi++, (byte) 0xF2);
38518 generateREXprefix(false, srcReg, null, dstBase);
38519 setMachineCodes(mi++, (byte) 0x0F);
38520 setMachineCodes(mi++, (byte) 0x11);
38521 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
38522 if (lister != null) lister.RDR(miStart, "MOVSD", dstBase, dstDisp, srcReg);
38523 }
38524
38525
38526 /**
38527 * Generate a register--register MOVLPD. That is,
38528 * <PRE>
38529 * dstReg <<= (quad) srcReg
38530 * </PRE>
38531 *
38532 * @param dstReg destination register
38533 * @param srcReg source register
38534 */
38535 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
38536 public final void emitMOVLPD_Reg_Reg(XMM dstReg, XMM srcReg) {
38537 int miStart = mi;
38538 setMachineCodes(mi++, (byte) 0x66);
38539 generateREXprefix(false, dstReg, null, srcReg);
38540 setMachineCodes(mi++, (byte) 0x0F);
38541 setMachineCodes(mi++, (byte) 0x12);
38542 emitRegRegOperands(srcReg, dstReg);
38543 if (lister != null) lister.RR(miStart, "MOVLPD", dstReg, srcReg);
38544 }
38545
38546 /**
38547 * Generate a register--register-displacement MOVLPD. That is,
38548 * <PRE>
38549 * dstReg <<= (quad) [srcBase + srcDisp]
38550 * </PRE>
38551 *
38552 * @param dstReg destination register
38553 * @param srcBase the source base register
38554 * @param srcDisp the source displacement
38555 */
38556 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
38557 public final void emitMOVLPD_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
38558 int miStart = mi;
38559 setMachineCodes(mi++, (byte) 0x66);
38560 generateREXprefix(false, dstReg, null, srcBase);
38561 setMachineCodes(mi++, (byte) 0x0F);
38562 setMachineCodes(mi++, (byte) 0x12);
38563 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
38564 if (lister != null) lister.RRD(miStart, "MOVLPD", dstReg, srcBase, srcDisp);
38565 }
38566
38567 /**
38568 * Generate a register--register-offset MOVLPD. That is,
38569 * <PRE>
38570 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
38571 * </PRE>
38572 *
38573 * @param dstReg destination register
38574 * @param srcIndex the source index register
38575 * @param srcScale the source scale
38576 * @param srcDisp the source displacement
38577 */
38578 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
38579 public final void emitMOVLPD_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
38580 int miStart = mi;
38581 setMachineCodes(mi++, (byte) 0x66);
38582 generateREXprefix(false, dstReg, srcIndex, null);
38583 setMachineCodes(mi++, (byte) 0x0F);
38584 setMachineCodes(mi++, (byte) 0x12);
38585 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
38586 if (lister != null) lister.RRFD(miStart, "MOVLPD", dstReg, srcIndex, srcScale, srcDisp);
38587 }
38588
38589 /**
38590 * Generate a register--absolute MOVLPD. That is,
38591 * <PRE>
38592 * dstReg <<= (quad) [srcDisp]
38593 * </PRE>
38594 *
38595 * @param dstReg destination register
38596 * @param srcDisp the source displacement
38597 */
38598 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
38599 public final void emitMOVLPD_Reg_Abs(XMM dstReg, Address srcDisp) {
38600 int miStart = mi;
38601 setMachineCodes(mi++, (byte) 0x66);
38602 generateREXprefix(false, dstReg, null, null);
38603 setMachineCodes(mi++, (byte) 0x0F);
38604 setMachineCodes(mi++, (byte) 0x12);
38605 emitAbsRegOperands(srcDisp, dstReg);
38606 if (lister != null) lister.RRA(miStart, "MOVLPD", dstReg, srcDisp);
38607 }
38608
38609 /**
38610 * Generate a register--register-index MOVLPD. That is,
38611 * <PRE>
38612 * dstReg <<= (quad) srcReg
38613 * </PRE>
38614 *
38615 * @param dstReg destination register
38616 * @param srcBase the source base register
38617 * @param srcIndex the source index register
38618 * @param srcScale the source scale
38619 * @param srcDisp the source displacement
38620 */
38621 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
38622 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
38623 public final void emitMOVLPD_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
38624 int miStart = mi;
38625 setMachineCodes(mi++, (byte) 0x66);
38626 generateREXprefix(false, dstReg, srcIndex, srcBase);
38627 setMachineCodes(mi++, (byte) 0x0F);
38628 setMachineCodes(mi++, (byte) 0x12);
38629 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
38630 if (lister != null) lister.RRXD(miStart, "MOVLPD", dstReg, srcBase, srcIndex, srcScale, srcDisp);
38631 }
38632
38633 /**
38634 * Generate a register--register-indirect MOVLPD. That is,
38635 * <PRE>
38636 * dstReg <<= (quad) [srcBase]
38637 * </PRE>
38638 *
38639 * @param dstReg destination register
38640 * @param srcBase the source base register
38641 */
38642 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
38643 public final void emitMOVLPD_Reg_RegInd(XMM dstReg, GPR srcBase) {
38644 int miStart = mi;
38645 setMachineCodes(mi++, (byte) 0x66);
38646 generateREXprefix(false, dstReg, null, srcBase);
38647 setMachineCodes(mi++, (byte) 0x0F);
38648 setMachineCodes(mi++, (byte) 0x12);
38649 emitRegIndirectRegOperands(srcBase, dstReg);
38650 if (lister != null) lister.RRN(miStart, "MOVLPD", dstReg, srcBase);
38651 }
38652
38653
38654 /**
38655 * Generate a register-indirect--register MOVLPD. That is,
38656 * <PRE>
38657 * [dstBase] <<= (quad) srcReg
38658 * </PRE>
38659 *
38660 * @param dstBase the destination base register
38661 * @param srcReg the source register
38662 */
38663 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
38664 public final void emitMOVLPD_RegInd_Reg(GPR dstBase, XMM srcReg) {
38665 int miStart = mi;
38666 setMachineCodes(mi++, (byte) 0x66);
38667 generateREXprefix(false, srcReg, null, dstBase);
38668 setMachineCodes(mi++, (byte) 0x0F);
38669 setMachineCodes(mi++, (byte) 0x13);
38670 emitRegIndirectRegOperands(dstBase, srcReg);
38671 if (lister != null) lister.RNR(miStart, "MOVLPD", dstBase, srcReg);
38672 }
38673
38674 /**
38675 * Generate a register-offset--register MOVLPD. That is,
38676 * <PRE>
38677 * [dstReg<<dstScale + dstDisp] <<= (quad) srcReg
38678 * </PRE>
38679 *
38680 * @param dstIndex the destination index register
38681 * @param dstScale the destination shift amount
38682 * @param dstDisp the destination displacement
38683 * @param srcReg the source register
38684 */
38685 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,4})
38686 public final void emitMOVLPD_RegOff_Reg(GPR dstIndex, short dstScale, Offset dstDisp, XMM srcReg) {
38687 int miStart = mi;
38688 setMachineCodes(mi++, (byte) 0x66);
38689 generateREXprefix(false, srcReg, dstIndex, null);
38690 setMachineCodes(mi++, (byte) 0x0F);
38691 setMachineCodes(mi++, (byte) 0x13);
38692 emitRegOffRegOperands(dstIndex, dstScale, dstDisp, srcReg);
38693 if (lister != null) lister.RFDR(miStart, "MOVLPD", dstIndex, dstScale, dstDisp, srcReg);
38694 }
38695
38696 /**
38697 * Generate a absolute--register MOVLPD. That is,
38698 * <PRE>
38699 * [dstDisp] <<= (quad) srcReg
38700 * </PRE>
38701 *
38702 * @param dstDisp the destination displacement
38703 * @param srcReg the source register
38704 */
38705 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={2})
38706 public final void emitMOVLPD_Abs_Reg(Address dstDisp, XMM srcReg) {
38707 int miStart = mi;
38708 setMachineCodes(mi++, (byte) 0x66);
38709 generateREXprefix(false, srcReg, null, null);
38710 setMachineCodes(mi++, (byte) 0x0F);
38711 setMachineCodes(mi++, (byte) 0x13);
38712 emitAbsRegOperands(dstDisp, srcReg);
38713 if (lister != null) lister.RAR(miStart, "MOVLPD", dstDisp, srcReg);
38714 }
38715
38716 /**
38717 * Generate a register-index--register MOVLPD. That is,
38718 * <PRE>
38719 * [dstBase + dstIndex<<dstScale + dstDisp] <<= (quad) srcReg
38720 * </PRE>
38721 *
38722 * @param dstBase the destination base register
38723 * @param dstIndex the destination index register
38724 * @param dstScale the destination shift amount
38725 * @param dstDisp the destination displacement
38726 * @param srcReg the source register
38727 */
38728 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,5})
38729 public final void emitMOVLPD_RegIdx_Reg(GPR dstBase, GPR dstIndex, short dstScale, Offset dstDisp, XMM srcReg) {
38730 int miStart = mi;
38731 setMachineCodes(mi++, (byte) 0x66);
38732 generateREXprefix(false, srcReg, dstIndex, dstBase);
38733 setMachineCodes(mi++, (byte) 0x0F);
38734 setMachineCodes(mi++, (byte) 0x13);
38735 emitSIBRegOperands(dstBase, dstIndex, dstScale, dstDisp, srcReg);
38736 if (lister != null) lister.RXDR(miStart, "MOVLPD", dstBase, dstIndex, dstScale, dstDisp, srcReg);
38737 }
38738
38739 /**
38740 * Generate a register-displacement--register MOVLPD. That is,
38741 * <PRE>
38742 * [dstBase + dstDisp] <<= (quad) srcReg
38743 * </PRE>
38744 *
38745 * @param dstBase the destination base register
38746 * @param dstDisp the destination displacement
38747 * @param srcReg the source register
38748 */
38749 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,3})
38750 public final void emitMOVLPD_RegDisp_Reg(GPR dstBase, Offset dstDisp, XMM srcReg) {
38751 int miStart = mi;
38752 setMachineCodes(mi++, (byte) 0x66);
38753 generateREXprefix(false, srcReg, null, dstBase);
38754 setMachineCodes(mi++, (byte) 0x0F);
38755 setMachineCodes(mi++, (byte) 0x13);
38756 emitRegDispRegOperands(dstBase, dstDisp, srcReg);
38757 if (lister != null) lister.RDR(miStart, "MOVLPD", dstBase, dstDisp, srcReg);
38758 }
38759
38760
38761 /**
38762 * Generate a register--register SQRTSD. That is,
38763 * <PRE>
38764 * dstReg <<= (quad) srcReg
38765 * </PRE>
38766 *
38767 * @param dstReg destination register
38768 * @param srcReg source register
38769 */
38770 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
38771 public final void emitSQRTSD_Reg_Reg(XMM dstReg, XMM srcReg) {
38772 int miStart = mi;
38773 setMachineCodes(mi++, (byte) 0xF2);
38774 generateREXprefix(false, dstReg, null, srcReg);
38775 setMachineCodes(mi++, (byte) 0x0F);
38776 setMachineCodes(mi++, (byte) 0x51);
38777 emitRegRegOperands(srcReg, dstReg);
38778 if (lister != null) lister.RR(miStart, "SQRTSD", dstReg, srcReg);
38779 }
38780
38781 /**
38782 * Generate a register--register-displacement SQRTSD. That is,
38783 * <PRE>
38784 * dstReg <<= (quad) [srcBase + srcDisp]
38785 * </PRE>
38786 *
38787 * @param dstReg destination register
38788 * @param srcBase the source base register
38789 * @param srcDisp the source displacement
38790 */
38791 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
38792 public final void emitSQRTSD_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
38793 int miStart = mi;
38794 setMachineCodes(mi++, (byte) 0xF2);
38795 generateREXprefix(false, dstReg, null, srcBase);
38796 setMachineCodes(mi++, (byte) 0x0F);
38797 setMachineCodes(mi++, (byte) 0x51);
38798 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
38799 if (lister != null) lister.RRD(miStart, "SQRTSD", dstReg, srcBase, srcDisp);
38800 }
38801
38802 /**
38803 * Generate a register--register-offset SQRTSD. That is,
38804 * <PRE>
38805 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
38806 * </PRE>
38807 *
38808 * @param dstReg destination register
38809 * @param srcIndex the source index register
38810 * @param srcScale the source scale
38811 * @param srcDisp the source displacement
38812 */
38813 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
38814 public final void emitSQRTSD_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
38815 int miStart = mi;
38816 setMachineCodes(mi++, (byte) 0xF2);
38817 generateREXprefix(false, dstReg, srcIndex, null);
38818 setMachineCodes(mi++, (byte) 0x0F);
38819 setMachineCodes(mi++, (byte) 0x51);
38820 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
38821 if (lister != null) lister.RRFD(miStart, "SQRTSD", dstReg, srcIndex, srcScale, srcDisp);
38822 }
38823
38824 /**
38825 * Generate a register--absolute SQRTSD. That is,
38826 * <PRE>
38827 * dstReg <<= (quad) [srcDisp]
38828 * </PRE>
38829 *
38830 * @param dstReg destination register
38831 * @param srcDisp the source displacement
38832 */
38833 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
38834 public final void emitSQRTSD_Reg_Abs(XMM dstReg, Address srcDisp) {
38835 int miStart = mi;
38836 setMachineCodes(mi++, (byte) 0xF2);
38837 generateREXprefix(false, dstReg, null, null);
38838 setMachineCodes(mi++, (byte) 0x0F);
38839 setMachineCodes(mi++, (byte) 0x51);
38840 emitAbsRegOperands(srcDisp, dstReg);
38841 if (lister != null) lister.RRA(miStart, "SQRTSD", dstReg, srcDisp);
38842 }
38843
38844 /**
38845 * Generate a register--register-index SQRTSD. That is,
38846 * <PRE>
38847 * dstReg <<= (quad) srcReg
38848 * </PRE>
38849 *
38850 * @param dstReg destination register
38851 * @param srcBase the source base register
38852 * @param srcIndex the source index register
38853 * @param srcScale the source scale
38854 * @param srcDisp the source displacement
38855 */
38856 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
38857 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
38858 public final void emitSQRTSD_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
38859 int miStart = mi;
38860 setMachineCodes(mi++, (byte) 0xF2);
38861 generateREXprefix(false, dstReg, srcIndex, srcBase);
38862 setMachineCodes(mi++, (byte) 0x0F);
38863 setMachineCodes(mi++, (byte) 0x51);
38864 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
38865 if (lister != null) lister.RRXD(miStart, "SQRTSD", dstReg, srcBase, srcIndex, srcScale, srcDisp);
38866 }
38867
38868 /**
38869 * Generate a register--register-indirect SQRTSD. That is,
38870 * <PRE>
38871 * dstReg <<= (quad) [srcBase]
38872 * </PRE>
38873 *
38874 * @param dstReg destination register
38875 * @param srcBase the source base register
38876 */
38877 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
38878 public final void emitSQRTSD_Reg_RegInd(XMM dstReg, GPR srcBase) {
38879 int miStart = mi;
38880 setMachineCodes(mi++, (byte) 0xF2);
38881 generateREXprefix(false, dstReg, null, srcBase);
38882 setMachineCodes(mi++, (byte) 0x0F);
38883 setMachineCodes(mi++, (byte) 0x51);
38884 emitRegIndirectRegOperands(srcBase, dstReg);
38885 if (lister != null) lister.RRN(miStart, "SQRTSD", dstReg, srcBase);
38886 }
38887
38888
38889 /**
38890 * Generate a register--register CVTSI2SD. That is,
38891 * <PRE>
38892 * dstReg <<= (quad) srcReg
38893 * </PRE>
38894 *
38895 * @param dstReg destination register
38896 * @param srcReg source register
38897 */
38898 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
38899 public final void emitCVTSI2SD_Reg_Reg(XMM dstReg, GPR srcReg) {
38900 int miStart = mi;
38901 setMachineCodes(mi++, (byte) 0xF2);
38902 generateREXprefix(false, dstReg, null, srcReg);
38903 setMachineCodes(mi++, (byte) 0x0F);
38904 setMachineCodes(mi++, (byte) 0x2A);
38905 emitRegRegOperands(srcReg, dstReg);
38906 if (lister != null) lister.RR(miStart, "CVTSI2SD", dstReg, srcReg);
38907 }
38908
38909 /**
38910 * Generate a register--register-displacement CVTSI2SD. That is,
38911 * <PRE>
38912 * dstReg <<= (quad) [srcBase + srcDisp]
38913 * </PRE>
38914 *
38915 * @param dstReg destination register
38916 * @param srcBase the source base register
38917 * @param srcDisp the source displacement
38918 */
38919 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
38920 public final void emitCVTSI2SD_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
38921 int miStart = mi;
38922 setMachineCodes(mi++, (byte) 0xF2);
38923 generateREXprefix(false, dstReg, null, srcBase);
38924 setMachineCodes(mi++, (byte) 0x0F);
38925 setMachineCodes(mi++, (byte) 0x2A);
38926 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
38927 if (lister != null) lister.RRD(miStart, "CVTSI2SD", dstReg, srcBase, srcDisp);
38928 }
38929
38930 /**
38931 * Generate a register--register-offset CVTSI2SD. That is,
38932 * <PRE>
38933 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
38934 * </PRE>
38935 *
38936 * @param dstReg destination register
38937 * @param srcIndex the source index register
38938 * @param srcScale the source scale
38939 * @param srcDisp the source displacement
38940 */
38941 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
38942 public final void emitCVTSI2SD_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
38943 int miStart = mi;
38944 setMachineCodes(mi++, (byte) 0xF2);
38945 generateREXprefix(false, dstReg, srcIndex, null);
38946 setMachineCodes(mi++, (byte) 0x0F);
38947 setMachineCodes(mi++, (byte) 0x2A);
38948 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
38949 if (lister != null) lister.RRFD(miStart, "CVTSI2SD", dstReg, srcIndex, srcScale, srcDisp);
38950 }
38951
38952 /**
38953 * Generate a register--absolute CVTSI2SD. That is,
38954 * <PRE>
38955 * dstReg <<= (quad) [srcDisp]
38956 * </PRE>
38957 *
38958 * @param dstReg destination register
38959 * @param srcDisp the source displacement
38960 */
38961 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
38962 public final void emitCVTSI2SD_Reg_Abs(XMM dstReg, Address srcDisp) {
38963 int miStart = mi;
38964 setMachineCodes(mi++, (byte) 0xF2);
38965 generateREXprefix(false, dstReg, null, null);
38966 setMachineCodes(mi++, (byte) 0x0F);
38967 setMachineCodes(mi++, (byte) 0x2A);
38968 emitAbsRegOperands(srcDisp, dstReg);
38969 if (lister != null) lister.RRA(miStart, "CVTSI2SD", dstReg, srcDisp);
38970 }
38971
38972 /**
38973 * Generate a register--register-index CVTSI2SD. That is,
38974 * <PRE>
38975 * dstReg <<= (quad) srcReg
38976 * </PRE>
38977 *
38978 * @param dstReg destination register
38979 * @param srcBase the source base register
38980 * @param srcIndex the source index register
38981 * @param srcScale the source scale
38982 * @param srcDisp the source displacement
38983 */
38984 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
38985 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
38986 public final void emitCVTSI2SD_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
38987 int miStart = mi;
38988 setMachineCodes(mi++, (byte) 0xF2);
38989 generateREXprefix(false, dstReg, srcIndex, srcBase);
38990 setMachineCodes(mi++, (byte) 0x0F);
38991 setMachineCodes(mi++, (byte) 0x2A);
38992 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
38993 if (lister != null) lister.RRXD(miStart, "CVTSI2SD", dstReg, srcBase, srcIndex, srcScale, srcDisp);
38994 }
38995
38996 /**
38997 * Generate a register--register-indirect CVTSI2SD. That is,
38998 * <PRE>
38999 * dstReg <<= (quad) [srcBase]
39000 * </PRE>
39001 *
39002 * @param dstReg destination register
39003 * @param srcBase the source base register
39004 */
39005 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
39006 public final void emitCVTSI2SD_Reg_RegInd(XMM dstReg, GPR srcBase) {
39007 int miStart = mi;
39008 setMachineCodes(mi++, (byte) 0xF2);
39009 generateREXprefix(false, dstReg, null, srcBase);
39010 setMachineCodes(mi++, (byte) 0x0F);
39011 setMachineCodes(mi++, (byte) 0x2A);
39012 emitRegIndirectRegOperands(srcBase, dstReg);
39013 if (lister != null) lister.RRN(miStart, "CVTSI2SD", dstReg, srcBase);
39014 }
39015
39016
39017 /**
39018 * Generate a register--register CVTSD2SS. That is,
39019 * <PRE>
39020 * dstReg <<= (quad) srcReg
39021 * </PRE>
39022 *
39023 * @param dstReg destination register
39024 * @param srcReg source register
39025 */
39026 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
39027 public final void emitCVTSD2SS_Reg_Reg(XMM dstReg, XMM srcReg) {
39028 int miStart = mi;
39029 setMachineCodes(mi++, (byte) 0xF2);
39030 generateREXprefix(false, dstReg, null, srcReg);
39031 setMachineCodes(mi++, (byte) 0x0F);
39032 setMachineCodes(mi++, (byte) 0x5A);
39033 emitRegRegOperands(srcReg, dstReg);
39034 if (lister != null) lister.RR(miStart, "CVTSD2SS", dstReg, srcReg);
39035 }
39036
39037 /**
39038 * Generate a register--register-displacement CVTSD2SS. That is,
39039 * <PRE>
39040 * dstReg <<= (quad) [srcBase + srcDisp]
39041 * </PRE>
39042 *
39043 * @param dstReg destination register
39044 * @param srcBase the source base register
39045 * @param srcDisp the source displacement
39046 */
39047 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
39048 public final void emitCVTSD2SS_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
39049 int miStart = mi;
39050 setMachineCodes(mi++, (byte) 0xF2);
39051 generateREXprefix(false, dstReg, null, srcBase);
39052 setMachineCodes(mi++, (byte) 0x0F);
39053 setMachineCodes(mi++, (byte) 0x5A);
39054 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
39055 if (lister != null) lister.RRD(miStart, "CVTSD2SS", dstReg, srcBase, srcDisp);
39056 }
39057
39058 /**
39059 * Generate a register--register-offset CVTSD2SS. That is,
39060 * <PRE>
39061 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
39062 * </PRE>
39063 *
39064 * @param dstReg destination register
39065 * @param srcIndex the source index register
39066 * @param srcScale the source scale
39067 * @param srcDisp the source displacement
39068 */
39069 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
39070 public final void emitCVTSD2SS_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
39071 int miStart = mi;
39072 setMachineCodes(mi++, (byte) 0xF2);
39073 generateREXprefix(false, dstReg, srcIndex, null);
39074 setMachineCodes(mi++, (byte) 0x0F);
39075 setMachineCodes(mi++, (byte) 0x5A);
39076 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
39077 if (lister != null) lister.RRFD(miStart, "CVTSD2SS", dstReg, srcIndex, srcScale, srcDisp);
39078 }
39079
39080 /**
39081 * Generate a register--absolute CVTSD2SS. That is,
39082 * <PRE>
39083 * dstReg <<= (quad) [srcDisp]
39084 * </PRE>
39085 *
39086 * @param dstReg destination register
39087 * @param srcDisp the source displacement
39088 */
39089 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
39090 public final void emitCVTSD2SS_Reg_Abs(XMM dstReg, Address srcDisp) {
39091 int miStart = mi;
39092 setMachineCodes(mi++, (byte) 0xF2);
39093 generateREXprefix(false, dstReg, null, null);
39094 setMachineCodes(mi++, (byte) 0x0F);
39095 setMachineCodes(mi++, (byte) 0x5A);
39096 emitAbsRegOperands(srcDisp, dstReg);
39097 if (lister != null) lister.RRA(miStart, "CVTSD2SS", dstReg, srcDisp);
39098 }
39099
39100 /**
39101 * Generate a register--register-index CVTSD2SS. That is,
39102 * <PRE>
39103 * dstReg <<= (quad) srcReg
39104 * </PRE>
39105 *
39106 * @param dstReg destination register
39107 * @param srcBase the source base register
39108 * @param srcIndex the source index register
39109 * @param srcScale the source scale
39110 * @param srcDisp the source displacement
39111 */
39112 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
39113 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
39114 public final void emitCVTSD2SS_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
39115 int miStart = mi;
39116 setMachineCodes(mi++, (byte) 0xF2);
39117 generateREXprefix(false, dstReg, srcIndex, srcBase);
39118 setMachineCodes(mi++, (byte) 0x0F);
39119 setMachineCodes(mi++, (byte) 0x5A);
39120 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
39121 if (lister != null) lister.RRXD(miStart, "CVTSD2SS", dstReg, srcBase, srcIndex, srcScale, srcDisp);
39122 }
39123
39124 /**
39125 * Generate a register--register-indirect CVTSD2SS. That is,
39126 * <PRE>
39127 * dstReg <<= (quad) [srcBase]
39128 * </PRE>
39129 *
39130 * @param dstReg destination register
39131 * @param srcBase the source base register
39132 */
39133 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
39134 public final void emitCVTSD2SS_Reg_RegInd(XMM dstReg, GPR srcBase) {
39135 int miStart = mi;
39136 setMachineCodes(mi++, (byte) 0xF2);
39137 generateREXprefix(false, dstReg, null, srcBase);
39138 setMachineCodes(mi++, (byte) 0x0F);
39139 setMachineCodes(mi++, (byte) 0x5A);
39140 emitRegIndirectRegOperands(srcBase, dstReg);
39141 if (lister != null) lister.RRN(miStart, "CVTSD2SS", dstReg, srcBase);
39142 }
39143
39144
39145 /**
39146 * Generate a register--register CVTSD2SI. That is,
39147 * <PRE>
39148 * dstReg <<= (quad) srcReg
39149 * </PRE>
39150 *
39151 * @param dstReg destination register
39152 * @param srcReg source register
39153 */
39154 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
39155 public final void emitCVTSD2SI_Reg_Reg(GPR dstReg, XMM srcReg) {
39156 int miStart = mi;
39157 setMachineCodes(mi++, (byte) 0xF2);
39158 generateREXprefix(false, dstReg, null, srcReg);
39159 setMachineCodes(mi++, (byte) 0x0F);
39160 setMachineCodes(mi++, (byte) 0x2D);
39161 emitRegRegOperands(srcReg, dstReg);
39162 if (lister != null) lister.RR(miStart, "CVTSD2SI", dstReg, srcReg);
39163 }
39164
39165 /**
39166 * Generate a register--register-displacement CVTSD2SI. That is,
39167 * <PRE>
39168 * dstReg <<= (quad) [srcBase + srcDisp]
39169 * </PRE>
39170 *
39171 * @param dstReg destination register
39172 * @param srcBase the source base register
39173 * @param srcDisp the source displacement
39174 */
39175 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
39176 public final void emitCVTSD2SI_Reg_RegDisp(GPR dstReg, GPR srcBase, Offset srcDisp) {
39177 int miStart = mi;
39178 setMachineCodes(mi++, (byte) 0xF2);
39179 generateREXprefix(false, dstReg, null, srcBase);
39180 setMachineCodes(mi++, (byte) 0x0F);
39181 setMachineCodes(mi++, (byte) 0x2D);
39182 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
39183 if (lister != null) lister.RRD(miStart, "CVTSD2SI", dstReg, srcBase, srcDisp);
39184 }
39185
39186 /**
39187 * Generate a register--register-offset CVTSD2SI. That is,
39188 * <PRE>
39189 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
39190 * </PRE>
39191 *
39192 * @param dstReg destination register
39193 * @param srcIndex the source index register
39194 * @param srcScale the source scale
39195 * @param srcDisp the source displacement
39196 */
39197 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
39198 public final void emitCVTSD2SI_Reg_RegOff(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
39199 int miStart = mi;
39200 setMachineCodes(mi++, (byte) 0xF2);
39201 generateREXprefix(false, dstReg, srcIndex, null);
39202 setMachineCodes(mi++, (byte) 0x0F);
39203 setMachineCodes(mi++, (byte) 0x2D);
39204 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
39205 if (lister != null) lister.RRFD(miStart, "CVTSD2SI", dstReg, srcIndex, srcScale, srcDisp);
39206 }
39207
39208 /**
39209 * Generate a register--absolute CVTSD2SI. That is,
39210 * <PRE>
39211 * dstReg <<= (quad) [srcDisp]
39212 * </PRE>
39213 *
39214 * @param dstReg destination register
39215 * @param srcDisp the source displacement
39216 */
39217 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
39218 public final void emitCVTSD2SI_Reg_Abs(GPR dstReg, Address srcDisp) {
39219 int miStart = mi;
39220 setMachineCodes(mi++, (byte) 0xF2);
39221 generateREXprefix(false, dstReg, null, null);
39222 setMachineCodes(mi++, (byte) 0x0F);
39223 setMachineCodes(mi++, (byte) 0x2D);
39224 emitAbsRegOperands(srcDisp, dstReg);
39225 if (lister != null) lister.RRA(miStart, "CVTSD2SI", dstReg, srcDisp);
39226 }
39227
39228 /**
39229 * Generate a register--register-index CVTSD2SI. That is,
39230 * <PRE>
39231 * dstReg <<= (quad) srcReg
39232 * </PRE>
39233 *
39234 * @param dstReg destination register
39235 * @param srcBase the source base register
39236 * @param srcIndex the source index register
39237 * @param srcScale the source scale
39238 * @param srcDisp the source displacement
39239 */
39240 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
39241 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
39242 public final void emitCVTSD2SI_Reg_RegIdx(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
39243 int miStart = mi;
39244 setMachineCodes(mi++, (byte) 0xF2);
39245 generateREXprefix(false, dstReg, srcIndex, srcBase);
39246 setMachineCodes(mi++, (byte) 0x0F);
39247 setMachineCodes(mi++, (byte) 0x2D);
39248 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
39249 if (lister != null) lister.RRXD(miStart, "CVTSD2SI", dstReg, srcBase, srcIndex, srcScale, srcDisp);
39250 }
39251
39252 /**
39253 * Generate a register--register-indirect CVTSD2SI. That is,
39254 * <PRE>
39255 * dstReg <<= (quad) [srcBase]
39256 * </PRE>
39257 *
39258 * @param dstReg destination register
39259 * @param srcBase the source base register
39260 */
39261 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
39262 public final void emitCVTSD2SI_Reg_RegInd(GPR dstReg, GPR srcBase) {
39263 int miStart = mi;
39264 setMachineCodes(mi++, (byte) 0xF2);
39265 generateREXprefix(false, dstReg, null, srcBase);
39266 setMachineCodes(mi++, (byte) 0x0F);
39267 setMachineCodes(mi++, (byte) 0x2D);
39268 emitRegIndirectRegOperands(srcBase, dstReg);
39269 if (lister != null) lister.RRN(miStart, "CVTSD2SI", dstReg, srcBase);
39270 }
39271
39272
39273 /**
39274 * Generate a register--register CVTTSD2SI. That is,
39275 * <PRE>
39276 * dstReg <<= (quad) srcReg
39277 * </PRE>
39278 *
39279 * @param dstReg destination register
39280 * @param srcReg source register
39281 */
39282 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
39283 public final void emitCVTTSD2SI_Reg_Reg(GPR dstReg, XMM srcReg) {
39284 int miStart = mi;
39285 setMachineCodes(mi++, (byte) 0xF2);
39286 generateREXprefix(false, dstReg, null, srcReg);
39287 setMachineCodes(mi++, (byte) 0x0F);
39288 setMachineCodes(mi++, (byte) 0x2C);
39289 emitRegRegOperands(srcReg, dstReg);
39290 if (lister != null) lister.RR(miStart, "CVTTSD2SI", dstReg, srcReg);
39291 }
39292
39293 /**
39294 * Generate a register--register-displacement CVTTSD2SI. That is,
39295 * <PRE>
39296 * dstReg <<= (quad) [srcBase + srcDisp]
39297 * </PRE>
39298 *
39299 * @param dstReg destination register
39300 * @param srcBase the source base register
39301 * @param srcDisp the source displacement
39302 */
39303 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
39304 public final void emitCVTTSD2SI_Reg_RegDisp(GPR dstReg, GPR srcBase, Offset srcDisp) {
39305 int miStart = mi;
39306 setMachineCodes(mi++, (byte) 0xF2);
39307 generateREXprefix(false, dstReg, null, srcBase);
39308 setMachineCodes(mi++, (byte) 0x0F);
39309 setMachineCodes(mi++, (byte) 0x2C);
39310 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
39311 if (lister != null) lister.RRD(miStart, "CVTTSD2SI", dstReg, srcBase, srcDisp);
39312 }
39313
39314 /**
39315 * Generate a register--register-offset CVTTSD2SI. That is,
39316 * <PRE>
39317 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
39318 * </PRE>
39319 *
39320 * @param dstReg destination register
39321 * @param srcIndex the source index register
39322 * @param srcScale the source scale
39323 * @param srcDisp the source displacement
39324 */
39325 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
39326 public final void emitCVTTSD2SI_Reg_RegOff(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
39327 int miStart = mi;
39328 setMachineCodes(mi++, (byte) 0xF2);
39329 generateREXprefix(false, dstReg, srcIndex, null);
39330 setMachineCodes(mi++, (byte) 0x0F);
39331 setMachineCodes(mi++, (byte) 0x2C);
39332 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
39333 if (lister != null) lister.RRFD(miStart, "CVTTSD2SI", dstReg, srcIndex, srcScale, srcDisp);
39334 }
39335
39336 /**
39337 * Generate a register--absolute CVTTSD2SI. That is,
39338 * <PRE>
39339 * dstReg <<= (quad) [srcDisp]
39340 * </PRE>
39341 *
39342 * @param dstReg destination register
39343 * @param srcDisp the source displacement
39344 */
39345 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
39346 public final void emitCVTTSD2SI_Reg_Abs(GPR dstReg, Address srcDisp) {
39347 int miStart = mi;
39348 setMachineCodes(mi++, (byte) 0xF2);
39349 generateREXprefix(false, dstReg, null, null);
39350 setMachineCodes(mi++, (byte) 0x0F);
39351 setMachineCodes(mi++, (byte) 0x2C);
39352 emitAbsRegOperands(srcDisp, dstReg);
39353 if (lister != null) lister.RRA(miStart, "CVTTSD2SI", dstReg, srcDisp);
39354 }
39355
39356 /**
39357 * Generate a register--register-index CVTTSD2SI. That is,
39358 * <PRE>
39359 * dstReg <<= (quad) srcReg
39360 * </PRE>
39361 *
39362 * @param dstReg destination register
39363 * @param srcBase the source base register
39364 * @param srcIndex the source index register
39365 * @param srcScale the source scale
39366 * @param srcDisp the source displacement
39367 */
39368 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
39369 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
39370 public final void emitCVTTSD2SI_Reg_RegIdx(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
39371 int miStart = mi;
39372 setMachineCodes(mi++, (byte) 0xF2);
39373 generateREXprefix(false, dstReg, srcIndex, srcBase);
39374 setMachineCodes(mi++, (byte) 0x0F);
39375 setMachineCodes(mi++, (byte) 0x2C);
39376 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
39377 if (lister != null) lister.RRXD(miStart, "CVTTSD2SI", dstReg, srcBase, srcIndex, srcScale, srcDisp);
39378 }
39379
39380 /**
39381 * Generate a register--register-indirect CVTTSD2SI. That is,
39382 * <PRE>
39383 * dstReg <<= (quad) [srcBase]
39384 * </PRE>
39385 *
39386 * @param dstReg destination register
39387 * @param srcBase the source base register
39388 */
39389 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
39390 public final void emitCVTTSD2SI_Reg_RegInd(GPR dstReg, GPR srcBase) {
39391 int miStart = mi;
39392 setMachineCodes(mi++, (byte) 0xF2);
39393 generateREXprefix(false, dstReg, null, srcBase);
39394 setMachineCodes(mi++, (byte) 0x0F);
39395 setMachineCodes(mi++, (byte) 0x2C);
39396 emitRegIndirectRegOperands(srcBase, dstReg);
39397 if (lister != null) lister.RRN(miStart, "CVTTSD2SI", dstReg, srcBase);
39398 }
39399
39400
39401 /**
39402 * Generate a register--register CVTSI2SDQ. That is,
39403 * <PRE>
39404 * dstReg <<= (quad) srcReg
39405 * </PRE>
39406 *
39407 * @param dstReg destination register
39408 * @param srcReg source register
39409 */
39410 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
39411 public final void emitCVTSI2SDQ_Reg_Reg_Quad(XMM dstReg, GPR srcReg) {
39412 int miStart = mi;
39413 setMachineCodes(mi++, (byte) 0xF2);
39414 generateREXprefix(true, dstReg, null, srcReg);
39415 setMachineCodes(mi++, (byte) 0x0F);
39416 setMachineCodes(mi++, (byte) 0x2A);
39417 emitRegRegOperands(srcReg, dstReg);
39418 if (lister != null) lister.RR(miStart, "CVTSI2SDQ", dstReg, srcReg);
39419 }
39420
39421 /**
39422 * Generate a register--register-displacement CVTSI2SDQ. That is,
39423 * <PRE>
39424 * dstReg <<= (quad) [srcBase + srcDisp]
39425 * </PRE>
39426 *
39427 * @param dstReg destination register
39428 * @param srcBase the source base register
39429 * @param srcDisp the source displacement
39430 */
39431 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
39432 public final void emitCVTSI2SDQ_Reg_RegDisp_Quad(XMM dstReg, GPR srcBase, Offset srcDisp) {
39433 int miStart = mi;
39434 setMachineCodes(mi++, (byte) 0xF2);
39435 generateREXprefix(true, dstReg, null, srcBase);
39436 setMachineCodes(mi++, (byte) 0x0F);
39437 setMachineCodes(mi++, (byte) 0x2A);
39438 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
39439 if (lister != null) lister.RRD(miStart, "CVTSI2SDQ", dstReg, srcBase, srcDisp);
39440 }
39441
39442 /**
39443 * Generate a register--register-offset CVTSI2SDQ. That is,
39444 * <PRE>
39445 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
39446 * </PRE>
39447 *
39448 * @param dstReg destination register
39449 * @param srcIndex the source index register
39450 * @param srcScale the source scale
39451 * @param srcDisp the source displacement
39452 */
39453 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
39454 public final void emitCVTSI2SDQ_Reg_RegOff_Quad(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
39455 int miStart = mi;
39456 setMachineCodes(mi++, (byte) 0xF2);
39457 generateREXprefix(true, dstReg, srcIndex, null);
39458 setMachineCodes(mi++, (byte) 0x0F);
39459 setMachineCodes(mi++, (byte) 0x2A);
39460 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
39461 if (lister != null) lister.RRFD(miStart, "CVTSI2SDQ", dstReg, srcIndex, srcScale, srcDisp);
39462 }
39463
39464 /**
39465 * Generate a register--absolute CVTSI2SDQ. That is,
39466 * <PRE>
39467 * dstReg <<= (quad) [srcDisp]
39468 * </PRE>
39469 *
39470 * @param dstReg destination register
39471 * @param srcDisp the source displacement
39472 */
39473 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
39474 public final void emitCVTSI2SDQ_Reg_Abs_Quad(XMM dstReg, Address srcDisp) {
39475 int miStart = mi;
39476 setMachineCodes(mi++, (byte) 0xF2);
39477 generateREXprefix(true, dstReg, null, null);
39478 setMachineCodes(mi++, (byte) 0x0F);
39479 setMachineCodes(mi++, (byte) 0x2A);
39480 emitAbsRegOperands(srcDisp, dstReg);
39481 if (lister != null) lister.RRA(miStart, "CVTSI2SDQ", dstReg, srcDisp);
39482 }
39483
39484 /**
39485 * Generate a register--register-index CVTSI2SDQ. That is,
39486 * <PRE>
39487 * dstReg <<= (quad) srcReg
39488 * </PRE>
39489 *
39490 * @param dstReg destination register
39491 * @param srcBase the source base register
39492 * @param srcIndex the source index register
39493 * @param srcScale the source scale
39494 * @param srcDisp the source displacement
39495 */
39496 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
39497 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
39498 public final void emitCVTSI2SDQ_Reg_RegIdx_Quad(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
39499 int miStart = mi;
39500 setMachineCodes(mi++, (byte) 0xF2);
39501 generateREXprefix(true, dstReg, srcIndex, srcBase);
39502 setMachineCodes(mi++, (byte) 0x0F);
39503 setMachineCodes(mi++, (byte) 0x2A);
39504 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
39505 if (lister != null) lister.RRXD(miStart, "CVTSI2SDQ", dstReg, srcBase, srcIndex, srcScale, srcDisp);
39506 }
39507
39508 /**
39509 * Generate a register--register-indirect CVTSI2SDQ. That is,
39510 * <PRE>
39511 * dstReg <<= (quad) [srcBase]
39512 * </PRE>
39513 *
39514 * @param dstReg destination register
39515 * @param srcBase the source base register
39516 */
39517 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
39518 public final void emitCVTSI2SDQ_Reg_RegInd_Quad(XMM dstReg, GPR srcBase) {
39519 int miStart = mi;
39520 setMachineCodes(mi++, (byte) 0xF2);
39521 generateREXprefix(true, dstReg, null, srcBase);
39522 setMachineCodes(mi++, (byte) 0x0F);
39523 setMachineCodes(mi++, (byte) 0x2A);
39524 emitRegIndirectRegOperands(srcBase, dstReg);
39525 if (lister != null) lister.RRN(miStart, "CVTSI2SDQ", dstReg, srcBase);
39526 }
39527
39528
39529 /**
39530 * Generate a register--register CVTSD2SIQ. That is,
39531 * <PRE>
39532 * dstReg <<= (quad) srcReg
39533 * </PRE>
39534 *
39535 * @param dstReg destination register
39536 * @param srcReg source register
39537 */
39538 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
39539 public final void emitCVTSD2SIQ_Reg_Reg_Quad(GPR dstReg, XMM srcReg) {
39540 int miStart = mi;
39541 setMachineCodes(mi++, (byte) 0xF2);
39542 generateREXprefix(true, dstReg, null, srcReg);
39543 setMachineCodes(mi++, (byte) 0x0F);
39544 setMachineCodes(mi++, (byte) 0x2D);
39545 emitRegRegOperands(srcReg, dstReg);
39546 if (lister != null) lister.RR(miStart, "CVTSD2SIQ", dstReg, srcReg);
39547 }
39548
39549 /**
39550 * Generate a register--register-displacement CVTSD2SIQ. That is,
39551 * <PRE>
39552 * dstReg <<= (quad) [srcBase + srcDisp]
39553 * </PRE>
39554 *
39555 * @param dstReg destination register
39556 * @param srcBase the source base register
39557 * @param srcDisp the source displacement
39558 */
39559 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
39560 public final void emitCVTSD2SIQ_Reg_RegDisp_Quad(GPR dstReg, GPR srcBase, Offset srcDisp) {
39561 int miStart = mi;
39562 setMachineCodes(mi++, (byte) 0xF2);
39563 generateREXprefix(true, dstReg, null, srcBase);
39564 setMachineCodes(mi++, (byte) 0x0F);
39565 setMachineCodes(mi++, (byte) 0x2D);
39566 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
39567 if (lister != null) lister.RRD(miStart, "CVTSD2SIQ", dstReg, srcBase, srcDisp);
39568 }
39569
39570 /**
39571 * Generate a register--register-offset CVTSD2SIQ. That is,
39572 * <PRE>
39573 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
39574 * </PRE>
39575 *
39576 * @param dstReg destination register
39577 * @param srcIndex the source index register
39578 * @param srcScale the source scale
39579 * @param srcDisp the source displacement
39580 */
39581 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
39582 public final void emitCVTSD2SIQ_Reg_RegOff_Quad(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
39583 int miStart = mi;
39584 setMachineCodes(mi++, (byte) 0xF2);
39585 generateREXprefix(true, dstReg, srcIndex, null);
39586 setMachineCodes(mi++, (byte) 0x0F);
39587 setMachineCodes(mi++, (byte) 0x2D);
39588 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
39589 if (lister != null) lister.RRFD(miStart, "CVTSD2SIQ", dstReg, srcIndex, srcScale, srcDisp);
39590 }
39591
39592 /**
39593 * Generate a register--absolute CVTSD2SIQ. That is,
39594 * <PRE>
39595 * dstReg <<= (quad) [srcDisp]
39596 * </PRE>
39597 *
39598 * @param dstReg destination register
39599 * @param srcDisp the source displacement
39600 */
39601 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
39602 public final void emitCVTSD2SIQ_Reg_Abs_Quad(GPR dstReg, Address srcDisp) {
39603 int miStart = mi;
39604 setMachineCodes(mi++, (byte) 0xF2);
39605 generateREXprefix(true, dstReg, null, null);
39606 setMachineCodes(mi++, (byte) 0x0F);
39607 setMachineCodes(mi++, (byte) 0x2D);
39608 emitAbsRegOperands(srcDisp, dstReg);
39609 if (lister != null) lister.RRA(miStart, "CVTSD2SIQ", dstReg, srcDisp);
39610 }
39611
39612 /**
39613 * Generate a register--register-index CVTSD2SIQ. That is,
39614 * <PRE>
39615 * dstReg <<= (quad) srcReg
39616 * </PRE>
39617 *
39618 * @param dstReg destination register
39619 * @param srcBase the source base register
39620 * @param srcIndex the source index register
39621 * @param srcScale the source scale
39622 * @param srcDisp the source displacement
39623 */
39624 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
39625 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
39626 public final void emitCVTSD2SIQ_Reg_RegIdx_Quad(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
39627 int miStart = mi;
39628 setMachineCodes(mi++, (byte) 0xF2);
39629 generateREXprefix(true, dstReg, srcIndex, srcBase);
39630 setMachineCodes(mi++, (byte) 0x0F);
39631 setMachineCodes(mi++, (byte) 0x2D);
39632 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
39633 if (lister != null) lister.RRXD(miStart, "CVTSD2SIQ", dstReg, srcBase, srcIndex, srcScale, srcDisp);
39634 }
39635
39636 /**
39637 * Generate a register--register-indirect CVTSD2SIQ. That is,
39638 * <PRE>
39639 * dstReg <<= (quad) [srcBase]
39640 * </PRE>
39641 *
39642 * @param dstReg destination register
39643 * @param srcBase the source base register
39644 */
39645 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
39646 public final void emitCVTSD2SIQ_Reg_RegInd_Quad(GPR dstReg, GPR srcBase) {
39647 int miStart = mi;
39648 setMachineCodes(mi++, (byte) 0xF2);
39649 generateREXprefix(true, dstReg, null, srcBase);
39650 setMachineCodes(mi++, (byte) 0x0F);
39651 setMachineCodes(mi++, (byte) 0x2D);
39652 emitRegIndirectRegOperands(srcBase, dstReg);
39653 if (lister != null) lister.RRN(miStart, "CVTSD2SIQ", dstReg, srcBase);
39654 }
39655
39656
39657 /**
39658 * Generate a register--register CVTTSD2SIQ. That is,
39659 * <PRE>
39660 * dstReg <<= (quad) srcReg
39661 * </PRE>
39662 *
39663 * @param dstReg destination register
39664 * @param srcReg source register
39665 */
39666 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
39667 public final void emitCVTTSD2SIQ_Reg_Reg_Quad(GPR dstReg, XMM srcReg) {
39668 int miStart = mi;
39669 setMachineCodes(mi++, (byte) 0xF2);
39670 generateREXprefix(true, dstReg, null, srcReg);
39671 setMachineCodes(mi++, (byte) 0x0F);
39672 setMachineCodes(mi++, (byte) 0x2C);
39673 emitRegRegOperands(srcReg, dstReg);
39674 if (lister != null) lister.RR(miStart, "CVTTSD2SIQ", dstReg, srcReg);
39675 }
39676
39677 /**
39678 * Generate a register--register-displacement CVTTSD2SIQ. That is,
39679 * <PRE>
39680 * dstReg <<= (quad) [srcBase + srcDisp]
39681 * </PRE>
39682 *
39683 * @param dstReg destination register
39684 * @param srcBase the source base register
39685 * @param srcDisp the source displacement
39686 */
39687 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
39688 public final void emitCVTTSD2SIQ_Reg_RegDisp_Quad(GPR dstReg, GPR srcBase, Offset srcDisp) {
39689 int miStart = mi;
39690 setMachineCodes(mi++, (byte) 0xF2);
39691 generateREXprefix(true, dstReg, null, srcBase);
39692 setMachineCodes(mi++, (byte) 0x0F);
39693 setMachineCodes(mi++, (byte) 0x2C);
39694 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
39695 if (lister != null) lister.RRD(miStart, "CVTTSD2SIQ", dstReg, srcBase, srcDisp);
39696 }
39697
39698 /**
39699 * Generate a register--register-offset CVTTSD2SIQ. That is,
39700 * <PRE>
39701 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
39702 * </PRE>
39703 *
39704 * @param dstReg destination register
39705 * @param srcIndex the source index register
39706 * @param srcScale the source scale
39707 * @param srcDisp the source displacement
39708 */
39709 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
39710 public final void emitCVTTSD2SIQ_Reg_RegOff_Quad(GPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
39711 int miStart = mi;
39712 setMachineCodes(mi++, (byte) 0xF2);
39713 generateREXprefix(true, dstReg, srcIndex, null);
39714 setMachineCodes(mi++, (byte) 0x0F);
39715 setMachineCodes(mi++, (byte) 0x2C);
39716 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
39717 if (lister != null) lister.RRFD(miStart, "CVTTSD2SIQ", dstReg, srcIndex, srcScale, srcDisp);
39718 }
39719
39720 /**
39721 * Generate a register--absolute CVTTSD2SIQ. That is,
39722 * <PRE>
39723 * dstReg <<= (quad) [srcDisp]
39724 * </PRE>
39725 *
39726 * @param dstReg destination register
39727 * @param srcDisp the source displacement
39728 */
39729 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
39730 public final void emitCVTTSD2SIQ_Reg_Abs_Quad(GPR dstReg, Address srcDisp) {
39731 int miStart = mi;
39732 setMachineCodes(mi++, (byte) 0xF2);
39733 generateREXprefix(true, dstReg, null, null);
39734 setMachineCodes(mi++, (byte) 0x0F);
39735 setMachineCodes(mi++, (byte) 0x2C);
39736 emitAbsRegOperands(srcDisp, dstReg);
39737 if (lister != null) lister.RRA(miStart, "CVTTSD2SIQ", dstReg, srcDisp);
39738 }
39739
39740 /**
39741 * Generate a register--register-index CVTTSD2SIQ. That is,
39742 * <PRE>
39743 * dstReg <<= (quad) srcReg
39744 * </PRE>
39745 *
39746 * @param dstReg destination register
39747 * @param srcBase the source base register
39748 * @param srcIndex the source index register
39749 * @param srcScale the source scale
39750 * @param srcDisp the source displacement
39751 */
39752 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
39753 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
39754 public final void emitCVTTSD2SIQ_Reg_RegIdx_Quad(GPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
39755 int miStart = mi;
39756 setMachineCodes(mi++, (byte) 0xF2);
39757 generateREXprefix(true, dstReg, srcIndex, srcBase);
39758 setMachineCodes(mi++, (byte) 0x0F);
39759 setMachineCodes(mi++, (byte) 0x2C);
39760 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
39761 if (lister != null) lister.RRXD(miStart, "CVTTSD2SIQ", dstReg, srcBase, srcIndex, srcScale, srcDisp);
39762 }
39763
39764 /**
39765 * Generate a register--register-indirect CVTTSD2SIQ. That is,
39766 * <PRE>
39767 * dstReg <<= (quad) [srcBase]
39768 * </PRE>
39769 *
39770 * @param dstReg destination register
39771 * @param srcBase the source base register
39772 */
39773 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
39774 public final void emitCVTTSD2SIQ_Reg_RegInd_Quad(GPR dstReg, GPR srcBase) {
39775 int miStart = mi;
39776 setMachineCodes(mi++, (byte) 0xF2);
39777 generateREXprefix(true, dstReg, null, srcBase);
39778 setMachineCodes(mi++, (byte) 0x0F);
39779 setMachineCodes(mi++, (byte) 0x2C);
39780 emitRegIndirectRegOperands(srcBase, dstReg);
39781 if (lister != null) lister.RRN(miStart, "CVTTSD2SIQ", dstReg, srcBase);
39782 }
39783
39784
39785 /**
39786 * Generate a register--register UCOMISD. That is,
39787 * <PRE>
39788 * dstReg <<= (quad) srcReg
39789 * </PRE>
39790 *
39791 * @param dstReg destination register
39792 * @param srcReg source register
39793 */
39794 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
39795 public final void emitUCOMISD_Reg_Reg(XMM dstReg, XMM srcReg) {
39796 int miStart = mi;
39797 setMachineCodes(mi++, (byte) 0x66);
39798 generateREXprefix(false, dstReg, null, srcReg);
39799 setMachineCodes(mi++, (byte) 0x0F);
39800 setMachineCodes(mi++, (byte) 0x2E);
39801 emitRegRegOperands(srcReg, dstReg);
39802 if (lister != null) lister.RR(miStart, "UCOMISD", dstReg, srcReg);
39803 }
39804
39805 /**
39806 * Generate a register--register-displacement UCOMISD. That is,
39807 * <PRE>
39808 * dstReg <<= (quad) [srcBase + srcDisp]
39809 * </PRE>
39810 *
39811 * @param dstReg destination register
39812 * @param srcBase the source base register
39813 * @param srcDisp the source displacement
39814 */
39815 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
39816 public final void emitUCOMISD_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
39817 int miStart = mi;
39818 setMachineCodes(mi++, (byte) 0x66);
39819 generateREXprefix(false, dstReg, null, srcBase);
39820 setMachineCodes(mi++, (byte) 0x0F);
39821 setMachineCodes(mi++, (byte) 0x2E);
39822 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
39823 if (lister != null) lister.RRD(miStart, "UCOMISD", dstReg, srcBase, srcDisp);
39824 }
39825
39826 /**
39827 * Generate a register--register-offset UCOMISD. That is,
39828 * <PRE>
39829 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
39830 * </PRE>
39831 *
39832 * @param dstReg destination register
39833 * @param srcIndex the source index register
39834 * @param srcScale the source scale
39835 * @param srcDisp the source displacement
39836 */
39837 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
39838 public final void emitUCOMISD_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
39839 int miStart = mi;
39840 setMachineCodes(mi++, (byte) 0x66);
39841 generateREXprefix(false, dstReg, srcIndex, null);
39842 setMachineCodes(mi++, (byte) 0x0F);
39843 setMachineCodes(mi++, (byte) 0x2E);
39844 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
39845 if (lister != null) lister.RRFD(miStart, "UCOMISD", dstReg, srcIndex, srcScale, srcDisp);
39846 }
39847
39848 /**
39849 * Generate a register--absolute UCOMISD. That is,
39850 * <PRE>
39851 * dstReg <<= (quad) [srcDisp]
39852 * </PRE>
39853 *
39854 * @param dstReg destination register
39855 * @param srcDisp the source displacement
39856 */
39857 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
39858 public final void emitUCOMISD_Reg_Abs(XMM dstReg, Address srcDisp) {
39859 int miStart = mi;
39860 setMachineCodes(mi++, (byte) 0x66);
39861 generateREXprefix(false, dstReg, null, null);
39862 setMachineCodes(mi++, (byte) 0x0F);
39863 setMachineCodes(mi++, (byte) 0x2E);
39864 emitAbsRegOperands(srcDisp, dstReg);
39865 if (lister != null) lister.RRA(miStart, "UCOMISD", dstReg, srcDisp);
39866 }
39867
39868 /**
39869 * Generate a register--register-index UCOMISD. That is,
39870 * <PRE>
39871 * dstReg <<= (quad) srcReg
39872 * </PRE>
39873 *
39874 * @param dstReg destination register
39875 * @param srcBase the source base register
39876 * @param srcIndex the source index register
39877 * @param srcScale the source scale
39878 * @param srcDisp the source displacement
39879 */
39880 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
39881 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
39882 public final void emitUCOMISD_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
39883 int miStart = mi;
39884 setMachineCodes(mi++, (byte) 0x66);
39885 generateREXprefix(false, dstReg, srcIndex, srcBase);
39886 setMachineCodes(mi++, (byte) 0x0F);
39887 setMachineCodes(mi++, (byte) 0x2E);
39888 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
39889 if (lister != null) lister.RRXD(miStart, "UCOMISD", dstReg, srcBase, srcIndex, srcScale, srcDisp);
39890 }
39891
39892 /**
39893 * Generate a register--register-indirect UCOMISD. That is,
39894 * <PRE>
39895 * dstReg <<= (quad) [srcBase]
39896 * </PRE>
39897 *
39898 * @param dstReg destination register
39899 * @param srcBase the source base register
39900 */
39901 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
39902 public final void emitUCOMISD_Reg_RegInd(XMM dstReg, GPR srcBase) {
39903 int miStart = mi;
39904 setMachineCodes(mi++, (byte) 0x66);
39905 generateREXprefix(false, dstReg, null, srcBase);
39906 setMachineCodes(mi++, (byte) 0x0F);
39907 setMachineCodes(mi++, (byte) 0x2E);
39908 emitRegIndirectRegOperands(srcBase, dstReg);
39909 if (lister != null) lister.RRN(miStart, "UCOMISD", dstReg, srcBase);
39910 }
39911
39912
39913 /**
39914 * Generate a register--register CMPEQSD. That is,
39915 * <PRE>
39916 * dstReg <<= (quad) srcReg
39917 * </PRE>
39918 *
39919 * @param dstReg destination register
39920 * @param srcReg source register
39921 */
39922 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
39923 public final void emitCMPEQSD_Reg_Reg(XMM dstReg, XMM srcReg) {
39924 int miStart = mi;
39925 setMachineCodes(mi++, (byte) 0xF2);
39926 generateREXprefix(false, dstReg, null, srcReg);
39927 setMachineCodes(mi++, (byte) 0x0F);
39928 setMachineCodes(mi++, (byte) 0xC2);
39929 emitRegRegOperands(srcReg, dstReg);
39930 setMachineCodes(mi++, (byte) 0);
39931 if (lister != null) lister.RR(miStart, "CMPEQSD", dstReg, srcReg);
39932 }
39933
39934 /**
39935 * Generate a register--register-displacement CMPEQSD. That is,
39936 * <PRE>
39937 * dstReg <<= (quad) [srcBase + srcDisp]
39938 * </PRE>
39939 *
39940 * @param dstReg destination register
39941 * @param srcBase the source base register
39942 * @param srcDisp the source displacement
39943 */
39944 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
39945 public final void emitCMPEQSD_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
39946 int miStart = mi;
39947 setMachineCodes(mi++, (byte) 0xF2);
39948 generateREXprefix(false, dstReg, null, srcBase);
39949 setMachineCodes(mi++, (byte) 0x0F);
39950 setMachineCodes(mi++, (byte) 0xC2);
39951 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
39952 setMachineCodes(mi++, (byte) 0);
39953 if (lister != null) lister.RRD(miStart, "CMPEQSD", dstReg, srcBase, srcDisp);
39954 }
39955
39956 /**
39957 * Generate a register--register-offset CMPEQSD. That is,
39958 * <PRE>
39959 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
39960 * </PRE>
39961 *
39962 * @param dstReg destination register
39963 * @param srcIndex the source index register
39964 * @param srcScale the source scale
39965 * @param srcDisp the source displacement
39966 */
39967 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
39968 public final void emitCMPEQSD_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
39969 int miStart = mi;
39970 setMachineCodes(mi++, (byte) 0xF2);
39971 generateREXprefix(false, dstReg, srcIndex, null);
39972 setMachineCodes(mi++, (byte) 0x0F);
39973 setMachineCodes(mi++, (byte) 0xC2);
39974 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
39975 setMachineCodes(mi++, (byte) 0);
39976 if (lister != null) lister.RRFD(miStart, "CMPEQSD", dstReg, srcIndex, srcScale, srcDisp);
39977 }
39978
39979 /**
39980 * Generate a register--absolute CMPEQSD. That is,
39981 * <PRE>
39982 * dstReg <<= (quad) [srcDisp]
39983 * </PRE>
39984 *
39985 * @param dstReg destination register
39986 * @param srcDisp the source displacement
39987 */
39988 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
39989 public final void emitCMPEQSD_Reg_Abs(XMM dstReg, Address srcDisp) {
39990 int miStart = mi;
39991 setMachineCodes(mi++, (byte) 0xF2);
39992 generateREXprefix(false, dstReg, null, null);
39993 setMachineCodes(mi++, (byte) 0x0F);
39994 setMachineCodes(mi++, (byte) 0xC2);
39995 emitAbsRegOperands(srcDisp, dstReg);
39996 setMachineCodes(mi++, (byte) 0);
39997 if (lister != null) lister.RRA(miStart, "CMPEQSD", dstReg, srcDisp);
39998 }
39999
40000 /**
40001 * Generate a register--register-index CMPEQSD. That is,
40002 * <PRE>
40003 * dstReg <<= (quad) srcReg
40004 * </PRE>
40005 *
40006 * @param dstReg destination register
40007 * @param srcBase the source base register
40008 * @param srcIndex the source index register
40009 * @param srcScale the source scale
40010 * @param srcDisp the source displacement
40011 */
40012 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
40013 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
40014 public final void emitCMPEQSD_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
40015 int miStart = mi;
40016 setMachineCodes(mi++, (byte) 0xF2);
40017 generateREXprefix(false, dstReg, srcIndex, srcBase);
40018 setMachineCodes(mi++, (byte) 0x0F);
40019 setMachineCodes(mi++, (byte) 0xC2);
40020 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
40021 setMachineCodes(mi++, (byte) 0);
40022 if (lister != null) lister.RRXD(miStart, "CMPEQSD", dstReg, srcBase, srcIndex, srcScale, srcDisp);
40023 }
40024
40025 /**
40026 * Generate a register--register-indirect CMPEQSD. That is,
40027 * <PRE>
40028 * dstReg <<= (quad) [srcBase]
40029 * </PRE>
40030 *
40031 * @param dstReg destination register
40032 * @param srcBase the source base register
40033 */
40034 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
40035 public final void emitCMPEQSD_Reg_RegInd(XMM dstReg, GPR srcBase) {
40036 int miStart = mi;
40037 setMachineCodes(mi++, (byte) 0xF2);
40038 generateREXprefix(false, dstReg, null, srcBase);
40039 setMachineCodes(mi++, (byte) 0x0F);
40040 setMachineCodes(mi++, (byte) 0xC2);
40041 emitRegIndirectRegOperands(srcBase, dstReg);
40042 setMachineCodes(mi++, (byte) 0);
40043 if (lister != null) lister.RRN(miStart, "CMPEQSD", dstReg, srcBase);
40044 }
40045
40046
40047 /**
40048 * Generate a register--register CMPLTSD. That is,
40049 * <PRE>
40050 * dstReg <<= (quad) srcReg
40051 * </PRE>
40052 *
40053 * @param dstReg destination register
40054 * @param srcReg source register
40055 */
40056 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
40057 public final void emitCMPLTSD_Reg_Reg(XMM dstReg, XMM srcReg) {
40058 int miStart = mi;
40059 setMachineCodes(mi++, (byte) 0xF2);
40060 generateREXprefix(false, dstReg, null, srcReg);
40061 setMachineCodes(mi++, (byte) 0x0F);
40062 setMachineCodes(mi++, (byte) 0xC2);
40063 emitRegRegOperands(srcReg, dstReg);
40064 setMachineCodes(mi++, (byte) 1);
40065 if (lister != null) lister.RR(miStart, "CMPLTSD", dstReg, srcReg);
40066 }
40067
40068 /**
40069 * Generate a register--register-displacement CMPLTSD. That is,
40070 * <PRE>
40071 * dstReg <<= (quad) [srcBase + srcDisp]
40072 * </PRE>
40073 *
40074 * @param dstReg destination register
40075 * @param srcBase the source base register
40076 * @param srcDisp the source displacement
40077 */
40078 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
40079 public final void emitCMPLTSD_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
40080 int miStart = mi;
40081 setMachineCodes(mi++, (byte) 0xF2);
40082 generateREXprefix(false, dstReg, null, srcBase);
40083 setMachineCodes(mi++, (byte) 0x0F);
40084 setMachineCodes(mi++, (byte) 0xC2);
40085 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
40086 setMachineCodes(mi++, (byte) 1);
40087 if (lister != null) lister.RRD(miStart, "CMPLTSD", dstReg, srcBase, srcDisp);
40088 }
40089
40090 /**
40091 * Generate a register--register-offset CMPLTSD. That is,
40092 * <PRE>
40093 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
40094 * </PRE>
40095 *
40096 * @param dstReg destination register
40097 * @param srcIndex the source index register
40098 * @param srcScale the source scale
40099 * @param srcDisp the source displacement
40100 */
40101 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
40102 public final void emitCMPLTSD_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
40103 int miStart = mi;
40104 setMachineCodes(mi++, (byte) 0xF2);
40105 generateREXprefix(false, dstReg, srcIndex, null);
40106 setMachineCodes(mi++, (byte) 0x0F);
40107 setMachineCodes(mi++, (byte) 0xC2);
40108 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
40109 setMachineCodes(mi++, (byte) 1);
40110 if (lister != null) lister.RRFD(miStart, "CMPLTSD", dstReg, srcIndex, srcScale, srcDisp);
40111 }
40112
40113 /**
40114 * Generate a register--absolute CMPLTSD. That is,
40115 * <PRE>
40116 * dstReg <<= (quad) [srcDisp]
40117 * </PRE>
40118 *
40119 * @param dstReg destination register
40120 * @param srcDisp the source displacement
40121 */
40122 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
40123 public final void emitCMPLTSD_Reg_Abs(XMM dstReg, Address srcDisp) {
40124 int miStart = mi;
40125 setMachineCodes(mi++, (byte) 0xF2);
40126 generateREXprefix(false, dstReg, null, null);
40127 setMachineCodes(mi++, (byte) 0x0F);
40128 setMachineCodes(mi++, (byte) 0xC2);
40129 emitAbsRegOperands(srcDisp, dstReg);
40130 setMachineCodes(mi++, (byte) 1);
40131 if (lister != null) lister.RRA(miStart, "CMPLTSD", dstReg, srcDisp);
40132 }
40133
40134 /**
40135 * Generate a register--register-index CMPLTSD. That is,
40136 * <PRE>
40137 * dstReg <<= (quad) srcReg
40138 * </PRE>
40139 *
40140 * @param dstReg destination register
40141 * @param srcBase the source base register
40142 * @param srcIndex the source index register
40143 * @param srcScale the source scale
40144 * @param srcDisp the source displacement
40145 */
40146 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
40147 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
40148 public final void emitCMPLTSD_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
40149 int miStart = mi;
40150 setMachineCodes(mi++, (byte) 0xF2);
40151 generateREXprefix(false, dstReg, srcIndex, srcBase);
40152 setMachineCodes(mi++, (byte) 0x0F);
40153 setMachineCodes(mi++, (byte) 0xC2);
40154 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
40155 setMachineCodes(mi++, (byte) 1);
40156 if (lister != null) lister.RRXD(miStart, "CMPLTSD", dstReg, srcBase, srcIndex, srcScale, srcDisp);
40157 }
40158
40159 /**
40160 * Generate a register--register-indirect CMPLTSD. That is,
40161 * <PRE>
40162 * dstReg <<= (quad) [srcBase]
40163 * </PRE>
40164 *
40165 * @param dstReg destination register
40166 * @param srcBase the source base register
40167 */
40168 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
40169 public final void emitCMPLTSD_Reg_RegInd(XMM dstReg, GPR srcBase) {
40170 int miStart = mi;
40171 setMachineCodes(mi++, (byte) 0xF2);
40172 generateREXprefix(false, dstReg, null, srcBase);
40173 setMachineCodes(mi++, (byte) 0x0F);
40174 setMachineCodes(mi++, (byte) 0xC2);
40175 emitRegIndirectRegOperands(srcBase, dstReg);
40176 setMachineCodes(mi++, (byte) 1);
40177 if (lister != null) lister.RRN(miStart, "CMPLTSD", dstReg, srcBase);
40178 }
40179
40180
40181 /**
40182 * Generate a register--register CMPLESD. That is,
40183 * <PRE>
40184 * dstReg <<= (quad) srcReg
40185 * </PRE>
40186 *
40187 * @param dstReg destination register
40188 * @param srcReg source register
40189 */
40190 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
40191 public final void emitCMPLESD_Reg_Reg(XMM dstReg, XMM srcReg) {
40192 int miStart = mi;
40193 setMachineCodes(mi++, (byte) 0xF2);
40194 generateREXprefix(false, dstReg, null, srcReg);
40195 setMachineCodes(mi++, (byte) 0x0F);
40196 setMachineCodes(mi++, (byte) 0xC2);
40197 emitRegRegOperands(srcReg, dstReg);
40198 setMachineCodes(mi++, (byte) 2);
40199 if (lister != null) lister.RR(miStart, "CMPLESD", dstReg, srcReg);
40200 }
40201
40202 /**
40203 * Generate a register--register-displacement CMPLESD. That is,
40204 * <PRE>
40205 * dstReg <<= (quad) [srcBase + srcDisp]
40206 * </PRE>
40207 *
40208 * @param dstReg destination register
40209 * @param srcBase the source base register
40210 * @param srcDisp the source displacement
40211 */
40212 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
40213 public final void emitCMPLESD_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
40214 int miStart = mi;
40215 setMachineCodes(mi++, (byte) 0xF2);
40216 generateREXprefix(false, dstReg, null, srcBase);
40217 setMachineCodes(mi++, (byte) 0x0F);
40218 setMachineCodes(mi++, (byte) 0xC2);
40219 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
40220 setMachineCodes(mi++, (byte) 2);
40221 if (lister != null) lister.RRD(miStart, "CMPLESD", dstReg, srcBase, srcDisp);
40222 }
40223
40224 /**
40225 * Generate a register--register-offset CMPLESD. That is,
40226 * <PRE>
40227 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
40228 * </PRE>
40229 *
40230 * @param dstReg destination register
40231 * @param srcIndex the source index register
40232 * @param srcScale the source scale
40233 * @param srcDisp the source displacement
40234 */
40235 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
40236 public final void emitCMPLESD_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
40237 int miStart = mi;
40238 setMachineCodes(mi++, (byte) 0xF2);
40239 generateREXprefix(false, dstReg, srcIndex, null);
40240 setMachineCodes(mi++, (byte) 0x0F);
40241 setMachineCodes(mi++, (byte) 0xC2);
40242 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
40243 setMachineCodes(mi++, (byte) 2);
40244 if (lister != null) lister.RRFD(miStart, "CMPLESD", dstReg, srcIndex, srcScale, srcDisp);
40245 }
40246
40247 /**
40248 * Generate a register--absolute CMPLESD. That is,
40249 * <PRE>
40250 * dstReg <<= (quad) [srcDisp]
40251 * </PRE>
40252 *
40253 * @param dstReg destination register
40254 * @param srcDisp the source displacement
40255 */
40256 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
40257 public final void emitCMPLESD_Reg_Abs(XMM dstReg, Address srcDisp) {
40258 int miStart = mi;
40259 setMachineCodes(mi++, (byte) 0xF2);
40260 generateREXprefix(false, dstReg, null, null);
40261 setMachineCodes(mi++, (byte) 0x0F);
40262 setMachineCodes(mi++, (byte) 0xC2);
40263 emitAbsRegOperands(srcDisp, dstReg);
40264 setMachineCodes(mi++, (byte) 2);
40265 if (lister != null) lister.RRA(miStart, "CMPLESD", dstReg, srcDisp);
40266 }
40267
40268 /**
40269 * Generate a register--register-index CMPLESD. That is,
40270 * <PRE>
40271 * dstReg <<= (quad) srcReg
40272 * </PRE>
40273 *
40274 * @param dstReg destination register
40275 * @param srcBase the source base register
40276 * @param srcIndex the source index register
40277 * @param srcScale the source scale
40278 * @param srcDisp the source displacement
40279 */
40280 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
40281 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
40282 public final void emitCMPLESD_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
40283 int miStart = mi;
40284 setMachineCodes(mi++, (byte) 0xF2);
40285 generateREXprefix(false, dstReg, srcIndex, srcBase);
40286 setMachineCodes(mi++, (byte) 0x0F);
40287 setMachineCodes(mi++, (byte) 0xC2);
40288 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
40289 setMachineCodes(mi++, (byte) 2);
40290 if (lister != null) lister.RRXD(miStart, "CMPLESD", dstReg, srcBase, srcIndex, srcScale, srcDisp);
40291 }
40292
40293 /**
40294 * Generate a register--register-indirect CMPLESD. That is,
40295 * <PRE>
40296 * dstReg <<= (quad) [srcBase]
40297 * </PRE>
40298 *
40299 * @param dstReg destination register
40300 * @param srcBase the source base register
40301 */
40302 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
40303 public final void emitCMPLESD_Reg_RegInd(XMM dstReg, GPR srcBase) {
40304 int miStart = mi;
40305 setMachineCodes(mi++, (byte) 0xF2);
40306 generateREXprefix(false, dstReg, null, srcBase);
40307 setMachineCodes(mi++, (byte) 0x0F);
40308 setMachineCodes(mi++, (byte) 0xC2);
40309 emitRegIndirectRegOperands(srcBase, dstReg);
40310 setMachineCodes(mi++, (byte) 2);
40311 if (lister != null) lister.RRN(miStart, "CMPLESD", dstReg, srcBase);
40312 }
40313
40314
40315 /**
40316 * Generate a register--register CMPUNORDSD. That is,
40317 * <PRE>
40318 * dstReg <<= (quad) srcReg
40319 * </PRE>
40320 *
40321 * @param dstReg destination register
40322 * @param srcReg source register
40323 */
40324 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
40325 public final void emitCMPUNORDSD_Reg_Reg(XMM dstReg, XMM srcReg) {
40326 int miStart = mi;
40327 setMachineCodes(mi++, (byte) 0xF2);
40328 generateREXprefix(false, dstReg, null, srcReg);
40329 setMachineCodes(mi++, (byte) 0x0F);
40330 setMachineCodes(mi++, (byte) 0xC2);
40331 emitRegRegOperands(srcReg, dstReg);
40332 setMachineCodes(mi++, (byte) 3);
40333 if (lister != null) lister.RR(miStart, "CMPUNORDSD", dstReg, srcReg);
40334 }
40335
40336 /**
40337 * Generate a register--register-displacement CMPUNORDSD. That is,
40338 * <PRE>
40339 * dstReg <<= (quad) [srcBase + srcDisp]
40340 * </PRE>
40341 *
40342 * @param dstReg destination register
40343 * @param srcBase the source base register
40344 * @param srcDisp the source displacement
40345 */
40346 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
40347 public final void emitCMPUNORDSD_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
40348 int miStart = mi;
40349 setMachineCodes(mi++, (byte) 0xF2);
40350 generateREXprefix(false, dstReg, null, srcBase);
40351 setMachineCodes(mi++, (byte) 0x0F);
40352 setMachineCodes(mi++, (byte) 0xC2);
40353 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
40354 setMachineCodes(mi++, (byte) 3);
40355 if (lister != null) lister.RRD(miStart, "CMPUNORDSD", dstReg, srcBase, srcDisp);
40356 }
40357
40358 /**
40359 * Generate a register--register-offset CMPUNORDSD. That is,
40360 * <PRE>
40361 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
40362 * </PRE>
40363 *
40364 * @param dstReg destination register
40365 * @param srcIndex the source index register
40366 * @param srcScale the source scale
40367 * @param srcDisp the source displacement
40368 */
40369 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
40370 public final void emitCMPUNORDSD_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
40371 int miStart = mi;
40372 setMachineCodes(mi++, (byte) 0xF2);
40373 generateREXprefix(false, dstReg, srcIndex, null);
40374 setMachineCodes(mi++, (byte) 0x0F);
40375 setMachineCodes(mi++, (byte) 0xC2);
40376 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
40377 setMachineCodes(mi++, (byte) 3);
40378 if (lister != null) lister.RRFD(miStart, "CMPUNORDSD", dstReg, srcIndex, srcScale, srcDisp);
40379 }
40380
40381 /**
40382 * Generate a register--absolute CMPUNORDSD. That is,
40383 * <PRE>
40384 * dstReg <<= (quad) [srcDisp]
40385 * </PRE>
40386 *
40387 * @param dstReg destination register
40388 * @param srcDisp the source displacement
40389 */
40390 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
40391 public final void emitCMPUNORDSD_Reg_Abs(XMM dstReg, Address srcDisp) {
40392 int miStart = mi;
40393 setMachineCodes(mi++, (byte) 0xF2);
40394 generateREXprefix(false, dstReg, null, null);
40395 setMachineCodes(mi++, (byte) 0x0F);
40396 setMachineCodes(mi++, (byte) 0xC2);
40397 emitAbsRegOperands(srcDisp, dstReg);
40398 setMachineCodes(mi++, (byte) 3);
40399 if (lister != null) lister.RRA(miStart, "CMPUNORDSD", dstReg, srcDisp);
40400 }
40401
40402 /**
40403 * Generate a register--register-index CMPUNORDSD. That is,
40404 * <PRE>
40405 * dstReg <<= (quad) srcReg
40406 * </PRE>
40407 *
40408 * @param dstReg destination register
40409 * @param srcBase the source base register
40410 * @param srcIndex the source index register
40411 * @param srcScale the source scale
40412 * @param srcDisp the source displacement
40413 */
40414 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
40415 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
40416 public final void emitCMPUNORDSD_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
40417 int miStart = mi;
40418 setMachineCodes(mi++, (byte) 0xF2);
40419 generateREXprefix(false, dstReg, srcIndex, srcBase);
40420 setMachineCodes(mi++, (byte) 0x0F);
40421 setMachineCodes(mi++, (byte) 0xC2);
40422 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
40423 setMachineCodes(mi++, (byte) 3);
40424 if (lister != null) lister.RRXD(miStart, "CMPUNORDSD", dstReg, srcBase, srcIndex, srcScale, srcDisp);
40425 }
40426
40427 /**
40428 * Generate a register--register-indirect CMPUNORDSD. That is,
40429 * <PRE>
40430 * dstReg <<= (quad) [srcBase]
40431 * </PRE>
40432 *
40433 * @param dstReg destination register
40434 * @param srcBase the source base register
40435 */
40436 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
40437 public final void emitCMPUNORDSD_Reg_RegInd(XMM dstReg, GPR srcBase) {
40438 int miStart = mi;
40439 setMachineCodes(mi++, (byte) 0xF2);
40440 generateREXprefix(false, dstReg, null, srcBase);
40441 setMachineCodes(mi++, (byte) 0x0F);
40442 setMachineCodes(mi++, (byte) 0xC2);
40443 emitRegIndirectRegOperands(srcBase, dstReg);
40444 setMachineCodes(mi++, (byte) 3);
40445 if (lister != null) lister.RRN(miStart, "CMPUNORDSD", dstReg, srcBase);
40446 }
40447
40448
40449 /**
40450 * Generate a register--register CMPNESD. That is,
40451 * <PRE>
40452 * dstReg <<= (quad) srcReg
40453 * </PRE>
40454 *
40455 * @param dstReg destination register
40456 * @param srcReg source register
40457 */
40458 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
40459 public final void emitCMPNESD_Reg_Reg(XMM dstReg, XMM srcReg) {
40460 int miStart = mi;
40461 setMachineCodes(mi++, (byte) 0xF2);
40462 generateREXprefix(false, dstReg, null, srcReg);
40463 setMachineCodes(mi++, (byte) 0x0F);
40464 setMachineCodes(mi++, (byte) 0xC2);
40465 emitRegRegOperands(srcReg, dstReg);
40466 setMachineCodes(mi++, (byte) 4);
40467 if (lister != null) lister.RR(miStart, "CMPNESD", dstReg, srcReg);
40468 }
40469
40470 /**
40471 * Generate a register--register-displacement CMPNESD. That is,
40472 * <PRE>
40473 * dstReg <<= (quad) [srcBase + srcDisp]
40474 * </PRE>
40475 *
40476 * @param dstReg destination register
40477 * @param srcBase the source base register
40478 * @param srcDisp the source displacement
40479 */
40480 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
40481 public final void emitCMPNESD_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
40482 int miStart = mi;
40483 setMachineCodes(mi++, (byte) 0xF2);
40484 generateREXprefix(false, dstReg, null, srcBase);
40485 setMachineCodes(mi++, (byte) 0x0F);
40486 setMachineCodes(mi++, (byte) 0xC2);
40487 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
40488 setMachineCodes(mi++, (byte) 4);
40489 if (lister != null) lister.RRD(miStart, "CMPNESD", dstReg, srcBase, srcDisp);
40490 }
40491
40492 /**
40493 * Generate a register--register-offset CMPNESD. That is,
40494 * <PRE>
40495 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
40496 * </PRE>
40497 *
40498 * @param dstReg destination register
40499 * @param srcIndex the source index register
40500 * @param srcScale the source scale
40501 * @param srcDisp the source displacement
40502 */
40503 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
40504 public final void emitCMPNESD_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
40505 int miStart = mi;
40506 setMachineCodes(mi++, (byte) 0xF2);
40507 generateREXprefix(false, dstReg, srcIndex, null);
40508 setMachineCodes(mi++, (byte) 0x0F);
40509 setMachineCodes(mi++, (byte) 0xC2);
40510 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
40511 setMachineCodes(mi++, (byte) 4);
40512 if (lister != null) lister.RRFD(miStart, "CMPNESD", dstReg, srcIndex, srcScale, srcDisp);
40513 }
40514
40515 /**
40516 * Generate a register--absolute CMPNESD. That is,
40517 * <PRE>
40518 * dstReg <<= (quad) [srcDisp]
40519 * </PRE>
40520 *
40521 * @param dstReg destination register
40522 * @param srcDisp the source displacement
40523 */
40524 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
40525 public final void emitCMPNESD_Reg_Abs(XMM dstReg, Address srcDisp) {
40526 int miStart = mi;
40527 setMachineCodes(mi++, (byte) 0xF2);
40528 generateREXprefix(false, dstReg, null, null);
40529 setMachineCodes(mi++, (byte) 0x0F);
40530 setMachineCodes(mi++, (byte) 0xC2);
40531 emitAbsRegOperands(srcDisp, dstReg);
40532 setMachineCodes(mi++, (byte) 4);
40533 if (lister != null) lister.RRA(miStart, "CMPNESD", dstReg, srcDisp);
40534 }
40535
40536 /**
40537 * Generate a register--register-index CMPNESD. That is,
40538 * <PRE>
40539 * dstReg <<= (quad) srcReg
40540 * </PRE>
40541 *
40542 * @param dstReg destination register
40543 * @param srcBase the source base register
40544 * @param srcIndex the source index register
40545 * @param srcScale the source scale
40546 * @param srcDisp the source displacement
40547 */
40548 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
40549 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
40550 public final void emitCMPNESD_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
40551 int miStart = mi;
40552 setMachineCodes(mi++, (byte) 0xF2);
40553 generateREXprefix(false, dstReg, srcIndex, srcBase);
40554 setMachineCodes(mi++, (byte) 0x0F);
40555 setMachineCodes(mi++, (byte) 0xC2);
40556 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
40557 setMachineCodes(mi++, (byte) 4);
40558 if (lister != null) lister.RRXD(miStart, "CMPNESD", dstReg, srcBase, srcIndex, srcScale, srcDisp);
40559 }
40560
40561 /**
40562 * Generate a register--register-indirect CMPNESD. That is,
40563 * <PRE>
40564 * dstReg <<= (quad) [srcBase]
40565 * </PRE>
40566 *
40567 * @param dstReg destination register
40568 * @param srcBase the source base register
40569 */
40570 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
40571 public final void emitCMPNESD_Reg_RegInd(XMM dstReg, GPR srcBase) {
40572 int miStart = mi;
40573 setMachineCodes(mi++, (byte) 0xF2);
40574 generateREXprefix(false, dstReg, null, srcBase);
40575 setMachineCodes(mi++, (byte) 0x0F);
40576 setMachineCodes(mi++, (byte) 0xC2);
40577 emitRegIndirectRegOperands(srcBase, dstReg);
40578 setMachineCodes(mi++, (byte) 4);
40579 if (lister != null) lister.RRN(miStart, "CMPNESD", dstReg, srcBase);
40580 }
40581
40582
40583 /**
40584 * Generate a register--register CMPNLTSD. That is,
40585 * <PRE>
40586 * dstReg <<= (quad) srcReg
40587 * </PRE>
40588 *
40589 * @param dstReg destination register
40590 * @param srcReg source register
40591 */
40592 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
40593 public final void emitCMPNLTSD_Reg_Reg(XMM dstReg, XMM srcReg) {
40594 int miStart = mi;
40595 setMachineCodes(mi++, (byte) 0xF2);
40596 generateREXprefix(false, dstReg, null, srcReg);
40597 setMachineCodes(mi++, (byte) 0x0F);
40598 setMachineCodes(mi++, (byte) 0xC2);
40599 emitRegRegOperands(srcReg, dstReg);
40600 setMachineCodes(mi++, (byte) 5);
40601 if (lister != null) lister.RR(miStart, "CMPNLTSD", dstReg, srcReg);
40602 }
40603
40604 /**
40605 * Generate a register--register-displacement CMPNLTSD. That is,
40606 * <PRE>
40607 * dstReg <<= (quad) [srcBase + srcDisp]
40608 * </PRE>
40609 *
40610 * @param dstReg destination register
40611 * @param srcBase the source base register
40612 * @param srcDisp the source displacement
40613 */
40614 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
40615 public final void emitCMPNLTSD_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
40616 int miStart = mi;
40617 setMachineCodes(mi++, (byte) 0xF2);
40618 generateREXprefix(false, dstReg, null, srcBase);
40619 setMachineCodes(mi++, (byte) 0x0F);
40620 setMachineCodes(mi++, (byte) 0xC2);
40621 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
40622 setMachineCodes(mi++, (byte) 5);
40623 if (lister != null) lister.RRD(miStart, "CMPNLTSD", dstReg, srcBase, srcDisp);
40624 }
40625
40626 /**
40627 * Generate a register--register-offset CMPNLTSD. That is,
40628 * <PRE>
40629 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
40630 * </PRE>
40631 *
40632 * @param dstReg destination register
40633 * @param srcIndex the source index register
40634 * @param srcScale the source scale
40635 * @param srcDisp the source displacement
40636 */
40637 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
40638 public final void emitCMPNLTSD_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
40639 int miStart = mi;
40640 setMachineCodes(mi++, (byte) 0xF2);
40641 generateREXprefix(false, dstReg, srcIndex, null);
40642 setMachineCodes(mi++, (byte) 0x0F);
40643 setMachineCodes(mi++, (byte) 0xC2);
40644 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
40645 setMachineCodes(mi++, (byte) 5);
40646 if (lister != null) lister.RRFD(miStart, "CMPNLTSD", dstReg, srcIndex, srcScale, srcDisp);
40647 }
40648
40649 /**
40650 * Generate a register--absolute CMPNLTSD. That is,
40651 * <PRE>
40652 * dstReg <<= (quad) [srcDisp]
40653 * </PRE>
40654 *
40655 * @param dstReg destination register
40656 * @param srcDisp the source displacement
40657 */
40658 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
40659 public final void emitCMPNLTSD_Reg_Abs(XMM dstReg, Address srcDisp) {
40660 int miStart = mi;
40661 setMachineCodes(mi++, (byte) 0xF2);
40662 generateREXprefix(false, dstReg, null, null);
40663 setMachineCodes(mi++, (byte) 0x0F);
40664 setMachineCodes(mi++, (byte) 0xC2);
40665 emitAbsRegOperands(srcDisp, dstReg);
40666 setMachineCodes(mi++, (byte) 5);
40667 if (lister != null) lister.RRA(miStart, "CMPNLTSD", dstReg, srcDisp);
40668 }
40669
40670 /**
40671 * Generate a register--register-index CMPNLTSD. That is,
40672 * <PRE>
40673 * dstReg <<= (quad) srcReg
40674 * </PRE>
40675 *
40676 * @param dstReg destination register
40677 * @param srcBase the source base register
40678 * @param srcIndex the source index register
40679 * @param srcScale the source scale
40680 * @param srcDisp the source displacement
40681 */
40682 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
40683 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
40684 public final void emitCMPNLTSD_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
40685 int miStart = mi;
40686 setMachineCodes(mi++, (byte) 0xF2);
40687 generateREXprefix(false, dstReg, srcIndex, srcBase);
40688 setMachineCodes(mi++, (byte) 0x0F);
40689 setMachineCodes(mi++, (byte) 0xC2);
40690 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
40691 setMachineCodes(mi++, (byte) 5);
40692 if (lister != null) lister.RRXD(miStart, "CMPNLTSD", dstReg, srcBase, srcIndex, srcScale, srcDisp);
40693 }
40694
40695 /**
40696 * Generate a register--register-indirect CMPNLTSD. That is,
40697 * <PRE>
40698 * dstReg <<= (quad) [srcBase]
40699 * </PRE>
40700 *
40701 * @param dstReg destination register
40702 * @param srcBase the source base register
40703 */
40704 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
40705 public final void emitCMPNLTSD_Reg_RegInd(XMM dstReg, GPR srcBase) {
40706 int miStart = mi;
40707 setMachineCodes(mi++, (byte) 0xF2);
40708 generateREXprefix(false, dstReg, null, srcBase);
40709 setMachineCodes(mi++, (byte) 0x0F);
40710 setMachineCodes(mi++, (byte) 0xC2);
40711 emitRegIndirectRegOperands(srcBase, dstReg);
40712 setMachineCodes(mi++, (byte) 5);
40713 if (lister != null) lister.RRN(miStart, "CMPNLTSD", dstReg, srcBase);
40714 }
40715
40716
40717 /**
40718 * Generate a register--register CMPNLESD. That is,
40719 * <PRE>
40720 * dstReg <<= (quad) srcReg
40721 * </PRE>
40722 *
40723 * @param dstReg destination register
40724 * @param srcReg source register
40725 */
40726 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
40727 public final void emitCMPNLESD_Reg_Reg(XMM dstReg, XMM srcReg) {
40728 int miStart = mi;
40729 setMachineCodes(mi++, (byte) 0xF2);
40730 generateREXprefix(false, dstReg, null, srcReg);
40731 setMachineCodes(mi++, (byte) 0x0F);
40732 setMachineCodes(mi++, (byte) 0xC2);
40733 emitRegRegOperands(srcReg, dstReg);
40734 setMachineCodes(mi++, (byte) 6);
40735 if (lister != null) lister.RR(miStart, "CMPNLESD", dstReg, srcReg);
40736 }
40737
40738 /**
40739 * Generate a register--register-displacement CMPNLESD. That is,
40740 * <PRE>
40741 * dstReg <<= (quad) [srcBase + srcDisp]
40742 * </PRE>
40743 *
40744 * @param dstReg destination register
40745 * @param srcBase the source base register
40746 * @param srcDisp the source displacement
40747 */
40748 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
40749 public final void emitCMPNLESD_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
40750 int miStart = mi;
40751 setMachineCodes(mi++, (byte) 0xF2);
40752 generateREXprefix(false, dstReg, null, srcBase);
40753 setMachineCodes(mi++, (byte) 0x0F);
40754 setMachineCodes(mi++, (byte) 0xC2);
40755 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
40756 setMachineCodes(mi++, (byte) 6);
40757 if (lister != null) lister.RRD(miStart, "CMPNLESD", dstReg, srcBase, srcDisp);
40758 }
40759
40760 /**
40761 * Generate a register--register-offset CMPNLESD. That is,
40762 * <PRE>
40763 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
40764 * </PRE>
40765 *
40766 * @param dstReg destination register
40767 * @param srcIndex the source index register
40768 * @param srcScale the source scale
40769 * @param srcDisp the source displacement
40770 */
40771 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
40772 public final void emitCMPNLESD_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
40773 int miStart = mi;
40774 setMachineCodes(mi++, (byte) 0xF2);
40775 generateREXprefix(false, dstReg, srcIndex, null);
40776 setMachineCodes(mi++, (byte) 0x0F);
40777 setMachineCodes(mi++, (byte) 0xC2);
40778 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
40779 setMachineCodes(mi++, (byte) 6);
40780 if (lister != null) lister.RRFD(miStart, "CMPNLESD", dstReg, srcIndex, srcScale, srcDisp);
40781 }
40782
40783 /**
40784 * Generate a register--absolute CMPNLESD. That is,
40785 * <PRE>
40786 * dstReg <<= (quad) [srcDisp]
40787 * </PRE>
40788 *
40789 * @param dstReg destination register
40790 * @param srcDisp the source displacement
40791 */
40792 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
40793 public final void emitCMPNLESD_Reg_Abs(XMM dstReg, Address srcDisp) {
40794 int miStart = mi;
40795 setMachineCodes(mi++, (byte) 0xF2);
40796 generateREXprefix(false, dstReg, null, null);
40797 setMachineCodes(mi++, (byte) 0x0F);
40798 setMachineCodes(mi++, (byte) 0xC2);
40799 emitAbsRegOperands(srcDisp, dstReg);
40800 setMachineCodes(mi++, (byte) 6);
40801 if (lister != null) lister.RRA(miStart, "CMPNLESD", dstReg, srcDisp);
40802 }
40803
40804 /**
40805 * Generate a register--register-index CMPNLESD. That is,
40806 * <PRE>
40807 * dstReg <<= (quad) srcReg
40808 * </PRE>
40809 *
40810 * @param dstReg destination register
40811 * @param srcBase the source base register
40812 * @param srcIndex the source index register
40813 * @param srcScale the source scale
40814 * @param srcDisp the source displacement
40815 */
40816 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
40817 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
40818 public final void emitCMPNLESD_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
40819 int miStart = mi;
40820 setMachineCodes(mi++, (byte) 0xF2);
40821 generateREXprefix(false, dstReg, srcIndex, srcBase);
40822 setMachineCodes(mi++, (byte) 0x0F);
40823 setMachineCodes(mi++, (byte) 0xC2);
40824 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
40825 setMachineCodes(mi++, (byte) 6);
40826 if (lister != null) lister.RRXD(miStart, "CMPNLESD", dstReg, srcBase, srcIndex, srcScale, srcDisp);
40827 }
40828
40829 /**
40830 * Generate a register--register-indirect CMPNLESD. That is,
40831 * <PRE>
40832 * dstReg <<= (quad) [srcBase]
40833 * </PRE>
40834 *
40835 * @param dstReg destination register
40836 * @param srcBase the source base register
40837 */
40838 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
40839 public final void emitCMPNLESD_Reg_RegInd(XMM dstReg, GPR srcBase) {
40840 int miStart = mi;
40841 setMachineCodes(mi++, (byte) 0xF2);
40842 generateREXprefix(false, dstReg, null, srcBase);
40843 setMachineCodes(mi++, (byte) 0x0F);
40844 setMachineCodes(mi++, (byte) 0xC2);
40845 emitRegIndirectRegOperands(srcBase, dstReg);
40846 setMachineCodes(mi++, (byte) 6);
40847 if (lister != null) lister.RRN(miStart, "CMPNLESD", dstReg, srcBase);
40848 }
40849
40850
40851 /**
40852 * Generate a register--register CMPORDSD. That is,
40853 * <PRE>
40854 * dstReg <<= (quad) srcReg
40855 * </PRE>
40856 *
40857 * @param dstReg destination register
40858 * @param srcReg source register
40859 */
40860 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
40861 public final void emitCMPORDSD_Reg_Reg(XMM dstReg, XMM srcReg) {
40862 int miStart = mi;
40863 setMachineCodes(mi++, (byte) 0xF2);
40864 generateREXprefix(false, dstReg, null, srcReg);
40865 setMachineCodes(mi++, (byte) 0x0F);
40866 setMachineCodes(mi++, (byte) 0xC2);
40867 emitRegRegOperands(srcReg, dstReg);
40868 setMachineCodes(mi++, (byte) 7);
40869 if (lister != null) lister.RR(miStart, "CMPORDSD", dstReg, srcReg);
40870 }
40871
40872 /**
40873 * Generate a register--register-displacement CMPORDSD. That is,
40874 * <PRE>
40875 * dstReg <<= (quad) [srcBase + srcDisp]
40876 * </PRE>
40877 *
40878 * @param dstReg destination register
40879 * @param srcBase the source base register
40880 * @param srcDisp the source displacement
40881 */
40882 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
40883 public final void emitCMPORDSD_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
40884 int miStart = mi;
40885 setMachineCodes(mi++, (byte) 0xF2);
40886 generateREXprefix(false, dstReg, null, srcBase);
40887 setMachineCodes(mi++, (byte) 0x0F);
40888 setMachineCodes(mi++, (byte) 0xC2);
40889 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
40890 setMachineCodes(mi++, (byte) 7);
40891 if (lister != null) lister.RRD(miStart, "CMPORDSD", dstReg, srcBase, srcDisp);
40892 }
40893
40894 /**
40895 * Generate a register--register-offset CMPORDSD. That is,
40896 * <PRE>
40897 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
40898 * </PRE>
40899 *
40900 * @param dstReg destination register
40901 * @param srcIndex the source index register
40902 * @param srcScale the source scale
40903 * @param srcDisp the source displacement
40904 */
40905 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
40906 public final void emitCMPORDSD_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
40907 int miStart = mi;
40908 setMachineCodes(mi++, (byte) 0xF2);
40909 generateREXprefix(false, dstReg, srcIndex, null);
40910 setMachineCodes(mi++, (byte) 0x0F);
40911 setMachineCodes(mi++, (byte) 0xC2);
40912 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
40913 setMachineCodes(mi++, (byte) 7);
40914 if (lister != null) lister.RRFD(miStart, "CMPORDSD", dstReg, srcIndex, srcScale, srcDisp);
40915 }
40916
40917 /**
40918 * Generate a register--absolute CMPORDSD. That is,
40919 * <PRE>
40920 * dstReg <<= (quad) [srcDisp]
40921 * </PRE>
40922 *
40923 * @param dstReg destination register
40924 * @param srcDisp the source displacement
40925 */
40926 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
40927 public final void emitCMPORDSD_Reg_Abs(XMM dstReg, Address srcDisp) {
40928 int miStart = mi;
40929 setMachineCodes(mi++, (byte) 0xF2);
40930 generateREXprefix(false, dstReg, null, null);
40931 setMachineCodes(mi++, (byte) 0x0F);
40932 setMachineCodes(mi++, (byte) 0xC2);
40933 emitAbsRegOperands(srcDisp, dstReg);
40934 setMachineCodes(mi++, (byte) 7);
40935 if (lister != null) lister.RRA(miStart, "CMPORDSD", dstReg, srcDisp);
40936 }
40937
40938 /**
40939 * Generate a register--register-index CMPORDSD. That is,
40940 * <PRE>
40941 * dstReg <<= (quad) srcReg
40942 * </PRE>
40943 *
40944 * @param dstReg destination register
40945 * @param srcBase the source base register
40946 * @param srcIndex the source index register
40947 * @param srcScale the source scale
40948 * @param srcDisp the source displacement
40949 */
40950 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
40951 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
40952 public final void emitCMPORDSD_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
40953 int miStart = mi;
40954 setMachineCodes(mi++, (byte) 0xF2);
40955 generateREXprefix(false, dstReg, srcIndex, srcBase);
40956 setMachineCodes(mi++, (byte) 0x0F);
40957 setMachineCodes(mi++, (byte) 0xC2);
40958 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
40959 setMachineCodes(mi++, (byte) 7);
40960 if (lister != null) lister.RRXD(miStart, "CMPORDSD", dstReg, srcBase, srcIndex, srcScale, srcDisp);
40961 }
40962
40963 /**
40964 * Generate a register--register-indirect CMPORDSD. That is,
40965 * <PRE>
40966 * dstReg <<= (quad) [srcBase]
40967 * </PRE>
40968 *
40969 * @param dstReg destination register
40970 * @param srcBase the source base register
40971 */
40972 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
40973 public final void emitCMPORDSD_Reg_RegInd(XMM dstReg, GPR srcBase) {
40974 int miStart = mi;
40975 setMachineCodes(mi++, (byte) 0xF2);
40976 generateREXprefix(false, dstReg, null, srcBase);
40977 setMachineCodes(mi++, (byte) 0x0F);
40978 setMachineCodes(mi++, (byte) 0xC2);
40979 emitRegIndirectRegOperands(srcBase, dstReg);
40980 setMachineCodes(mi++, (byte) 7);
40981 if (lister != null) lister.RRN(miStart, "CMPORDSD", dstReg, srcBase);
40982 }
40983
40984
40985 /**
40986 * Generate a register--register PSLLQ. That is,
40987 * <PRE>
40988 * dstReg <<= (quad) srcReg
40989 * </PRE>
40990 *
40991 * @param dstReg destination register
40992 * @param srcReg source register
40993 */
40994 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
40995 public final void emitPSLLQ_Reg_Reg(MM dstReg, MM srcReg) {
40996 int miStart = mi;
40997 generateREXprefix(false, dstReg, null, srcReg);
40998 setMachineCodes(mi++, (byte) 0x0F);
40999 setMachineCodes(mi++, (byte) 0xF3);
41000 emitRegRegOperands(srcReg, dstReg);
41001 if (lister != null) lister.RR(miStart, "PSLLQ", dstReg, srcReg);
41002 }
41003
41004 /**
41005 * Generate a register--register-displacement PSLLQ. That is,
41006 * <PRE>
41007 * dstReg <<= (quad) [srcBase + srcDisp]
41008 * </PRE>
41009 *
41010 * @param dstReg destination register
41011 * @param srcBase the source base register
41012 * @param srcDisp the source displacement
41013 */
41014 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
41015 public final void emitPSLLQ_Reg_RegDisp(MM dstReg, GPR srcBase, Offset srcDisp) {
41016 int miStart = mi;
41017 generateREXprefix(false, dstReg, null, srcBase);
41018 setMachineCodes(mi++, (byte) 0x0F);
41019 setMachineCodes(mi++, (byte) 0xF3);
41020 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
41021 if (lister != null) lister.RRD(miStart, "PSLLQ", dstReg, srcBase, srcDisp);
41022 }
41023
41024 /**
41025 * Generate a register--register-offset PSLLQ. That is,
41026 * <PRE>
41027 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
41028 * </PRE>
41029 *
41030 * @param dstReg destination register
41031 * @param srcIndex the source index register
41032 * @param srcScale the source scale
41033 * @param srcDisp the source displacement
41034 */
41035 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
41036 public final void emitPSLLQ_Reg_RegOff(MM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
41037 int miStart = mi;
41038 generateREXprefix(false, dstReg, srcIndex, null);
41039 setMachineCodes(mi++, (byte) 0x0F);
41040 setMachineCodes(mi++, (byte) 0xF3);
41041 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
41042 if (lister != null) lister.RRFD(miStart, "PSLLQ", dstReg, srcIndex, srcScale, srcDisp);
41043 }
41044
41045 /**
41046 * Generate a register--absolute PSLLQ. That is,
41047 * <PRE>
41048 * dstReg <<= (quad) [srcDisp]
41049 * </PRE>
41050 *
41051 * @param dstReg destination register
41052 * @param srcDisp the source displacement
41053 */
41054 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
41055 public final void emitPSLLQ_Reg_Abs(MM dstReg, Address srcDisp) {
41056 int miStart = mi;
41057 generateREXprefix(false, dstReg, null, null);
41058 setMachineCodes(mi++, (byte) 0x0F);
41059 setMachineCodes(mi++, (byte) 0xF3);
41060 emitAbsRegOperands(srcDisp, dstReg);
41061 if (lister != null) lister.RRA(miStart, "PSLLQ", dstReg, srcDisp);
41062 }
41063
41064 /**
41065 * Generate a register--register-index PSLLQ. That is,
41066 * <PRE>
41067 * dstReg <<= (quad) srcReg
41068 * </PRE>
41069 *
41070 * @param dstReg destination register
41071 * @param srcBase the source base register
41072 * @param srcIndex the source index register
41073 * @param srcScale the source scale
41074 * @param srcDisp the source displacement
41075 */
41076 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
41077 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
41078 public final void emitPSLLQ_Reg_RegIdx(MM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
41079 int miStart = mi;
41080 generateREXprefix(false, dstReg, srcIndex, srcBase);
41081 setMachineCodes(mi++, (byte) 0x0F);
41082 setMachineCodes(mi++, (byte) 0xF3);
41083 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
41084 if (lister != null) lister.RRXD(miStart, "PSLLQ", dstReg, srcBase, srcIndex, srcScale, srcDisp);
41085 }
41086
41087 /**
41088 * Generate a register--register-indirect PSLLQ. That is,
41089 * <PRE>
41090 * dstReg <<= (quad) [srcBase]
41091 * </PRE>
41092 *
41093 * @param dstReg destination register
41094 * @param srcBase the source base register
41095 */
41096 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
41097 public final void emitPSLLQ_Reg_RegInd(MM dstReg, GPR srcBase) {
41098 int miStart = mi;
41099 generateREXprefix(false, dstReg, null, srcBase);
41100 setMachineCodes(mi++, (byte) 0x0F);
41101 setMachineCodes(mi++, (byte) 0xF3);
41102 emitRegIndirectRegOperands(srcBase, dstReg);
41103 if (lister != null) lister.RRN(miStart, "PSLLQ", dstReg, srcBase);
41104 }
41105
41106
41107 /**
41108 * Generate a register--register PSRLQ. That is,
41109 * <PRE>
41110 * dstReg <<= (quad) srcReg
41111 * </PRE>
41112 *
41113 * @param dstReg destination register
41114 * @param srcReg source register
41115 */
41116 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
41117 public final void emitPSRLQ_Reg_Reg(MM dstReg, MM srcReg) {
41118 int miStart = mi;
41119 generateREXprefix(false, dstReg, null, srcReg);
41120 setMachineCodes(mi++, (byte) 0x0F);
41121 setMachineCodes(mi++, (byte) 0xD3);
41122 emitRegRegOperands(srcReg, dstReg);
41123 if (lister != null) lister.RR(miStart, "PSRLQ", dstReg, srcReg);
41124 }
41125
41126 /**
41127 * Generate a register--register-displacement PSRLQ. That is,
41128 * <PRE>
41129 * dstReg <<= (quad) [srcBase + srcDisp]
41130 * </PRE>
41131 *
41132 * @param dstReg destination register
41133 * @param srcBase the source base register
41134 * @param srcDisp the source displacement
41135 */
41136 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
41137 public final void emitPSRLQ_Reg_RegDisp(MM dstReg, GPR srcBase, Offset srcDisp) {
41138 int miStart = mi;
41139 generateREXprefix(false, dstReg, null, srcBase);
41140 setMachineCodes(mi++, (byte) 0x0F);
41141 setMachineCodes(mi++, (byte) 0xD3);
41142 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
41143 if (lister != null) lister.RRD(miStart, "PSRLQ", dstReg, srcBase, srcDisp);
41144 }
41145
41146 /**
41147 * Generate a register--register-offset PSRLQ. That is,
41148 * <PRE>
41149 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
41150 * </PRE>
41151 *
41152 * @param dstReg destination register
41153 * @param srcIndex the source index register
41154 * @param srcScale the source scale
41155 * @param srcDisp the source displacement
41156 */
41157 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
41158 public final void emitPSRLQ_Reg_RegOff(MM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
41159 int miStart = mi;
41160 generateREXprefix(false, dstReg, srcIndex, null);
41161 setMachineCodes(mi++, (byte) 0x0F);
41162 setMachineCodes(mi++, (byte) 0xD3);
41163 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
41164 if (lister != null) lister.RRFD(miStart, "PSRLQ", dstReg, srcIndex, srcScale, srcDisp);
41165 }
41166
41167 /**
41168 * Generate a register--absolute PSRLQ. That is,
41169 * <PRE>
41170 * dstReg <<= (quad) [srcDisp]
41171 * </PRE>
41172 *
41173 * @param dstReg destination register
41174 * @param srcDisp the source displacement
41175 */
41176 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
41177 public final void emitPSRLQ_Reg_Abs(MM dstReg, Address srcDisp) {
41178 int miStart = mi;
41179 generateREXprefix(false, dstReg, null, null);
41180 setMachineCodes(mi++, (byte) 0x0F);
41181 setMachineCodes(mi++, (byte) 0xD3);
41182 emitAbsRegOperands(srcDisp, dstReg);
41183 if (lister != null) lister.RRA(miStart, "PSRLQ", dstReg, srcDisp);
41184 }
41185
41186 /**
41187 * Generate a register--register-index PSRLQ. That is,
41188 * <PRE>
41189 * dstReg <<= (quad) srcReg
41190 * </PRE>
41191 *
41192 * @param dstReg destination register
41193 * @param srcBase the source base register
41194 * @param srcIndex the source index register
41195 * @param srcScale the source scale
41196 * @param srcDisp the source displacement
41197 */
41198 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
41199 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
41200 public final void emitPSRLQ_Reg_RegIdx(MM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
41201 int miStart = mi;
41202 generateREXprefix(false, dstReg, srcIndex, srcBase);
41203 setMachineCodes(mi++, (byte) 0x0F);
41204 setMachineCodes(mi++, (byte) 0xD3);
41205 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
41206 if (lister != null) lister.RRXD(miStart, "PSRLQ", dstReg, srcBase, srcIndex, srcScale, srcDisp);
41207 }
41208
41209 /**
41210 * Generate a register--register-indirect PSRLQ. That is,
41211 * <PRE>
41212 * dstReg <<= (quad) [srcBase]
41213 * </PRE>
41214 *
41215 * @param dstReg destination register
41216 * @param srcBase the source base register
41217 */
41218 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
41219 public final void emitPSRLQ_Reg_RegInd(MM dstReg, GPR srcBase) {
41220 int miStart = mi;
41221 generateREXprefix(false, dstReg, null, srcBase);
41222 setMachineCodes(mi++, (byte) 0x0F);
41223 setMachineCodes(mi++, (byte) 0xD3);
41224 emitRegIndirectRegOperands(srcBase, dstReg);
41225 if (lister != null) lister.RRN(miStart, "PSRLQ", dstReg, srcBase);
41226 }
41227
41228
41229 /**
41230 * Generate a register--register PSLLQ. That is,
41231 * <PRE>
41232 * dstReg <<= (quad) srcReg
41233 * </PRE>
41234 *
41235 * @param dstReg destination register
41236 * @param srcReg source register
41237 */
41238 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
41239 public final void emitPSLLQ_Reg_Reg(XMM dstReg, XMM srcReg) {
41240 int miStart = mi;
41241 setMachineCodes(mi++, (byte) 0x66);
41242 generateREXprefix(false, dstReg, null, srcReg);
41243 setMachineCodes(mi++, (byte) 0x0F);
41244 setMachineCodes(mi++, (byte) 0xF3);
41245 emitRegRegOperands(srcReg, dstReg);
41246 if (lister != null) lister.RR(miStart, "PSLLQ", dstReg, srcReg);
41247 }
41248
41249 /**
41250 * Generate a register--register-displacement PSLLQ. That is,
41251 * <PRE>
41252 * dstReg <<= (quad) [srcBase + srcDisp]
41253 * </PRE>
41254 *
41255 * @param dstReg destination register
41256 * @param srcBase the source base register
41257 * @param srcDisp the source displacement
41258 */
41259 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
41260 public final void emitPSLLQ_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
41261 int miStart = mi;
41262 setMachineCodes(mi++, (byte) 0x66);
41263 generateREXprefix(false, dstReg, null, srcBase);
41264 setMachineCodes(mi++, (byte) 0x0F);
41265 setMachineCodes(mi++, (byte) 0xF3);
41266 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
41267 if (lister != null) lister.RRD(miStart, "PSLLQ", dstReg, srcBase, srcDisp);
41268 }
41269
41270 /**
41271 * Generate a register--register-offset PSLLQ. That is,
41272 * <PRE>
41273 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
41274 * </PRE>
41275 *
41276 * @param dstReg destination register
41277 * @param srcIndex the source index register
41278 * @param srcScale the source scale
41279 * @param srcDisp the source displacement
41280 */
41281 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
41282 public final void emitPSLLQ_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
41283 int miStart = mi;
41284 setMachineCodes(mi++, (byte) 0x66);
41285 generateREXprefix(false, dstReg, srcIndex, null);
41286 setMachineCodes(mi++, (byte) 0x0F);
41287 setMachineCodes(mi++, (byte) 0xF3);
41288 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
41289 if (lister != null) lister.RRFD(miStart, "PSLLQ", dstReg, srcIndex, srcScale, srcDisp);
41290 }
41291
41292 /**
41293 * Generate a register--absolute PSLLQ. That is,
41294 * <PRE>
41295 * dstReg <<= (quad) [srcDisp]
41296 * </PRE>
41297 *
41298 * @param dstReg destination register
41299 * @param srcDisp the source displacement
41300 */
41301 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
41302 public final void emitPSLLQ_Reg_Abs(XMM dstReg, Address srcDisp) {
41303 int miStart = mi;
41304 setMachineCodes(mi++, (byte) 0x66);
41305 generateREXprefix(false, dstReg, null, null);
41306 setMachineCodes(mi++, (byte) 0x0F);
41307 setMachineCodes(mi++, (byte) 0xF3);
41308 emitAbsRegOperands(srcDisp, dstReg);
41309 if (lister != null) lister.RRA(miStart, "PSLLQ", dstReg, srcDisp);
41310 }
41311
41312 /**
41313 * Generate a register--register-index PSLLQ. That is,
41314 * <PRE>
41315 * dstReg <<= (quad) srcReg
41316 * </PRE>
41317 *
41318 * @param dstReg destination register
41319 * @param srcBase the source base register
41320 * @param srcIndex the source index register
41321 * @param srcScale the source scale
41322 * @param srcDisp the source displacement
41323 */
41324 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
41325 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
41326 public final void emitPSLLQ_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
41327 int miStart = mi;
41328 setMachineCodes(mi++, (byte) 0x66);
41329 generateREXprefix(false, dstReg, srcIndex, srcBase);
41330 setMachineCodes(mi++, (byte) 0x0F);
41331 setMachineCodes(mi++, (byte) 0xF3);
41332 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
41333 if (lister != null) lister.RRXD(miStart, "PSLLQ", dstReg, srcBase, srcIndex, srcScale, srcDisp);
41334 }
41335
41336 /**
41337 * Generate a register--register-indirect PSLLQ. That is,
41338 * <PRE>
41339 * dstReg <<= (quad) [srcBase]
41340 * </PRE>
41341 *
41342 * @param dstReg destination register
41343 * @param srcBase the source base register
41344 */
41345 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
41346 public final void emitPSLLQ_Reg_RegInd(XMM dstReg, GPR srcBase) {
41347 int miStart = mi;
41348 setMachineCodes(mi++, (byte) 0x66);
41349 generateREXprefix(false, dstReg, null, srcBase);
41350 setMachineCodes(mi++, (byte) 0x0F);
41351 setMachineCodes(mi++, (byte) 0xF3);
41352 emitRegIndirectRegOperands(srcBase, dstReg);
41353 if (lister != null) lister.RRN(miStart, "PSLLQ", dstReg, srcBase);
41354 }
41355
41356
41357 /**
41358 * Generate a register--register PSRLQ. That is,
41359 * <PRE>
41360 * dstReg <<= (quad) srcReg
41361 * </PRE>
41362 *
41363 * @param dstReg destination register
41364 * @param srcReg source register
41365 */
41366 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
41367 public final void emitPSRLQ_Reg_Reg(XMM dstReg, XMM srcReg) {
41368 int miStart = mi;
41369 setMachineCodes(mi++, (byte) 0x66);
41370 generateREXprefix(false, dstReg, null, srcReg);
41371 setMachineCodes(mi++, (byte) 0x0F);
41372 setMachineCodes(mi++, (byte) 0xD3);
41373 emitRegRegOperands(srcReg, dstReg);
41374 if (lister != null) lister.RR(miStart, "PSRLQ", dstReg, srcReg);
41375 }
41376
41377 /**
41378 * Generate a register--register-displacement PSRLQ. That is,
41379 * <PRE>
41380 * dstReg <<= (quad) [srcBase + srcDisp]
41381 * </PRE>
41382 *
41383 * @param dstReg destination register
41384 * @param srcBase the source base register
41385 * @param srcDisp the source displacement
41386 */
41387 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
41388 public final void emitPSRLQ_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
41389 int miStart = mi;
41390 setMachineCodes(mi++, (byte) 0x66);
41391 generateREXprefix(false, dstReg, null, srcBase);
41392 setMachineCodes(mi++, (byte) 0x0F);
41393 setMachineCodes(mi++, (byte) 0xD3);
41394 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
41395 if (lister != null) lister.RRD(miStart, "PSRLQ", dstReg, srcBase, srcDisp);
41396 }
41397
41398 /**
41399 * Generate a register--register-offset PSRLQ. That is,
41400 * <PRE>
41401 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
41402 * </PRE>
41403 *
41404 * @param dstReg destination register
41405 * @param srcIndex the source index register
41406 * @param srcScale the source scale
41407 * @param srcDisp the source displacement
41408 */
41409 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
41410 public final void emitPSRLQ_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
41411 int miStart = mi;
41412 setMachineCodes(mi++, (byte) 0x66);
41413 generateREXprefix(false, dstReg, srcIndex, null);
41414 setMachineCodes(mi++, (byte) 0x0F);
41415 setMachineCodes(mi++, (byte) 0xD3);
41416 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
41417 if (lister != null) lister.RRFD(miStart, "PSRLQ", dstReg, srcIndex, srcScale, srcDisp);
41418 }
41419
41420 /**
41421 * Generate a register--absolute PSRLQ. That is,
41422 * <PRE>
41423 * dstReg <<= (quad) [srcDisp]
41424 * </PRE>
41425 *
41426 * @param dstReg destination register
41427 * @param srcDisp the source displacement
41428 */
41429 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
41430 public final void emitPSRLQ_Reg_Abs(XMM dstReg, Address srcDisp) {
41431 int miStart = mi;
41432 setMachineCodes(mi++, (byte) 0x66);
41433 generateREXprefix(false, dstReg, null, null);
41434 setMachineCodes(mi++, (byte) 0x0F);
41435 setMachineCodes(mi++, (byte) 0xD3);
41436 emitAbsRegOperands(srcDisp, dstReg);
41437 if (lister != null) lister.RRA(miStart, "PSRLQ", dstReg, srcDisp);
41438 }
41439
41440 /**
41441 * Generate a register--register-index PSRLQ. That is,
41442 * <PRE>
41443 * dstReg <<= (quad) srcReg
41444 * </PRE>
41445 *
41446 * @param dstReg destination register
41447 * @param srcBase the source base register
41448 * @param srcIndex the source index register
41449 * @param srcScale the source scale
41450 * @param srcDisp the source displacement
41451 */
41452 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
41453 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
41454 public final void emitPSRLQ_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
41455 int miStart = mi;
41456 setMachineCodes(mi++, (byte) 0x66);
41457 generateREXprefix(false, dstReg, srcIndex, srcBase);
41458 setMachineCodes(mi++, (byte) 0x0F);
41459 setMachineCodes(mi++, (byte) 0xD3);
41460 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
41461 if (lister != null) lister.RRXD(miStart, "PSRLQ", dstReg, srcBase, srcIndex, srcScale, srcDisp);
41462 }
41463
41464 /**
41465 * Generate a register--register-indirect PSRLQ. That is,
41466 * <PRE>
41467 * dstReg <<= (quad) [srcBase]
41468 * </PRE>
41469 *
41470 * @param dstReg destination register
41471 * @param srcBase the source base register
41472 */
41473 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
41474 public final void emitPSRLQ_Reg_RegInd(XMM dstReg, GPR srcBase) {
41475 int miStart = mi;
41476 setMachineCodes(mi++, (byte) 0x66);
41477 generateREXprefix(false, dstReg, null, srcBase);
41478 setMachineCodes(mi++, (byte) 0x0F);
41479 setMachineCodes(mi++, (byte) 0xD3);
41480 emitRegIndirectRegOperands(srcBase, dstReg);
41481 if (lister != null) lister.RRN(miStart, "PSRLQ", dstReg, srcBase);
41482 }
41483
41484
41485 /**
41486 * Generate a register--register ANDPS. That is,
41487 * <PRE>
41488 * dstReg <<= (quad) srcReg
41489 * </PRE>
41490 *
41491 * @param dstReg destination register
41492 * @param srcReg source register
41493 */
41494 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
41495 public final void emitANDPS_Reg_Reg(XMM dstReg, XMM srcReg) {
41496 int miStart = mi;
41497 generateREXprefix(false, dstReg, null, srcReg);
41498 setMachineCodes(mi++, (byte) 0x0F);
41499 setMachineCodes(mi++, (byte) 0x54);
41500 emitRegRegOperands(srcReg, dstReg);
41501 if (lister != null) lister.RR(miStart, "ANDPS", dstReg, srcReg);
41502 }
41503
41504 /**
41505 * Generate a register--register-displacement ANDPS. That is,
41506 * <PRE>
41507 * dstReg <<= (quad) [srcBase + srcDisp]
41508 * </PRE>
41509 *
41510 * @param dstReg destination register
41511 * @param srcBase the source base register
41512 * @param srcDisp the source displacement
41513 */
41514 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
41515 public final void emitANDPS_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
41516 int miStart = mi;
41517 generateREXprefix(false, dstReg, null, srcBase);
41518 setMachineCodes(mi++, (byte) 0x0F);
41519 setMachineCodes(mi++, (byte) 0x54);
41520 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
41521 if (lister != null) lister.RRD(miStart, "ANDPS", dstReg, srcBase, srcDisp);
41522 }
41523
41524 /**
41525 * Generate a register--register-offset ANDPS. That is,
41526 * <PRE>
41527 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
41528 * </PRE>
41529 *
41530 * @param dstReg destination register
41531 * @param srcIndex the source index register
41532 * @param srcScale the source scale
41533 * @param srcDisp the source displacement
41534 */
41535 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
41536 public final void emitANDPS_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
41537 int miStart = mi;
41538 generateREXprefix(false, dstReg, srcIndex, null);
41539 setMachineCodes(mi++, (byte) 0x0F);
41540 setMachineCodes(mi++, (byte) 0x54);
41541 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
41542 if (lister != null) lister.RRFD(miStart, "ANDPS", dstReg, srcIndex, srcScale, srcDisp);
41543 }
41544
41545 /**
41546 * Generate a register--absolute ANDPS. That is,
41547 * <PRE>
41548 * dstReg <<= (quad) [srcDisp]
41549 * </PRE>
41550 *
41551 * @param dstReg destination register
41552 * @param srcDisp the source displacement
41553 */
41554 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
41555 public final void emitANDPS_Reg_Abs(XMM dstReg, Address srcDisp) {
41556 int miStart = mi;
41557 generateREXprefix(false, dstReg, null, null);
41558 setMachineCodes(mi++, (byte) 0x0F);
41559 setMachineCodes(mi++, (byte) 0x54);
41560 emitAbsRegOperands(srcDisp, dstReg);
41561 if (lister != null) lister.RRA(miStart, "ANDPS", dstReg, srcDisp);
41562 }
41563
41564 /**
41565 * Generate a register--register-index ANDPS. That is,
41566 * <PRE>
41567 * dstReg <<= (quad) srcReg
41568 * </PRE>
41569 *
41570 * @param dstReg destination register
41571 * @param srcBase the source base register
41572 * @param srcIndex the source index register
41573 * @param srcScale the source scale
41574 * @param srcDisp the source displacement
41575 */
41576 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
41577 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
41578 public final void emitANDPS_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
41579 int miStart = mi;
41580 generateREXprefix(false, dstReg, srcIndex, srcBase);
41581 setMachineCodes(mi++, (byte) 0x0F);
41582 setMachineCodes(mi++, (byte) 0x54);
41583 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
41584 if (lister != null) lister.RRXD(miStart, "ANDPS", dstReg, srcBase, srcIndex, srcScale, srcDisp);
41585 }
41586
41587 /**
41588 * Generate a register--register-indirect ANDPS. That is,
41589 * <PRE>
41590 * dstReg <<= (quad) [srcBase]
41591 * </PRE>
41592 *
41593 * @param dstReg destination register
41594 * @param srcBase the source base register
41595 */
41596 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
41597 public final void emitANDPS_Reg_RegInd(XMM dstReg, GPR srcBase) {
41598 int miStart = mi;
41599 generateREXprefix(false, dstReg, null, srcBase);
41600 setMachineCodes(mi++, (byte) 0x0F);
41601 setMachineCodes(mi++, (byte) 0x54);
41602 emitRegIndirectRegOperands(srcBase, dstReg);
41603 if (lister != null) lister.RRN(miStart, "ANDPS", dstReg, srcBase);
41604 }
41605
41606
41607 /**
41608 * Generate a register--register ANDPD. That is,
41609 * <PRE>
41610 * dstReg <<= (quad) srcReg
41611 * </PRE>
41612 *
41613 * @param dstReg destination register
41614 * @param srcReg source register
41615 */
41616 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
41617 public final void emitANDPD_Reg_Reg(XMM dstReg, XMM srcReg) {
41618 int miStart = mi;
41619 setMachineCodes(mi++, (byte) 0x66);
41620 generateREXprefix(false, dstReg, null, srcReg);
41621 setMachineCodes(mi++, (byte) 0x0F);
41622 setMachineCodes(mi++, (byte) 0x54);
41623 emitRegRegOperands(srcReg, dstReg);
41624 if (lister != null) lister.RR(miStart, "ANDPD", dstReg, srcReg);
41625 }
41626
41627 /**
41628 * Generate a register--register-displacement ANDPD. That is,
41629 * <PRE>
41630 * dstReg <<= (quad) [srcBase + srcDisp]
41631 * </PRE>
41632 *
41633 * @param dstReg destination register
41634 * @param srcBase the source base register
41635 * @param srcDisp the source displacement
41636 */
41637 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
41638 public final void emitANDPD_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
41639 int miStart = mi;
41640 setMachineCodes(mi++, (byte) 0x66);
41641 generateREXprefix(false, dstReg, null, srcBase);
41642 setMachineCodes(mi++, (byte) 0x0F);
41643 setMachineCodes(mi++, (byte) 0x54);
41644 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
41645 if (lister != null) lister.RRD(miStart, "ANDPD", dstReg, srcBase, srcDisp);
41646 }
41647
41648 /**
41649 * Generate a register--register-offset ANDPD. That is,
41650 * <PRE>
41651 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
41652 * </PRE>
41653 *
41654 * @param dstReg destination register
41655 * @param srcIndex the source index register
41656 * @param srcScale the source scale
41657 * @param srcDisp the source displacement
41658 */
41659 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
41660 public final void emitANDPD_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
41661 int miStart = mi;
41662 setMachineCodes(mi++, (byte) 0x66);
41663 generateREXprefix(false, dstReg, srcIndex, null);
41664 setMachineCodes(mi++, (byte) 0x0F);
41665 setMachineCodes(mi++, (byte) 0x54);
41666 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
41667 if (lister != null) lister.RRFD(miStart, "ANDPD", dstReg, srcIndex, srcScale, srcDisp);
41668 }
41669
41670 /**
41671 * Generate a register--absolute ANDPD. That is,
41672 * <PRE>
41673 * dstReg <<= (quad) [srcDisp]
41674 * </PRE>
41675 *
41676 * @param dstReg destination register
41677 * @param srcDisp the source displacement
41678 */
41679 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
41680 public final void emitANDPD_Reg_Abs(XMM dstReg, Address srcDisp) {
41681 int miStart = mi;
41682 setMachineCodes(mi++, (byte) 0x66);
41683 generateREXprefix(false, dstReg, null, null);
41684 setMachineCodes(mi++, (byte) 0x0F);
41685 setMachineCodes(mi++, (byte) 0x54);
41686 emitAbsRegOperands(srcDisp, dstReg);
41687 if (lister != null) lister.RRA(miStart, "ANDPD", dstReg, srcDisp);
41688 }
41689
41690 /**
41691 * Generate a register--register-index ANDPD. That is,
41692 * <PRE>
41693 * dstReg <<= (quad) srcReg
41694 * </PRE>
41695 *
41696 * @param dstReg destination register
41697 * @param srcBase the source base register
41698 * @param srcIndex the source index register
41699 * @param srcScale the source scale
41700 * @param srcDisp the source displacement
41701 */
41702 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
41703 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
41704 public final void emitANDPD_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
41705 int miStart = mi;
41706 setMachineCodes(mi++, (byte) 0x66);
41707 generateREXprefix(false, dstReg, srcIndex, srcBase);
41708 setMachineCodes(mi++, (byte) 0x0F);
41709 setMachineCodes(mi++, (byte) 0x54);
41710 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
41711 if (lister != null) lister.RRXD(miStart, "ANDPD", dstReg, srcBase, srcIndex, srcScale, srcDisp);
41712 }
41713
41714 /**
41715 * Generate a register--register-indirect ANDPD. That is,
41716 * <PRE>
41717 * dstReg <<= (quad) [srcBase]
41718 * </PRE>
41719 *
41720 * @param dstReg destination register
41721 * @param srcBase the source base register
41722 */
41723 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
41724 public final void emitANDPD_Reg_RegInd(XMM dstReg, GPR srcBase) {
41725 int miStart = mi;
41726 setMachineCodes(mi++, (byte) 0x66);
41727 generateREXprefix(false, dstReg, null, srcBase);
41728 setMachineCodes(mi++, (byte) 0x0F);
41729 setMachineCodes(mi++, (byte) 0x54);
41730 emitRegIndirectRegOperands(srcBase, dstReg);
41731 if (lister != null) lister.RRN(miStart, "ANDPD", dstReg, srcBase);
41732 }
41733
41734
41735 /**
41736 * Generate a register--register ANDNPS. That is,
41737 * <PRE>
41738 * dstReg <<= (quad) srcReg
41739 * </PRE>
41740 *
41741 * @param dstReg destination register
41742 * @param srcReg source register
41743 */
41744 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
41745 public final void emitANDNPS_Reg_Reg(XMM dstReg, XMM srcReg) {
41746 int miStart = mi;
41747 generateREXprefix(false, dstReg, null, srcReg);
41748 setMachineCodes(mi++, (byte) 0x0F);
41749 setMachineCodes(mi++, (byte) 0x55);
41750 emitRegRegOperands(srcReg, dstReg);
41751 if (lister != null) lister.RR(miStart, "ANDNPS", dstReg, srcReg);
41752 }
41753
41754 /**
41755 * Generate a register--register-displacement ANDNPS. That is,
41756 * <PRE>
41757 * dstReg <<= (quad) [srcBase + srcDisp]
41758 * </PRE>
41759 *
41760 * @param dstReg destination register
41761 * @param srcBase the source base register
41762 * @param srcDisp the source displacement
41763 */
41764 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
41765 public final void emitANDNPS_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
41766 int miStart = mi;
41767 generateREXprefix(false, dstReg, null, srcBase);
41768 setMachineCodes(mi++, (byte) 0x0F);
41769 setMachineCodes(mi++, (byte) 0x55);
41770 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
41771 if (lister != null) lister.RRD(miStart, "ANDNPS", dstReg, srcBase, srcDisp);
41772 }
41773
41774 /**
41775 * Generate a register--register-offset ANDNPS. That is,
41776 * <PRE>
41777 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
41778 * </PRE>
41779 *
41780 * @param dstReg destination register
41781 * @param srcIndex the source index register
41782 * @param srcScale the source scale
41783 * @param srcDisp the source displacement
41784 */
41785 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
41786 public final void emitANDNPS_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
41787 int miStart = mi;
41788 generateREXprefix(false, dstReg, srcIndex, null);
41789 setMachineCodes(mi++, (byte) 0x0F);
41790 setMachineCodes(mi++, (byte) 0x55);
41791 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
41792 if (lister != null) lister.RRFD(miStart, "ANDNPS", dstReg, srcIndex, srcScale, srcDisp);
41793 }
41794
41795 /**
41796 * Generate a register--absolute ANDNPS. That is,
41797 * <PRE>
41798 * dstReg <<= (quad) [srcDisp]
41799 * </PRE>
41800 *
41801 * @param dstReg destination register
41802 * @param srcDisp the source displacement
41803 */
41804 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
41805 public final void emitANDNPS_Reg_Abs(XMM dstReg, Address srcDisp) {
41806 int miStart = mi;
41807 generateREXprefix(false, dstReg, null, null);
41808 setMachineCodes(mi++, (byte) 0x0F);
41809 setMachineCodes(mi++, (byte) 0x55);
41810 emitAbsRegOperands(srcDisp, dstReg);
41811 if (lister != null) lister.RRA(miStart, "ANDNPS", dstReg, srcDisp);
41812 }
41813
41814 /**
41815 * Generate a register--register-index ANDNPS. That is,
41816 * <PRE>
41817 * dstReg <<= (quad) srcReg
41818 * </PRE>
41819 *
41820 * @param dstReg destination register
41821 * @param srcBase the source base register
41822 * @param srcIndex the source index register
41823 * @param srcScale the source scale
41824 * @param srcDisp the source displacement
41825 */
41826 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
41827 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
41828 public final void emitANDNPS_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
41829 int miStart = mi;
41830 generateREXprefix(false, dstReg, srcIndex, srcBase);
41831 setMachineCodes(mi++, (byte) 0x0F);
41832 setMachineCodes(mi++, (byte) 0x55);
41833 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
41834 if (lister != null) lister.RRXD(miStart, "ANDNPS", dstReg, srcBase, srcIndex, srcScale, srcDisp);
41835 }
41836
41837 /**
41838 * Generate a register--register-indirect ANDNPS. That is,
41839 * <PRE>
41840 * dstReg <<= (quad) [srcBase]
41841 * </PRE>
41842 *
41843 * @param dstReg destination register
41844 * @param srcBase the source base register
41845 */
41846 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
41847 public final void emitANDNPS_Reg_RegInd(XMM dstReg, GPR srcBase) {
41848 int miStart = mi;
41849 generateREXprefix(false, dstReg, null, srcBase);
41850 setMachineCodes(mi++, (byte) 0x0F);
41851 setMachineCodes(mi++, (byte) 0x55);
41852 emitRegIndirectRegOperands(srcBase, dstReg);
41853 if (lister != null) lister.RRN(miStart, "ANDNPS", dstReg, srcBase);
41854 }
41855
41856
41857 /**
41858 * Generate a register--register ANDNPD. That is,
41859 * <PRE>
41860 * dstReg <<= (quad) srcReg
41861 * </PRE>
41862 *
41863 * @param dstReg destination register
41864 * @param srcReg source register
41865 */
41866 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
41867 public final void emitANDNPD_Reg_Reg(XMM dstReg, XMM srcReg) {
41868 int miStart = mi;
41869 setMachineCodes(mi++, (byte) 0x66);
41870 generateREXprefix(false, dstReg, null, srcReg);
41871 setMachineCodes(mi++, (byte) 0x0F);
41872 setMachineCodes(mi++, (byte) 0x55);
41873 emitRegRegOperands(srcReg, dstReg);
41874 if (lister != null) lister.RR(miStart, "ANDNPD", dstReg, srcReg);
41875 }
41876
41877 /**
41878 * Generate a register--register-displacement ANDNPD. That is,
41879 * <PRE>
41880 * dstReg <<= (quad) [srcBase + srcDisp]
41881 * </PRE>
41882 *
41883 * @param dstReg destination register
41884 * @param srcBase the source base register
41885 * @param srcDisp the source displacement
41886 */
41887 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
41888 public final void emitANDNPD_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
41889 int miStart = mi;
41890 setMachineCodes(mi++, (byte) 0x66);
41891 generateREXprefix(false, dstReg, null, srcBase);
41892 setMachineCodes(mi++, (byte) 0x0F);
41893 setMachineCodes(mi++, (byte) 0x55);
41894 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
41895 if (lister != null) lister.RRD(miStart, "ANDNPD", dstReg, srcBase, srcDisp);
41896 }
41897
41898 /**
41899 * Generate a register--register-offset ANDNPD. That is,
41900 * <PRE>
41901 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
41902 * </PRE>
41903 *
41904 * @param dstReg destination register
41905 * @param srcIndex the source index register
41906 * @param srcScale the source scale
41907 * @param srcDisp the source displacement
41908 */
41909 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
41910 public final void emitANDNPD_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
41911 int miStart = mi;
41912 setMachineCodes(mi++, (byte) 0x66);
41913 generateREXprefix(false, dstReg, srcIndex, null);
41914 setMachineCodes(mi++, (byte) 0x0F);
41915 setMachineCodes(mi++, (byte) 0x55);
41916 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
41917 if (lister != null) lister.RRFD(miStart, "ANDNPD", dstReg, srcIndex, srcScale, srcDisp);
41918 }
41919
41920 /**
41921 * Generate a register--absolute ANDNPD. That is,
41922 * <PRE>
41923 * dstReg <<= (quad) [srcDisp]
41924 * </PRE>
41925 *
41926 * @param dstReg destination register
41927 * @param srcDisp the source displacement
41928 */
41929 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
41930 public final void emitANDNPD_Reg_Abs(XMM dstReg, Address srcDisp) {
41931 int miStart = mi;
41932 setMachineCodes(mi++, (byte) 0x66);
41933 generateREXprefix(false, dstReg, null, null);
41934 setMachineCodes(mi++, (byte) 0x0F);
41935 setMachineCodes(mi++, (byte) 0x55);
41936 emitAbsRegOperands(srcDisp, dstReg);
41937 if (lister != null) lister.RRA(miStart, "ANDNPD", dstReg, srcDisp);
41938 }
41939
41940 /**
41941 * Generate a register--register-index ANDNPD. That is,
41942 * <PRE>
41943 * dstReg <<= (quad) srcReg
41944 * </PRE>
41945 *
41946 * @param dstReg destination register
41947 * @param srcBase the source base register
41948 * @param srcIndex the source index register
41949 * @param srcScale the source scale
41950 * @param srcDisp the source displacement
41951 */
41952 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
41953 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
41954 public final void emitANDNPD_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
41955 int miStart = mi;
41956 setMachineCodes(mi++, (byte) 0x66);
41957 generateREXprefix(false, dstReg, srcIndex, srcBase);
41958 setMachineCodes(mi++, (byte) 0x0F);
41959 setMachineCodes(mi++, (byte) 0x55);
41960 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
41961 if (lister != null) lister.RRXD(miStart, "ANDNPD", dstReg, srcBase, srcIndex, srcScale, srcDisp);
41962 }
41963
41964 /**
41965 * Generate a register--register-indirect ANDNPD. That is,
41966 * <PRE>
41967 * dstReg <<= (quad) [srcBase]
41968 * </PRE>
41969 *
41970 * @param dstReg destination register
41971 * @param srcBase the source base register
41972 */
41973 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
41974 public final void emitANDNPD_Reg_RegInd(XMM dstReg, GPR srcBase) {
41975 int miStart = mi;
41976 setMachineCodes(mi++, (byte) 0x66);
41977 generateREXprefix(false, dstReg, null, srcBase);
41978 setMachineCodes(mi++, (byte) 0x0F);
41979 setMachineCodes(mi++, (byte) 0x55);
41980 emitRegIndirectRegOperands(srcBase, dstReg);
41981 if (lister != null) lister.RRN(miStart, "ANDNPD", dstReg, srcBase);
41982 }
41983
41984
41985 /**
41986 * Generate a register--register ORPS. That is,
41987 * <PRE>
41988 * dstReg <<= (quad) srcReg
41989 * </PRE>
41990 *
41991 * @param dstReg destination register
41992 * @param srcReg source register
41993 */
41994 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
41995 public final void emitORPS_Reg_Reg(XMM dstReg, XMM srcReg) {
41996 int miStart = mi;
41997 generateREXprefix(false, dstReg, null, srcReg);
41998 setMachineCodes(mi++, (byte) 0x0F);
41999 setMachineCodes(mi++, (byte) 0x56);
42000 emitRegRegOperands(srcReg, dstReg);
42001 if (lister != null) lister.RR(miStart, "ORPS", dstReg, srcReg);
42002 }
42003
42004 /**
42005 * Generate a register--register-displacement ORPS. That is,
42006 * <PRE>
42007 * dstReg <<= (quad) [srcBase + srcDisp]
42008 * </PRE>
42009 *
42010 * @param dstReg destination register
42011 * @param srcBase the source base register
42012 * @param srcDisp the source displacement
42013 */
42014 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
42015 public final void emitORPS_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
42016 int miStart = mi;
42017 generateREXprefix(false, dstReg, null, srcBase);
42018 setMachineCodes(mi++, (byte) 0x0F);
42019 setMachineCodes(mi++, (byte) 0x56);
42020 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
42021 if (lister != null) lister.RRD(miStart, "ORPS", dstReg, srcBase, srcDisp);
42022 }
42023
42024 /**
42025 * Generate a register--register-offset ORPS. That is,
42026 * <PRE>
42027 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
42028 * </PRE>
42029 *
42030 * @param dstReg destination register
42031 * @param srcIndex the source index register
42032 * @param srcScale the source scale
42033 * @param srcDisp the source displacement
42034 */
42035 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
42036 public final void emitORPS_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
42037 int miStart = mi;
42038 generateREXprefix(false, dstReg, srcIndex, null);
42039 setMachineCodes(mi++, (byte) 0x0F);
42040 setMachineCodes(mi++, (byte) 0x56);
42041 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
42042 if (lister != null) lister.RRFD(miStart, "ORPS", dstReg, srcIndex, srcScale, srcDisp);
42043 }
42044
42045 /**
42046 * Generate a register--absolute ORPS. That is,
42047 * <PRE>
42048 * dstReg <<= (quad) [srcDisp]
42049 * </PRE>
42050 *
42051 * @param dstReg destination register
42052 * @param srcDisp the source displacement
42053 */
42054 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
42055 public final void emitORPS_Reg_Abs(XMM dstReg, Address srcDisp) {
42056 int miStart = mi;
42057 generateREXprefix(false, dstReg, null, null);
42058 setMachineCodes(mi++, (byte) 0x0F);
42059 setMachineCodes(mi++, (byte) 0x56);
42060 emitAbsRegOperands(srcDisp, dstReg);
42061 if (lister != null) lister.RRA(miStart, "ORPS", dstReg, srcDisp);
42062 }
42063
42064 /**
42065 * Generate a register--register-index ORPS. That is,
42066 * <PRE>
42067 * dstReg <<= (quad) srcReg
42068 * </PRE>
42069 *
42070 * @param dstReg destination register
42071 * @param srcBase the source base register
42072 * @param srcIndex the source index register
42073 * @param srcScale the source scale
42074 * @param srcDisp the source displacement
42075 */
42076 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
42077 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
42078 public final void emitORPS_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
42079 int miStart = mi;
42080 generateREXprefix(false, dstReg, srcIndex, srcBase);
42081 setMachineCodes(mi++, (byte) 0x0F);
42082 setMachineCodes(mi++, (byte) 0x56);
42083 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
42084 if (lister != null) lister.RRXD(miStart, "ORPS", dstReg, srcBase, srcIndex, srcScale, srcDisp);
42085 }
42086
42087 /**
42088 * Generate a register--register-indirect ORPS. That is,
42089 * <PRE>
42090 * dstReg <<= (quad) [srcBase]
42091 * </PRE>
42092 *
42093 * @param dstReg destination register
42094 * @param srcBase the source base register
42095 */
42096 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
42097 public final void emitORPS_Reg_RegInd(XMM dstReg, GPR srcBase) {
42098 int miStart = mi;
42099 generateREXprefix(false, dstReg, null, srcBase);
42100 setMachineCodes(mi++, (byte) 0x0F);
42101 setMachineCodes(mi++, (byte) 0x56);
42102 emitRegIndirectRegOperands(srcBase, dstReg);
42103 if (lister != null) lister.RRN(miStart, "ORPS", dstReg, srcBase);
42104 }
42105
42106
42107 /**
42108 * Generate a register--register ORPD. That is,
42109 * <PRE>
42110 * dstReg <<= (quad) srcReg
42111 * </PRE>
42112 *
42113 * @param dstReg destination register
42114 * @param srcReg source register
42115 */
42116 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
42117 public final void emitORPD_Reg_Reg(XMM dstReg, XMM srcReg) {
42118 int miStart = mi;
42119 setMachineCodes(mi++, (byte) 0x66);
42120 generateREXprefix(false, dstReg, null, srcReg);
42121 setMachineCodes(mi++, (byte) 0x0F);
42122 setMachineCodes(mi++, (byte) 0x56);
42123 emitRegRegOperands(srcReg, dstReg);
42124 if (lister != null) lister.RR(miStart, "ORPD", dstReg, srcReg);
42125 }
42126
42127 /**
42128 * Generate a register--register-displacement ORPD. That is,
42129 * <PRE>
42130 * dstReg <<= (quad) [srcBase + srcDisp]
42131 * </PRE>
42132 *
42133 * @param dstReg destination register
42134 * @param srcBase the source base register
42135 * @param srcDisp the source displacement
42136 */
42137 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
42138 public final void emitORPD_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
42139 int miStart = mi;
42140 setMachineCodes(mi++, (byte) 0x66);
42141 generateREXprefix(false, dstReg, null, srcBase);
42142 setMachineCodes(mi++, (byte) 0x0F);
42143 setMachineCodes(mi++, (byte) 0x56);
42144 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
42145 if (lister != null) lister.RRD(miStart, "ORPD", dstReg, srcBase, srcDisp);
42146 }
42147
42148 /**
42149 * Generate a register--register-offset ORPD. That is,
42150 * <PRE>
42151 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
42152 * </PRE>
42153 *
42154 * @param dstReg destination register
42155 * @param srcIndex the source index register
42156 * @param srcScale the source scale
42157 * @param srcDisp the source displacement
42158 */
42159 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
42160 public final void emitORPD_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
42161 int miStart = mi;
42162 setMachineCodes(mi++, (byte) 0x66);
42163 generateREXprefix(false, dstReg, srcIndex, null);
42164 setMachineCodes(mi++, (byte) 0x0F);
42165 setMachineCodes(mi++, (byte) 0x56);
42166 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
42167 if (lister != null) lister.RRFD(miStart, "ORPD", dstReg, srcIndex, srcScale, srcDisp);
42168 }
42169
42170 /**
42171 * Generate a register--absolute ORPD. That is,
42172 * <PRE>
42173 * dstReg <<= (quad) [srcDisp]
42174 * </PRE>
42175 *
42176 * @param dstReg destination register
42177 * @param srcDisp the source displacement
42178 */
42179 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
42180 public final void emitORPD_Reg_Abs(XMM dstReg, Address srcDisp) {
42181 int miStart = mi;
42182 setMachineCodes(mi++, (byte) 0x66);
42183 generateREXprefix(false, dstReg, null, null);
42184 setMachineCodes(mi++, (byte) 0x0F);
42185 setMachineCodes(mi++, (byte) 0x56);
42186 emitAbsRegOperands(srcDisp, dstReg);
42187 if (lister != null) lister.RRA(miStart, "ORPD", dstReg, srcDisp);
42188 }
42189
42190 /**
42191 * Generate a register--register-index ORPD. That is,
42192 * <PRE>
42193 * dstReg <<= (quad) srcReg
42194 * </PRE>
42195 *
42196 * @param dstReg destination register
42197 * @param srcBase the source base register
42198 * @param srcIndex the source index register
42199 * @param srcScale the source scale
42200 * @param srcDisp the source displacement
42201 */
42202 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
42203 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
42204 public final void emitORPD_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
42205 int miStart = mi;
42206 setMachineCodes(mi++, (byte) 0x66);
42207 generateREXprefix(false, dstReg, srcIndex, srcBase);
42208 setMachineCodes(mi++, (byte) 0x0F);
42209 setMachineCodes(mi++, (byte) 0x56);
42210 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
42211 if (lister != null) lister.RRXD(miStart, "ORPD", dstReg, srcBase, srcIndex, srcScale, srcDisp);
42212 }
42213
42214 /**
42215 * Generate a register--register-indirect ORPD. That is,
42216 * <PRE>
42217 * dstReg <<= (quad) [srcBase]
42218 * </PRE>
42219 *
42220 * @param dstReg destination register
42221 * @param srcBase the source base register
42222 */
42223 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
42224 public final void emitORPD_Reg_RegInd(XMM dstReg, GPR srcBase) {
42225 int miStart = mi;
42226 setMachineCodes(mi++, (byte) 0x66);
42227 generateREXprefix(false, dstReg, null, srcBase);
42228 setMachineCodes(mi++, (byte) 0x0F);
42229 setMachineCodes(mi++, (byte) 0x56);
42230 emitRegIndirectRegOperands(srcBase, dstReg);
42231 if (lister != null) lister.RRN(miStart, "ORPD", dstReg, srcBase);
42232 }
42233
42234
42235 /**
42236 * Generate a register--register XORPS. That is,
42237 * <PRE>
42238 * dstReg <<= (quad) srcReg
42239 * </PRE>
42240 *
42241 * @param dstReg destination register
42242 * @param srcReg source register
42243 */
42244 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
42245 public final void emitXORPS_Reg_Reg(XMM dstReg, XMM srcReg) {
42246 int miStart = mi;
42247 generateREXprefix(false, dstReg, null, srcReg);
42248 setMachineCodes(mi++, (byte) 0x0F);
42249 setMachineCodes(mi++, (byte) 0x57);
42250 emitRegRegOperands(srcReg, dstReg);
42251 if (lister != null) lister.RR(miStart, "XORPS", dstReg, srcReg);
42252 }
42253
42254 /**
42255 * Generate a register--register-displacement XORPS. That is,
42256 * <PRE>
42257 * dstReg <<= (quad) [srcBase + srcDisp]
42258 * </PRE>
42259 *
42260 * @param dstReg destination register
42261 * @param srcBase the source base register
42262 * @param srcDisp the source displacement
42263 */
42264 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
42265 public final void emitXORPS_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
42266 int miStart = mi;
42267 generateREXprefix(false, dstReg, null, srcBase);
42268 setMachineCodes(mi++, (byte) 0x0F);
42269 setMachineCodes(mi++, (byte) 0x57);
42270 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
42271 if (lister != null) lister.RRD(miStart, "XORPS", dstReg, srcBase, srcDisp);
42272 }
42273
42274 /**
42275 * Generate a register--register-offset XORPS. That is,
42276 * <PRE>
42277 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
42278 * </PRE>
42279 *
42280 * @param dstReg destination register
42281 * @param srcIndex the source index register
42282 * @param srcScale the source scale
42283 * @param srcDisp the source displacement
42284 */
42285 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
42286 public final void emitXORPS_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
42287 int miStart = mi;
42288 generateREXprefix(false, dstReg, srcIndex, null);
42289 setMachineCodes(mi++, (byte) 0x0F);
42290 setMachineCodes(mi++, (byte) 0x57);
42291 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
42292 if (lister != null) lister.RRFD(miStart, "XORPS", dstReg, srcIndex, srcScale, srcDisp);
42293 }
42294
42295 /**
42296 * Generate a register--absolute XORPS. That is,
42297 * <PRE>
42298 * dstReg <<= (quad) [srcDisp]
42299 * </PRE>
42300 *
42301 * @param dstReg destination register
42302 * @param srcDisp the source displacement
42303 */
42304 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
42305 public final void emitXORPS_Reg_Abs(XMM dstReg, Address srcDisp) {
42306 int miStart = mi;
42307 generateREXprefix(false, dstReg, null, null);
42308 setMachineCodes(mi++, (byte) 0x0F);
42309 setMachineCodes(mi++, (byte) 0x57);
42310 emitAbsRegOperands(srcDisp, dstReg);
42311 if (lister != null) lister.RRA(miStart, "XORPS", dstReg, srcDisp);
42312 }
42313
42314 /**
42315 * Generate a register--register-index XORPS. That is,
42316 * <PRE>
42317 * dstReg <<= (quad) srcReg
42318 * </PRE>
42319 *
42320 * @param dstReg destination register
42321 * @param srcBase the source base register
42322 * @param srcIndex the source index register
42323 * @param srcScale the source scale
42324 * @param srcDisp the source displacement
42325 */
42326 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
42327 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
42328 public final void emitXORPS_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
42329 int miStart = mi;
42330 generateREXprefix(false, dstReg, srcIndex, srcBase);
42331 setMachineCodes(mi++, (byte) 0x0F);
42332 setMachineCodes(mi++, (byte) 0x57);
42333 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
42334 if (lister != null) lister.RRXD(miStart, "XORPS", dstReg, srcBase, srcIndex, srcScale, srcDisp);
42335 }
42336
42337 /**
42338 * Generate a register--register-indirect XORPS. That is,
42339 * <PRE>
42340 * dstReg <<= (quad) [srcBase]
42341 * </PRE>
42342 *
42343 * @param dstReg destination register
42344 * @param srcBase the source base register
42345 */
42346 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
42347 public final void emitXORPS_Reg_RegInd(XMM dstReg, GPR srcBase) {
42348 int miStart = mi;
42349 generateREXprefix(false, dstReg, null, srcBase);
42350 setMachineCodes(mi++, (byte) 0x0F);
42351 setMachineCodes(mi++, (byte) 0x57);
42352 emitRegIndirectRegOperands(srcBase, dstReg);
42353 if (lister != null) lister.RRN(miStart, "XORPS", dstReg, srcBase);
42354 }
42355
42356
42357 /**
42358 * Generate a register--register XORPD. That is,
42359 * <PRE>
42360 * dstReg <<= (quad) srcReg
42361 * </PRE>
42362 *
42363 * @param dstReg destination register
42364 * @param srcReg source register
42365 */
42366 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
42367 public final void emitXORPD_Reg_Reg(XMM dstReg, XMM srcReg) {
42368 int miStart = mi;
42369 setMachineCodes(mi++, (byte) 0x66);
42370 generateREXprefix(false, dstReg, null, srcReg);
42371 setMachineCodes(mi++, (byte) 0x0F);
42372 setMachineCodes(mi++, (byte) 0x57);
42373 emitRegRegOperands(srcReg, dstReg);
42374 if (lister != null) lister.RR(miStart, "XORPD", dstReg, srcReg);
42375 }
42376
42377 /**
42378 * Generate a register--register-displacement XORPD. That is,
42379 * <PRE>
42380 * dstReg <<= (quad) [srcBase + srcDisp]
42381 * </PRE>
42382 *
42383 * @param dstReg destination register
42384 * @param srcBase the source base register
42385 * @param srcDisp the source displacement
42386 */
42387 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
42388 public final void emitXORPD_Reg_RegDisp(XMM dstReg, GPR srcBase, Offset srcDisp) {
42389 int miStart = mi;
42390 setMachineCodes(mi++, (byte) 0x66);
42391 generateREXprefix(false, dstReg, null, srcBase);
42392 setMachineCodes(mi++, (byte) 0x0F);
42393 setMachineCodes(mi++, (byte) 0x57);
42394 emitRegDispRegOperands(srcBase, srcDisp, dstReg);
42395 if (lister != null) lister.RRD(miStart, "XORPD", dstReg, srcBase, srcDisp);
42396 }
42397
42398 /**
42399 * Generate a register--register-offset XORPD. That is,
42400 * <PRE>
42401 * dstReg <<= (quad) [srcIndex<<srcScale + srcDisp]
42402 * </PRE>
42403 *
42404 * @param dstReg destination register
42405 * @param srcIndex the source index register
42406 * @param srcScale the source scale
42407 * @param srcDisp the source displacement
42408 */
42409 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
42410 public final void emitXORPD_Reg_RegOff(XMM dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
42411 int miStart = mi;
42412 setMachineCodes(mi++, (byte) 0x66);
42413 generateREXprefix(false, dstReg, srcIndex, null);
42414 setMachineCodes(mi++, (byte) 0x0F);
42415 setMachineCodes(mi++, (byte) 0x57);
42416 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, dstReg);
42417 if (lister != null) lister.RRFD(miStart, "XORPD", dstReg, srcIndex, srcScale, srcDisp);
42418 }
42419
42420 /**
42421 * Generate a register--absolute XORPD. That is,
42422 * <PRE>
42423 * dstReg <<= (quad) [srcDisp]
42424 * </PRE>
42425 *
42426 * @param dstReg destination register
42427 * @param srcDisp the source displacement
42428 */
42429 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
42430 public final void emitXORPD_Reg_Abs(XMM dstReg, Address srcDisp) {
42431 int miStart = mi;
42432 setMachineCodes(mi++, (byte) 0x66);
42433 generateREXprefix(false, dstReg, null, null);
42434 setMachineCodes(mi++, (byte) 0x0F);
42435 setMachineCodes(mi++, (byte) 0x57);
42436 emitAbsRegOperands(srcDisp, dstReg);
42437 if (lister != null) lister.RRA(miStart, "XORPD", dstReg, srcDisp);
42438 }
42439
42440 /**
42441 * Generate a register--register-index XORPD. That is,
42442 * <PRE>
42443 * dstReg <<= (quad) srcReg
42444 * </PRE>
42445 *
42446 * @param dstReg destination register
42447 * @param srcBase the source base register
42448 * @param srcIndex the source index register
42449 * @param srcScale the source scale
42450 * @param srcDisp the source displacement
42451 */
42452 // dstReg <<= (quad) [srcBase + srcIndex<<scale + srcDisp]
42453 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
42454 public final void emitXORPD_Reg_RegIdx(XMM dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
42455 int miStart = mi;
42456 setMachineCodes(mi++, (byte) 0x66);
42457 generateREXprefix(false, dstReg, srcIndex, srcBase);
42458 setMachineCodes(mi++, (byte) 0x0F);
42459 setMachineCodes(mi++, (byte) 0x57);
42460 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, dstReg);
42461 if (lister != null) lister.RRXD(miStart, "XORPD", dstReg, srcBase, srcIndex, srcScale, srcDisp);
42462 }
42463
42464 /**
42465 * Generate a register--register-indirect XORPD. That is,
42466 * <PRE>
42467 * dstReg <<= (quad) [srcBase]
42468 * </PRE>
42469 *
42470 * @param dstReg destination register
42471 * @param srcBase the source base register
42472 */
42473 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
42474 public final void emitXORPD_Reg_RegInd(XMM dstReg, GPR srcBase) {
42475 int miStart = mi;
42476 setMachineCodes(mi++, (byte) 0x66);
42477 generateREXprefix(false, dstReg, null, srcBase);
42478 setMachineCodes(mi++, (byte) 0x0F);
42479 setMachineCodes(mi++, (byte) 0x57);
42480 emitRegIndirectRegOperands(srcBase, dstReg);
42481 if (lister != null) lister.RRN(miStart, "XORPD", dstReg, srcBase);
42482 }
42483
42484 /**
42485 * Perform + on FP0. That is,
42486 * <PRE>
42487 * dstReg += () [srcBase + srcDisp]
42488 * </PRE>
42489 *
42490 * @param dstReg destination register, must be FP0
42491 * @param srcBase source base register
42492 * @param srcDisp source displacement
42493 */
42494 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
42495 public final void emitFADD_Reg_RegDisp(FPR dstReg, GPR srcBase, Offset srcDisp) {
42496 int miStart = mi;
42497 // Must store result to top of stack
42498 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
42499 setMachineCodes(mi++, (byte) 0xD8);
42500 // The register'' 0 is really part of the opcode
42501 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(0));
42502 if (lister != null) lister.RRD(miStart, "FADD", dstReg, srcBase, srcDisp);
42503 }
42504
42505 /**
42506 * Perform + on FP0. That is,
42507 * <PRE>
42508 * dstReg += () [srcBase]
42509 * </PRE>
42510 *
42511 * @param dstReg destination register, must be FP0
42512 * @param srcBase source base register
42513 */
42514 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
42515 public final void emitFADD_Reg_RegInd(FPR dstReg, GPR srcBase) {
42516 int miStart = mi;
42517 // Must store result to top of stack
42518 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
42519 setMachineCodes(mi++, (byte) 0xD8);
42520 // The register'' 0 is really part of the opcode
42521 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(0));
42522 if (lister != null) lister.RRN(miStart, "FADD", dstReg, srcBase);
42523 }
42524
42525 /**
42526 * Perform + on dstReg. That is,
42527 * <PRE>
42528 * dstReg += () [srcBase + srcIndex<<srcScale + srcDisp]
42529 * </PRE>
42530 *
42531 * @param dstReg destination register, must be FP0
42532 * @param srcBase source base register
42533 * @param srcIndex source index register
42534 * @param srcScale source scale
42535 * @param srcDisp source displacement
42536 */
42537 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
42538 public final void emitFADD_Reg_RegIdx(FPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
42539 int miStart = mi;
42540 // Must store result to top of stack
42541 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
42542 setMachineCodes(mi++, (byte) 0xD8);
42543 // The register'' 0 is really part of the opcode
42544 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(0));
42545 if (lister != null) lister.RRXD(miStart, "FADD", dstReg, srcBase, srcIndex, srcScale, srcDisp);
42546 }
42547
42548 /**
42549 * Perform + on FP0. That is,
42550 * <PRE>
42551 * dstReg += () [srcIndex<<srcScale + srcDisp]
42552 * </PRE>
42553 *
42554 * @param dstReg destination register, must be FP0
42555 * @param srcIndex source index register
42556 * @param srcScale source scale
42557 * @param srcDisp source displacement
42558 */
42559 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
42560 public final void emitFADD_Reg_RegOff(FPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
42561 int miStart = mi;
42562 // Must store result to top of stack
42563 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
42564 setMachineCodes(mi++, (byte) 0xD8);
42565 // The register'' 0 is really part of the opcode
42566 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(0));
42567 if (lister != null) lister.RRFD(miStart, "FADD", dstReg, srcIndex, srcScale, srcDisp);
42568 }
42569
42570 /**
42571 * Perform + on FP0. That is,
42572 * <PRE>
42573 * dstReg += () [srcDisp]
42574 * </PRE>
42575 *
42576 * @param dstReg destination register, must be FP0
42577 * @param srcDisp source displacement
42578 */
42579 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
42580 public final void emitFADD_Reg_Abs(FPR dstReg, Address srcDisp) {
42581 int miStart = mi;
42582 // Must store result to top of stack
42583 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
42584 setMachineCodes(mi++, (byte) 0xD8);
42585 // The register'' 0 is really part of the opcode
42586 emitAbsRegOperands(srcDisp, GPR.getForOpcode(0));
42587 if (lister != null) lister.RRA(miStart, "FADD", dstReg, srcDisp);
42588 }
42589
42590 /**
42591 * Perform + on FP0. That is,
42592 * <PRE>
42593 * dstReg += (quad) [srcBase + srcDisp]
42594 * </PRE>
42595 *
42596 * @param dstReg destination register, must be FP0
42597 * @param srcBase source base register
42598 * @param srcDisp source displacement
42599 */
42600 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
42601 public final void emitFADD_Reg_RegDisp_Quad(FPR dstReg, GPR srcBase, Offset srcDisp) {
42602 int miStart = mi;
42603 // Must store result to top of stack
42604 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
42605 setMachineCodes(mi++, (byte) 0xDC);
42606 // The register'' 0 is really part of the opcode
42607 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(0));
42608 if (lister != null) lister.RRD(miStart, "FADD", dstReg, srcBase, srcDisp);
42609 }
42610
42611 /**
42612 * Perform + on FP0. That is,
42613 * <PRE>
42614 * dstReg += (quad) [srcBase]
42615 * </PRE>
42616 *
42617 * @param dstReg destination register, must be FP0
42618 * @param srcBase source base register
42619 */
42620 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
42621 public final void emitFADD_Reg_RegInd_Quad(FPR dstReg, GPR srcBase) {
42622 int miStart = mi;
42623 // Must store result to top of stack
42624 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
42625 setMachineCodes(mi++, (byte) 0xDC);
42626 // The register'' 0 is really part of the opcode
42627 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(0));
42628 if (lister != null) lister.RRN(miStart, "FADD", dstReg, srcBase);
42629 }
42630
42631 /**
42632 * Perform + on dstReg. That is,
42633 * <PRE>
42634 * dstReg += (quad) [srcBase + srcIndex<<srcScale + srcDisp]
42635 * </PRE>
42636 *
42637 * @param dstReg destination register, must be FP0
42638 * @param srcBase source base register
42639 * @param srcIndex source index register
42640 * @param srcScale source scale
42641 * @param srcDisp source displacement
42642 */
42643 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
42644 public final void emitFADD_Reg_RegIdx_Quad(FPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
42645 int miStart = mi;
42646 // Must store result to top of stack
42647 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
42648 setMachineCodes(mi++, (byte) 0xDC);
42649 // The register'' 0 is really part of the opcode
42650 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(0));
42651 if (lister != null) lister.RRXD(miStart, "FADD", dstReg, srcBase, srcIndex, srcScale, srcDisp);
42652 }
42653
42654 /**
42655 * Perform + on FP0. That is,
42656 * <PRE>
42657 * dstReg += (quad) [srcIndex<<srcScale + srcDisp]
42658 * </PRE>
42659 *
42660 * @param dstReg destination register, must be FP0
42661 * @param srcIndex source index register
42662 * @param srcScale source scale
42663 * @param srcDisp source displacement
42664 */
42665 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
42666 public final void emitFADD_Reg_RegOff_Quad(FPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
42667 int miStart = mi;
42668 // Must store result to top of stack
42669 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
42670 setMachineCodes(mi++, (byte) 0xDC);
42671 // The register'' 0 is really part of the opcode
42672 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(0));
42673 if (lister != null) lister.RRFD(miStart, "FADD", dstReg, srcIndex, srcScale, srcDisp);
42674 }
42675
42676 /**
42677 * Perform + on FP0. That is,
42678 * <PRE>
42679 * dstReg += (quad) [srcDisp]
42680 * </PRE>
42681 *
42682 * @param dstReg destination register, must be FP0
42683 * @param srcDisp source displacement
42684 */
42685 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
42686 public final void emitFADD_Reg_Abs_Quad(FPR dstReg, Address srcDisp) {
42687 int miStart = mi;
42688 // Must store result to top of stack
42689 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
42690 setMachineCodes(mi++, (byte) 0xDC);
42691 // The register'' 0 is really part of the opcode
42692 emitAbsRegOperands(srcDisp, GPR.getForOpcode(0));
42693 if (lister != null) lister.RRA(miStart, "FADD", dstReg, srcDisp);
42694 }
42695
42696 /**
42697 * Perform + on FP0. That is,
42698 * <PRE>
42699 * dstReg += () [srcBase + srcDisp]
42700 * </PRE>
42701 *
42702 * @param dstReg destination register, must be FP0
42703 * @param srcBase source base register
42704 * @param srcDisp source displacement
42705 */
42706 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
42707 public final void emitFIADD_Reg_RegDisp(FPR dstReg, GPR srcBase, Offset srcDisp) {
42708 int miStart = mi;
42709 // Must store result to top of stack
42710 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
42711 setMachineCodes(mi++, (byte) 0xDA);
42712 // The register'' 0 is really part of the opcode
42713 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(0));
42714 if (lister != null) lister.RRD(miStart, "FIADD", dstReg, srcBase, srcDisp);
42715 }
42716
42717 /**
42718 * Perform + on FP0. That is,
42719 * <PRE>
42720 * dstReg += () [srcBase]
42721 * </PRE>
42722 *
42723 * @param dstReg destination register, must be FP0
42724 * @param srcBase source base register
42725 */
42726 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
42727 public final void emitFIADD_Reg_RegInd(FPR dstReg, GPR srcBase) {
42728 int miStart = mi;
42729 // Must store result to top of stack
42730 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
42731 setMachineCodes(mi++, (byte) 0xDA);
42732 // The register'' 0 is really part of the opcode
42733 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(0));
42734 if (lister != null) lister.RRN(miStart, "FIADD", dstReg, srcBase);
42735 }
42736
42737 /**
42738 * Perform + on dstReg. That is,
42739 * <PRE>
42740 * dstReg += () [srcBase + srcIndex<<srcScale + srcDisp]
42741 * </PRE>
42742 *
42743 * @param dstReg destination register, must be FP0
42744 * @param srcBase source base register
42745 * @param srcIndex source index register
42746 * @param srcScale source scale
42747 * @param srcDisp source displacement
42748 */
42749 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
42750 public final void emitFIADD_Reg_RegIdx(FPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
42751 int miStart = mi;
42752 // Must store result to top of stack
42753 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
42754 setMachineCodes(mi++, (byte) 0xDA);
42755 // The register'' 0 is really part of the opcode
42756 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(0));
42757 if (lister != null) lister.RRXD(miStart, "FIADD", dstReg, srcBase, srcIndex, srcScale, srcDisp);
42758 }
42759
42760 /**
42761 * Perform + on FP0. That is,
42762 * <PRE>
42763 * dstReg += () [srcIndex<<srcScale + srcDisp]
42764 * </PRE>
42765 *
42766 * @param dstReg destination register, must be FP0
42767 * @param srcIndex source index register
42768 * @param srcScale source scale
42769 * @param srcDisp source displacement
42770 */
42771 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
42772 public final void emitFIADD_Reg_RegOff(FPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
42773 int miStart = mi;
42774 // Must store result to top of stack
42775 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
42776 setMachineCodes(mi++, (byte) 0xDA);
42777 // The register'' 0 is really part of the opcode
42778 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(0));
42779 if (lister != null) lister.RRFD(miStart, "FIADD", dstReg, srcIndex, srcScale, srcDisp);
42780 }
42781
42782 /**
42783 * Perform + on FP0. That is,
42784 * <PRE>
42785 * dstReg += () [srcDisp]
42786 * </PRE>
42787 *
42788 * @param dstReg destination register, must be FP0
42789 * @param srcDisp source displacement
42790 */
42791 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
42792 public final void emitFIADD_Reg_Abs(FPR dstReg, Address srcDisp) {
42793 int miStart = mi;
42794 // Must store result to top of stack
42795 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
42796 setMachineCodes(mi++, (byte) 0xDA);
42797 // The register'' 0 is really part of the opcode
42798 emitAbsRegOperands(srcDisp, GPR.getForOpcode(0));
42799 if (lister != null) lister.RRA(miStart, "FIADD", dstReg, srcDisp);
42800 }
42801
42802 /**
42803 * Perform + on FP0. That is,
42804 * <PRE>
42805 * dstReg += (word) [srcBase + srcDisp]
42806 * </PRE>
42807 *
42808 * @param dstReg destination register, must be FP0
42809 * @param srcBase source base register
42810 * @param srcDisp source displacement
42811 */
42812 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
42813 public final void emitFIADD_Reg_RegDisp_Word(FPR dstReg, GPR srcBase, Offset srcDisp) {
42814 int miStart = mi;
42815 // Must store result to top of stack
42816 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
42817 setMachineCodes(mi++, (byte) 0xDE);
42818 // The register'' 0 is really part of the opcode
42819 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(0));
42820 if (lister != null) lister.RRD(miStart, "FIADD", dstReg, srcBase, srcDisp);
42821 }
42822
42823 /**
42824 * Perform + on FP0. That is,
42825 * <PRE>
42826 * dstReg += (word) [srcBase]
42827 * </PRE>
42828 *
42829 * @param dstReg destination register, must be FP0
42830 * @param srcBase source base register
42831 */
42832 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
42833 public final void emitFIADD_Reg_RegInd_Word(FPR dstReg, GPR srcBase) {
42834 int miStart = mi;
42835 // Must store result to top of stack
42836 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
42837 setMachineCodes(mi++, (byte) 0xDE);
42838 // The register'' 0 is really part of the opcode
42839 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(0));
42840 if (lister != null) lister.RRN(miStart, "FIADD", dstReg, srcBase);
42841 }
42842
42843 /**
42844 * Perform + on dstReg. That is,
42845 * <PRE>
42846 * dstReg += (word) [srcBase + srcIndex<<srcScale + srcDisp]
42847 * </PRE>
42848 *
42849 * @param dstReg destination register, must be FP0
42850 * @param srcBase source base register
42851 * @param srcIndex source index register
42852 * @param srcScale source scale
42853 * @param srcDisp source displacement
42854 */
42855 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
42856 public final void emitFIADD_Reg_RegIdx_Word(FPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
42857 int miStart = mi;
42858 // Must store result to top of stack
42859 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
42860 setMachineCodes(mi++, (byte) 0xDE);
42861 // The register'' 0 is really part of the opcode
42862 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(0));
42863 if (lister != null) lister.RRXD(miStart, "FIADD", dstReg, srcBase, srcIndex, srcScale, srcDisp);
42864 }
42865
42866 /**
42867 * Perform + on FP0. That is,
42868 * <PRE>
42869 * dstReg += (word) [srcIndex<<srcScale + srcDisp]
42870 * </PRE>
42871 *
42872 * @param dstReg destination register, must be FP0
42873 * @param srcIndex source index register
42874 * @param srcScale source scale
42875 * @param srcDisp source displacement
42876 */
42877 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
42878 public final void emitFIADD_Reg_RegOff_Word(FPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
42879 int miStart = mi;
42880 // Must store result to top of stack
42881 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
42882 setMachineCodes(mi++, (byte) 0xDE);
42883 // The register'' 0 is really part of the opcode
42884 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(0));
42885 if (lister != null) lister.RRFD(miStart, "FIADD", dstReg, srcIndex, srcScale, srcDisp);
42886 }
42887
42888 /**
42889 * Perform + on FP0. That is,
42890 * <PRE>
42891 * dstReg += (word) [srcDisp]
42892 * </PRE>
42893 *
42894 * @param dstReg destination register, must be FP0
42895 * @param srcDisp source displacement
42896 */
42897 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
42898 public final void emitFIADD_Reg_Abs_Word(FPR dstReg, Address srcDisp) {
42899 int miStart = mi;
42900 // Must store result to top of stack
42901 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
42902 setMachineCodes(mi++, (byte) 0xDE);
42903 // The register'' 0 is really part of the opcode
42904 emitAbsRegOperands(srcDisp, GPR.getForOpcode(0));
42905 if (lister != null) lister.RRA(miStart, "FIADD", dstReg, srcDisp);
42906 }
42907
42908 /**
42909 * Perform + either to or from FP0. That is,
42910 * <PRE>
42911 * dstReg += srcReg
42912 * </PRE>
42913 *
42914 * @param dstReg destination register, this or srcReg must be FP0
42915 * @param srcReg source register, this or dstReg must be FP0
42916 */
42917 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
42918 public final void emitFADD_Reg_Reg(FPR dstReg, FPR srcReg) {
42919 int miStart = mi;
42920 if (VM.VerifyAssertions) VM._assert(srcReg == FP0 || dstReg == FP0);
42921 if (dstReg == FP0) {
42922 setMachineCodes(mi++, (byte) 0xD8);
42923 setMachineCodes(mi++, (byte) (0xC0 | srcReg.value()));
42924 } else if (srcReg == FP0) {
42925 setMachineCodes(mi++, (byte) 0xDC);
42926 setMachineCodes(mi++, (byte) (0xC0 | dstReg.value()));
42927 }
42928 if (lister != null) lister.RR(miStart, "FADD", dstReg, srcReg);
42929 }
42930
42931 /**
42932 * Perform + then pop stack. That is,
42933 * <PRE>
42934 * srcReg += ST(0); pop stack
42935 * </PRE>
42936 *
42937 * @param dstReg destination register
42938 * @param srcReg source register
42939 */
42940 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
42941 public final void emitFADDP_Reg_Reg(FPR dstReg, FPR srcReg) {
42942 int miStart = mi;
42943 if (VM.VerifyAssertions) VM._assert(srcReg == FP0);
42944 setMachineCodes(mi++, (byte) 0xDE);
42945 setMachineCodes(mi++, (byte) (0xC0 | dstReg.value()));
42946 if (lister != null) lister.R(miStart, "FADDP", dstReg);
42947 }
42948
42949 /**
42950 * Perform / on FP0. That is,
42951 * <PRE>
42952 * dstReg /= () [srcBase + srcDisp]
42953 * </PRE>
42954 *
42955 * @param dstReg destination register, must be FP0
42956 * @param srcBase source base register
42957 * @param srcDisp source displacement
42958 */
42959 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
42960 public final void emitFDIV_Reg_RegDisp(FPR dstReg, GPR srcBase, Offset srcDisp) {
42961 int miStart = mi;
42962 // Must store result to top of stack
42963 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
42964 setMachineCodes(mi++, (byte) 0xD8);
42965 // The register'' 6 is really part of the opcode
42966 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(6));
42967 if (lister != null) lister.RRD(miStart, "FDIV", dstReg, srcBase, srcDisp);
42968 }
42969
42970 /**
42971 * Perform / on FP0. That is,
42972 * <PRE>
42973 * dstReg /= () [srcBase]
42974 * </PRE>
42975 *
42976 * @param dstReg destination register, must be FP0
42977 * @param srcBase source base register
42978 */
42979 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
42980 public final void emitFDIV_Reg_RegInd(FPR dstReg, GPR srcBase) {
42981 int miStart = mi;
42982 // Must store result to top of stack
42983 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
42984 setMachineCodes(mi++, (byte) 0xD8);
42985 // The register'' 6 is really part of the opcode
42986 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(6));
42987 if (lister != null) lister.RRN(miStart, "FDIV", dstReg, srcBase);
42988 }
42989
42990 /**
42991 * Perform / on dstReg. That is,
42992 * <PRE>
42993 * dstReg /= () [srcBase + srcIndex<<srcScale + srcDisp]
42994 * </PRE>
42995 *
42996 * @param dstReg destination register, must be FP0
42997 * @param srcBase source base register
42998 * @param srcIndex source index register
42999 * @param srcScale source scale
43000 * @param srcDisp source displacement
43001 */
43002 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
43003 public final void emitFDIV_Reg_RegIdx(FPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
43004 int miStart = mi;
43005 // Must store result to top of stack
43006 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43007 setMachineCodes(mi++, (byte) 0xD8);
43008 // The register'' 6 is really part of the opcode
43009 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(6));
43010 if (lister != null) lister.RRXD(miStart, "FDIV", dstReg, srcBase, srcIndex, srcScale, srcDisp);
43011 }
43012
43013 /**
43014 * Perform / on FP0. That is,
43015 * <PRE>
43016 * dstReg /= () [srcIndex<<srcScale + srcDisp]
43017 * </PRE>
43018 *
43019 * @param dstReg destination register, must be FP0
43020 * @param srcIndex source index register
43021 * @param srcScale source scale
43022 * @param srcDisp source displacement
43023 */
43024 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
43025 public final void emitFDIV_Reg_RegOff(FPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
43026 int miStart = mi;
43027 // Must store result to top of stack
43028 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43029 setMachineCodes(mi++, (byte) 0xD8);
43030 // The register'' 6 is really part of the opcode
43031 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(6));
43032 if (lister != null) lister.RRFD(miStart, "FDIV", dstReg, srcIndex, srcScale, srcDisp);
43033 }
43034
43035 /**
43036 * Perform / on FP0. That is,
43037 * <PRE>
43038 * dstReg /= () [srcDisp]
43039 * </PRE>
43040 *
43041 * @param dstReg destination register, must be FP0
43042 * @param srcDisp source displacement
43043 */
43044 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
43045 public final void emitFDIV_Reg_Abs(FPR dstReg, Address srcDisp) {
43046 int miStart = mi;
43047 // Must store result to top of stack
43048 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43049 setMachineCodes(mi++, (byte) 0xD8);
43050 // The register'' 6 is really part of the opcode
43051 emitAbsRegOperands(srcDisp, GPR.getForOpcode(6));
43052 if (lister != null) lister.RRA(miStart, "FDIV", dstReg, srcDisp);
43053 }
43054
43055 /**
43056 * Perform / on FP0. That is,
43057 * <PRE>
43058 * dstReg /= (quad) [srcBase + srcDisp]
43059 * </PRE>
43060 *
43061 * @param dstReg destination register, must be FP0
43062 * @param srcBase source base register
43063 * @param srcDisp source displacement
43064 */
43065 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
43066 public final void emitFDIV_Reg_RegDisp_Quad(FPR dstReg, GPR srcBase, Offset srcDisp) {
43067 int miStart = mi;
43068 // Must store result to top of stack
43069 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43070 setMachineCodes(mi++, (byte) 0xDC);
43071 // The register'' 6 is really part of the opcode
43072 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(6));
43073 if (lister != null) lister.RRD(miStart, "FDIV", dstReg, srcBase, srcDisp);
43074 }
43075
43076 /**
43077 * Perform / on FP0. That is,
43078 * <PRE>
43079 * dstReg /= (quad) [srcBase]
43080 * </PRE>
43081 *
43082 * @param dstReg destination register, must be FP0
43083 * @param srcBase source base register
43084 */
43085 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
43086 public final void emitFDIV_Reg_RegInd_Quad(FPR dstReg, GPR srcBase) {
43087 int miStart = mi;
43088 // Must store result to top of stack
43089 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43090 setMachineCodes(mi++, (byte) 0xDC);
43091 // The register'' 6 is really part of the opcode
43092 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(6));
43093 if (lister != null) lister.RRN(miStart, "FDIV", dstReg, srcBase);
43094 }
43095
43096 /**
43097 * Perform / on dstReg. That is,
43098 * <PRE>
43099 * dstReg /= (quad) [srcBase + srcIndex<<srcScale + srcDisp]
43100 * </PRE>
43101 *
43102 * @param dstReg destination register, must be FP0
43103 * @param srcBase source base register
43104 * @param srcIndex source index register
43105 * @param srcScale source scale
43106 * @param srcDisp source displacement
43107 */
43108 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
43109 public final void emitFDIV_Reg_RegIdx_Quad(FPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
43110 int miStart = mi;
43111 // Must store result to top of stack
43112 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43113 setMachineCodes(mi++, (byte) 0xDC);
43114 // The register'' 6 is really part of the opcode
43115 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(6));
43116 if (lister != null) lister.RRXD(miStart, "FDIV", dstReg, srcBase, srcIndex, srcScale, srcDisp);
43117 }
43118
43119 /**
43120 * Perform / on FP0. That is,
43121 * <PRE>
43122 * dstReg /= (quad) [srcIndex<<srcScale + srcDisp]
43123 * </PRE>
43124 *
43125 * @param dstReg destination register, must be FP0
43126 * @param srcIndex source index register
43127 * @param srcScale source scale
43128 * @param srcDisp source displacement
43129 */
43130 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
43131 public final void emitFDIV_Reg_RegOff_Quad(FPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
43132 int miStart = mi;
43133 // Must store result to top of stack
43134 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43135 setMachineCodes(mi++, (byte) 0xDC);
43136 // The register'' 6 is really part of the opcode
43137 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(6));
43138 if (lister != null) lister.RRFD(miStart, "FDIV", dstReg, srcIndex, srcScale, srcDisp);
43139 }
43140
43141 /**
43142 * Perform / on FP0. That is,
43143 * <PRE>
43144 * dstReg /= (quad) [srcDisp]
43145 * </PRE>
43146 *
43147 * @param dstReg destination register, must be FP0
43148 * @param srcDisp source displacement
43149 */
43150 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
43151 public final void emitFDIV_Reg_Abs_Quad(FPR dstReg, Address srcDisp) {
43152 int miStart = mi;
43153 // Must store result to top of stack
43154 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43155 setMachineCodes(mi++, (byte) 0xDC);
43156 // The register'' 6 is really part of the opcode
43157 emitAbsRegOperands(srcDisp, GPR.getForOpcode(6));
43158 if (lister != null) lister.RRA(miStart, "FDIV", dstReg, srcDisp);
43159 }
43160
43161 /**
43162 * Perform / on FP0. That is,
43163 * <PRE>
43164 * dstReg /= () [srcBase + srcDisp]
43165 * </PRE>
43166 *
43167 * @param dstReg destination register, must be FP0
43168 * @param srcBase source base register
43169 * @param srcDisp source displacement
43170 */
43171 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
43172 public final void emitFIDIV_Reg_RegDisp(FPR dstReg, GPR srcBase, Offset srcDisp) {
43173 int miStart = mi;
43174 // Must store result to top of stack
43175 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43176 setMachineCodes(mi++, (byte) 0xDA);
43177 // The register'' 6 is really part of the opcode
43178 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(6));
43179 if (lister != null) lister.RRD(miStart, "FIDIV", dstReg, srcBase, srcDisp);
43180 }
43181
43182 /**
43183 * Perform / on FP0. That is,
43184 * <PRE>
43185 * dstReg /= () [srcBase]
43186 * </PRE>
43187 *
43188 * @param dstReg destination register, must be FP0
43189 * @param srcBase source base register
43190 */
43191 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
43192 public final void emitFIDIV_Reg_RegInd(FPR dstReg, GPR srcBase) {
43193 int miStart = mi;
43194 // Must store result to top of stack
43195 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43196 setMachineCodes(mi++, (byte) 0xDA);
43197 // The register'' 6 is really part of the opcode
43198 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(6));
43199 if (lister != null) lister.RRN(miStart, "FIDIV", dstReg, srcBase);
43200 }
43201
43202 /**
43203 * Perform / on dstReg. That is,
43204 * <PRE>
43205 * dstReg /= () [srcBase + srcIndex<<srcScale + srcDisp]
43206 * </PRE>
43207 *
43208 * @param dstReg destination register, must be FP0
43209 * @param srcBase source base register
43210 * @param srcIndex source index register
43211 * @param srcScale source scale
43212 * @param srcDisp source displacement
43213 */
43214 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
43215 public final void emitFIDIV_Reg_RegIdx(FPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
43216 int miStart = mi;
43217 // Must store result to top of stack
43218 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43219 setMachineCodes(mi++, (byte) 0xDA);
43220 // The register'' 6 is really part of the opcode
43221 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(6));
43222 if (lister != null) lister.RRXD(miStart, "FIDIV", dstReg, srcBase, srcIndex, srcScale, srcDisp);
43223 }
43224
43225 /**
43226 * Perform / on FP0. That is,
43227 * <PRE>
43228 * dstReg /= () [srcIndex<<srcScale + srcDisp]
43229 * </PRE>
43230 *
43231 * @param dstReg destination register, must be FP0
43232 * @param srcIndex source index register
43233 * @param srcScale source scale
43234 * @param srcDisp source displacement
43235 */
43236 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
43237 public final void emitFIDIV_Reg_RegOff(FPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
43238 int miStart = mi;
43239 // Must store result to top of stack
43240 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43241 setMachineCodes(mi++, (byte) 0xDA);
43242 // The register'' 6 is really part of the opcode
43243 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(6));
43244 if (lister != null) lister.RRFD(miStart, "FIDIV", dstReg, srcIndex, srcScale, srcDisp);
43245 }
43246
43247 /**
43248 * Perform / on FP0. That is,
43249 * <PRE>
43250 * dstReg /= () [srcDisp]
43251 * </PRE>
43252 *
43253 * @param dstReg destination register, must be FP0
43254 * @param srcDisp source displacement
43255 */
43256 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
43257 public final void emitFIDIV_Reg_Abs(FPR dstReg, Address srcDisp) {
43258 int miStart = mi;
43259 // Must store result to top of stack
43260 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43261 setMachineCodes(mi++, (byte) 0xDA);
43262 // The register'' 6 is really part of the opcode
43263 emitAbsRegOperands(srcDisp, GPR.getForOpcode(6));
43264 if (lister != null) lister.RRA(miStart, "FIDIV", dstReg, srcDisp);
43265 }
43266
43267 /**
43268 * Perform / on FP0. That is,
43269 * <PRE>
43270 * dstReg /= (word) [srcBase + srcDisp]
43271 * </PRE>
43272 *
43273 * @param dstReg destination register, must be FP0
43274 * @param srcBase source base register
43275 * @param srcDisp source displacement
43276 */
43277 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
43278 public final void emitFIDIV_Reg_RegDisp_Word(FPR dstReg, GPR srcBase, Offset srcDisp) {
43279 int miStart = mi;
43280 // Must store result to top of stack
43281 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43282 setMachineCodes(mi++, (byte) 0xDE);
43283 // The register'' 6 is really part of the opcode
43284 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(6));
43285 if (lister != null) lister.RRD(miStart, "FIDIV", dstReg, srcBase, srcDisp);
43286 }
43287
43288 /**
43289 * Perform / on FP0. That is,
43290 * <PRE>
43291 * dstReg /= (word) [srcBase]
43292 * </PRE>
43293 *
43294 * @param dstReg destination register, must be FP0
43295 * @param srcBase source base register
43296 */
43297 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
43298 public final void emitFIDIV_Reg_RegInd_Word(FPR dstReg, GPR srcBase) {
43299 int miStart = mi;
43300 // Must store result to top of stack
43301 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43302 setMachineCodes(mi++, (byte) 0xDE);
43303 // The register'' 6 is really part of the opcode
43304 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(6));
43305 if (lister != null) lister.RRN(miStart, "FIDIV", dstReg, srcBase);
43306 }
43307
43308 /**
43309 * Perform / on dstReg. That is,
43310 * <PRE>
43311 * dstReg /= (word) [srcBase + srcIndex<<srcScale + srcDisp]
43312 * </PRE>
43313 *
43314 * @param dstReg destination register, must be FP0
43315 * @param srcBase source base register
43316 * @param srcIndex source index register
43317 * @param srcScale source scale
43318 * @param srcDisp source displacement
43319 */
43320 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
43321 public final void emitFIDIV_Reg_RegIdx_Word(FPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
43322 int miStart = mi;
43323 // Must store result to top of stack
43324 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43325 setMachineCodes(mi++, (byte) 0xDE);
43326 // The register'' 6 is really part of the opcode
43327 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(6));
43328 if (lister != null) lister.RRXD(miStart, "FIDIV", dstReg, srcBase, srcIndex, srcScale, srcDisp);
43329 }
43330
43331 /**
43332 * Perform / on FP0. That is,
43333 * <PRE>
43334 * dstReg /= (word) [srcIndex<<srcScale + srcDisp]
43335 * </PRE>
43336 *
43337 * @param dstReg destination register, must be FP0
43338 * @param srcIndex source index register
43339 * @param srcScale source scale
43340 * @param srcDisp source displacement
43341 */
43342 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
43343 public final void emitFIDIV_Reg_RegOff_Word(FPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
43344 int miStart = mi;
43345 // Must store result to top of stack
43346 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43347 setMachineCodes(mi++, (byte) 0xDE);
43348 // The register'' 6 is really part of the opcode
43349 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(6));
43350 if (lister != null) lister.RRFD(miStart, "FIDIV", dstReg, srcIndex, srcScale, srcDisp);
43351 }
43352
43353 /**
43354 * Perform / on FP0. That is,
43355 * <PRE>
43356 * dstReg /= (word) [srcDisp]
43357 * </PRE>
43358 *
43359 * @param dstReg destination register, must be FP0
43360 * @param srcDisp source displacement
43361 */
43362 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
43363 public final void emitFIDIV_Reg_Abs_Word(FPR dstReg, Address srcDisp) {
43364 int miStart = mi;
43365 // Must store result to top of stack
43366 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43367 setMachineCodes(mi++, (byte) 0xDE);
43368 // The register'' 6 is really part of the opcode
43369 emitAbsRegOperands(srcDisp, GPR.getForOpcode(6));
43370 if (lister != null) lister.RRA(miStart, "FIDIV", dstReg, srcDisp);
43371 }
43372
43373 /**
43374 * Perform / either to or from FP0. That is,
43375 * <PRE>
43376 * dstReg /= srcReg
43377 * </PRE>
43378 *
43379 * @param dstReg destination register, this or srcReg must be FP0
43380 * @param srcReg source register, this or dstReg must be FP0
43381 */
43382 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
43383 public final void emitFDIV_Reg_Reg(FPR dstReg, FPR srcReg) {
43384 int miStart = mi;
43385 if (VM.VerifyAssertions) VM._assert(srcReg == FP0 || dstReg == FP0);
43386 if (dstReg == FP0) {
43387 setMachineCodes(mi++, (byte) 0xD8);
43388 setMachineCodes(mi++, (byte) (0xF0 | srcReg.value()));
43389 } else if (srcReg == FP0) {
43390 setMachineCodes(mi++, (byte) 0xDC);
43391 setMachineCodes(mi++, (byte) (0xF8 | dstReg.value()));
43392 }
43393 if (lister != null) lister.RR(miStart, "FDIV", dstReg, srcReg);
43394 }
43395
43396 /**
43397 * Perform / then pop stack. That is,
43398 * <PRE>
43399 * srcReg /= ST(0); pop stack
43400 * </PRE>
43401 *
43402 * @param dstReg destination register
43403 * @param srcReg source register
43404 */
43405 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
43406 public final void emitFDIVP_Reg_Reg(FPR dstReg, FPR srcReg) {
43407 int miStart = mi;
43408 if (VM.VerifyAssertions) VM._assert(srcReg == FP0);
43409 setMachineCodes(mi++, (byte) 0xDE);
43410 setMachineCodes(mi++, (byte) (0xF8 | dstReg.value()));
43411 if (lister != null) lister.R(miStart, "FDIVP", dstReg);
43412 }
43413
43414 /**
43415 * Perform / on FP0. That is,
43416 * <PRE>
43417 * dstReg /= () [srcBase + srcDisp]
43418 * </PRE>
43419 *
43420 * @param dstReg destination register, must be FP0
43421 * @param srcBase source base register
43422 * @param srcDisp source displacement
43423 */
43424 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
43425 public final void emitFDIVR_Reg_RegDisp(FPR dstReg, GPR srcBase, Offset srcDisp) {
43426 int miStart = mi;
43427 // Must store result to top of stack
43428 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43429 setMachineCodes(mi++, (byte) 0xD8);
43430 // The register'' 7 is really part of the opcode
43431 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(7));
43432 if (lister != null) lister.RRD(miStart, "FDIVR", dstReg, srcBase, srcDisp);
43433 }
43434
43435 /**
43436 * Perform / on FP0. That is,
43437 * <PRE>
43438 * dstReg /= () [srcBase]
43439 * </PRE>
43440 *
43441 * @param dstReg destination register, must be FP0
43442 * @param srcBase source base register
43443 */
43444 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
43445 public final void emitFDIVR_Reg_RegInd(FPR dstReg, GPR srcBase) {
43446 int miStart = mi;
43447 // Must store result to top of stack
43448 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43449 setMachineCodes(mi++, (byte) 0xD8);
43450 // The register'' 7 is really part of the opcode
43451 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(7));
43452 if (lister != null) lister.RRN(miStart, "FDIVR", dstReg, srcBase);
43453 }
43454
43455 /**
43456 * Perform / on dstReg. That is,
43457 * <PRE>
43458 * dstReg /= () [srcBase + srcIndex<<srcScale + srcDisp]
43459 * </PRE>
43460 *
43461 * @param dstReg destination register, must be FP0
43462 * @param srcBase source base register
43463 * @param srcIndex source index register
43464 * @param srcScale source scale
43465 * @param srcDisp source displacement
43466 */
43467 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
43468 public final void emitFDIVR_Reg_RegIdx(FPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
43469 int miStart = mi;
43470 // Must store result to top of stack
43471 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43472 setMachineCodes(mi++, (byte) 0xD8);
43473 // The register'' 7 is really part of the opcode
43474 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(7));
43475 if (lister != null) lister.RRXD(miStart, "FDIVR", dstReg, srcBase, srcIndex, srcScale, srcDisp);
43476 }
43477
43478 /**
43479 * Perform / on FP0. That is,
43480 * <PRE>
43481 * dstReg /= () [srcIndex<<srcScale + srcDisp]
43482 * </PRE>
43483 *
43484 * @param dstReg destination register, must be FP0
43485 * @param srcIndex source index register
43486 * @param srcScale source scale
43487 * @param srcDisp source displacement
43488 */
43489 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
43490 public final void emitFDIVR_Reg_RegOff(FPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
43491 int miStart = mi;
43492 // Must store result to top of stack
43493 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43494 setMachineCodes(mi++, (byte) 0xD8);
43495 // The register'' 7 is really part of the opcode
43496 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(7));
43497 if (lister != null) lister.RRFD(miStart, "FDIVR", dstReg, srcIndex, srcScale, srcDisp);
43498 }
43499
43500 /**
43501 * Perform / on FP0. That is,
43502 * <PRE>
43503 * dstReg /= () [srcDisp]
43504 * </PRE>
43505 *
43506 * @param dstReg destination register, must be FP0
43507 * @param srcDisp source displacement
43508 */
43509 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
43510 public final void emitFDIVR_Reg_Abs(FPR dstReg, Address srcDisp) {
43511 int miStart = mi;
43512 // Must store result to top of stack
43513 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43514 setMachineCodes(mi++, (byte) 0xD8);
43515 // The register'' 7 is really part of the opcode
43516 emitAbsRegOperands(srcDisp, GPR.getForOpcode(7));
43517 if (lister != null) lister.RRA(miStart, "FDIVR", dstReg, srcDisp);
43518 }
43519
43520 /**
43521 * Perform / on FP0. That is,
43522 * <PRE>
43523 * dstReg /= (quad) [srcBase + srcDisp]
43524 * </PRE>
43525 *
43526 * @param dstReg destination register, must be FP0
43527 * @param srcBase source base register
43528 * @param srcDisp source displacement
43529 */
43530 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
43531 public final void emitFDIVR_Reg_RegDisp_Quad(FPR dstReg, GPR srcBase, Offset srcDisp) {
43532 int miStart = mi;
43533 // Must store result to top of stack
43534 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43535 setMachineCodes(mi++, (byte) 0xDC);
43536 // The register'' 7 is really part of the opcode
43537 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(7));
43538 if (lister != null) lister.RRD(miStart, "FDIVR", dstReg, srcBase, srcDisp);
43539 }
43540
43541 /**
43542 * Perform / on FP0. That is,
43543 * <PRE>
43544 * dstReg /= (quad) [srcBase]
43545 * </PRE>
43546 *
43547 * @param dstReg destination register, must be FP0
43548 * @param srcBase source base register
43549 */
43550 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
43551 public final void emitFDIVR_Reg_RegInd_Quad(FPR dstReg, GPR srcBase) {
43552 int miStart = mi;
43553 // Must store result to top of stack
43554 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43555 setMachineCodes(mi++, (byte) 0xDC);
43556 // The register'' 7 is really part of the opcode
43557 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(7));
43558 if (lister != null) lister.RRN(miStart, "FDIVR", dstReg, srcBase);
43559 }
43560
43561 /**
43562 * Perform / on dstReg. That is,
43563 * <PRE>
43564 * dstReg /= (quad) [srcBase + srcIndex<<srcScale + srcDisp]
43565 * </PRE>
43566 *
43567 * @param dstReg destination register, must be FP0
43568 * @param srcBase source base register
43569 * @param srcIndex source index register
43570 * @param srcScale source scale
43571 * @param srcDisp source displacement
43572 */
43573 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
43574 public final void emitFDIVR_Reg_RegIdx_Quad(FPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
43575 int miStart = mi;
43576 // Must store result to top of stack
43577 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43578 setMachineCodes(mi++, (byte) 0xDC);
43579 // The register'' 7 is really part of the opcode
43580 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(7));
43581 if (lister != null) lister.RRXD(miStart, "FDIVR", dstReg, srcBase, srcIndex, srcScale, srcDisp);
43582 }
43583
43584 /**
43585 * Perform / on FP0. That is,
43586 * <PRE>
43587 * dstReg /= (quad) [srcIndex<<srcScale + srcDisp]
43588 * </PRE>
43589 *
43590 * @param dstReg destination register, must be FP0
43591 * @param srcIndex source index register
43592 * @param srcScale source scale
43593 * @param srcDisp source displacement
43594 */
43595 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
43596 public final void emitFDIVR_Reg_RegOff_Quad(FPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
43597 int miStart = mi;
43598 // Must store result to top of stack
43599 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43600 setMachineCodes(mi++, (byte) 0xDC);
43601 // The register'' 7 is really part of the opcode
43602 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(7));
43603 if (lister != null) lister.RRFD(miStart, "FDIVR", dstReg, srcIndex, srcScale, srcDisp);
43604 }
43605
43606 /**
43607 * Perform / on FP0. That is,
43608 * <PRE>
43609 * dstReg /= (quad) [srcDisp]
43610 * </PRE>
43611 *
43612 * @param dstReg destination register, must be FP0
43613 * @param srcDisp source displacement
43614 */
43615 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
43616 public final void emitFDIVR_Reg_Abs_Quad(FPR dstReg, Address srcDisp) {
43617 int miStart = mi;
43618 // Must store result to top of stack
43619 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43620 setMachineCodes(mi++, (byte) 0xDC);
43621 // The register'' 7 is really part of the opcode
43622 emitAbsRegOperands(srcDisp, GPR.getForOpcode(7));
43623 if (lister != null) lister.RRA(miStart, "FDIVR", dstReg, srcDisp);
43624 }
43625
43626 /**
43627 * Perform / on FP0. That is,
43628 * <PRE>
43629 * dstReg /= () [srcBase + srcDisp]
43630 * </PRE>
43631 *
43632 * @param dstReg destination register, must be FP0
43633 * @param srcBase source base register
43634 * @param srcDisp source displacement
43635 */
43636 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
43637 public final void emitFIDIVR_Reg_RegDisp(FPR dstReg, GPR srcBase, Offset srcDisp) {
43638 int miStart = mi;
43639 // Must store result to top of stack
43640 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43641 setMachineCodes(mi++, (byte) 0xDA);
43642 // The register'' 7 is really part of the opcode
43643 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(7));
43644 if (lister != null) lister.RRD(miStart, "FIDIVR", dstReg, srcBase, srcDisp);
43645 }
43646
43647 /**
43648 * Perform / on FP0. That is,
43649 * <PRE>
43650 * dstReg /= () [srcBase]
43651 * </PRE>
43652 *
43653 * @param dstReg destination register, must be FP0
43654 * @param srcBase source base register
43655 */
43656 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
43657 public final void emitFIDIVR_Reg_RegInd(FPR dstReg, GPR srcBase) {
43658 int miStart = mi;
43659 // Must store result to top of stack
43660 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43661 setMachineCodes(mi++, (byte) 0xDA);
43662 // The register'' 7 is really part of the opcode
43663 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(7));
43664 if (lister != null) lister.RRN(miStart, "FIDIVR", dstReg, srcBase);
43665 }
43666
43667 /**
43668 * Perform / on dstReg. That is,
43669 * <PRE>
43670 * dstReg /= () [srcBase + srcIndex<<srcScale + srcDisp]
43671 * </PRE>
43672 *
43673 * @param dstReg destination register, must be FP0
43674 * @param srcBase source base register
43675 * @param srcIndex source index register
43676 * @param srcScale source scale
43677 * @param srcDisp source displacement
43678 */
43679 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
43680 public final void emitFIDIVR_Reg_RegIdx(FPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
43681 int miStart = mi;
43682 // Must store result to top of stack
43683 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43684 setMachineCodes(mi++, (byte) 0xDA);
43685 // The register'' 7 is really part of the opcode
43686 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(7));
43687 if (lister != null) lister.RRXD(miStart, "FIDIVR", dstReg, srcBase, srcIndex, srcScale, srcDisp);
43688 }
43689
43690 /**
43691 * Perform / on FP0. That is,
43692 * <PRE>
43693 * dstReg /= () [srcIndex<<srcScale + srcDisp]
43694 * </PRE>
43695 *
43696 * @param dstReg destination register, must be FP0
43697 * @param srcIndex source index register
43698 * @param srcScale source scale
43699 * @param srcDisp source displacement
43700 */
43701 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
43702 public final void emitFIDIVR_Reg_RegOff(FPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
43703 int miStart = mi;
43704 // Must store result to top of stack
43705 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43706 setMachineCodes(mi++, (byte) 0xDA);
43707 // The register'' 7 is really part of the opcode
43708 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(7));
43709 if (lister != null) lister.RRFD(miStart, "FIDIVR", dstReg, srcIndex, srcScale, srcDisp);
43710 }
43711
43712 /**
43713 * Perform / on FP0. That is,
43714 * <PRE>
43715 * dstReg /= () [srcDisp]
43716 * </PRE>
43717 *
43718 * @param dstReg destination register, must be FP0
43719 * @param srcDisp source displacement
43720 */
43721 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
43722 public final void emitFIDIVR_Reg_Abs(FPR dstReg, Address srcDisp) {
43723 int miStart = mi;
43724 // Must store result to top of stack
43725 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43726 setMachineCodes(mi++, (byte) 0xDA);
43727 // The register'' 7 is really part of the opcode
43728 emitAbsRegOperands(srcDisp, GPR.getForOpcode(7));
43729 if (lister != null) lister.RRA(miStart, "FIDIVR", dstReg, srcDisp);
43730 }
43731
43732 /**
43733 * Perform / on FP0. That is,
43734 * <PRE>
43735 * dstReg /= (word) [srcBase + srcDisp]
43736 * </PRE>
43737 *
43738 * @param dstReg destination register, must be FP0
43739 * @param srcBase source base register
43740 * @param srcDisp source displacement
43741 */
43742 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
43743 public final void emitFIDIVR_Reg_RegDisp_Word(FPR dstReg, GPR srcBase, Offset srcDisp) {
43744 int miStart = mi;
43745 // Must store result to top of stack
43746 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43747 setMachineCodes(mi++, (byte) 0xDE);
43748 // The register'' 7 is really part of the opcode
43749 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(7));
43750 if (lister != null) lister.RRD(miStart, "FIDIVR", dstReg, srcBase, srcDisp);
43751 }
43752
43753 /**
43754 * Perform / on FP0. That is,
43755 * <PRE>
43756 * dstReg /= (word) [srcBase]
43757 * </PRE>
43758 *
43759 * @param dstReg destination register, must be FP0
43760 * @param srcBase source base register
43761 */
43762 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
43763 public final void emitFIDIVR_Reg_RegInd_Word(FPR dstReg, GPR srcBase) {
43764 int miStart = mi;
43765 // Must store result to top of stack
43766 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43767 setMachineCodes(mi++, (byte) 0xDE);
43768 // The register'' 7 is really part of the opcode
43769 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(7));
43770 if (lister != null) lister.RRN(miStart, "FIDIVR", dstReg, srcBase);
43771 }
43772
43773 /**
43774 * Perform / on dstReg. That is,
43775 * <PRE>
43776 * dstReg /= (word) [srcBase + srcIndex<<srcScale + srcDisp]
43777 * </PRE>
43778 *
43779 * @param dstReg destination register, must be FP0
43780 * @param srcBase source base register
43781 * @param srcIndex source index register
43782 * @param srcScale source scale
43783 * @param srcDisp source displacement
43784 */
43785 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
43786 public final void emitFIDIVR_Reg_RegIdx_Word(FPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
43787 int miStart = mi;
43788 // Must store result to top of stack
43789 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43790 setMachineCodes(mi++, (byte) 0xDE);
43791 // The register'' 7 is really part of the opcode
43792 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(7));
43793 if (lister != null) lister.RRXD(miStart, "FIDIVR", dstReg, srcBase, srcIndex, srcScale, srcDisp);
43794 }
43795
43796 /**
43797 * Perform / on FP0. That is,
43798 * <PRE>
43799 * dstReg /= (word) [srcIndex<<srcScale + srcDisp]
43800 * </PRE>
43801 *
43802 * @param dstReg destination register, must be FP0
43803 * @param srcIndex source index register
43804 * @param srcScale source scale
43805 * @param srcDisp source displacement
43806 */
43807 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
43808 public final void emitFIDIVR_Reg_RegOff_Word(FPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
43809 int miStart = mi;
43810 // Must store result to top of stack
43811 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43812 setMachineCodes(mi++, (byte) 0xDE);
43813 // The register'' 7 is really part of the opcode
43814 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(7));
43815 if (lister != null) lister.RRFD(miStart, "FIDIVR", dstReg, srcIndex, srcScale, srcDisp);
43816 }
43817
43818 /**
43819 * Perform / on FP0. That is,
43820 * <PRE>
43821 * dstReg /= (word) [srcDisp]
43822 * </PRE>
43823 *
43824 * @param dstReg destination register, must be FP0
43825 * @param srcDisp source displacement
43826 */
43827 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
43828 public final void emitFIDIVR_Reg_Abs_Word(FPR dstReg, Address srcDisp) {
43829 int miStart = mi;
43830 // Must store result to top of stack
43831 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43832 setMachineCodes(mi++, (byte) 0xDE);
43833 // The register'' 7 is really part of the opcode
43834 emitAbsRegOperands(srcDisp, GPR.getForOpcode(7));
43835 if (lister != null) lister.RRA(miStart, "FIDIVR", dstReg, srcDisp);
43836 }
43837
43838 /**
43839 * Perform / either to or from FP0. That is,
43840 * <PRE>
43841 * dstReg /= srcReg
43842 * </PRE>
43843 *
43844 * @param dstReg destination register, this or srcReg must be FP0
43845 * @param srcReg source register, this or dstReg must be FP0
43846 */
43847 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
43848 public final void emitFDIVR_Reg_Reg(FPR dstReg, FPR srcReg) {
43849 int miStart = mi;
43850 if (VM.VerifyAssertions) VM._assert(srcReg == FP0 || dstReg == FP0);
43851 if (dstReg == FP0) {
43852 setMachineCodes(mi++, (byte) 0xD8);
43853 setMachineCodes(mi++, (byte) (0xF8 | srcReg.value()));
43854 } else if (srcReg == FP0) {
43855 setMachineCodes(mi++, (byte) 0xDC);
43856 setMachineCodes(mi++, (byte) (0xF0 | dstReg.value()));
43857 }
43858 if (lister != null) lister.RR(miStart, "FDIVR", dstReg, srcReg);
43859 }
43860
43861 /**
43862 * Perform / then pop stack. That is,
43863 * <PRE>
43864 * srcReg /= ST(0); pop stack
43865 * </PRE>
43866 *
43867 * @param dstReg destination register
43868 * @param srcReg source register
43869 */
43870 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
43871 public final void emitFDIVRP_Reg_Reg(FPR dstReg, FPR srcReg) {
43872 int miStart = mi;
43873 if (VM.VerifyAssertions) VM._assert(srcReg == FP0);
43874 setMachineCodes(mi++, (byte) 0xDE);
43875 setMachineCodes(mi++, (byte) (0xF0 | dstReg.value()));
43876 if (lister != null) lister.R(miStart, "FDIVRP", dstReg);
43877 }
43878
43879 /**
43880 * Perform x on FP0. That is,
43881 * <PRE>
43882 * dstReg x= () [srcBase + srcDisp]
43883 * </PRE>
43884 *
43885 * @param dstReg destination register, must be FP0
43886 * @param srcBase source base register
43887 * @param srcDisp source displacement
43888 */
43889 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
43890 public final void emitFMUL_Reg_RegDisp(FPR dstReg, GPR srcBase, Offset srcDisp) {
43891 int miStart = mi;
43892 // Must store result to top of stack
43893 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43894 setMachineCodes(mi++, (byte) 0xD8);
43895 // The register'' 1 is really part of the opcode
43896 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(1));
43897 if (lister != null) lister.RRD(miStart, "FMUL", dstReg, srcBase, srcDisp);
43898 }
43899
43900 /**
43901 * Perform x on FP0. That is,
43902 * <PRE>
43903 * dstReg x= () [srcBase]
43904 * </PRE>
43905 *
43906 * @param dstReg destination register, must be FP0
43907 * @param srcBase source base register
43908 */
43909 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
43910 public final void emitFMUL_Reg_RegInd(FPR dstReg, GPR srcBase) {
43911 int miStart = mi;
43912 // Must store result to top of stack
43913 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43914 setMachineCodes(mi++, (byte) 0xD8);
43915 // The register'' 1 is really part of the opcode
43916 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(1));
43917 if (lister != null) lister.RRN(miStart, "FMUL", dstReg, srcBase);
43918 }
43919
43920 /**
43921 * Perform x on dstReg. That is,
43922 * <PRE>
43923 * dstReg x= () [srcBase + srcIndex<<srcScale + srcDisp]
43924 * </PRE>
43925 *
43926 * @param dstReg destination register, must be FP0
43927 * @param srcBase source base register
43928 * @param srcIndex source index register
43929 * @param srcScale source scale
43930 * @param srcDisp source displacement
43931 */
43932 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
43933 public final void emitFMUL_Reg_RegIdx(FPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
43934 int miStart = mi;
43935 // Must store result to top of stack
43936 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43937 setMachineCodes(mi++, (byte) 0xD8);
43938 // The register'' 1 is really part of the opcode
43939 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(1));
43940 if (lister != null) lister.RRXD(miStart, "FMUL", dstReg, srcBase, srcIndex, srcScale, srcDisp);
43941 }
43942
43943 /**
43944 * Perform x on FP0. That is,
43945 * <PRE>
43946 * dstReg x= () [srcIndex<<srcScale + srcDisp]
43947 * </PRE>
43948 *
43949 * @param dstReg destination register, must be FP0
43950 * @param srcIndex source index register
43951 * @param srcScale source scale
43952 * @param srcDisp source displacement
43953 */
43954 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
43955 public final void emitFMUL_Reg_RegOff(FPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
43956 int miStart = mi;
43957 // Must store result to top of stack
43958 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43959 setMachineCodes(mi++, (byte) 0xD8);
43960 // The register'' 1 is really part of the opcode
43961 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(1));
43962 if (lister != null) lister.RRFD(miStart, "FMUL", dstReg, srcIndex, srcScale, srcDisp);
43963 }
43964
43965 /**
43966 * Perform x on FP0. That is,
43967 * <PRE>
43968 * dstReg x= () [srcDisp]
43969 * </PRE>
43970 *
43971 * @param dstReg destination register, must be FP0
43972 * @param srcDisp source displacement
43973 */
43974 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
43975 public final void emitFMUL_Reg_Abs(FPR dstReg, Address srcDisp) {
43976 int miStart = mi;
43977 // Must store result to top of stack
43978 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
43979 setMachineCodes(mi++, (byte) 0xD8);
43980 // The register'' 1 is really part of the opcode
43981 emitAbsRegOperands(srcDisp, GPR.getForOpcode(1));
43982 if (lister != null) lister.RRA(miStart, "FMUL", dstReg, srcDisp);
43983 }
43984
43985 /**
43986 * Perform x on FP0. That is,
43987 * <PRE>
43988 * dstReg x= (quad) [srcBase + srcDisp]
43989 * </PRE>
43990 *
43991 * @param dstReg destination register, must be FP0
43992 * @param srcBase source base register
43993 * @param srcDisp source displacement
43994 */
43995 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
43996 public final void emitFMUL_Reg_RegDisp_Quad(FPR dstReg, GPR srcBase, Offset srcDisp) {
43997 int miStart = mi;
43998 // Must store result to top of stack
43999 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44000 setMachineCodes(mi++, (byte) 0xDC);
44001 // The register'' 1 is really part of the opcode
44002 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(1));
44003 if (lister != null) lister.RRD(miStart, "FMUL", dstReg, srcBase, srcDisp);
44004 }
44005
44006 /**
44007 * Perform x on FP0. That is,
44008 * <PRE>
44009 * dstReg x= (quad) [srcBase]
44010 * </PRE>
44011 *
44012 * @param dstReg destination register, must be FP0
44013 * @param srcBase source base register
44014 */
44015 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
44016 public final void emitFMUL_Reg_RegInd_Quad(FPR dstReg, GPR srcBase) {
44017 int miStart = mi;
44018 // Must store result to top of stack
44019 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44020 setMachineCodes(mi++, (byte) 0xDC);
44021 // The register'' 1 is really part of the opcode
44022 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(1));
44023 if (lister != null) lister.RRN(miStart, "FMUL", dstReg, srcBase);
44024 }
44025
44026 /**
44027 * Perform x on dstReg. That is,
44028 * <PRE>
44029 * dstReg x= (quad) [srcBase + srcIndex<<srcScale + srcDisp]
44030 * </PRE>
44031 *
44032 * @param dstReg destination register, must be FP0
44033 * @param srcBase source base register
44034 * @param srcIndex source index register
44035 * @param srcScale source scale
44036 * @param srcDisp source displacement
44037 */
44038 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
44039 public final void emitFMUL_Reg_RegIdx_Quad(FPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
44040 int miStart = mi;
44041 // Must store result to top of stack
44042 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44043 setMachineCodes(mi++, (byte) 0xDC);
44044 // The register'' 1 is really part of the opcode
44045 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(1));
44046 if (lister != null) lister.RRXD(miStart, "FMUL", dstReg, srcBase, srcIndex, srcScale, srcDisp);
44047 }
44048
44049 /**
44050 * Perform x on FP0. That is,
44051 * <PRE>
44052 * dstReg x= (quad) [srcIndex<<srcScale + srcDisp]
44053 * </PRE>
44054 *
44055 * @param dstReg destination register, must be FP0
44056 * @param srcIndex source index register
44057 * @param srcScale source scale
44058 * @param srcDisp source displacement
44059 */
44060 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
44061 public final void emitFMUL_Reg_RegOff_Quad(FPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
44062 int miStart = mi;
44063 // Must store result to top of stack
44064 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44065 setMachineCodes(mi++, (byte) 0xDC);
44066 // The register'' 1 is really part of the opcode
44067 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(1));
44068 if (lister != null) lister.RRFD(miStart, "FMUL", dstReg, srcIndex, srcScale, srcDisp);
44069 }
44070
44071 /**
44072 * Perform x on FP0. That is,
44073 * <PRE>
44074 * dstReg x= (quad) [srcDisp]
44075 * </PRE>
44076 *
44077 * @param dstReg destination register, must be FP0
44078 * @param srcDisp source displacement
44079 */
44080 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
44081 public final void emitFMUL_Reg_Abs_Quad(FPR dstReg, Address srcDisp) {
44082 int miStart = mi;
44083 // Must store result to top of stack
44084 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44085 setMachineCodes(mi++, (byte) 0xDC);
44086 // The register'' 1 is really part of the opcode
44087 emitAbsRegOperands(srcDisp, GPR.getForOpcode(1));
44088 if (lister != null) lister.RRA(miStart, "FMUL", dstReg, srcDisp);
44089 }
44090
44091 /**
44092 * Perform x on FP0. That is,
44093 * <PRE>
44094 * dstReg x= () [srcBase + srcDisp]
44095 * </PRE>
44096 *
44097 * @param dstReg destination register, must be FP0
44098 * @param srcBase source base register
44099 * @param srcDisp source displacement
44100 */
44101 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
44102 public final void emitFIMUL_Reg_RegDisp(FPR dstReg, GPR srcBase, Offset srcDisp) {
44103 int miStart = mi;
44104 // Must store result to top of stack
44105 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44106 setMachineCodes(mi++, (byte) 0xDA);
44107 // The register'' 1 is really part of the opcode
44108 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(1));
44109 if (lister != null) lister.RRD(miStart, "FIMUL", dstReg, srcBase, srcDisp);
44110 }
44111
44112 /**
44113 * Perform x on FP0. That is,
44114 * <PRE>
44115 * dstReg x= () [srcBase]
44116 * </PRE>
44117 *
44118 * @param dstReg destination register, must be FP0
44119 * @param srcBase source base register
44120 */
44121 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
44122 public final void emitFIMUL_Reg_RegInd(FPR dstReg, GPR srcBase) {
44123 int miStart = mi;
44124 // Must store result to top of stack
44125 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44126 setMachineCodes(mi++, (byte) 0xDA);
44127 // The register'' 1 is really part of the opcode
44128 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(1));
44129 if (lister != null) lister.RRN(miStart, "FIMUL", dstReg, srcBase);
44130 }
44131
44132 /**
44133 * Perform x on dstReg. That is,
44134 * <PRE>
44135 * dstReg x= () [srcBase + srcIndex<<srcScale + srcDisp]
44136 * </PRE>
44137 *
44138 * @param dstReg destination register, must be FP0
44139 * @param srcBase source base register
44140 * @param srcIndex source index register
44141 * @param srcScale source scale
44142 * @param srcDisp source displacement
44143 */
44144 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
44145 public final void emitFIMUL_Reg_RegIdx(FPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
44146 int miStart = mi;
44147 // Must store result to top of stack
44148 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44149 setMachineCodes(mi++, (byte) 0xDA);
44150 // The register'' 1 is really part of the opcode
44151 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(1));
44152 if (lister != null) lister.RRXD(miStart, "FIMUL", dstReg, srcBase, srcIndex, srcScale, srcDisp);
44153 }
44154
44155 /**
44156 * Perform x on FP0. That is,
44157 * <PRE>
44158 * dstReg x= () [srcIndex<<srcScale + srcDisp]
44159 * </PRE>
44160 *
44161 * @param dstReg destination register, must be FP0
44162 * @param srcIndex source index register
44163 * @param srcScale source scale
44164 * @param srcDisp source displacement
44165 */
44166 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
44167 public final void emitFIMUL_Reg_RegOff(FPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
44168 int miStart = mi;
44169 // Must store result to top of stack
44170 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44171 setMachineCodes(mi++, (byte) 0xDA);
44172 // The register'' 1 is really part of the opcode
44173 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(1));
44174 if (lister != null) lister.RRFD(miStart, "FIMUL", dstReg, srcIndex, srcScale, srcDisp);
44175 }
44176
44177 /**
44178 * Perform x on FP0. That is,
44179 * <PRE>
44180 * dstReg x= () [srcDisp]
44181 * </PRE>
44182 *
44183 * @param dstReg destination register, must be FP0
44184 * @param srcDisp source displacement
44185 */
44186 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
44187 public final void emitFIMUL_Reg_Abs(FPR dstReg, Address srcDisp) {
44188 int miStart = mi;
44189 // Must store result to top of stack
44190 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44191 setMachineCodes(mi++, (byte) 0xDA);
44192 // The register'' 1 is really part of the opcode
44193 emitAbsRegOperands(srcDisp, GPR.getForOpcode(1));
44194 if (lister != null) lister.RRA(miStart, "FIMUL", dstReg, srcDisp);
44195 }
44196
44197 /**
44198 * Perform x on FP0. That is,
44199 * <PRE>
44200 * dstReg x= (word) [srcBase + srcDisp]
44201 * </PRE>
44202 *
44203 * @param dstReg destination register, must be FP0
44204 * @param srcBase source base register
44205 * @param srcDisp source displacement
44206 */
44207 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
44208 public final void emitFIMUL_Reg_RegDisp_Word(FPR dstReg, GPR srcBase, Offset srcDisp) {
44209 int miStart = mi;
44210 // Must store result to top of stack
44211 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44212 setMachineCodes(mi++, (byte) 0xDE);
44213 // The register'' 1 is really part of the opcode
44214 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(1));
44215 if (lister != null) lister.RRD(miStart, "FIMUL", dstReg, srcBase, srcDisp);
44216 }
44217
44218 /**
44219 * Perform x on FP0. That is,
44220 * <PRE>
44221 * dstReg x= (word) [srcBase]
44222 * </PRE>
44223 *
44224 * @param dstReg destination register, must be FP0
44225 * @param srcBase source base register
44226 */
44227 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
44228 public final void emitFIMUL_Reg_RegInd_Word(FPR dstReg, GPR srcBase) {
44229 int miStart = mi;
44230 // Must store result to top of stack
44231 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44232 setMachineCodes(mi++, (byte) 0xDE);
44233 // The register'' 1 is really part of the opcode
44234 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(1));
44235 if (lister != null) lister.RRN(miStart, "FIMUL", dstReg, srcBase);
44236 }
44237
44238 /**
44239 * Perform x on dstReg. That is,
44240 * <PRE>
44241 * dstReg x= (word) [srcBase + srcIndex<<srcScale + srcDisp]
44242 * </PRE>
44243 *
44244 * @param dstReg destination register, must be FP0
44245 * @param srcBase source base register
44246 * @param srcIndex source index register
44247 * @param srcScale source scale
44248 * @param srcDisp source displacement
44249 */
44250 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
44251 public final void emitFIMUL_Reg_RegIdx_Word(FPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
44252 int miStart = mi;
44253 // Must store result to top of stack
44254 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44255 setMachineCodes(mi++, (byte) 0xDE);
44256 // The register'' 1 is really part of the opcode
44257 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(1));
44258 if (lister != null) lister.RRXD(miStart, "FIMUL", dstReg, srcBase, srcIndex, srcScale, srcDisp);
44259 }
44260
44261 /**
44262 * Perform x on FP0. That is,
44263 * <PRE>
44264 * dstReg x= (word) [srcIndex<<srcScale + srcDisp]
44265 * </PRE>
44266 *
44267 * @param dstReg destination register, must be FP0
44268 * @param srcIndex source index register
44269 * @param srcScale source scale
44270 * @param srcDisp source displacement
44271 */
44272 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
44273 public final void emitFIMUL_Reg_RegOff_Word(FPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
44274 int miStart = mi;
44275 // Must store result to top of stack
44276 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44277 setMachineCodes(mi++, (byte) 0xDE);
44278 // The register'' 1 is really part of the opcode
44279 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(1));
44280 if (lister != null) lister.RRFD(miStart, "FIMUL", dstReg, srcIndex, srcScale, srcDisp);
44281 }
44282
44283 /**
44284 * Perform x on FP0. That is,
44285 * <PRE>
44286 * dstReg x= (word) [srcDisp]
44287 * </PRE>
44288 *
44289 * @param dstReg destination register, must be FP0
44290 * @param srcDisp source displacement
44291 */
44292 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
44293 public final void emitFIMUL_Reg_Abs_Word(FPR dstReg, Address srcDisp) {
44294 int miStart = mi;
44295 // Must store result to top of stack
44296 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44297 setMachineCodes(mi++, (byte) 0xDE);
44298 // The register'' 1 is really part of the opcode
44299 emitAbsRegOperands(srcDisp, GPR.getForOpcode(1));
44300 if (lister != null) lister.RRA(miStart, "FIMUL", dstReg, srcDisp);
44301 }
44302
44303 /**
44304 * Perform x either to or from FP0. That is,
44305 * <PRE>
44306 * dstReg x= srcReg
44307 * </PRE>
44308 *
44309 * @param dstReg destination register, this or srcReg must be FP0
44310 * @param srcReg source register, this or dstReg must be FP0
44311 */
44312 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
44313 public final void emitFMUL_Reg_Reg(FPR dstReg, FPR srcReg) {
44314 int miStart = mi;
44315 if (VM.VerifyAssertions) VM._assert(srcReg == FP0 || dstReg == FP0);
44316 if (dstReg == FP0) {
44317 setMachineCodes(mi++, (byte) 0xD8);
44318 setMachineCodes(mi++, (byte) (0xC8 | srcReg.value()));
44319 } else if (srcReg == FP0) {
44320 setMachineCodes(mi++, (byte) 0xDC);
44321 setMachineCodes(mi++, (byte) (0xC8 | dstReg.value()));
44322 }
44323 if (lister != null) lister.RR(miStart, "FMUL", dstReg, srcReg);
44324 }
44325
44326 /**
44327 * Perform x then pop stack. That is,
44328 * <PRE>
44329 * srcReg x= ST(0); pop stack
44330 * </PRE>
44331 *
44332 * @param dstReg destination register
44333 * @param srcReg source register
44334 */
44335 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
44336 public final void emitFMULP_Reg_Reg(FPR dstReg, FPR srcReg) {
44337 int miStart = mi;
44338 if (VM.VerifyAssertions) VM._assert(srcReg == FP0);
44339 setMachineCodes(mi++, (byte) 0xDE);
44340 setMachineCodes(mi++, (byte) (0xC8 | dstReg.value()));
44341 if (lister != null) lister.R(miStart, "FMULP", dstReg);
44342 }
44343
44344 /**
44345 * Perform - on FP0. That is,
44346 * <PRE>
44347 * dstReg -= () [srcBase + srcDisp]
44348 * </PRE>
44349 *
44350 * @param dstReg destination register, must be FP0
44351 * @param srcBase source base register
44352 * @param srcDisp source displacement
44353 */
44354 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
44355 public final void emitFSUB_Reg_RegDisp(FPR dstReg, GPR srcBase, Offset srcDisp) {
44356 int miStart = mi;
44357 // Must store result to top of stack
44358 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44359 setMachineCodes(mi++, (byte) 0xD8);
44360 // The register'' 4 is really part of the opcode
44361 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(4));
44362 if (lister != null) lister.RRD(miStart, "FSUB", dstReg, srcBase, srcDisp);
44363 }
44364
44365 /**
44366 * Perform - on FP0. That is,
44367 * <PRE>
44368 * dstReg -= () [srcBase]
44369 * </PRE>
44370 *
44371 * @param dstReg destination register, must be FP0
44372 * @param srcBase source base register
44373 */
44374 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
44375 public final void emitFSUB_Reg_RegInd(FPR dstReg, GPR srcBase) {
44376 int miStart = mi;
44377 // Must store result to top of stack
44378 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44379 setMachineCodes(mi++, (byte) 0xD8);
44380 // The register'' 4 is really part of the opcode
44381 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(4));
44382 if (lister != null) lister.RRN(miStart, "FSUB", dstReg, srcBase);
44383 }
44384
44385 /**
44386 * Perform - on dstReg. That is,
44387 * <PRE>
44388 * dstReg -= () [srcBase + srcIndex<<srcScale + srcDisp]
44389 * </PRE>
44390 *
44391 * @param dstReg destination register, must be FP0
44392 * @param srcBase source base register
44393 * @param srcIndex source index register
44394 * @param srcScale source scale
44395 * @param srcDisp source displacement
44396 */
44397 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
44398 public final void emitFSUB_Reg_RegIdx(FPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
44399 int miStart = mi;
44400 // Must store result to top of stack
44401 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44402 setMachineCodes(mi++, (byte) 0xD8);
44403 // The register'' 4 is really part of the opcode
44404 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(4));
44405 if (lister != null) lister.RRXD(miStart, "FSUB", dstReg, srcBase, srcIndex, srcScale, srcDisp);
44406 }
44407
44408 /**
44409 * Perform - on FP0. That is,
44410 * <PRE>
44411 * dstReg -= () [srcIndex<<srcScale + srcDisp]
44412 * </PRE>
44413 *
44414 * @param dstReg destination register, must be FP0
44415 * @param srcIndex source index register
44416 * @param srcScale source scale
44417 * @param srcDisp source displacement
44418 */
44419 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
44420 public final void emitFSUB_Reg_RegOff(FPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
44421 int miStart = mi;
44422 // Must store result to top of stack
44423 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44424 setMachineCodes(mi++, (byte) 0xD8);
44425 // The register'' 4 is really part of the opcode
44426 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(4));
44427 if (lister != null) lister.RRFD(miStart, "FSUB", dstReg, srcIndex, srcScale, srcDisp);
44428 }
44429
44430 /**
44431 * Perform - on FP0. That is,
44432 * <PRE>
44433 * dstReg -= () [srcDisp]
44434 * </PRE>
44435 *
44436 * @param dstReg destination register, must be FP0
44437 * @param srcDisp source displacement
44438 */
44439 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
44440 public final void emitFSUB_Reg_Abs(FPR dstReg, Address srcDisp) {
44441 int miStart = mi;
44442 // Must store result to top of stack
44443 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44444 setMachineCodes(mi++, (byte) 0xD8);
44445 // The register'' 4 is really part of the opcode
44446 emitAbsRegOperands(srcDisp, GPR.getForOpcode(4));
44447 if (lister != null) lister.RRA(miStart, "FSUB", dstReg, srcDisp);
44448 }
44449
44450 /**
44451 * Perform - on FP0. That is,
44452 * <PRE>
44453 * dstReg -= (quad) [srcBase + srcDisp]
44454 * </PRE>
44455 *
44456 * @param dstReg destination register, must be FP0
44457 * @param srcBase source base register
44458 * @param srcDisp source displacement
44459 */
44460 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
44461 public final void emitFSUB_Reg_RegDisp_Quad(FPR dstReg, GPR srcBase, Offset srcDisp) {
44462 int miStart = mi;
44463 // Must store result to top of stack
44464 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44465 setMachineCodes(mi++, (byte) 0xDC);
44466 // The register'' 4 is really part of the opcode
44467 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(4));
44468 if (lister != null) lister.RRD(miStart, "FSUB", dstReg, srcBase, srcDisp);
44469 }
44470
44471 /**
44472 * Perform - on FP0. That is,
44473 * <PRE>
44474 * dstReg -= (quad) [srcBase]
44475 * </PRE>
44476 *
44477 * @param dstReg destination register, must be FP0
44478 * @param srcBase source base register
44479 */
44480 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
44481 public final void emitFSUB_Reg_RegInd_Quad(FPR dstReg, GPR srcBase) {
44482 int miStart = mi;
44483 // Must store result to top of stack
44484 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44485 setMachineCodes(mi++, (byte) 0xDC);
44486 // The register'' 4 is really part of the opcode
44487 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(4));
44488 if (lister != null) lister.RRN(miStart, "FSUB", dstReg, srcBase);
44489 }
44490
44491 /**
44492 * Perform - on dstReg. That is,
44493 * <PRE>
44494 * dstReg -= (quad) [srcBase + srcIndex<<srcScale + srcDisp]
44495 * </PRE>
44496 *
44497 * @param dstReg destination register, must be FP0
44498 * @param srcBase source base register
44499 * @param srcIndex source index register
44500 * @param srcScale source scale
44501 * @param srcDisp source displacement
44502 */
44503 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
44504 public final void emitFSUB_Reg_RegIdx_Quad(FPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
44505 int miStart = mi;
44506 // Must store result to top of stack
44507 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44508 setMachineCodes(mi++, (byte) 0xDC);
44509 // The register'' 4 is really part of the opcode
44510 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(4));
44511 if (lister != null) lister.RRXD(miStart, "FSUB", dstReg, srcBase, srcIndex, srcScale, srcDisp);
44512 }
44513
44514 /**
44515 * Perform - on FP0. That is,
44516 * <PRE>
44517 * dstReg -= (quad) [srcIndex<<srcScale + srcDisp]
44518 * </PRE>
44519 *
44520 * @param dstReg destination register, must be FP0
44521 * @param srcIndex source index register
44522 * @param srcScale source scale
44523 * @param srcDisp source displacement
44524 */
44525 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
44526 public final void emitFSUB_Reg_RegOff_Quad(FPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
44527 int miStart = mi;
44528 // Must store result to top of stack
44529 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44530 setMachineCodes(mi++, (byte) 0xDC);
44531 // The register'' 4 is really part of the opcode
44532 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(4));
44533 if (lister != null) lister.RRFD(miStart, "FSUB", dstReg, srcIndex, srcScale, srcDisp);
44534 }
44535
44536 /**
44537 * Perform - on FP0. That is,
44538 * <PRE>
44539 * dstReg -= (quad) [srcDisp]
44540 * </PRE>
44541 *
44542 * @param dstReg destination register, must be FP0
44543 * @param srcDisp source displacement
44544 */
44545 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
44546 public final void emitFSUB_Reg_Abs_Quad(FPR dstReg, Address srcDisp) {
44547 int miStart = mi;
44548 // Must store result to top of stack
44549 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44550 setMachineCodes(mi++, (byte) 0xDC);
44551 // The register'' 4 is really part of the opcode
44552 emitAbsRegOperands(srcDisp, GPR.getForOpcode(4));
44553 if (lister != null) lister.RRA(miStart, "FSUB", dstReg, srcDisp);
44554 }
44555
44556 /**
44557 * Perform - on FP0. That is,
44558 * <PRE>
44559 * dstReg -= () [srcBase + srcDisp]
44560 * </PRE>
44561 *
44562 * @param dstReg destination register, must be FP0
44563 * @param srcBase source base register
44564 * @param srcDisp source displacement
44565 */
44566 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
44567 public final void emitFISUB_Reg_RegDisp(FPR dstReg, GPR srcBase, Offset srcDisp) {
44568 int miStart = mi;
44569 // Must store result to top of stack
44570 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44571 setMachineCodes(mi++, (byte) 0xDA);
44572 // The register'' 4 is really part of the opcode
44573 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(4));
44574 if (lister != null) lister.RRD(miStart, "FISUB", dstReg, srcBase, srcDisp);
44575 }
44576
44577 /**
44578 * Perform - on FP0. That is,
44579 * <PRE>
44580 * dstReg -= () [srcBase]
44581 * </PRE>
44582 *
44583 * @param dstReg destination register, must be FP0
44584 * @param srcBase source base register
44585 */
44586 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
44587 public final void emitFISUB_Reg_RegInd(FPR dstReg, GPR srcBase) {
44588 int miStart = mi;
44589 // Must store result to top of stack
44590 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44591 setMachineCodes(mi++, (byte) 0xDA);
44592 // The register'' 4 is really part of the opcode
44593 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(4));
44594 if (lister != null) lister.RRN(miStart, "FISUB", dstReg, srcBase);
44595 }
44596
44597 /**
44598 * Perform - on dstReg. That is,
44599 * <PRE>
44600 * dstReg -= () [srcBase + srcIndex<<srcScale + srcDisp]
44601 * </PRE>
44602 *
44603 * @param dstReg destination register, must be FP0
44604 * @param srcBase source base register
44605 * @param srcIndex source index register
44606 * @param srcScale source scale
44607 * @param srcDisp source displacement
44608 */
44609 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
44610 public final void emitFISUB_Reg_RegIdx(FPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
44611 int miStart = mi;
44612 // Must store result to top of stack
44613 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44614 setMachineCodes(mi++, (byte) 0xDA);
44615 // The register'' 4 is really part of the opcode
44616 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(4));
44617 if (lister != null) lister.RRXD(miStart, "FISUB", dstReg, srcBase, srcIndex, srcScale, srcDisp);
44618 }
44619
44620 /**
44621 * Perform - on FP0. That is,
44622 * <PRE>
44623 * dstReg -= () [srcIndex<<srcScale + srcDisp]
44624 * </PRE>
44625 *
44626 * @param dstReg destination register, must be FP0
44627 * @param srcIndex source index register
44628 * @param srcScale source scale
44629 * @param srcDisp source displacement
44630 */
44631 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
44632 public final void emitFISUB_Reg_RegOff(FPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
44633 int miStart = mi;
44634 // Must store result to top of stack
44635 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44636 setMachineCodes(mi++, (byte) 0xDA);
44637 // The register'' 4 is really part of the opcode
44638 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(4));
44639 if (lister != null) lister.RRFD(miStart, "FISUB", dstReg, srcIndex, srcScale, srcDisp);
44640 }
44641
44642 /**
44643 * Perform - on FP0. That is,
44644 * <PRE>
44645 * dstReg -= () [srcDisp]
44646 * </PRE>
44647 *
44648 * @param dstReg destination register, must be FP0
44649 * @param srcDisp source displacement
44650 */
44651 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
44652 public final void emitFISUB_Reg_Abs(FPR dstReg, Address srcDisp) {
44653 int miStart = mi;
44654 // Must store result to top of stack
44655 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44656 setMachineCodes(mi++, (byte) 0xDA);
44657 // The register'' 4 is really part of the opcode
44658 emitAbsRegOperands(srcDisp, GPR.getForOpcode(4));
44659 if (lister != null) lister.RRA(miStart, "FISUB", dstReg, srcDisp);
44660 }
44661
44662 /**
44663 * Perform - on FP0. That is,
44664 * <PRE>
44665 * dstReg -= (word) [srcBase + srcDisp]
44666 * </PRE>
44667 *
44668 * @param dstReg destination register, must be FP0
44669 * @param srcBase source base register
44670 * @param srcDisp source displacement
44671 */
44672 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
44673 public final void emitFISUB_Reg_RegDisp_Word(FPR dstReg, GPR srcBase, Offset srcDisp) {
44674 int miStart = mi;
44675 // Must store result to top of stack
44676 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44677 setMachineCodes(mi++, (byte) 0xDE);
44678 // The register'' 4 is really part of the opcode
44679 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(4));
44680 if (lister != null) lister.RRD(miStart, "FISUB", dstReg, srcBase, srcDisp);
44681 }
44682
44683 /**
44684 * Perform - on FP0. That is,
44685 * <PRE>
44686 * dstReg -= (word) [srcBase]
44687 * </PRE>
44688 *
44689 * @param dstReg destination register, must be FP0
44690 * @param srcBase source base register
44691 */
44692 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
44693 public final void emitFISUB_Reg_RegInd_Word(FPR dstReg, GPR srcBase) {
44694 int miStart = mi;
44695 // Must store result to top of stack
44696 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44697 setMachineCodes(mi++, (byte) 0xDE);
44698 // The register'' 4 is really part of the opcode
44699 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(4));
44700 if (lister != null) lister.RRN(miStart, "FISUB", dstReg, srcBase);
44701 }
44702
44703 /**
44704 * Perform - on dstReg. That is,
44705 * <PRE>
44706 * dstReg -= (word) [srcBase + srcIndex<<srcScale + srcDisp]
44707 * </PRE>
44708 *
44709 * @param dstReg destination register, must be FP0
44710 * @param srcBase source base register
44711 * @param srcIndex source index register
44712 * @param srcScale source scale
44713 * @param srcDisp source displacement
44714 */
44715 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
44716 public final void emitFISUB_Reg_RegIdx_Word(FPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
44717 int miStart = mi;
44718 // Must store result to top of stack
44719 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44720 setMachineCodes(mi++, (byte) 0xDE);
44721 // The register'' 4 is really part of the opcode
44722 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(4));
44723 if (lister != null) lister.RRXD(miStart, "FISUB", dstReg, srcBase, srcIndex, srcScale, srcDisp);
44724 }
44725
44726 /**
44727 * Perform - on FP0. That is,
44728 * <PRE>
44729 * dstReg -= (word) [srcIndex<<srcScale + srcDisp]
44730 * </PRE>
44731 *
44732 * @param dstReg destination register, must be FP0
44733 * @param srcIndex source index register
44734 * @param srcScale source scale
44735 * @param srcDisp source displacement
44736 */
44737 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
44738 public final void emitFISUB_Reg_RegOff_Word(FPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
44739 int miStart = mi;
44740 // Must store result to top of stack
44741 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44742 setMachineCodes(mi++, (byte) 0xDE);
44743 // The register'' 4 is really part of the opcode
44744 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(4));
44745 if (lister != null) lister.RRFD(miStart, "FISUB", dstReg, srcIndex, srcScale, srcDisp);
44746 }
44747
44748 /**
44749 * Perform - on FP0. That is,
44750 * <PRE>
44751 * dstReg -= (word) [srcDisp]
44752 * </PRE>
44753 *
44754 * @param dstReg destination register, must be FP0
44755 * @param srcDisp source displacement
44756 */
44757 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
44758 public final void emitFISUB_Reg_Abs_Word(FPR dstReg, Address srcDisp) {
44759 int miStart = mi;
44760 // Must store result to top of stack
44761 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44762 setMachineCodes(mi++, (byte) 0xDE);
44763 // The register'' 4 is really part of the opcode
44764 emitAbsRegOperands(srcDisp, GPR.getForOpcode(4));
44765 if (lister != null) lister.RRA(miStart, "FISUB", dstReg, srcDisp);
44766 }
44767
44768 /**
44769 * Perform - either to or from FP0. That is,
44770 * <PRE>
44771 * dstReg -= srcReg
44772 * </PRE>
44773 *
44774 * @param dstReg destination register, this or srcReg must be FP0
44775 * @param srcReg source register, this or dstReg must be FP0
44776 */
44777 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
44778 public final void emitFSUB_Reg_Reg(FPR dstReg, FPR srcReg) {
44779 int miStart = mi;
44780 if (VM.VerifyAssertions) VM._assert(srcReg == FP0 || dstReg == FP0);
44781 if (dstReg == FP0) {
44782 setMachineCodes(mi++, (byte) 0xD8);
44783 setMachineCodes(mi++, (byte) (0xE0 | srcReg.value()));
44784 } else if (srcReg == FP0) {
44785 setMachineCodes(mi++, (byte) 0xDC);
44786 setMachineCodes(mi++, (byte) (0xE8 | dstReg.value()));
44787 }
44788 if (lister != null) lister.RR(miStart, "FSUB", dstReg, srcReg);
44789 }
44790
44791 /**
44792 * Perform - then pop stack. That is,
44793 * <PRE>
44794 * srcReg -= ST(0); pop stack
44795 * </PRE>
44796 *
44797 * @param dstReg destination register
44798 * @param srcReg source register
44799 */
44800 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
44801 public final void emitFSUBP_Reg_Reg(FPR dstReg, FPR srcReg) {
44802 int miStart = mi;
44803 if (VM.VerifyAssertions) VM._assert(srcReg == FP0);
44804 setMachineCodes(mi++, (byte) 0xDE);
44805 setMachineCodes(mi++, (byte) (0xE8 | dstReg.value()));
44806 if (lister != null) lister.R(miStart, "FSUBP", dstReg);
44807 }
44808
44809 /**
44810 * Perform - on FP0. That is,
44811 * <PRE>
44812 * dstReg -= () [srcBase + srcDisp]
44813 * </PRE>
44814 *
44815 * @param dstReg destination register, must be FP0
44816 * @param srcBase source base register
44817 * @param srcDisp source displacement
44818 */
44819 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
44820 public final void emitFSUBR_Reg_RegDisp(FPR dstReg, GPR srcBase, Offset srcDisp) {
44821 int miStart = mi;
44822 // Must store result to top of stack
44823 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44824 setMachineCodes(mi++, (byte) 0xD8);
44825 // The register'' 5 is really part of the opcode
44826 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(5));
44827 if (lister != null) lister.RRD(miStart, "FSUBR", dstReg, srcBase, srcDisp);
44828 }
44829
44830 /**
44831 * Perform - on FP0. That is,
44832 * <PRE>
44833 * dstReg -= () [srcBase]
44834 * </PRE>
44835 *
44836 * @param dstReg destination register, must be FP0
44837 * @param srcBase source base register
44838 */
44839 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
44840 public final void emitFSUBR_Reg_RegInd(FPR dstReg, GPR srcBase) {
44841 int miStart = mi;
44842 // Must store result to top of stack
44843 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44844 setMachineCodes(mi++, (byte) 0xD8);
44845 // The register'' 5 is really part of the opcode
44846 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(5));
44847 if (lister != null) lister.RRN(miStart, "FSUBR", dstReg, srcBase);
44848 }
44849
44850 /**
44851 * Perform - on dstReg. That is,
44852 * <PRE>
44853 * dstReg -= () [srcBase + srcIndex<<srcScale + srcDisp]
44854 * </PRE>
44855 *
44856 * @param dstReg destination register, must be FP0
44857 * @param srcBase source base register
44858 * @param srcIndex source index register
44859 * @param srcScale source scale
44860 * @param srcDisp source displacement
44861 */
44862 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
44863 public final void emitFSUBR_Reg_RegIdx(FPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
44864 int miStart = mi;
44865 // Must store result to top of stack
44866 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44867 setMachineCodes(mi++, (byte) 0xD8);
44868 // The register'' 5 is really part of the opcode
44869 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(5));
44870 if (lister != null) lister.RRXD(miStart, "FSUBR", dstReg, srcBase, srcIndex, srcScale, srcDisp);
44871 }
44872
44873 /**
44874 * Perform - on FP0. That is,
44875 * <PRE>
44876 * dstReg -= () [srcIndex<<srcScale + srcDisp]
44877 * </PRE>
44878 *
44879 * @param dstReg destination register, must be FP0
44880 * @param srcIndex source index register
44881 * @param srcScale source scale
44882 * @param srcDisp source displacement
44883 */
44884 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
44885 public final void emitFSUBR_Reg_RegOff(FPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
44886 int miStart = mi;
44887 // Must store result to top of stack
44888 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44889 setMachineCodes(mi++, (byte) 0xD8);
44890 // The register'' 5 is really part of the opcode
44891 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(5));
44892 if (lister != null) lister.RRFD(miStart, "FSUBR", dstReg, srcIndex, srcScale, srcDisp);
44893 }
44894
44895 /**
44896 * Perform - on FP0. That is,
44897 * <PRE>
44898 * dstReg -= () [srcDisp]
44899 * </PRE>
44900 *
44901 * @param dstReg destination register, must be FP0
44902 * @param srcDisp source displacement
44903 */
44904 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
44905 public final void emitFSUBR_Reg_Abs(FPR dstReg, Address srcDisp) {
44906 int miStart = mi;
44907 // Must store result to top of stack
44908 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44909 setMachineCodes(mi++, (byte) 0xD8);
44910 // The register'' 5 is really part of the opcode
44911 emitAbsRegOperands(srcDisp, GPR.getForOpcode(5));
44912 if (lister != null) lister.RRA(miStart, "FSUBR", dstReg, srcDisp);
44913 }
44914
44915 /**
44916 * Perform - on FP0. That is,
44917 * <PRE>
44918 * dstReg -= (quad) [srcBase + srcDisp]
44919 * </PRE>
44920 *
44921 * @param dstReg destination register, must be FP0
44922 * @param srcBase source base register
44923 * @param srcDisp source displacement
44924 */
44925 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
44926 public final void emitFSUBR_Reg_RegDisp_Quad(FPR dstReg, GPR srcBase, Offset srcDisp) {
44927 int miStart = mi;
44928 // Must store result to top of stack
44929 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44930 setMachineCodes(mi++, (byte) 0xDC);
44931 // The register'' 5 is really part of the opcode
44932 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(5));
44933 if (lister != null) lister.RRD(miStart, "FSUBR", dstReg, srcBase, srcDisp);
44934 }
44935
44936 /**
44937 * Perform - on FP0. That is,
44938 * <PRE>
44939 * dstReg -= (quad) [srcBase]
44940 * </PRE>
44941 *
44942 * @param dstReg destination register, must be FP0
44943 * @param srcBase source base register
44944 */
44945 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
44946 public final void emitFSUBR_Reg_RegInd_Quad(FPR dstReg, GPR srcBase) {
44947 int miStart = mi;
44948 // Must store result to top of stack
44949 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44950 setMachineCodes(mi++, (byte) 0xDC);
44951 // The register'' 5 is really part of the opcode
44952 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(5));
44953 if (lister != null) lister.RRN(miStart, "FSUBR", dstReg, srcBase);
44954 }
44955
44956 /**
44957 * Perform - on dstReg. That is,
44958 * <PRE>
44959 * dstReg -= (quad) [srcBase + srcIndex<<srcScale + srcDisp]
44960 * </PRE>
44961 *
44962 * @param dstReg destination register, must be FP0
44963 * @param srcBase source base register
44964 * @param srcIndex source index register
44965 * @param srcScale source scale
44966 * @param srcDisp source displacement
44967 */
44968 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
44969 public final void emitFSUBR_Reg_RegIdx_Quad(FPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
44970 int miStart = mi;
44971 // Must store result to top of stack
44972 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44973 setMachineCodes(mi++, (byte) 0xDC);
44974 // The register'' 5 is really part of the opcode
44975 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(5));
44976 if (lister != null) lister.RRXD(miStart, "FSUBR", dstReg, srcBase, srcIndex, srcScale, srcDisp);
44977 }
44978
44979 /**
44980 * Perform - on FP0. That is,
44981 * <PRE>
44982 * dstReg -= (quad) [srcIndex<<srcScale + srcDisp]
44983 * </PRE>
44984 *
44985 * @param dstReg destination register, must be FP0
44986 * @param srcIndex source index register
44987 * @param srcScale source scale
44988 * @param srcDisp source displacement
44989 */
44990 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
44991 public final void emitFSUBR_Reg_RegOff_Quad(FPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
44992 int miStart = mi;
44993 // Must store result to top of stack
44994 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
44995 setMachineCodes(mi++, (byte) 0xDC);
44996 // The register'' 5 is really part of the opcode
44997 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(5));
44998 if (lister != null) lister.RRFD(miStart, "FSUBR", dstReg, srcIndex, srcScale, srcDisp);
44999 }
45000
45001 /**
45002 * Perform - on FP0. That is,
45003 * <PRE>
45004 * dstReg -= (quad) [srcDisp]
45005 * </PRE>
45006 *
45007 * @param dstReg destination register, must be FP0
45008 * @param srcDisp source displacement
45009 */
45010 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45011 public final void emitFSUBR_Reg_Abs_Quad(FPR dstReg, Address srcDisp) {
45012 int miStart = mi;
45013 // Must store result to top of stack
45014 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
45015 setMachineCodes(mi++, (byte) 0xDC);
45016 // The register'' 5 is really part of the opcode
45017 emitAbsRegOperands(srcDisp, GPR.getForOpcode(5));
45018 if (lister != null) lister.RRA(miStart, "FSUBR", dstReg, srcDisp);
45019 }
45020
45021 /**
45022 * Perform - on FP0. That is,
45023 * <PRE>
45024 * dstReg -= () [srcBase + srcDisp]
45025 * </PRE>
45026 *
45027 * @param dstReg destination register, must be FP0
45028 * @param srcBase source base register
45029 * @param srcDisp source displacement
45030 */
45031 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
45032 public final void emitFISUBR_Reg_RegDisp(FPR dstReg, GPR srcBase, Offset srcDisp) {
45033 int miStart = mi;
45034 // Must store result to top of stack
45035 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
45036 setMachineCodes(mi++, (byte) 0xDA);
45037 // The register'' 5 is really part of the opcode
45038 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(5));
45039 if (lister != null) lister.RRD(miStart, "FISUBR", dstReg, srcBase, srcDisp);
45040 }
45041
45042 /**
45043 * Perform - on FP0. That is,
45044 * <PRE>
45045 * dstReg -= () [srcBase]
45046 * </PRE>
45047 *
45048 * @param dstReg destination register, must be FP0
45049 * @param srcBase source base register
45050 */
45051 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
45052 public final void emitFISUBR_Reg_RegInd(FPR dstReg, GPR srcBase) {
45053 int miStart = mi;
45054 // Must store result to top of stack
45055 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
45056 setMachineCodes(mi++, (byte) 0xDA);
45057 // The register'' 5 is really part of the opcode
45058 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(5));
45059 if (lister != null) lister.RRN(miStart, "FISUBR", dstReg, srcBase);
45060 }
45061
45062 /**
45063 * Perform - on dstReg. That is,
45064 * <PRE>
45065 * dstReg -= () [srcBase + srcIndex<<srcScale + srcDisp]
45066 * </PRE>
45067 *
45068 * @param dstReg destination register, must be FP0
45069 * @param srcBase source base register
45070 * @param srcIndex source index register
45071 * @param srcScale source scale
45072 * @param srcDisp source displacement
45073 */
45074 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
45075 public final void emitFISUBR_Reg_RegIdx(FPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
45076 int miStart = mi;
45077 // Must store result to top of stack
45078 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
45079 setMachineCodes(mi++, (byte) 0xDA);
45080 // The register'' 5 is really part of the opcode
45081 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(5));
45082 if (lister != null) lister.RRXD(miStart, "FISUBR", dstReg, srcBase, srcIndex, srcScale, srcDisp);
45083 }
45084
45085 /**
45086 * Perform - on FP0. That is,
45087 * <PRE>
45088 * dstReg -= () [srcIndex<<srcScale + srcDisp]
45089 * </PRE>
45090 *
45091 * @param dstReg destination register, must be FP0
45092 * @param srcIndex source index register
45093 * @param srcScale source scale
45094 * @param srcDisp source displacement
45095 */
45096 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
45097 public final void emitFISUBR_Reg_RegOff(FPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
45098 int miStart = mi;
45099 // Must store result to top of stack
45100 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
45101 setMachineCodes(mi++, (byte) 0xDA);
45102 // The register'' 5 is really part of the opcode
45103 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(5));
45104 if (lister != null) lister.RRFD(miStart, "FISUBR", dstReg, srcIndex, srcScale, srcDisp);
45105 }
45106
45107 /**
45108 * Perform - on FP0. That is,
45109 * <PRE>
45110 * dstReg -= () [srcDisp]
45111 * </PRE>
45112 *
45113 * @param dstReg destination register, must be FP0
45114 * @param srcDisp source displacement
45115 */
45116 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45117 public final void emitFISUBR_Reg_Abs(FPR dstReg, Address srcDisp) {
45118 int miStart = mi;
45119 // Must store result to top of stack
45120 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
45121 setMachineCodes(mi++, (byte) 0xDA);
45122 // The register'' 5 is really part of the opcode
45123 emitAbsRegOperands(srcDisp, GPR.getForOpcode(5));
45124 if (lister != null) lister.RRA(miStart, "FISUBR", dstReg, srcDisp);
45125 }
45126
45127 /**
45128 * Perform - on FP0. That is,
45129 * <PRE>
45130 * dstReg -= (word) [srcBase + srcDisp]
45131 * </PRE>
45132 *
45133 * @param dstReg destination register, must be FP0
45134 * @param srcBase source base register
45135 * @param srcDisp source displacement
45136 */
45137 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
45138 public final void emitFISUBR_Reg_RegDisp_Word(FPR dstReg, GPR srcBase, Offset srcDisp) {
45139 int miStart = mi;
45140 // Must store result to top of stack
45141 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
45142 setMachineCodes(mi++, (byte) 0xDE);
45143 // The register'' 5 is really part of the opcode
45144 emitRegDispRegOperands(srcBase, srcDisp, GPR.getForOpcode(5));
45145 if (lister != null) lister.RRD(miStart, "FISUBR", dstReg, srcBase, srcDisp);
45146 }
45147
45148 /**
45149 * Perform - on FP0. That is,
45150 * <PRE>
45151 * dstReg -= (word) [srcBase]
45152 * </PRE>
45153 *
45154 * @param dstReg destination register, must be FP0
45155 * @param srcBase source base register
45156 */
45157 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
45158 public final void emitFISUBR_Reg_RegInd_Word(FPR dstReg, GPR srcBase) {
45159 int miStart = mi;
45160 // Must store result to top of stack
45161 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
45162 setMachineCodes(mi++, (byte) 0xDE);
45163 // The register'' 5 is really part of the opcode
45164 emitRegIndirectRegOperands(srcBase, GPR.getForOpcode(5));
45165 if (lister != null) lister.RRN(miStart, "FISUBR", dstReg, srcBase);
45166 }
45167
45168 /**
45169 * Perform - on dstReg. That is,
45170 * <PRE>
45171 * dstReg -= (word) [srcBase + srcIndex<<srcScale + srcDisp]
45172 * </PRE>
45173 *
45174 * @param dstReg destination register, must be FP0
45175 * @param srcBase source base register
45176 * @param srcIndex source index register
45177 * @param srcScale source scale
45178 * @param srcDisp source displacement
45179 */
45180 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2,3})
45181 public final void emitFISUBR_Reg_RegIdx_Word(FPR dstReg, GPR srcBase, GPR srcIndex, short srcScale, Offset srcDisp) {
45182 int miStart = mi;
45183 // Must store result to top of stack
45184 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
45185 setMachineCodes(mi++, (byte) 0xDE);
45186 // The register'' 5 is really part of the opcode
45187 emitSIBRegOperands(srcBase, srcIndex, srcScale, srcDisp, GPR.getForOpcode(5));
45188 if (lister != null) lister.RRXD(miStart, "FISUBR", dstReg, srcBase, srcIndex, srcScale, srcDisp);
45189 }
45190
45191 /**
45192 * Perform - on FP0. That is,
45193 * <PRE>
45194 * dstReg -= (word) [srcIndex<<srcScale + srcDisp]
45195 * </PRE>
45196 *
45197 * @param dstReg destination register, must be FP0
45198 * @param srcIndex source index register
45199 * @param srcScale source scale
45200 * @param srcDisp source displacement
45201 */
45202 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
45203 public final void emitFISUBR_Reg_RegOff_Word(FPR dstReg, GPR srcIndex, short srcScale, Offset srcDisp) {
45204 int miStart = mi;
45205 // Must store result to top of stack
45206 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
45207 setMachineCodes(mi++, (byte) 0xDE);
45208 // The register'' 5 is really part of the opcode
45209 emitRegOffRegOperands(srcIndex, srcScale, srcDisp, GPR.getForOpcode(5));
45210 if (lister != null) lister.RRFD(miStart, "FISUBR", dstReg, srcIndex, srcScale, srcDisp);
45211 }
45212
45213 /**
45214 * Perform - on FP0. That is,
45215 * <PRE>
45216 * dstReg -= (word) [srcDisp]
45217 * </PRE>
45218 *
45219 * @param dstReg destination register, must be FP0
45220 * @param srcDisp source displacement
45221 */
45222 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45223 public final void emitFISUBR_Reg_Abs_Word(FPR dstReg, Address srcDisp) {
45224 int miStart = mi;
45225 // Must store result to top of stack
45226 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
45227 setMachineCodes(mi++, (byte) 0xDE);
45228 // The register'' 5 is really part of the opcode
45229 emitAbsRegOperands(srcDisp, GPR.getForOpcode(5));
45230 if (lister != null) lister.RRA(miStart, "FISUBR", dstReg, srcDisp);
45231 }
45232
45233 /**
45234 * Perform - either to or from FP0. That is,
45235 * <PRE>
45236 * dstReg -= srcReg
45237 * </PRE>
45238 *
45239 * @param dstReg destination register, this or srcReg must be FP0
45240 * @param srcReg source register, this or dstReg must be FP0
45241 */
45242 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
45243 public final void emitFSUBR_Reg_Reg(FPR dstReg, FPR srcReg) {
45244 int miStart = mi;
45245 if (VM.VerifyAssertions) VM._assert(srcReg == FP0 || dstReg == FP0);
45246 if (dstReg == FP0) {
45247 setMachineCodes(mi++, (byte) 0xD8);
45248 setMachineCodes(mi++, (byte) (0xE8 | srcReg.value()));
45249 } else if (srcReg == FP0) {
45250 setMachineCodes(mi++, (byte) 0xDC);
45251 setMachineCodes(mi++, (byte) (0xE0 | dstReg.value()));
45252 }
45253 if (lister != null) lister.RR(miStart, "FSUBR", dstReg, srcReg);
45254 }
45255
45256 /**
45257 * Perform - then pop stack. That is,
45258 * <PRE>
45259 * srcReg -= ST(0); pop stack
45260 * </PRE>
45261 *
45262 * @param dstReg destination register
45263 * @param srcReg source register
45264 */
45265 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
45266 public final void emitFSUBRP_Reg_Reg(FPR dstReg, FPR srcReg) {
45267 int miStart = mi;
45268 if (VM.VerifyAssertions) VM._assert(srcReg == FP0);
45269 setMachineCodes(mi++, (byte) 0xDE);
45270 setMachineCodes(mi++, (byte) (0xE0 | dstReg.value()));
45271 if (lister != null) lister.R(miStart, "FSUBRP", dstReg);
45272 }
45273
45274 /** top of stack loaded from (double word) [reg + disp] */
45275 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45276 public final void emitFLD_Reg_RegDisp(FPR dummy, GPR reg, Offset disp) {
45277 int miStart = mi;
45278 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45279 setMachineCodes(mi++, (byte) 0xD9);
45280 emitRegDispRegOperands(reg, disp, GPR.getForOpcode(0));
45281 if (lister != null) lister.RD(miStart, "FLD", reg, disp);
45282 }
45283
45284 /** top of stack loaded from (double word) [reg] */
45285 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45286 public final void emitFLD_Reg_RegInd(FPR dummy, GPR reg) {
45287 int miStart = mi;
45288 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45289 setMachineCodes(mi++, (byte) 0xD9);
45290 emitRegIndirectRegOperands(reg, GPR.getForOpcode(0));
45291 if (lister != null) lister.RN(miStart, "FLD", reg);
45292 }
45293
45294 /** top of stack loaded from (double word) [baseReg + idxReg<<scale + disp] */
45295 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
45296 public final void emitFLD_Reg_RegIdx(FPR dummy, GPR baseReg, GPR idxReg, short scale, Offset disp) {
45297 int miStart = mi;
45298 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45299 setMachineCodes(mi++, (byte) 0xD9);
45300 emitSIBRegOperands(baseReg, idxReg, scale, disp, GPR.getForOpcode(0));
45301 if (lister != null) lister.RXD(miStart, "FLD", baseReg, idxReg, scale, disp);
45302 }
45303
45304 /** top of stack loaded from (double word) [idxReg<<scale + disp] */
45305 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45306 public final void emitFLD_Reg_RegOff(FPR dummy, GPR idxReg, short scale, Offset disp) {
45307 int miStart = mi;
45308 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45309 setMachineCodes(mi++, (byte) 0xD9);
45310 emitRegOffRegOperands(idxReg, scale, disp, GPR.getForOpcode(0));
45311 if (lister != null) lister.RFD(miStart, "FLD", idxReg, scale, disp);
45312 }
45313
45314 /** top of stack loaded from (double word) [disp] */
45315 public final void emitFLD_Reg_Abs(FPR dummy, Address disp) {
45316 int miStart = mi;
45317 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45318 setMachineCodes(mi++, (byte) 0xD9);
45319 emitAbsRegOperands(disp, GPR.getForOpcode(0));
45320 if (lister != null) lister.RA(miStart, "FLD", disp);
45321 }
45322
45323 /** top of stack loaded from (quad) [reg + disp] */
45324 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45325 public final void emitFLD_Reg_RegDisp_Quad(FPR dummy, GPR reg, Offset disp) {
45326 int miStart = mi;
45327 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45328 setMachineCodes(mi++, (byte) 0xDD);
45329 emitRegDispRegOperands(reg, disp, GPR.getForOpcode(0));
45330 if (lister != null) lister.RD(miStart, "FLD", reg, disp);
45331 }
45332
45333 /** top of stack loaded from (quad) [reg] */
45334 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45335 public final void emitFLD_Reg_RegInd_Quad(FPR dummy, GPR reg) {
45336 int miStart = mi;
45337 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45338 setMachineCodes(mi++, (byte) 0xDD);
45339 emitRegIndirectRegOperands(reg, GPR.getForOpcode(0));
45340 if (lister != null) lister.RN(miStart, "FLD", reg);
45341 }
45342
45343 /** top of stack loaded from (quad) [baseReg + idxReg<<scale + disp] */
45344 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
45345 public final void emitFLD_Reg_RegIdx_Quad(FPR dummy, GPR baseReg, GPR idxReg, short scale, Offset disp) {
45346 int miStart = mi;
45347 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45348 setMachineCodes(mi++, (byte) 0xDD);
45349 emitSIBRegOperands(baseReg, idxReg, scale, disp, GPR.getForOpcode(0));
45350 if (lister != null) lister.RXD(miStart, "FLD", baseReg, idxReg, scale, disp);
45351 }
45352
45353 /** top of stack loaded from (quad) [idxReg<<scale + disp] */
45354 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45355 public final void emitFLD_Reg_RegOff_Quad(FPR dummy, GPR idxReg, short scale, Offset disp) {
45356 int miStart = mi;
45357 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45358 setMachineCodes(mi++, (byte) 0xDD);
45359 emitRegOffRegOperands(idxReg, scale, disp, GPR.getForOpcode(0));
45360 if (lister != null) lister.RFD(miStart, "FLD", idxReg, scale, disp);
45361 }
45362
45363 /** top of stack loaded from (quad) [disp] */
45364 public final void emitFLD_Reg_Abs_Quad(FPR dummy, Address disp) {
45365 int miStart = mi;
45366 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45367 setMachineCodes(mi++, (byte) 0xDD);
45368 emitAbsRegOperands(disp, GPR.getForOpcode(0));
45369 if (lister != null) lister.RA(miStart, "FLD", disp);
45370 }
45371
45372 /** top of stack loaded from (word) [reg + disp] */
45373 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45374 public final void emitFILD_Reg_RegDisp_Word(FPR dummy, GPR reg, Offset disp) {
45375 int miStart = mi;
45376 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45377 setMachineCodes(mi++, (byte) 0xDF);
45378 emitRegDispRegOperands(reg, disp, GPR.getForOpcode(0));
45379 if (lister != null) lister.RD(miStart, "FILD", reg, disp);
45380 }
45381
45382 /** top of stack loaded from (word) [reg] */
45383 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45384 public final void emitFILD_Reg_RegInd_Word(FPR dummy, GPR reg) {
45385 int miStart = mi;
45386 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45387 setMachineCodes(mi++, (byte) 0xDF);
45388 emitRegIndirectRegOperands(reg, GPR.getForOpcode(0));
45389 if (lister != null) lister.RN(miStart, "FILD", reg);
45390 }
45391
45392 /** top of stack loaded from (word) [baseReg + idxReg<<scale + disp] */
45393 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
45394 public final void emitFILD_Reg_RegIdx_Word(FPR dummy, GPR baseReg, GPR idxReg, short scale, Offset disp) {
45395 int miStart = mi;
45396 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45397 setMachineCodes(mi++, (byte) 0xDF);
45398 emitSIBRegOperands(baseReg, idxReg, scale, disp, GPR.getForOpcode(0));
45399 if (lister != null) lister.RXD(miStart, "FILD", baseReg, idxReg, scale, disp);
45400 }
45401
45402 /** top of stack loaded from (word) [idxReg<<scale + disp] */
45403 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45404 public final void emitFILD_Reg_RegOff_Word(FPR dummy, GPR idxReg, short scale, Offset disp) {
45405 int miStart = mi;
45406 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45407 setMachineCodes(mi++, (byte) 0xDF);
45408 emitRegOffRegOperands(idxReg, scale, disp, GPR.getForOpcode(0));
45409 if (lister != null) lister.RFD(miStart, "FILD", idxReg, scale, disp);
45410 }
45411
45412 /** top of stack loaded from (word) [disp] */
45413 public final void emitFILD_Reg_Abs_Word(FPR dummy, Address disp) {
45414 int miStart = mi;
45415 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45416 setMachineCodes(mi++, (byte) 0xDF);
45417 emitAbsRegOperands(disp, GPR.getForOpcode(0));
45418 if (lister != null) lister.RA(miStart, "FILD", disp);
45419 }
45420
45421 /** top of stack loaded from (double word) [reg + disp] */
45422 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45423 public final void emitFILD_Reg_RegDisp(FPR dummy, GPR reg, Offset disp) {
45424 int miStart = mi;
45425 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45426 setMachineCodes(mi++, (byte) 0xDB);
45427 emitRegDispRegOperands(reg, disp, GPR.getForOpcode(0));
45428 if (lister != null) lister.RD(miStart, "FILD", reg, disp);
45429 }
45430
45431 /** top of stack loaded from (double word) [reg] */
45432 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45433 public final void emitFILD_Reg_RegInd(FPR dummy, GPR reg) {
45434 int miStart = mi;
45435 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45436 setMachineCodes(mi++, (byte) 0xDB);
45437 emitRegIndirectRegOperands(reg, GPR.getForOpcode(0));
45438 if (lister != null) lister.RN(miStart, "FILD", reg);
45439 }
45440
45441 /** top of stack loaded from (double word) [baseReg + idxReg<<scale + disp] */
45442 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
45443 public final void emitFILD_Reg_RegIdx(FPR dummy, GPR baseReg, GPR idxReg, short scale, Offset disp) {
45444 int miStart = mi;
45445 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45446 setMachineCodes(mi++, (byte) 0xDB);
45447 emitSIBRegOperands(baseReg, idxReg, scale, disp, GPR.getForOpcode(0));
45448 if (lister != null) lister.RXD(miStart, "FILD", baseReg, idxReg, scale, disp);
45449 }
45450
45451 /** top of stack loaded from (double word) [idxReg<<scale + disp] */
45452 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45453 public final void emitFILD_Reg_RegOff(FPR dummy, GPR idxReg, short scale, Offset disp) {
45454 int miStart = mi;
45455 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45456 setMachineCodes(mi++, (byte) 0xDB);
45457 emitRegOffRegOperands(idxReg, scale, disp, GPR.getForOpcode(0));
45458 if (lister != null) lister.RFD(miStart, "FILD", idxReg, scale, disp);
45459 }
45460
45461 /** top of stack loaded from (double word) [disp] */
45462 public final void emitFILD_Reg_Abs(FPR dummy, Address disp) {
45463 int miStart = mi;
45464 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45465 setMachineCodes(mi++, (byte) 0xDB);
45466 emitAbsRegOperands(disp, GPR.getForOpcode(0));
45467 if (lister != null) lister.RA(miStart, "FILD", disp);
45468 }
45469
45470 /** top of stack loaded from (quad) [reg + disp] */
45471 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45472 public final void emitFILD_Reg_RegDisp_Quad(FPR dummy, GPR reg, Offset disp) {
45473 int miStart = mi;
45474 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45475 setMachineCodes(mi++, (byte) 0xDF);
45476 emitRegDispRegOperands(reg, disp, GPR.getForOpcode(5));
45477 if (lister != null) lister.RD(miStart, "FILD", reg, disp);
45478 }
45479
45480 /** top of stack loaded from (quad) [reg] */
45481 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45482 public final void emitFILD_Reg_RegInd_Quad(FPR dummy, GPR reg) {
45483 int miStart = mi;
45484 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45485 setMachineCodes(mi++, (byte) 0xDF);
45486 emitRegIndirectRegOperands(reg, GPR.getForOpcode(5));
45487 if (lister != null) lister.RN(miStart, "FILD", reg);
45488 }
45489
45490 /** top of stack loaded from (quad) [baseReg + idxReg<<scale + disp] */
45491 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
45492 public final void emitFILD_Reg_RegIdx_Quad(FPR dummy, GPR baseReg, GPR idxReg, short scale, Offset disp) {
45493 int miStart = mi;
45494 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45495 setMachineCodes(mi++, (byte) 0xDF);
45496 emitSIBRegOperands(baseReg, idxReg, scale, disp, GPR.getForOpcode(5));
45497 if (lister != null) lister.RXD(miStart, "FILD", baseReg, idxReg, scale, disp);
45498 }
45499
45500 /** top of stack loaded from (quad) [idxReg<<scale + disp] */
45501 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45502 public final void emitFILD_Reg_RegOff_Quad(FPR dummy, GPR idxReg, short scale, Offset disp) {
45503 int miStart = mi;
45504 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45505 setMachineCodes(mi++, (byte) 0xDF);
45506 emitRegOffRegOperands(idxReg, scale, disp, GPR.getForOpcode(5));
45507 if (lister != null) lister.RFD(miStart, "FILD", idxReg, scale, disp);
45508 }
45509
45510 /** top of stack loaded from (quad) [disp] */
45511 public final void emitFILD_Reg_Abs_Quad(FPR dummy, Address disp) {
45512 int miStart = mi;
45513 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45514 setMachineCodes(mi++, (byte) 0xDF);
45515 emitAbsRegOperands(disp, GPR.getForOpcode(5));
45516 if (lister != null) lister.RA(miStart, "FILD", disp);
45517 }
45518
45519 /** top of stack stored to (word) [reg + disp] */
45520 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45521 public final void emitFIST_RegDisp_Reg_Word(GPR reg, Offset disp, FPR dummy) {
45522 int miStart = mi;
45523 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45524 setMachineCodes(mi++, (byte) 0xDF);
45525 emitRegDispRegOperands(reg, disp, GPR.getForOpcode(2));
45526 if (lister != null) lister.RD(miStart, "FIST", reg, disp);
45527 }
45528
45529 /** top of stack stored to (word) [reg] */
45530 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45531 public final void emitFIST_RegInd_Reg_Word(GPR reg, FPR dummy) {
45532 int miStart = mi;
45533 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45534 setMachineCodes(mi++, (byte) 0xDF);
45535 emitRegIndirectRegOperands(reg, GPR.getForOpcode(2));
45536 if (lister != null) lister.RN(miStart, "FIST", reg);
45537 }
45538
45539 /** top of stack stored to (word) [baseReg + idxReg<<scale + disp] */
45540 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
45541 public final void emitFIST_RegIdx_Reg_Word(GPR baseReg, GPR idxReg, short scale, Offset disp, FPR dummy) {
45542 int miStart = mi;
45543 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45544 setMachineCodes(mi++, (byte) 0xDF);
45545 emitSIBRegOperands(baseReg, idxReg, scale, disp, GPR.getForOpcode(2));
45546 if (lister != null) lister.RXD(miStart, "FIST", baseReg, idxReg, scale, disp);
45547 }
45548
45549 /** top of stack stored to (word) [idxReg<<scale + disp] */
45550 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45551 public final void emitFIST_RegOff_Reg_Word(GPR idxReg, short scale, Offset disp, FPR dummy) {
45552 int miStart = mi;
45553 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45554 setMachineCodes(mi++, (byte) 0xDF);
45555 emitRegOffRegOperands(idxReg, scale, disp, GPR.getForOpcode(2));
45556 if (lister != null) lister.RFD(miStart, "FIST", idxReg, scale, disp);
45557 }
45558
45559 /** top of stack stored to (word) [disp] */
45560 public final void emitFIST_Abs_Reg_Word(Address disp, FPR dummy) {
45561 int miStart = mi;
45562 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45563 setMachineCodes(mi++, (byte) 0xDF);
45564 emitAbsRegOperands(disp, GPR.getForOpcode(2));
45565 if (lister != null) lister.RA(miStart, "FIST", disp);
45566 }
45567
45568 /** top of stack stored to (double word) [reg + disp] */
45569 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45570 public final void emitFIST_RegDisp_Reg(GPR reg, Offset disp, FPR dummy) {
45571 int miStart = mi;
45572 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45573 setMachineCodes(mi++, (byte) 0xDB);
45574 emitRegDispRegOperands(reg, disp, GPR.getForOpcode(2));
45575 if (lister != null) lister.RD(miStart, "FIST", reg, disp);
45576 }
45577
45578 /** top of stack stored to (double word) [reg] */
45579 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45580 public final void emitFIST_RegInd_Reg(GPR reg, FPR dummy) {
45581 int miStart = mi;
45582 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45583 setMachineCodes(mi++, (byte) 0xDB);
45584 emitRegIndirectRegOperands(reg, GPR.getForOpcode(2));
45585 if (lister != null) lister.RN(miStart, "FIST", reg);
45586 }
45587
45588 /** top of stack stored to (double word) [baseReg + idxReg<<scale + disp] */
45589 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
45590 public final void emitFIST_RegIdx_Reg(GPR baseReg, GPR idxReg, short scale, Offset disp, FPR dummy) {
45591 int miStart = mi;
45592 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45593 setMachineCodes(mi++, (byte) 0xDB);
45594 emitSIBRegOperands(baseReg, idxReg, scale, disp, GPR.getForOpcode(2));
45595 if (lister != null) lister.RXD(miStart, "FIST", baseReg, idxReg, scale, disp);
45596 }
45597
45598 /** top of stack stored to (double word) [idxReg<<scale + disp] */
45599 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45600 public final void emitFIST_RegOff_Reg(GPR idxReg, short scale, Offset disp, FPR dummy) {
45601 int miStart = mi;
45602 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45603 setMachineCodes(mi++, (byte) 0xDB);
45604 emitRegOffRegOperands(idxReg, scale, disp, GPR.getForOpcode(2));
45605 if (lister != null) lister.RFD(miStart, "FIST", idxReg, scale, disp);
45606 }
45607
45608 /** top of stack stored to (double word) [disp] */
45609 public final void emitFIST_Abs_Reg(Address disp, FPR dummy) {
45610 int miStart = mi;
45611 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45612 setMachineCodes(mi++, (byte) 0xDB);
45613 emitAbsRegOperands(disp, GPR.getForOpcode(2));
45614 if (lister != null) lister.RA(miStart, "FIST", disp);
45615 }
45616
45617 /** top of stack stored to (word) [reg + disp] */
45618 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45619 public final void emitFISTP_RegDisp_Reg_Word(GPR reg, Offset disp, FPR dummy) {
45620 int miStart = mi;
45621 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45622 setMachineCodes(mi++, (byte) 0xDF);
45623 emitRegDispRegOperands(reg, disp, GPR.getForOpcode(3));
45624 if (lister != null) lister.RD(miStart, "FISTP", reg, disp);
45625 }
45626
45627 /** top of stack stored to (word) [reg] */
45628 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45629 public final void emitFISTP_RegInd_Reg_Word(GPR reg, FPR dummy) {
45630 int miStart = mi;
45631 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45632 setMachineCodes(mi++, (byte) 0xDF);
45633 emitRegIndirectRegOperands(reg, GPR.getForOpcode(3));
45634 if (lister != null) lister.RN(miStart, "FISTP", reg);
45635 }
45636
45637 /** top of stack stored to (word) [baseReg + idxReg<<scale + disp] */
45638 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
45639 public final void emitFISTP_RegIdx_Reg_Word(GPR baseReg, GPR idxReg, short scale, Offset disp, FPR dummy) {
45640 int miStart = mi;
45641 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45642 setMachineCodes(mi++, (byte) 0xDF);
45643 emitSIBRegOperands(baseReg, idxReg, scale, disp, GPR.getForOpcode(3));
45644 if (lister != null) lister.RXD(miStart, "FISTP", baseReg, idxReg, scale, disp);
45645 }
45646
45647 /** top of stack stored to (word) [idxReg<<scale + disp] */
45648 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45649 public final void emitFISTP_RegOff_Reg_Word(GPR idxReg, short scale, Offset disp, FPR dummy) {
45650 int miStart = mi;
45651 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45652 setMachineCodes(mi++, (byte) 0xDF);
45653 emitRegOffRegOperands(idxReg, scale, disp, GPR.getForOpcode(3));
45654 if (lister != null) lister.RFD(miStart, "FISTP", idxReg, scale, disp);
45655 }
45656
45657 /** top of stack stored to (word) [disp] */
45658 public final void emitFISTP_Abs_Reg_Word(Address disp, FPR dummy) {
45659 int miStart = mi;
45660 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45661 setMachineCodes(mi++, (byte) 0xDF);
45662 emitAbsRegOperands(disp, GPR.getForOpcode(3));
45663 if (lister != null) lister.RA(miStart, "FISTP", disp);
45664 }
45665
45666 /** top of stack stored to (double word) [reg + disp] */
45667 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45668 public final void emitFISTP_RegDisp_Reg(GPR reg, Offset disp, FPR dummy) {
45669 int miStart = mi;
45670 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45671 setMachineCodes(mi++, (byte) 0xDB);
45672 emitRegDispRegOperands(reg, disp, GPR.getForOpcode(3));
45673 if (lister != null) lister.RD(miStart, "FISTP", reg, disp);
45674 }
45675
45676 /** top of stack stored to (double word) [reg] */
45677 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45678 public final void emitFISTP_RegInd_Reg(GPR reg, FPR dummy) {
45679 int miStart = mi;
45680 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45681 setMachineCodes(mi++, (byte) 0xDB);
45682 emitRegIndirectRegOperands(reg, GPR.getForOpcode(3));
45683 if (lister != null) lister.RN(miStart, "FISTP", reg);
45684 }
45685
45686 /** top of stack stored to (double word) [baseReg + idxReg<<scale + disp] */
45687 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
45688 public final void emitFISTP_RegIdx_Reg(GPR baseReg, GPR idxReg, short scale, Offset disp, FPR dummy) {
45689 int miStart = mi;
45690 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45691 setMachineCodes(mi++, (byte) 0xDB);
45692 emitSIBRegOperands(baseReg, idxReg, scale, disp, GPR.getForOpcode(3));
45693 if (lister != null) lister.RXD(miStart, "FISTP", baseReg, idxReg, scale, disp);
45694 }
45695
45696 /** top of stack stored to (double word) [idxReg<<scale + disp] */
45697 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45698 public final void emitFISTP_RegOff_Reg(GPR idxReg, short scale, Offset disp, FPR dummy) {
45699 int miStart = mi;
45700 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45701 setMachineCodes(mi++, (byte) 0xDB);
45702 emitRegOffRegOperands(idxReg, scale, disp, GPR.getForOpcode(3));
45703 if (lister != null) lister.RFD(miStart, "FISTP", idxReg, scale, disp);
45704 }
45705
45706 /** top of stack stored to (double word) [disp] */
45707 public final void emitFISTP_Abs_Reg(Address disp, FPR dummy) {
45708 int miStart = mi;
45709 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45710 setMachineCodes(mi++, (byte) 0xDB);
45711 emitAbsRegOperands(disp, GPR.getForOpcode(3));
45712 if (lister != null) lister.RA(miStart, "FISTP", disp);
45713 }
45714
45715 /** top of stack stored to (quad) [reg + disp] */
45716 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45717 public final void emitFISTP_RegDisp_Reg_Quad(GPR reg, Offset disp, FPR dummy) {
45718 int miStart = mi;
45719 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45720 setMachineCodes(mi++, (byte) 0xDF);
45721 emitRegDispRegOperands(reg, disp, GPR.getForOpcode(7));
45722 if (lister != null) lister.RD(miStart, "FISTP", reg, disp);
45723 }
45724
45725 /** top of stack stored to (quad) [reg] */
45726 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45727 public final void emitFISTP_RegInd_Reg_Quad(GPR reg, FPR dummy) {
45728 int miStart = mi;
45729 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45730 setMachineCodes(mi++, (byte) 0xDF);
45731 emitRegIndirectRegOperands(reg, GPR.getForOpcode(7));
45732 if (lister != null) lister.RN(miStart, "FISTP", reg);
45733 }
45734
45735 /** top of stack stored to (quad) [baseReg + idxReg<<scale + disp] */
45736 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
45737 public final void emitFISTP_RegIdx_Reg_Quad(GPR baseReg, GPR idxReg, short scale, Offset disp, FPR dummy) {
45738 int miStart = mi;
45739 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45740 setMachineCodes(mi++, (byte) 0xDF);
45741 emitSIBRegOperands(baseReg, idxReg, scale, disp, GPR.getForOpcode(7));
45742 if (lister != null) lister.RXD(miStart, "FISTP", baseReg, idxReg, scale, disp);
45743 }
45744
45745 /** top of stack stored to (quad) [idxReg<<scale + disp] */
45746 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45747 public final void emitFISTP_RegOff_Reg_Quad(GPR idxReg, short scale, Offset disp, FPR dummy) {
45748 int miStart = mi;
45749 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45750 setMachineCodes(mi++, (byte) 0xDF);
45751 emitRegOffRegOperands(idxReg, scale, disp, GPR.getForOpcode(7));
45752 if (lister != null) lister.RFD(miStart, "FISTP", idxReg, scale, disp);
45753 }
45754
45755 /** top of stack stored to (quad) [disp] */
45756 public final void emitFISTP_Abs_Reg_Quad(Address disp, FPR dummy) {
45757 int miStart = mi;
45758 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45759 setMachineCodes(mi++, (byte) 0xDF);
45760 emitAbsRegOperands(disp, GPR.getForOpcode(7));
45761 if (lister != null) lister.RA(miStart, "FISTP", disp);
45762 }
45763
45764 /** top of stack stored to (double word) [reg + disp] */
45765 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45766 public final void emitFST_RegDisp_Reg(GPR reg, Offset disp, FPR dummy) {
45767 int miStart = mi;
45768 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45769 setMachineCodes(mi++, (byte) 0xD9);
45770 emitRegDispRegOperands(reg, disp, GPR.getForOpcode(2));
45771 if (lister != null) lister.RD(miStart, "FST", reg, disp);
45772 }
45773
45774 /** top of stack stored to (double word) [reg] */
45775 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45776 public final void emitFST_RegInd_Reg(GPR reg, FPR dummy) {
45777 int miStart = mi;
45778 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45779 setMachineCodes(mi++, (byte) 0xD9);
45780 emitRegIndirectRegOperands(reg, GPR.getForOpcode(2));
45781 if (lister != null) lister.RN(miStart, "FST", reg);
45782 }
45783
45784 /** top of stack stored to (double word) [baseReg + idxReg<<scale + disp] */
45785 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
45786 public final void emitFST_RegIdx_Reg(GPR baseReg, GPR idxReg, short scale, Offset disp, FPR dummy) {
45787 int miStart = mi;
45788 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45789 setMachineCodes(mi++, (byte) 0xD9);
45790 emitSIBRegOperands(baseReg, idxReg, scale, disp, GPR.getForOpcode(2));
45791 if (lister != null) lister.RXD(miStart, "FST", baseReg, idxReg, scale, disp);
45792 }
45793
45794 /** top of stack stored to (double word) [idxReg<<scale + disp] */
45795 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45796 public final void emitFST_RegOff_Reg(GPR idxReg, short scale, Offset disp, FPR dummy) {
45797 int miStart = mi;
45798 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45799 setMachineCodes(mi++, (byte) 0xD9);
45800 emitRegOffRegOperands(idxReg, scale, disp, GPR.getForOpcode(2));
45801 if (lister != null) lister.RFD(miStart, "FST", idxReg, scale, disp);
45802 }
45803
45804 /** top of stack stored to (double word) [disp] */
45805 public final void emitFST_Abs_Reg(Address disp, FPR dummy) {
45806 int miStart = mi;
45807 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45808 setMachineCodes(mi++, (byte) 0xD9);
45809 emitAbsRegOperands(disp, GPR.getForOpcode(2));
45810 if (lister != null) lister.RA(miStart, "FST", disp);
45811 }
45812
45813 /** top of stack stored to (quad) [reg + disp] */
45814 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45815 public final void emitFST_RegDisp_Reg_Quad(GPR reg, Offset disp, FPR dummy) {
45816 int miStart = mi;
45817 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45818 setMachineCodes(mi++, (byte) 0xDD);
45819 emitRegDispRegOperands(reg, disp, GPR.getForOpcode(2));
45820 if (lister != null) lister.RD(miStart, "FST", reg, disp);
45821 }
45822
45823 /** top of stack stored to (quad) [reg] */
45824 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45825 public final void emitFST_RegInd_Reg_Quad(GPR reg, FPR dummy) {
45826 int miStart = mi;
45827 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45828 setMachineCodes(mi++, (byte) 0xDD);
45829 emitRegIndirectRegOperands(reg, GPR.getForOpcode(2));
45830 if (lister != null) lister.RN(miStart, "FST", reg);
45831 }
45832
45833 /** top of stack stored to (quad) [baseReg + idxReg<<scale + disp] */
45834 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
45835 public final void emitFST_RegIdx_Reg_Quad(GPR baseReg, GPR idxReg, short scale, Offset disp, FPR dummy) {
45836 int miStart = mi;
45837 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45838 setMachineCodes(mi++, (byte) 0xDD);
45839 emitSIBRegOperands(baseReg, idxReg, scale, disp, GPR.getForOpcode(2));
45840 if (lister != null) lister.RXD(miStart, "FST", baseReg, idxReg, scale, disp);
45841 }
45842
45843 /** top of stack stored to (quad) [idxReg<<scale + disp] */
45844 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45845 public final void emitFST_RegOff_Reg_Quad(GPR idxReg, short scale, Offset disp, FPR dummy) {
45846 int miStart = mi;
45847 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45848 setMachineCodes(mi++, (byte) 0xDD);
45849 emitRegOffRegOperands(idxReg, scale, disp, GPR.getForOpcode(2));
45850 if (lister != null) lister.RFD(miStart, "FST", idxReg, scale, disp);
45851 }
45852
45853 /** top of stack stored to (quad) [disp] */
45854 public final void emitFST_Abs_Reg_Quad(Address disp, FPR dummy) {
45855 int miStart = mi;
45856 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45857 setMachineCodes(mi++, (byte) 0xDD);
45858 emitAbsRegOperands(disp, GPR.getForOpcode(2));
45859 if (lister != null) lister.RA(miStart, "FST", disp);
45860 }
45861
45862 /** top of stack stored to (double word) [reg + disp] */
45863 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45864 public final void emitFSTP_RegDisp_Reg(GPR reg, Offset disp, FPR dummy) {
45865 int miStart = mi;
45866 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45867 setMachineCodes(mi++, (byte) 0xD9);
45868 emitRegDispRegOperands(reg, disp, GPR.getForOpcode(3));
45869 if (lister != null) lister.RD(miStart, "FSTP", reg, disp);
45870 }
45871
45872 /** top of stack stored to (double word) [reg] */
45873 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45874 public final void emitFSTP_RegInd_Reg(GPR reg, FPR dummy) {
45875 int miStart = mi;
45876 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45877 setMachineCodes(mi++, (byte) 0xD9);
45878 emitRegIndirectRegOperands(reg, GPR.getForOpcode(3));
45879 if (lister != null) lister.RN(miStart, "FSTP", reg);
45880 }
45881
45882 /** top of stack stored to (double word) [baseReg + idxReg<<scale + disp] */
45883 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
45884 public final void emitFSTP_RegIdx_Reg(GPR baseReg, GPR idxReg, short scale, Offset disp, FPR dummy) {
45885 int miStart = mi;
45886 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45887 setMachineCodes(mi++, (byte) 0xD9);
45888 emitSIBRegOperands(baseReg, idxReg, scale, disp, GPR.getForOpcode(3));
45889 if (lister != null) lister.RXD(miStart, "FSTP", baseReg, idxReg, scale, disp);
45890 }
45891
45892 /** top of stack stored to (double word) [idxReg<<scale + disp] */
45893 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45894 public final void emitFSTP_RegOff_Reg(GPR idxReg, short scale, Offset disp, FPR dummy) {
45895 int miStart = mi;
45896 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45897 setMachineCodes(mi++, (byte) 0xD9);
45898 emitRegOffRegOperands(idxReg, scale, disp, GPR.getForOpcode(3));
45899 if (lister != null) lister.RFD(miStart, "FSTP", idxReg, scale, disp);
45900 }
45901
45902 /** top of stack stored to (double word) [disp] */
45903 public final void emitFSTP_Abs_Reg(Address disp, FPR dummy) {
45904 int miStart = mi;
45905 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45906 setMachineCodes(mi++, (byte) 0xD9);
45907 emitAbsRegOperands(disp, GPR.getForOpcode(3));
45908 if (lister != null) lister.RA(miStart, "FSTP", disp);
45909 }
45910
45911 /** top of stack stored to (quad) [reg + disp] */
45912 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45913 public final void emitFSTP_RegDisp_Reg_Quad(GPR reg, Offset disp, FPR dummy) {
45914 int miStart = mi;
45915 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45916 setMachineCodes(mi++, (byte) 0xDD);
45917 emitRegDispRegOperands(reg, disp, GPR.getForOpcode(3));
45918 if (lister != null) lister.RD(miStart, "FSTP", reg, disp);
45919 }
45920
45921 /** top of stack stored to (quad) [reg] */
45922 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45923 public final void emitFSTP_RegInd_Reg_Quad(GPR reg, FPR dummy) {
45924 int miStart = mi;
45925 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45926 setMachineCodes(mi++, (byte) 0xDD);
45927 emitRegIndirectRegOperands(reg, GPR.getForOpcode(3));
45928 if (lister != null) lister.RN(miStart, "FSTP", reg);
45929 }
45930
45931 /** top of stack stored to (quad) [baseReg + idxReg<<scale + disp] */
45932 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
45933 public final void emitFSTP_RegIdx_Reg_Quad(GPR baseReg, GPR idxReg, short scale, Offset disp, FPR dummy) {
45934 int miStart = mi;
45935 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45936 setMachineCodes(mi++, (byte) 0xDD);
45937 emitSIBRegOperands(baseReg, idxReg, scale, disp, GPR.getForOpcode(3));
45938 if (lister != null) lister.RXD(miStart, "FSTP", baseReg, idxReg, scale, disp);
45939 }
45940
45941 /** top of stack stored to (quad) [idxReg<<scale + disp] */
45942 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
45943 public final void emitFSTP_RegOff_Reg_Quad(GPR idxReg, short scale, Offset disp, FPR dummy) {
45944 int miStart = mi;
45945 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45946 setMachineCodes(mi++, (byte) 0xDD);
45947 emitRegOffRegOperands(idxReg, scale, disp, GPR.getForOpcode(3));
45948 if (lister != null) lister.RFD(miStart, "FSTP", idxReg, scale, disp);
45949 }
45950
45951 /** top of stack stored to (quad) [disp] */
45952 public final void emitFSTP_Abs_Reg_Quad(Address disp, FPR dummy) {
45953 int miStart = mi;
45954 if (VM.VerifyAssertions) VM._assert(dummy == FP0);
45955 setMachineCodes(mi++, (byte) 0xDD);
45956 emitAbsRegOperands(disp, GPR.getForOpcode(3));
45957 if (lister != null) lister.RA(miStart, "FSTP", disp);
45958 }
45959
45960 /**
45961 * FCOMI floating point comparison
45962 *
45963 * @param reg1 register for comparison
45964 * @param reg2 register for comparison
45965 */
45966 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
45967 public final void emitFCOMI_Reg_Reg (FPR reg1, FPR reg2) {
45968 int miStart = mi;
45969 if (VM.VerifyAssertions) VM._assert(reg1 == FP0);
45970 setMachineCodes(mi++, (byte) 0xDB);
45971 setMachineCodes(mi++, (byte) (0xF0 | reg2.value()));
45972 if (lister != null) lister.RR(miStart, "FCOMI", reg1, reg2);
45973 }
45974
45975 /**
45976 * FCOMIP floating point comparison
45977 *
45978 * @param reg1 register for comparison
45979 * @param reg2 register for comparison
45980 */
45981 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
45982 public final void emitFCOMIP_Reg_Reg (FPR reg1, FPR reg2) {
45983 int miStart = mi;
45984 if (VM.VerifyAssertions) VM._assert(reg1 == FP0);
45985 setMachineCodes(mi++, (byte) 0xDF);
45986 setMachineCodes(mi++, (byte) (0xF0 | reg2.value()));
45987 if (lister != null) lister.RR(miStart, "FCOMIP", reg1, reg2);
45988 }
45989
45990 /**
45991 * FUCOMI floating point comparison
45992 *
45993 * @param reg1 register for comparison
45994 * @param reg2 register for comparison
45995 */
45996 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
45997 public final void emitFUCOMI_Reg_Reg (FPR reg1, FPR reg2) {
45998 int miStart = mi;
45999 if (VM.VerifyAssertions) VM._assert(reg1 == FP0);
46000 setMachineCodes(mi++, (byte) 0xDB);
46001 setMachineCodes(mi++, (byte) (0xE8 | reg2.value()));
46002 if (lister != null) lister.RR(miStart, "FUCOMI", reg1, reg2);
46003 }
46004
46005 /**
46006 * FUCOMIP floating point comparison
46007 *
46008 * @param reg1 register for comparison
46009 * @param reg2 register for comparison
46010 */
46011 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
46012 public final void emitFUCOMIP_Reg_Reg (FPR reg1, FPR reg2) {
46013 int miStart = mi;
46014 if (VM.VerifyAssertions) VM._assert(reg1 == FP0);
46015 setMachineCodes(mi++, (byte) 0xDF);
46016 setMachineCodes(mi++, (byte) (0xE8 | reg2.value()));
46017 if (lister != null) lister.RR(miStart, "FUCOMIP", reg1, reg2);
46018 }
46019
46020 /**
46021 * save FPU state ignoring pending exceptions - register displacement
46022 *
46023 * @param baseReg destination base register
46024 * @param disp destination displacement
46025 */
46026 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
46027 public final void emitFNSAVE_RegDisp (GPR baseReg, Offset disp) {
46028 int miStart = mi;
46029 // no prefix byte
46030 setMachineCodes(mi++, (byte) 0xDD);
46031 emitRegDispRegOperands(baseReg, disp, GPR.getForOpcode(6));
46032 if (lister != null) lister.RD(miStart, "FNSAVE", baseReg, disp);
46033 }
46034
46035 /**
46036 * save FPU state ignoring pending exceptions - register indirect
46037 *
46038 * @param baseReg destination base register
46039 */
46040 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
46041 public final void emitFNSAVE_RegInd (GPR baseReg) {
46042 int miStart = mi;
46043 // no prefix byte
46044 setMachineCodes(mi++, (byte) 0xDD);
46045 emitRegIndirectRegOperands(baseReg, GPR.getForOpcode(6));
46046 if (lister != null) lister.RN(miStart, "FNSAVE", baseReg);
46047 }
46048
46049 /**
46050 * save FPU state ignoring pending exceptions - register index
46051 *
46052 * @param baseReg destination base register
46053 * @param indexReg destination index register
46054 * @param scale destination scale
46055 * @param disp destination displacement
46056 */
46057 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
46058 public final void emitFNSAVE_RegIdx (GPR baseReg, GPR indexReg, short scale, Offset disp) {
46059 int miStart = mi;
46060 // no prefix byte
46061 setMachineCodes(mi++, (byte) 0xDD);
46062 emitSIBRegOperands(baseReg, indexReg, scale, disp, GPR.getForOpcode(6));
46063 if (lister != null) lister.RXD(miStart, "FNSAVE", baseReg, indexReg, scale, disp);
46064 }
46065
46066 /**
46067 * save FPU state ignoring pending exceptions - register offset
46068 *
46069 * @param indexReg destination index register
46070 * @param scale destination scale
46071 * @param disp destination displacement
46072 */
46073 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
46074 public final void emitFNSAVE_RegOff (GPR indexReg, short scale, Offset disp) {
46075 int miStart = mi;
46076 // no prefix byte
46077 setMachineCodes(mi++, (byte) 0xDD);
46078 emitRegOffRegOperands(indexReg, scale, disp, GPR.getForOpcode(6));
46079 if (lister != null) lister.RFD(miStart, "FNSAVE", indexReg, scale, disp);
46080 }
46081
46082 /**
46083 * save FPU state ignoring pending exceptions - absolute address
46084 *
46085 * @param disp address to store to
46086 */
46087 public final void emitFNSAVE_Abs (Address disp) {
46088 int miStart = mi;
46089 // no prefix byte
46090 setMachineCodes(mi++, (byte) 0xDD);
46091 emitAbsRegOperands(disp, GPR.getForOpcode(6));
46092 if (lister != null) lister.RA(miStart, "FNSAVE", disp);
46093 }
46094
46095 /**
46096 * save FPU state respecting pending exceptions - register displacement
46097 *
46098 * @param baseReg destination base register
46099 * @param disp destination displacement
46100 */
46101 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
46102 public final void emitFSAVE_RegDisp (GPR baseReg, Offset disp) {
46103 int miStart = mi;
46104 setMachineCodes(mi++, (byte) 0x9B);
46105 setMachineCodes(mi++, (byte) 0xDD);
46106 emitRegDispRegOperands(baseReg, disp, GPR.getForOpcode(6));
46107 if (lister != null) lister.RD(miStart, "FSAVE", baseReg, disp);
46108 }
46109
46110 /**
46111 * save FPU state respecting pending exceptions - register indirect
46112 *
46113 * @param baseReg destination base register
46114 */
46115 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
46116 public final void emitFSAVE_RegInd (GPR baseReg) {
46117 int miStart = mi;
46118 setMachineCodes(mi++, (byte) 0x9B);
46119 setMachineCodes(mi++, (byte) 0xDD);
46120 emitRegIndirectRegOperands(baseReg, GPR.getForOpcode(6));
46121 if (lister != null) lister.RN(miStart, "FSAVE", baseReg);
46122 }
46123
46124 /**
46125 * save FPU state respecting pending exceptions - register index
46126 *
46127 * @param baseReg destination base register
46128 * @param indexReg destination index register
46129 * @param scale destination scale
46130 * @param disp destination displacement
46131 */
46132 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
46133 public final void emitFSAVE_RegIdx (GPR baseReg, GPR indexReg, short scale, Offset disp) {
46134 int miStart = mi;
46135 setMachineCodes(mi++, (byte) 0x9B);
46136 setMachineCodes(mi++, (byte) 0xDD);
46137 emitSIBRegOperands(baseReg, indexReg, scale, disp, GPR.getForOpcode(6));
46138 if (lister != null) lister.RXD(miStart, "FSAVE", baseReg, indexReg, scale, disp);
46139 }
46140
46141 /**
46142 * save FPU state respecting pending exceptions - register offset
46143 *
46144 * @param indexReg destination index register
46145 * @param scale destination scale
46146 * @param disp destination displacement
46147 */
46148 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
46149 public final void emitFSAVE_RegOff (GPR indexReg, short scale, Offset disp) {
46150 int miStart = mi;
46151 setMachineCodes(mi++, (byte) 0x9B);
46152 setMachineCodes(mi++, (byte) 0xDD);
46153 emitRegOffRegOperands(indexReg, scale, disp, GPR.getForOpcode(6));
46154 if (lister != null) lister.RFD(miStart, "FSAVE", indexReg, scale, disp);
46155 }
46156
46157 /**
46158 * save FPU state respecting pending exceptions - absolute address
46159 *
46160 * @param disp address to store to
46161 */
46162 public final void emitFSAVE_Abs (Address disp) {
46163 int miStart = mi;
46164 setMachineCodes(mi++, (byte) 0x9B);
46165 setMachineCodes(mi++, (byte) 0xDD);
46166 emitAbsRegOperands(disp, GPR.getForOpcode(6));
46167 if (lister != null) lister.RA(miStart, "FSAVE", disp);
46168 }
46169
46170 /**
46171 * restore FPU state - register displacement
46172 *
46173 * @param baseReg destination base register
46174 * @param disp destination displacement
46175 */
46176 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
46177 public final void emitFRSTOR_RegDisp (GPR baseReg, Offset disp) {
46178 int miStart = mi;
46179 // no prefix byte
46180 setMachineCodes(mi++, (byte) 0xDD);
46181 emitRegDispRegOperands(baseReg, disp, GPR.getForOpcode(4));
46182 if (lister != null) lister.RD(miStart, "FRSTOR", baseReg, disp);
46183 }
46184
46185 /**
46186 * restore FPU state - register indirect
46187 *
46188 * @param baseReg destination base register
46189 */
46190 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
46191 public final void emitFRSTOR_RegInd (GPR baseReg) {
46192 int miStart = mi;
46193 // no prefix byte
46194 setMachineCodes(mi++, (byte) 0xDD);
46195 emitRegIndirectRegOperands(baseReg, GPR.getForOpcode(4));
46196 if (lister != null) lister.RN(miStart, "FRSTOR", baseReg);
46197 }
46198
46199 /**
46200 * restore FPU state - register index
46201 *
46202 * @param baseReg destination base register
46203 * @param indexReg destination index register
46204 * @param scale destination scale
46205 * @param disp destination displacement
46206 */
46207 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
46208 public final void emitFRSTOR_RegIdx (GPR baseReg, GPR indexReg, short scale, Offset disp) {
46209 int miStart = mi;
46210 // no prefix byte
46211 setMachineCodes(mi++, (byte) 0xDD);
46212 emitSIBRegOperands(baseReg, indexReg, scale, disp, GPR.getForOpcode(4));
46213 if (lister != null) lister.RXD(miStart, "FRSTOR", baseReg, indexReg, scale, disp);
46214 }
46215
46216 /**
46217 * restore FPU state - register offset
46218 *
46219 * @param indexReg destination index register
46220 * @param scale destination scale
46221 * @param disp destination displacement
46222 */
46223 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
46224 public final void emitFRSTOR_RegOff (GPR indexReg, short scale, Offset disp) {
46225 int miStart = mi;
46226 // no prefix byte
46227 setMachineCodes(mi++, (byte) 0xDD);
46228 emitRegOffRegOperands(indexReg, scale, disp, GPR.getForOpcode(4));
46229 if (lister != null) lister.RFD(miStart, "FRSTOR", indexReg, scale, disp);
46230 }
46231
46232 /**
46233 * restore FPU state - absolute address
46234 *
46235 * @param disp address to store to
46236 */
46237 public final void emitFRSTOR_Abs (Address disp) {
46238 int miStart = mi;
46239 // no prefix byte
46240 setMachineCodes(mi++, (byte) 0xDD);
46241 emitAbsRegOperands(disp, GPR.getForOpcode(4));
46242 if (lister != null) lister.RA(miStart, "FRSTOR", disp);
46243 }
46244
46245 /**
46246 * load FPU control word - register displacement
46247 *
46248 * @param baseReg destination base register
46249 * @param disp destination displacement
46250 */
46251 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
46252 public final void emitFLDCW_RegDisp (GPR baseReg, Offset disp) {
46253 int miStart = mi;
46254 // no prefix byte
46255 setMachineCodes(mi++, (byte) 0xD9);
46256 emitRegDispRegOperands(baseReg, disp, GPR.getForOpcode(5));
46257 if (lister != null) lister.RD(miStart, "FLDCW", baseReg, disp);
46258 }
46259
46260 /**
46261 * load FPU control word - register indirect
46262 *
46263 * @param baseReg destination base register
46264 */
46265 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
46266 public final void emitFLDCW_RegInd (GPR baseReg) {
46267 int miStart = mi;
46268 // no prefix byte
46269 setMachineCodes(mi++, (byte) 0xD9);
46270 emitRegIndirectRegOperands(baseReg, GPR.getForOpcode(5));
46271 if (lister != null) lister.RN(miStart, "FLDCW", baseReg);
46272 }
46273
46274 /**
46275 * load FPU control word - register index
46276 *
46277 * @param baseReg destination base register
46278 * @param indexReg destination index register
46279 * @param scale destination scale
46280 * @param disp destination displacement
46281 */
46282 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
46283 public final void emitFLDCW_RegIdx (GPR baseReg, GPR indexReg, short scale, Offset disp) {
46284 int miStart = mi;
46285 // no prefix byte
46286 setMachineCodes(mi++, (byte) 0xD9);
46287 emitSIBRegOperands(baseReg, indexReg, scale, disp, GPR.getForOpcode(5));
46288 if (lister != null) lister.RXD(miStart, "FLDCW", baseReg, indexReg, scale, disp);
46289 }
46290
46291 /**
46292 * load FPU control word - register offset
46293 *
46294 * @param indexReg destination index register
46295 * @param scale destination scale
46296 * @param disp destination displacement
46297 */
46298 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
46299 public final void emitFLDCW_RegOff (GPR indexReg, short scale, Offset disp) {
46300 int miStart = mi;
46301 // no prefix byte
46302 setMachineCodes(mi++, (byte) 0xD9);
46303 emitRegOffRegOperands(indexReg, scale, disp, GPR.getForOpcode(5));
46304 if (lister != null) lister.RFD(miStart, "FLDCW", indexReg, scale, disp);
46305 }
46306
46307 /**
46308 * load FPU control word - absolute address
46309 *
46310 * @param disp address to store to
46311 */
46312 public final void emitFLDCW_Abs (Address disp) {
46313 int miStart = mi;
46314 // no prefix byte
46315 setMachineCodes(mi++, (byte) 0xD9);
46316 emitAbsRegOperands(disp, GPR.getForOpcode(5));
46317 if (lister != null) lister.RA(miStart, "FLDCW", disp);
46318 }
46319
46320 /**
46321 * store FPU control word, checking for exceptions - register displacement
46322 *
46323 * @param baseReg destination base register
46324 * @param disp destination displacement
46325 */
46326 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
46327 public final void emitFSTCW_RegDisp (GPR baseReg, Offset disp) {
46328 int miStart = mi;
46329 setMachineCodes(mi++, (byte) 0x9B);
46330 setMachineCodes(mi++, (byte) 0xD9);
46331 emitRegDispRegOperands(baseReg, disp, GPR.getForOpcode(7));
46332 if (lister != null) lister.RD(miStart, "FSTCW", baseReg, disp);
46333 }
46334
46335 /**
46336 * store FPU control word, checking for exceptions - register indirect
46337 *
46338 * @param baseReg destination base register
46339 */
46340 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
46341 public final void emitFSTCW_RegInd (GPR baseReg) {
46342 int miStart = mi;
46343 setMachineCodes(mi++, (byte) 0x9B);
46344 setMachineCodes(mi++, (byte) 0xD9);
46345 emitRegIndirectRegOperands(baseReg, GPR.getForOpcode(7));
46346 if (lister != null) lister.RN(miStart, "FSTCW", baseReg);
46347 }
46348
46349 /**
46350 * store FPU control word, checking for exceptions - register index
46351 *
46352 * @param baseReg destination base register
46353 * @param indexReg destination index register
46354 * @param scale destination scale
46355 * @param disp destination displacement
46356 */
46357 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
46358 public final void emitFSTCW_RegIdx (GPR baseReg, GPR indexReg, short scale, Offset disp) {
46359 int miStart = mi;
46360 setMachineCodes(mi++, (byte) 0x9B);
46361 setMachineCodes(mi++, (byte) 0xD9);
46362 emitSIBRegOperands(baseReg, indexReg, scale, disp, GPR.getForOpcode(7));
46363 if (lister != null) lister.RXD(miStart, "FSTCW", baseReg, indexReg, scale, disp);
46364 }
46365
46366 /**
46367 * store FPU control word, checking for exceptions - register offset
46368 *
46369 * @param indexReg destination index register
46370 * @param scale destination scale
46371 * @param disp destination displacement
46372 */
46373 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
46374 public final void emitFSTCW_RegOff (GPR indexReg, short scale, Offset disp) {
46375 int miStart = mi;
46376 setMachineCodes(mi++, (byte) 0x9B);
46377 setMachineCodes(mi++, (byte) 0xD9);
46378 emitRegOffRegOperands(indexReg, scale, disp, GPR.getForOpcode(7));
46379 if (lister != null) lister.RFD(miStart, "FSTCW", indexReg, scale, disp);
46380 }
46381
46382 /**
46383 * store FPU control word, checking for exceptions - absolute address
46384 *
46385 * @param disp address to store to
46386 */
46387 public final void emitFSTCW_Abs (Address disp) {
46388 int miStart = mi;
46389 setMachineCodes(mi++, (byte) 0x9B);
46390 setMachineCodes(mi++, (byte) 0xD9);
46391 emitAbsRegOperands(disp, GPR.getForOpcode(7));
46392 if (lister != null) lister.RA(miStart, "FSTCW", disp);
46393 }
46394
46395 /**
46396 * store FPU control word, ignoring exceptions - register displacement
46397 *
46398 * @param baseReg destination base register
46399 * @param disp destination displacement
46400 */
46401 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
46402 public final void emitFNSTCW_RegDisp (GPR baseReg, Offset disp) {
46403 int miStart = mi;
46404 // no prefix byte
46405 setMachineCodes(mi++, (byte) 0xD9);
46406 emitRegDispRegOperands(baseReg, disp, GPR.getForOpcode(7));
46407 if (lister != null) lister.RD(miStart, "FNSTCW", baseReg, disp);
46408 }
46409
46410 /**
46411 * store FPU control word, ignoring exceptions - register indirect
46412 *
46413 * @param baseReg destination base register
46414 */
46415 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
46416 public final void emitFNSTCW_RegInd (GPR baseReg) {
46417 int miStart = mi;
46418 // no prefix byte
46419 setMachineCodes(mi++, (byte) 0xD9);
46420 emitRegIndirectRegOperands(baseReg, GPR.getForOpcode(7));
46421 if (lister != null) lister.RN(miStart, "FNSTCW", baseReg);
46422 }
46423
46424 /**
46425 * store FPU control word, ignoring exceptions - register index
46426 *
46427 * @param baseReg destination base register
46428 * @param indexReg destination index register
46429 * @param scale destination scale
46430 * @param disp destination displacement
46431 */
46432 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1,2})
46433 public final void emitFNSTCW_RegIdx (GPR baseReg, GPR indexReg, short scale, Offset disp) {
46434 int miStart = mi;
46435 // no prefix byte
46436 setMachineCodes(mi++, (byte) 0xD9);
46437 emitSIBRegOperands(baseReg, indexReg, scale, disp, GPR.getForOpcode(7));
46438 if (lister != null) lister.RXD(miStart, "FNSTCW", baseReg, indexReg, scale, disp);
46439 }
46440
46441 /**
46442 * store FPU control word, ignoring exceptions - register offset
46443 *
46444 * @param indexReg destination index register
46445 * @param scale destination scale
46446 * @param disp destination displacement
46447 */
46448 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
46449 public final void emitFNSTCW_RegOff (GPR indexReg, short scale, Offset disp) {
46450 int miStart = mi;
46451 // no prefix byte
46452 setMachineCodes(mi++, (byte) 0xD9);
46453 emitRegOffRegOperands(indexReg, scale, disp, GPR.getForOpcode(7));
46454 if (lister != null) lister.RFD(miStart, "FNSTCW", indexReg, scale, disp);
46455 }
46456
46457 /**
46458 * store FPU control word, ignoring exceptions - absolute address
46459 *
46460 * @param disp address to store to
46461 */
46462 public final void emitFNSTCW_Abs (Address disp) {
46463 int miStart = mi;
46464 // no prefix byte
46465 setMachineCodes(mi++, (byte) 0xD9);
46466 emitAbsRegOperands(disp, GPR.getForOpcode(7));
46467 if (lister != null) lister.RA(miStart, "FNSTCW", disp);
46468 }
46469
46470 /**
46471 * load 1.0 into FP0
46472 *
46473 * @param dstReg must be FP0
46474 */
46475 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
46476 public final void emitFLD1_Reg(FPR dstReg) {
46477 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
46478 int miStart = mi;
46479 setMachineCodes(mi++, (byte) 0xD9);
46480 setMachineCodes(mi++, (byte) 0xE8);
46481 if (lister != null) lister.R(miStart, "FLD1", dstReg);
46482 }
46483
46484 /**
46485 * load log_2(10) into FP0
46486 *
46487 * @param dstReg must be FP0
46488 */
46489 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
46490 public final void emitFLDL2T_Reg(FPR dstReg) {
46491 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
46492 int miStart = mi;
46493 setMachineCodes(mi++, (byte) 0xD9);
46494 setMachineCodes(mi++, (byte) 0xE9);
46495 if (lister != null) lister.R(miStart, "FLDL2T", dstReg);
46496 }
46497
46498 /**
46499 * load log_2(e) into FP0
46500 *
46501 * @param dstReg must be FP0
46502 */
46503 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
46504 public final void emitFLDL2E_Reg(FPR dstReg) {
46505 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
46506 int miStart = mi;
46507 setMachineCodes(mi++, (byte) 0xD9);
46508 setMachineCodes(mi++, (byte) 0xEA);
46509 if (lister != null) lister.R(miStart, "FLDL2E", dstReg);
46510 }
46511
46512 /**
46513 * load pi into FP0
46514 *
46515 * @param dstReg must be FP0
46516 */
46517 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
46518 public final void emitFLDPI_Reg(FPR dstReg) {
46519 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
46520 int miStart = mi;
46521 setMachineCodes(mi++, (byte) 0xD9);
46522 setMachineCodes(mi++, (byte) 0xEB);
46523 if (lister != null) lister.R(miStart, "FLDPI", dstReg);
46524 }
46525
46526 /**
46527 * load log_10(2) into FP0
46528 *
46529 * @param dstReg must be FP0
46530 */
46531 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
46532 public final void emitFLDLG2_Reg(FPR dstReg) {
46533 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
46534 int miStart = mi;
46535 setMachineCodes(mi++, (byte) 0xD9);
46536 setMachineCodes(mi++, (byte) 0xEC);
46537 if (lister != null) lister.R(miStart, "FLDLG2", dstReg);
46538 }
46539
46540 /**
46541 * load log_e(2) into FP0
46542 *
46543 * @param dstReg must be FP0
46544 */
46545 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
46546 public final void emitFLDLN2_Reg(FPR dstReg) {
46547 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
46548 int miStart = mi;
46549 setMachineCodes(mi++, (byte) 0xD9);
46550 setMachineCodes(mi++, (byte) 0xED);
46551 if (lister != null) lister.R(miStart, "FLDLN2", dstReg);
46552 }
46553
46554 /**
46555 * load 0.0 into FP0
46556 *
46557 * @param dstReg must be FP0
46558 */
46559 @Inline(value=Inline.When.ArgumentsAreConstant, arguments={1})
46560 public final void emitFLDZ_Reg(FPR dstReg) {
46561 if (VM.VerifyAssertions) VM._assert(dstReg == FP0);
46562 int miStart = mi;
46563 setMachineCodes(mi++, (byte) 0xD9);
46564 setMachineCodes(mi++, (byte) 0xEE);
46565 if (lister != null) lister.R(miStart, "FLDZ", dstReg);
46566 }
46567
46568 }